Merge with git://www.denx.de/git/u-boot.git

CHANGELOG

@@ -1,3 +1,453 @@
+commit 885ec89b648a899a2f32393fd3ffd9f7234c4402
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Sat May 5 18:05:02 2007 +0200
+
+    Add STX GP3 SSA board to MAKEALL script; update CHANGELOG.
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 5499645b3fe17a548af9dfc479ca6e2455f179a2
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Sat May 5 17:15:50 2007 +0200
+
+    Make "file" command happy with some config.mk files; update CHANGELOG
+
+commit e3b8c78bc2489c27ae020986ef0eaca684866cef
+Author: Jeffrey Mann <mannj@embeddedplanet.com>
+Date:	Sat May 5 08:32:14 2007 +0200
+
+    ppc4xx: Detect if the sysclk on Sequoia is 33 or 33.333 MHz
+
+    The AMCC Secquoia board has been changed in a new revision from using a
+    33.000 MHz clock to a 33.333 MHz system clock. A bit in the CPLD
+    indicates the difference. This patch reads that bit and uses the correct
+    clock speed for the board. This code is backward compatable will all
+    prior boards. All prior boards will be read as 33.000.
+
+    Signed-off-by: Jeffrey Mann <mannj@embeddedplanet.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit f544ff6656fca263ed1ebe39899b6d95da67c8b8
+Author: Stefan Roese <sr@denx.de>
+Date:	Sat May 5 08:29:01 2007 +0200
+
+    ppc4xx: Sequoia: Remove cpu/ppc4xx/speed.c from NAND booting
+
+    Using cpu/ppc4xx/speed.c to calculate the bus frequency is too big
+    for the 4k NAND boot image so define bus_frequency to 133MHz here
+    which is save for the refresh counter setup.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit a79886590593ba1d667c840caa4940c61639f18f
+Author: Thomas Knobloch <knobloch@siemens.com>
+Date:	Sat May 5 07:04:42 2007 +0200
+
+    NAND: Wrong calculation of page number in nand_block_bad()
+
+    In case that there is no memory based bad block table available the
+    function nand_block_checkbad() in drivers/mtd/nand/nand_base.c will call
+    nand_block_bad() directly. When parameter 'getchip' is set to zero,
+    nand_block_bad() will not right shift the offset to calculate the
+    correct page number.
+
+    Signed-off-by: Thomas Knobloch <knobloch@siemens.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 9877d7dcd1eebe61aa5d8b8ffe9c048ea426e6f6
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Fri May 4 10:02:33 2007 +0200
+
+    Fix initrd length corruption in bootm command.
+
+    When using FDT Images, the length of an inital ramdisk was
+    overwritten (bug introduced by commit 87a449c8, 22 Aug 2006).
+
+    Patches by Timur Tabi & Johns Daniel.
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit c64a89d6ce8584b9fc64f4e85da9ecac3cfc2c2a
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Thu May 3 16:34:41 2007 +0200
+
+    Update board configuration for STX GP3SSA board:
+
+    Enable hush shell, environment in flash rather in EEPROM,
+    more user-friendly default environment, etc.
+    The simple EEPROM environment can be selected easily in the board
+    config file.
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 2c6fb199dc5756fc72f49d1f4de105e089049d65
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Tue Apr 24 14:37:49 2007 +0200
+
+    Cleanup STX GP3SSA code; fix build and compile problems.
+
+commit 35171dc04e028ecacc23ad916a66295472555dbf
+Author: Dan Malek <dan@embeddedalley.com>
+Date:	Fri Jan 5 09:15:34 2007 +0100
+
+    Add support for STX GP3SSA (stxssa) Board
+
+    Signed-off-by Dan Malek, <dan@embeddedalley.com>
+
+commit ffa621a0d12a1ccd81c936c567f8917a213787a8
+Author: Andy Fleming <afleming@freescale.com>
+Date:	Sat Feb 24 01:08:13 2007 -0600
+
+    Cleaned up some 85xx PCI bugs
+
+    * Cleaned up the CDS PCI Config Tables and added NULL entries to
+      the end
+    * Fixed PCIe LAWBAR assignemt to use the cpu-relative address
+    * Fixed 85xx PCI code to assign powar region sizes based on the
+      config values (rather than hard-coding them)
+    * Fixed the 8548 CDS PCI2 IO to once again have 0 as the base address
+
+    Signed-off-by: Andy Fleming <afleming@freescale.com>
+
+commit 6743105988fc44d5b0d30388c790607835aae7a6
+Author: Andy Fleming <afleming@freescale.com>
+Date:	Mon Apr 23 02:54:25 2007 -0500
+
+    Add support for the 8568 MDS board
+
+    This included some changes to common files:
+    * Add 8568 processor SVR to various places
+    * Add support for setting the qe bus-frequency value in the dts
+    * Add the 8568MDS target to the Makefile
+
+    Signed-off-by: Andy Fleming <afleming@freescale.com>
+
+commit af1c2b84bf27c8565baddc82d1abb93700d10e2e
+Author: David Updegraff <dave@cray.com>
+Date:	Fri Apr 20 14:34:48 2007 -0500
+
+    Add support for treating unknown PHYs as generic PHYs.
+
+    When bringing up u-boot on new boards, PHY support sometimes gets
+    neglected.	Most PHYs don't really need any special support,
+    though.  By adding a generic entry that always matches if nothing
+    else does, we can provide support for "unsupported" PHYs for the
+    tsec.
+
+    The generic PHY driver supports most PHYs, including gigabit.
+
+    Signed-off-by: David Updegraff <dave@cray.com>
+    Signed-off-by: Andy Fleming <afleming@freescale.com>
+
+commit a75af9bfd8fff0499efdbb90601cec5a2afef117
+Author: James Yang <James.Yang@freescale.com>
+Date:	Wed Feb 7 15:28:04 2007 -0600
+
+    Conditionalize 8641 Rev1.0 MCM workarounds
+
+    Signed-off-by: James Yang <James.Yang@freescale.com>
+    Signed-off-by: Jon Loeliger <jdl@freescale.com>
+
+commit c1ab82669d9525998c34e802a12cad662723f22a
+Author: James Yang <James.Yang@freescale.com>
+Date:	Fri Mar 16 13:02:53 2007 -0500
+
+    Rewrote picos_to_clk() to avoid rounding errors.
+    Clarified that conversion is to DRAM clocks rather than platform clocks.
+    Made function static to spd_sdram.c.
+
+    Signed-off-by: James Yang <James.Yang@freescale.com>
+    Signed-off-by: Jon Loeliger <jdl@freescale.com>
+
+commit 8b39501d28754e72726ce7fb02310e56dbdf116a
+Author: Stefan Roese <sr@denx.de>
+Date:	Sun Apr 29 14:13:01 2007 +0200
+
+    ppc4xx: Bamboo: Use current NAND driver and *not* the legacy driver
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 37ed6cdd4159195bfad68d8a237f6adda8f482cb
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Tue Apr 24 14:03:45 2007 +0200
+
+    ppc4xx: setup 440EPx/GRx ZMII/RGMII bridge depending on PFC register content.
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+
+commit 66ed6cca3f340f7a8a06d9272ae2ef8e96f0273d
+Author: Andy Fleming <afleming@freescale.com>
+Date:	Mon Apr 23 02:37:47 2007 -0500
+
+    Reworked 85xx speed detection code
+
+    Changed the code to read the registers and calculate the clock
+    rates, rather than using a "switch" statement.
+
+    Idea from Andrew Klossner <andrew@cesa.opbu.xerox.com>
+
+    Signed-off-by: Andy Fleming <afleming@freescale.com>
+
+commit 81f481ca708ed6a56bf9c410e3191dbad581c565
+Author: Andy Fleming <afleming@freescale.com>
+Date:	Mon Apr 23 02:24:28 2007 -0500
+
+    Enable 8544 support
+
+    * Add support to the Makefile
+    * Add 8544 configuration support to the tsec driver
+    * Add 8544 SVR numbers to processor.h
+
+    Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
+    Signed-off-by: Jon Loeliger <jdl@freescale.com>
+
+commit 0d8c3a2096eaff8d7de89d45e9af4d4b0d4868fe
+Author: Andy Fleming <afleming@freescale.com>
+Date:	Fri Feb 23 17:12:25 2007 -0600
+
+    Support 1G size on 8548
+
+    e500v2 and newer cores support 1G page sizes.
+
+    Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
+    Signed-off-by: Andy Fleming <afleming@freescale.com>
+
+commit 45cef612cc601d2d1c890fbbd7cdc9609a189a46
+Author: Andy Fleming <afleming@freescale.com>
+Date:	Fri Feb 23 17:11:16 2007 -0600
+
+    Changed BOOKE_PAGESZ_nGB to BOOKE_PAGESZ_nG
+
+    The other pagesz constants use one letter to specify order of
+    magnitude.	Also change the one reference to it in mpc8548cds/init.S
+
+    Signed-off-by: Andy Fleming <afleming@freescale.com>
+
+commit 1f9a318cea14272edd10d63739e2d326c90f430e
+Author: Andy Fleming <afleming@freescale.com>
+Date:	Fri Feb 23 16:28:46 2007 -0600
+
+    Only set ddrioovcr for 8548 rev1.
+
+    Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
+    Signed-off-by: Andy Fleming <afleming@freescale.com>
+
+commit 9343dbf85bc03033f2102d8e8543567c2c1ad2d2
+Author: Andy Fleming <afleming@freescale.com>
+Date:	Sat Feb 24 01:16:45 2007 -0600
+
+    Tweak DDR ECC error counter
+
+    Enable single-bit error counter when memory was cleared by ddr controller.
+
+    Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
+    Signed-off-by: Andy Fleming <afleming@freescale.com>
+
+commit 85e7c7a45e3dd9c7ce3e722352ba60f8df1a7a4b
+Author: Timur Tabi <timur@freescale.com>
+Date:	Mon Feb 12 13:34:55 2007 -0600
+
+    85xx: write MAC address to mac-address and local-mac-address
+
+    Some device trees have a mac-address property, some have local-mac-address,
+    and some have both.  To support all of these device trees, ftp_cpu_setup()
+    should write the MAC address to mac-address and local-mac-address, if they
+    exist.
+
+    Signed-off-by: Timur Tabi <timur@freescale.com>
+
+commit 03b81b48eec0ad249ec97a4ae16c36fa2e014ff4
+Author: Andy Fleming <afleming@freescale.com>
+Date:	Mon Apr 23 01:44:44 2007 -0500
+
+    Some 85xx cpu cleanups
+
+    * Cleaned up the TSR[WIS] clearing
+    * Cleaned up DMA initialization
+
+    Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
+    Signed-off-by: Jon Loeliger <jdl@freescale.com>
+    Acked-by: Andy Fleming <afleming@freescale.com>
+
+commit 151d5d992eab8c497b24c816c73dc1ad8bffb4eb
+Author: Andy Fleming <afleming@freescale.com>
+Date:	Mon Apr 23 01:32:22 2007 -0500
+
+    Add cpu support for the 8544
+
+    Recognize new SVR values, and add a few register definitions
+
+    Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
+    Signed-off-by: Jon Loeliger <jdl@freescale.com>
+    Acked-by: Andy Fleming <afleming@freescale.com>
+
+commit 25d83d7f4ac65727182d8ddaf7ba42fa74cf65ae
+Author: Jon Loeliger <jdl@freescale.com>
+Date:	Wed Apr 11 16:51:02 2007 -0500
+
+    Add MPC8544DS basic port board files.
+
+    Add board port under new board/freescale directory
+    structure and reuse existing PIXIS FPGA support there.
+
+    Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
+    Signed-off-by: Jon Loeliger <jdl@freescale.com>
+
+commit 0cde4b00fc7393b89f379d83a9d436dcb1334bfa
+Author: Jon Loeliger <jdl@freescale.com>
+Date:	Wed Apr 11 16:50:57 2007 -0500
+
+    Add MPC8544DS main configuration file.
+
+    Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
+    Signed-off-by: Jon Loeliger <jdl@freescale.com>
+
+commit 362dd83077ac04c0296bca3e824ec2fb3d44d9d6
+Author: Sergei Shtylyov <sshtylyov@ru.mvista.com>
+Date:	Wed Dec 27 22:07:15 2006 +0300
+
+    Fix PCI I/O space mapping on Freescale MPC85x0ADS
+
+    The PCI I/O space mapping for Freescale MPC8540ADS board was broken by commit
+    52c7a68b8d587ebcf5a6b051b58b3d3ffa377ddc which failed to update the #define's
+    describing the local address window used for the PCI I/O space accesses -- fix
+    this and carry over the necessary changes into the MPC8560ADS code since the
+    PCI I/O space mapping was also broken for this board (by the earlier commit
+    087454609e47295443af793a282cddcd91a5f49c).	Add the comments clarifying how
+    the PCI I/O space must be mapped to all the MPC85xx board config. headers.
+
+    Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
+
+     board/mpc8540ads/init.S	  |    4 ++--
+     board/mpc8560ads/init.S	  |    4 ++--
+     include/configs/MPC8540ADS.h |    5 ++---
+     include/configs/MPC8541CDS.h |    2 +-
+     include/configs/MPC8548CDS.h |    2 +-
+     include/configs/MPC8560ADS.h |    8 ++++----
+     6 files changed, 12 insertions(+), 13 deletions(-)
+
+commit 96629cbabdb727d4a5e62542deefc01d498db6dc
+Author: Zang Roy-r61911 <tie-fei.zang@freescale.com>
+Date:	Tue Dec 5 16:42:30 2006 +0800
+
+    u-boot: Fix e500 v2 core reset bug
+
+    The following patch fixes the e500 v2 core reset bug.
+    For e500 v2 core, a new reset control register is added to reset the
+    processor.
+
+    Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
+
+commit 63247a5acd58032e6cf33f525bc3923b467bac88
+Author: Zang Roy-r61911 <tie-fei.zang@freescale.com>
+Date:	Wed Dec 20 11:01:00 2006 +0800
+
+    u-boot: v2: Remove the fixed TLB and LAW entrynubmer
+
+    Remove the fixed TLB and LAW entry nubmer. Use actually TLB and LAW
+    entry number to control the loop.  This can reduce the potential risk
+    for the 85xx processor increasing its TLB adn LAW entry number.
+
+    Signed-off-by: Swarthout Edward <swarthout@freescale.com>
+    Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
+
+commit 0b1934ba12fd408fcc3b8bd9f4b04864c42a42bf
+Author: Zang Roy-r61911 <tie-fei.zang@freescale.com>
+Date:	Mon Dec 18 17:01:04 2006 +0800
+
+    u-boot: Fix the 85xxcds tsec bug
+
+    Fix the 85xxcds tsec bug.
+    When enable PCI, tsec.o should be added to u-boot.lds to make tsec work.
+
+    Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
+
+commit 7337b237ffc4aaf1b9467024fe472a880d852598
+Author: Zang Roy-r61911 <tie-fei.zang@freescale.com>
+Date:	Fri Dec 15 14:43:31 2006 +0800
+
+    u-boot: Fix CPU2 errata on MPC8548CDS board
+
+    This patch apply workaround of CPU2 errata on MPC8548CDS board.
+
+    Signed-off-by:Ebony Zhu <ebony.zhu@freescale.com>
+
+commit 39b18c4f3e0b6d0dc00f4e68bad2da3766c85f09
+Author: ebony.zhu@freescale.com <ebony.zhu@freescale.com>
+Date:	Mon Dec 18 16:25:15 2006 +0800
+
+    u-boot: Disables MPC8548CDS 2T_TIMING for DDR by default
+
+    This patch disables MPC8548CDS 2T_TIMING for DDR by default.
+
+    Signed-off-by:Ebony Zhu <ebony.zhu@freescale.com>
+
+commit 41fb7e0f1ec9b91bdae2565bab5f2e3ee15039c7
+Author: Zang Roy-r61911 <tie-fei.zang@freescale.com>
+Date:	Thu Dec 14 14:14:55 2006 +0800
+
+    u-boot: Enable PCI function and add PEX & rapidio memory map on MPC8548CDS board
+
+    Enable PCI function and add PEX & rapidio memory map on MPC8548CDS
+    board.
+    Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
+
+commit 323bfa8f436dc3bc57187c9b1488bc3146ff1522
+Author: Stefan Roese <sr@denx.de>
+Date:	Mon Apr 23 12:00:22 2007 +0200
+
+    Remove BOARDLIBS usage completely
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 2e343b9a57f32e1bd08c35c9976910333fb4e13d
+Author: Ed Swarthout <Ed.Swarthout@freescale.com>
+Date:	Wed Feb 28 05:37:29 2007 -0600
+
+    mpc8641hpcn: Fix LAW and TLB setup to use the IO_PHYS #defines.
+
+    Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
+
+commit 79cb47391eebef85acadb3f6961ef6c55cace6ac
+Author: Zhang Wei <wei.zhang@freescale.com>
+Date:	Fri Jan 19 10:42:37 2007 +0800
+
+    Enable LAWs for MPC8641 PCI-Ex2.
+
+    Signed-off-by: Zhang Wei <wei.zhang@freescale.com>
+    Signed-off-by: Jon Loeliger <jdl@freescale.com>
+
+commit bd7851ce1e1f140665b520026abf1042968b1102
+Author: Jon Loeliger <jdl@freescale.com>
+Date:	Fri Apr 20 14:12:26 2007 -0500
+
+    mpc86xx; Write MAC address to mac-address and local-mac-address
+
+    Some device trees have a mac-address property, some have local-mac-address,
+    and some have both.  To support all of these device trees, ftp_cpu_setup()
+    should write the MAC address to mac-address and local-mac-address, if they
+    exist.
+
+    Signed-off-by: Timur Tabi <timur@freescale.com>
+    Signed-off-by: Jon Loeliger <jdl@freescale.com>
+
+commit 7dbdf28b8bd855a8530dc3292e4982575a197060
+Author: Jon Loeliger <jdl@freescale.com>
+Date:	Fri Apr 20 14:11:38 2007 -0500
+
+    mpc86xx: protect memcpy to bad address if a mac-address is missing from dt
+
+    Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+    Signed-off-by: Jon Loeliger <jdl@freescale.com>
+
+commit 14da5f7675bbb427c469e3f45006e027b6e21db9
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Fri Apr 20 17:43:28 2007 +0200
+
+    Cleanup compiler warnings, update CHANGELOG
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
 commit 6923565db12af34fd5e02d354ee65a8c78ac460f
 Author: Detlev Zundel <dzu@denx.de>
 Date:	Fri Apr 20 12:01:47 2007 +0200
@@ -30,6 +480,20 @@ Date:	Thu Apr 19 23:14:39 2007 -0400
     Also moved the libfdt.a requirement into the main Makefile.  That is
       The U-Boot Way.
 
+commit d21686263574e95cb3e9e9b0496f968b1b897fdb
+Author: Stefan Roese <sr@denx.de>
+Date:	Thu Apr 19 09:53:52 2007 +0200
+
+    ppc4xx: Fix chip select timing for SysACE access on AMCC Katmai
+
+    Previous versions used full wait states for the chip select #1 which
+    is connected to the Xilinix SystemACE controller on the AMCC Katmai
+    evaluation board. This leads to really slow access and therefore low
+    performance. This patch now sets up the chip select a lot faster
+    resulting in much better read/write performance of the Linux driver.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
 commit 37837828d89084879bee2f2b8c7c68d4695940df
 Author: Wolfgang Denk <wd@denx.de>
 Date:	Wed Apr 18 17:49:29 2007 +0200

MAINTAINERS

@@ -221,10 +221,11 @@ Jon Loeliger <jdl@freescale.com>
 
 	MPC8641HPCN		MPC8641D
 
-Dan Malek <dan@embeddededge.com>
+Dan Malek <dan@embeddedalley.com>
 
-	STxGP3			MPC85xx
-	STxXTc			MPC8xx
+	stxgp3			MPC85xx
+	stxssa			MPC85xx
+	stxxtc			MPC8xx
 
 Eran Man <eran@nbase.co.il>
 

MAKEALL

@@ -142,10 +142,11 @@ LIST_83xx="	\
 #########################################################################
 
 LIST_85xx="	\
-	MPC8540ADS	MPC8540EVAL	MPC8541CDS	MPC8548CDS	\
-	MPC8555CDS	MPC8560ADS	PM854		PM856		\
-	sbc8540		sbc8560		stxgp3		TQM8540		\
-	TQM8541		TQM8555		TQM8560				\
+	MPC8540ADS	MPC8540EVAL	MPC8541CDS	MPC8544DS	\
+	MPC8548CDS	MPC8555CDS	MPC8560ADS	PM854		\
+	PM856		sbc8540		sbc8560		stxgp3		\
+	stxssa		TQM8540		TQM8541		TQM8555		\
+	TQM8560								\
 "
 
 #########################################################################

Makefile

@@ -197,6 +197,9 @@ LIBS += cpu/$(CPU)/lib$(CPU).a
 ifdef SOC
 LIBS += cpu/$(CPU)/$(SOC)/lib$(SOC).a
 endif
+ifeq ($(CPU),ixp)
+LIBS += cpu/ixp/npe/libnpe.a
+endif
 LIBS += lib_$(ARCH)/lib$(ARCH).a
 LIBS += fs/cramfs/libcramfs.a fs/fat/libfat.a fs/fdos/libfdos.a fs/jffs2/libjffs2.a \
 	fs/reiserfs/libreiserfs.a fs/ext2/libext2fs.a
@@ -220,7 +223,6 @@ LIBS += $(shell if [ -d post/board/$(BOARDDIR) ]; then echo \
 	"post/board/$(BOARDDIR)/libpost$(BOARD).a"; fi)
 LIBS += common/libcommon.a
 LIBS += libfdt/libfdt.a
-LIBS += $(BOARDLIBS)
 
 LIBS := $(addprefix $(obj),$(LIBS))
 .PHONY : $(LIBS)
@@ -1733,12 +1735,18 @@ MPC8560ADS_config:	unconfig
 MPC8541CDS_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8541cds cds
 
+MPC8544DS_config:	unconfig
+	@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8544ds freescale
+
 MPC8548CDS_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8548cds cds
 
 MPC8555CDS_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8555cds cds
 
+MPC8568MDS_config:	unconfig
+	@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8568mds
+
 PM854_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc mpc85xx pm854
 
@@ -1774,6 +1782,9 @@ sbc8560_66_config:      unconfig
 stxgp3_config:		unconfig
 	@$(MKCONFIG) $(@:_config=) ppc mpc85xx stxgp3
 
+stxssa_config:		unconfig
+	@$(MKCONFIG) $(@:_config=) ppc mpc85xx stxssa
+
 TQM8540_config		\
 TQM8541_config		\
 TQM8555_config		\

board/amcc/bamboo/bamboo.c

@@ -277,87 +277,6 @@ int board_early_init_f(void)
 	return 0;
 }
 
-#if (CONFIG_COMMANDS & CFG_CMD_NAND)
-#include <linux/mtd/nand_legacy.h>
-extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
-
-/*----------------------------------------------------------------------------+
-  | nand_reset.
-  |   Reset Nand flash
-  |   This routine will abort previous cmd
-  +----------------------------------------------------------------------------*/
-int nand_reset(ulong addr)
-{
-	int wait=0, stat=0;
-
-	out8(addr + NAND_CMD_REG, NAND0_CMD_RESET);
-	out8(addr + NAND_CMD_REG, NAND0_CMD_READ_STATUS);
-
-	while ((stat != 0xc0) && (wait != 0xffff)) {
-		stat = in8(addr + NAND_DATA_REG);
-		wait++;
-	}
-
-	if (stat == 0xc0) {
-		return 0;
-	} else {
-		printf("NAND Reset timeout.\n");
-		return -1;
-	}
-}
-
-void board_nand_set_device(int cs, ulong addr)
-{
-	/* Set NandFlash Core Configuration Register */
-	out32(addr + NAND_CCR_REG, 0x00001000 | (cs << 24));
-
-	switch (cs) {
-	case 1:
-		/* -------
-		 *  NAND0
-		 * -------
-		 * K9F1208U0A : 4 addr cyc, 1 col + 3 Row
-		 * Set NDF1CR - Enable External CS1 in NAND FLASH controller
-		 */
-		out32(addr + NAND_CR1_REG, 0x80002222);
-		break;
-
-	case 2:
-		/* -------
-		 *  NAND1
-		 * -------
-		 * K9K2G0B : 5 addr cyc, 2 col + 3 Row
-		 * Set NDF2CR : Enable External CS2 in NAND FLASH controller
-		 */
-		out32(addr + NAND_CR2_REG, 0xC0007777);
-		break;
-	}
-
-	/* Perform Reset Command */
-	if (nand_reset(addr) != 0)
-		return;
-}
-
-void nand_init(void)
-{
-	board_nand_set_device(1, CFG_NAND_ADDR);
-
-	nand_probe(CFG_NAND_ADDR);
-	if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
-		print_size(nand_dev_desc[0].totlen, "\n");
-	}
-
-#if 0 /* NAND1 not supported yet */
-	board_nand_set_device(2, CFG_NAND2_ADDR);
-
-	nand_probe(CFG_NAND2_ADDR);
-	if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
-		print_size(nand_dev_desc[0].totlen, "\n");
-	}
-#endif
-}
-#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */
-
 int checkboard(void)
 {
 	char *s = getenv("serial#");

board/amcc/bamboo/u-boot.lds

@@ -68,19 +68,7 @@ SECTIONS
 
     cpu/ppc4xx/start.o	(.text)
     board/amcc/bamboo/init.o	(.text)
-    cpu/ppc4xx/kgdb.o	(.text)
-    cpu/ppc4xx/traps.o	(.text)
-    cpu/ppc4xx/interrupts.o	(.text)
-    cpu/ppc4xx/serial.o	(.text)
-    cpu/ppc4xx/cpu_init.o	(.text)
-    cpu/ppc4xx/speed.o	(.text)
-    common/dlmalloc.o	(.text)
-    lib_generic/crc32.o		(.text)
-    lib_ppc/extable.o	(.text)
-    lib_generic/zlib.o		(.text)
-
-/*    . = env_offset;*/
-/*    common/environment.o(.text)*/
+    board/amcc/bamboo/bamboo.o	(.text)
 
     *(.text)
     *(.fixup)

board/amcc/sequoia/sdram.c

@@ -371,6 +371,14 @@ void denali_core_search_data_eye(unsigned long memory_size)
 }
 #endif /* CONFIG_DDR_DATA_EYE */
 
+#if defined(CONFIG_NAND_SPL)
+/* Using cpu/ppc4xx/speed.c to calculate the bus frequency is too big
+ * for the 4k NAND boot image so define bus_frequency to 133MHz here
+ * which is save for the refresh counter setup.
+ */
+#define get_bus_freq(val)	133000000
+#endif
+
 /*************************************************************************
  *
  * initdram -- 440EPx's DDR controller is a DENALI Core
@@ -404,7 +412,7 @@ long int initdram (int board_type)
 	mtsdram(DDR0_22, 0x00267F0B);
 	mtsdram(DDR0_23, 0x00000000);
 	mtsdram(DDR0_24, 0x01010002);
-	if (speed > 133333333)
+	if (speed > 133333334)
 		mtsdram(DDR0_26, 0x5B26050C);
 	else
 		mtsdram(DDR0_26, 0x5B260408);

board/cds/mpc8541cds/mpc8541cds.c

@@ -477,11 +477,14 @@ void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_ta
 static struct pci_config_table pci_mpc85xxcds_config_table[] = {
 	{0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
 	{0x1106, 0x0686, PCI_ANY_ID, 1, 2, 0, mpc85xx_config_via, {0,0,0}},
-	{0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1, mpc85xx_config_via_usbide, {0,0,0}},
+	{0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1,
+		mpc85xx_config_via_usbide, {0,0,0}},
 	{0x1105, 0x3038, PCI_ANY_ID, 1, 2, 2, mpc85xx_config_via_usb, {0,0,0}},
 	{0x1106, 0x3038, PCI_ANY_ID, 1, 2, 3, mpc85xx_config_via_usb2, {0,0,0}},
-	{0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5, mpc85xx_config_via_power, {0,0,0}},
-	{0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}}
+	{0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5,
+		mpc85xx_config_via_power, {0,0,0}},
+	{0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}},
+	{},
 };
 
 static struct pci_controller hose[] = {

board/cds/mpc8541cds/u-boot.lds

@@ -69,6 +69,7 @@ SECTIONS
     cpu/mpc85xx/interrupts.o (.text)
     cpu/mpc85xx/cpu_init.o (.text)
     cpu/mpc85xx/cpu.o (.text)
+    drivers/tsec.o (.text)
     cpu/mpc85xx/speed.o (.text)
     cpu/mpc85xx/pci.o (.text)
     common/dlmalloc.o (.text)

board/cds/mpc8548cds/init.S

@@ -64,8 +64,9 @@ tlb1_entry:
 	/*
 	 * Number of TLB0 and TLB1 entries in the following table
 	 */
-	.long 13
+	.long (2f-1f)/16
 
+1:
 #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
 	/*
 	 * TLB0		4K	Non-cacheable, guarded
@@ -134,7 +135,7 @@ tlb1_entry:
 
 	/*
 	 * TLB 1:	256M	Non-cacheable, guarded
-	 * 0x80000000	256M	PCI1 MEM First half
+	 * 0x80000000	256M	PCI1 MEM
 	 */
 	.long TLB1_MAS0(1, 1, 0)
 	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
@@ -143,40 +144,37 @@ tlb1_entry:
 
 	/*
 	 * TLB 2:	256M	Non-cacheable, guarded
-	 * 0x90000000	256M	PCI1 MEM Second half
+	 * 0x90000000	256M	PCI2 MEM
 	 */
 	.long TLB1_MAS0(1, 2, 0)
 	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000),
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE),
 			0,0,0,0,1,0,1,0)
-	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000),
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE),
 			0,0,0,0,0,1,0,1,0,1)
 
 	/*
-	 * TLB 3:	256M	Non-cacheable, guarded
-	 * 0xa0000000	256M	PCI2 MEM First half
+	 * TLB 3:	1GB	Non-cacheable, guarded
+	 * 0xa0000000	256M	PEX MEM First half
+	 * 0xb0000000	256M	PEX MEM Second half
+	 * 0xc0000000	256M	Rapid IO MEM First half
+	 * 0xd0000000	256M	Rapid IO MEM Second half
 	 */
 	.long TLB1_MAS0(1, 3, 0)
-	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE), 0,0,0,0,1,0,1,0)
-	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_PEX_MEM_BASE), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_PEX_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
 
 	/*
-	 * TLB 4:	256M	Non-cacheable, guarded
-	 * 0xb0000000	256M	PCI2 MEM Second half
+	 * TLB 4:	Reserved for future usage
 	 */
-	.long TLB1_MAS0(1, 4, 0)
-	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE + 0x10000000),
-			0,0,0,0,1,0,1,0)
-	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE + 0x10000000),
-			0,0,0,0,0,1,0,1,0,1)
 
 	/*
 	 * TLB 5:	64M	Non-cacheable, guarded
 	 * 0xe000_0000	1M	CCSRBAR
-	 * 0xe200_0000	16M	PCI1 IO
-	 * 0xe300_0000	16M	PCI2 IO
+	 * 0xe200_0000	8M	PCI1 IO
+	 * 0xe280_0000	8M	PCI2 IO
+	 * 0xe300_0000	16M	PEX IO
 	 */
 	.long TLB1_MAS0(1, 5, 0)
 	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
@@ -200,19 +198,22 @@ tlb1_entry:
 	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)
 	.long TLB1_MAS2(E500_TLB_EPN(CADMUS_BASE_ADDR), 0,0,0,0,1,0,1,0)
 	.long TLB1_MAS3(E500_TLB_RPN(CADMUS_BASE_ADDR), 0,0,0,0,0,1,0,1,0,1)
-
+2:
 	entry_end
 
 /*
  * LAW(Local Access Window) configuration:
  *
  * 0x0000_0000     0x7fff_ffff     DDR                     2G
- * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
- * 0xa000_0000     0xbfff_ffff     PCI2 MEM                512M
+ * 0x8000_0000     0x8fff_ffff     PCI1 MEM                256M
+ * 0x9000_0000     0x9fff_ffff     PCI2 MEM                256M
+ * 0xa000_0000     0xbfff_ffff     PEX MEM                 512M
+ * 0xc000_0000     0xdfff_ffff     RapidIO                 512M
  * 0xe000_0000     0xe000_ffff     CCSR                    1M
- * 0xe200_0000     0xe20f_ffff     PCI1 IO                 1M
- * 0xe210_0000     0xe21f_ffff     PCI2 IO                 1M
- * 0xf000_0000     0xf7ff_ffff     SDRAM                   128M
+ * 0xe200_0000     0xe27f_ffff     PCI1 IO                 8M
+ * 0xe280_0000     0xe2ff_ffff     PCI2 IO                 8M
+ * 0xe300_0000     0xe3ff_ffff     PEX IO                  16M
+ * 0xf000_0000     0xf3ff_ffff     SDRAM                   64M
  * 0xf800_0000     0xf80f_ffff     NVRAM/CADMUS (*)        1M
  * 0xff00_0000     0xff7f_ffff     FLASH (2nd bank)        8M
  * 0xff80_0000     0xffff_ffff     FLASH (boot bank)       8M
@@ -229,27 +230,39 @@ tlb1_entry:
 #define LAWAR0  ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
 
 #define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
-#define LAWAR1 	(LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
+#define LAWAR1 	(LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_256M))
 
 #define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff)
-#define LAWAR2 	(LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M))
+#define LAWAR2 	(LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_256M))
 
 #define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
-#define LAWAR3 	(LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M))
+#define LAWAR3 	(LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_8M))
 
 #define LAWBAR4 ((CFG_PCI2_IO_PHYS>>12) & 0xfffff)
-#define LAWAR4 	(LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M))
+#define LAWAR4 	(LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_8M))
 
 /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
 #define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
 #define LAWAR5 	(LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
 
+#define LAWBAR6 ((CFG_PEX_MEM_BASE>>12) & 0xfffff)
+#define LAWAR6 	(LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
+#define LAWBAR7 ((CFG_PEX_IO_PHYS>>12) & 0xfffff)
+#define LAWAR7 	(LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_16M))
+
+#define LAWBAR8 ((CFG_RIO_MEM_BASE>>12) & 0xfffff)
+#define LAWAR8  (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
 	.section .bootpg, "ax"
 	.globl	law_entry
 
 law_entry:
 	entry_start
-	.long 6
+	.long (4f-3f)/8
+3:
 	.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
-	.long LAWBAR4,LAWAR4,LAWBAR5,LAWAR5
+	.long LAWBAR4,LAWAR4,LAWBAR5,LAWAR5,LAWBAR6,LAWAR6,LAWBAR7,LAWAR7
+	.long LAWBAR8,LAWAR8
+4:
 	entry_end

board/cds/mpc8548cds/mpc8548cds.c

@@ -51,6 +51,7 @@ int checkboard (void)
 {
 	volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
 	volatile ccsr_gur_t *gur = &immap->im_gur;
+	volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm;
 
 	/* PCI slot in USER bits CSR[6:7] by convention. */
 	uint pci_slot = get_pci_slot ();
@@ -89,6 +90,12 @@ int checkboard (void)
 	 */
 	local_bus_init ();
 
+	/*
+	 * Fix CPU2 errata: A core hang possible while executing a
+	 * msync instruction and a snoopable transaction from an I/O
+	 * master tagged to make quick forward progress is present.
+	 */
+	ecm->eebpcr |= (1 << 16);
 
 	/*
 	 * Hack TSEC 3 and 4 IO voltages.
@@ -303,11 +310,14 @@ void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_ta
 static struct pci_config_table pci_mpc85xxcds_config_table[] = {
 	{0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
 	{0x1106, 0x0686, PCI_ANY_ID, 1, 2, 0, mpc85xx_config_via, {0,0,0}},
-	{0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1, mpc85xx_config_via_usbide, {0,0,0}},
+	{0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1,
+		mpc85xx_config_via_usbide, {0,0,0}},
 	{0x1105, 0x3038, PCI_ANY_ID, 1, 2, 2, mpc85xx_config_via_usb, {0,0,0}},
 	{0x1106, 0x3038, PCI_ANY_ID, 1, 2, 3, mpc85xx_config_via_usb2, {0,0,0}},
-	{0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5, mpc85xx_config_via_power, {0,0,0}},
-	{0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}}
+	{0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5,
+		mpc85xx_config_via_power, {0,0,0}},
+	{0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}},
+	{},
 };
 
 static struct pci_controller hose[] = {

board/cds/mpc8548cds/u-boot.lds

@@ -69,6 +69,7 @@ SECTIONS
     cpu/mpc85xx/interrupts.o (.text)
     cpu/mpc85xx/cpu_init.o (.text)
     cpu/mpc85xx/cpu.o (.text)
+    drivers/tsec.o (.text)
     cpu/mpc85xx/speed.o (.text)
     cpu/mpc85xx/pci.o (.text)
     common/dlmalloc.o (.text)

board/cds/mpc8555cds/mpc8555cds.c

@@ -474,11 +474,14 @@ void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_ta
 static struct pci_config_table pci_mpc85xxcds_config_table[] = {
 	{0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
 	{0x1106, 0x0686, PCI_ANY_ID, 1, 2, 0, mpc85xx_config_via, {0,0,0}},
-	{0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1, mpc85xx_config_via_usbide, {0,0,0}},
+	{0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1,
+		mpc85xx_config_via_usbide, {0,0,0}},
 	{0x1105, 0x3038, PCI_ANY_ID, 1, 2, 2, mpc85xx_config_via_usb, {0,0,0}},
 	{0x1106, 0x3038, PCI_ANY_ID, 1, 2, 3, mpc85xx_config_via_usb2, {0,0,0}},
-	{0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5, mpc85xx_config_via_power, {0,0,0}},
-	{0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}}
+	{0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5,
+		mpc85xx_config_via_power, {0,0,0}},
+	{0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}},
+	{},
 };
 
 
@@ -487,7 +490,7 @@ static struct pci_controller hose[] = {
 	config_table: pci_mpc85xxcds_config_table,
 	},
 #ifdef CONFIG_MPC85XX_PCI2
-	{ }
+	{},
 #endif
 };
 

board/cds/mpc8555cds/u-boot.lds

@@ -69,6 +69,7 @@ SECTIONS
     cpu/mpc85xx/interrupts.o (.text)
     cpu/mpc85xx/cpu_init.o (.text)
     cpu/mpc85xx/cpu.o (.text)
+    drivers/tsec.o (.text)
     cpu/mpc85xx/speed.o (.text)
     cpu/mpc85xx/pci.o (.text)
     common/dlmalloc.o (.text)

board/freescale/mpc8544ds/Makefile

@@ -0,0 +1,58 @@
+#
+# Copyright 2007 Freescale Semiconductor, Inc.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+# ifneq ($(OBJTREE),$(SRCTREE))
+# $(shell mkdir -p $(obj)./common)
+# endif
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= $(BOARD).o \
+	   ../common/pixis.o
+
+SOBJS	:= init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

board/freescale/mpc8544ds/config.mk

@@ -0,0 +1,32 @@
+#
+# Copyright 2007 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# mpc8544ds board
+#
+ifndef TEXT_BASE
+TEXT_BASE = 0xfff80000
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_E500=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC8544=1

board/freescale/mpc8544ds/init.S

@@ -0,0 +1,243 @@
+/*
+ * Copyright 2007 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <config.h>
+#include <mpc85xx.h>
+
+#define LAWAR_TRGT_PCI1		0x00000000
+#define LAWAR_TRGT_PCIE1	0x00200000
+#define LAWAR_TRGT_PCIE2	0x00100000
+#define LAWAR_TRGT_PCIE3	0x00300000
+#define LAWAR_TRGT_LBC		0x00400000
+#define LAWAR_TRGT_DDR		0x00f00000
+
+/*
+ * TLB0 and TLB1 Entries
+ *
+ * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
+ * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
+ * these TLB entries are established.
+ *
+ * The TLB entries for DDR are dynamically setup in spd_sdram()
+ * and use TLB1 Entries 8 through 15 as needed according to the
+ * size of DDR memory.
+ *
+ * MAS0: tlbsel, esel, nv
+ * MAS1: valid, iprot, tid, ts, tsize
+ * MAS2: epn, sharen, x0, x1, w, i, m, g, e
+ * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
+ */
+
+#define	entry_start \
+	mflr	r1 	;	\
+	bl	0f 	;
+
+#define	entry_end \
+0:	mflr	r0	;	\
+	mtlr	r1	;	\
+	blr		;
+
+
+	.section	.bootpg, "ax"
+	.globl	tlb1_entry
+tlb1_entry:
+	entry_start
+
+	/*
+	 * Number of TLB0 and TLB1 entries in the following table
+	 */
+	.long (2f-1f)/16
+1:
+	/*
+	 * TLB0		4K	Non-cacheable, guarded
+	 * 0xff700000	4K	Initial CCSRBAR mapping
+	 *
+	 * This ends up at a TLB0 Index==0 entry, and must not collide
+	 * with other TLB0 Entries.
+	 */
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB0		16K	Cacheable, guarded
+	 * Temporary Global data for initialization
+	 *
+	 * Use four 4K TLB0 entries.  These entries must be cacheable
+	 * as they provide the bootstrap memory before the memory
+	 * controler and real memory have been configured.
+	 *
+	 * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
+	 * and must not collide with other TLB0 entries.
+	 */
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
+			0,0,0,0,0,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
+			0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
+			0,0,0,0,0,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
+			0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
+			0,0,0,0,0,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
+			0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
+			0,0,0,0,0,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
+			0,0,0,0,0,1,0,1,0,1)
+
+
+	/*
+	 * TLB 0:	64M	Non-cacheable, guarded
+	 * 0xfc000000	64M	Covers FLASH at 0xFE800000 and 0xFF800000
+	 * Out of reset this entry is only 4K.
+	 */
+	.long TLB1_MAS0(1, 0, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_BOOT_BLOCK), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_BOOT_BLOCK), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 1:	1G	Non-cacheable, guarded
+	 * 0x80000000	1G	PCIE  8,9,a,b
+	 */
+	.long TLB1_MAS0(1, 1, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCIE_PHYS),
+		0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCIE_PHYS),
+		0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 2:	256M	Non-cacheable, guarded
+	 */
+	.long TLB1_MAS0(1, 2, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI_PHYS),
+			0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI_PHYS),	0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 3:	256M	Non-cacheable, guarded
+	 */
+	.long TLB1_MAS0(1, 3, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI_PHYS + 0x10000000),
+			0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI_PHYS + 0x10000000),
+			0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 4:	64M	Non-cacheable, guarded
+	 * 0xe000_0000	1M	CCSRBAR
+	 * 0xe100_0000	255M	PCI IO range
+	 */
+	.long TLB1_MAS0(1, 4, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
+
+#ifdef CFG_LBC_CACHE_BASE
+	/*
+	 * TLB 5:	64M	Cacheable, non-guarded
+	 */
+	.long TLB1_MAS0(1, 5, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_CACHE_BASE), 0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_CACHE_BASE), 0,0,0,0,0,1,0,1,0,1)
+#endif
+	/*
+	 * TLB 6:	64M	Non-cacheable, guarded
+	 * 0xf8000000	64M	PIXIS 0xF8000000 - 0xFBFFFFFF
+	 */
+	.long TLB1_MAS0(1, 6, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_NONCACHE_BASE), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_NONCACHE_BASE), 0,0,0,0,0,1,0,1,0,1)
+2:
+	entry_end
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ *
+ * Notes:
+ *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ *
+ * LAW 0 is reserved for boot mapping
+ */
+
+	.section .bootpg, "ax"
+	.globl	law_entry
+law_entry:
+	entry_start
+
+	.long (4f-3f)/8
+3:
+	.long	0
+	.long	(LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN
+
+	.long	(CFG_PCI1_MEM_BASE>>12) & 0xfffff
+	.long	LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
+
+	.long	(CFG_PCI1_IO_PHYS>>12) & 0xfffff
+	.long	LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M)
+
+	.long	(CFG_LBC_CACHE_BASE>>12) & 0xfffff
+	.long	LAWAR_EN | LAWAR_TRGT_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)
+
+	.long	(CFG_PCIE1_MEM_PHYS>>12) & 0xfffff
+	.long	LAWAR_EN | LAWAR_TRGT_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_256M)
+
+	/* To keep to 10 LAWs, PCIE1_IO_PHYS must use top of mem region  */
+
+	.long	(CFG_PCIE2_MEM_PHYS>>12) & 0xfffff
+	.long	LAWAR_EN | LAWAR_TRGT_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_512M)
+
+	.long	(CFG_PCIE2_IO_PHYS>>12) & 0xfffff
+	.long	LAWAR_EN | LAWAR_TRGT_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_16M)
+
+	.long	(CFG_PCIE3_MEM_PHYS>>12) & 0xfffff
+	.long	LAWAR_EN | LAWAR_TRGT_PCIE3 | (LAWAR_SIZE & LAWAR_SIZE_256M)
+
+	.long	(CFG_PCIE3_IO_PHYS>>12) & 0xfffff
+	.long	LAWAR_EN | LAWAR_TRGT_PCIE3 | (LAWAR_SIZE & LAWAR_SIZE_16M)
+4:
+	entry_end

board/freescale/mpc8544ds/mpc8544ds.c

@@ -0,0 +1,201 @@
+/*
+ * Copyright 2007 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <spd.h>
+#include <miiphy.h>
+
+#include "../common/pixis.h"
+
+#if defined(CONFIG_OF_FLAT_TREE)
+#include <ft_build.h>
+extern void ft_cpu_setup(void *blob, bd_t *bd);
+#endif
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+extern void ddr_enable_ecc(unsigned int dram_size);
+#endif
+
+extern long int spd_sdram(void);
+
+void sdram_init(void);
+
+int board_early_init_f (void)
+{
+	return 0;
+}
+
+int checkboard (void)
+{
+	volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
+	volatile ccsr_gur_t *gur = &immap->im_gur;
+
+	if ((uint)&gur->porpllsr != 0xe00e0000) {
+		printf("immap size error %x\n",&gur->porpllsr);
+	}
+	printf ("Board: MPC8544DS\n");
+
+	return 0;
+}
+
+long int
+initdram(int board_type)
+{
+	long dram_size = 0;
+
+	puts("Initializing\n");
+
+	dram_size = spd_sdram();
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+	/*
+	 * Initialize and enable DDR ECC.
+	 */
+	ddr_enable_ecc(dram_size);
+#endif
+	puts("    DDR: ");
+	return dram_size;
+}
+
+#if defined(CFG_DRAM_TEST)
+int
+testdram(void)
+{
+	uint *pstart = (uint *) CFG_MEMTEST_START;
+	uint *pend = (uint *) CFG_MEMTEST_END;
+	uint *p;
+
+	printf("Testing DRAM from 0x%08x to 0x%08x\n",
+	       CFG_MEMTEST_START,
+	       CFG_MEMTEST_END);
+
+	printf("DRAM test phase 1:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0xaaaaaaaa;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0xaaaaaaaa) {
+			printf ("DRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("DRAM test phase 2:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0x55555555;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0x55555555) {
+			printf ("DRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("DRAM test passed.\n");
+	return 0;
+}
+#endif
+
+int last_stage_init(void)
+{
+	return 0;
+}
+
+
+unsigned long
+get_board_sys_clk(ulong dummy)
+{
+	u8 i, go_bit, rd_clks;
+	ulong val = 0;
+
+	go_bit = in8(PIXIS_BASE + PIXIS_VCTL);
+	go_bit &= 0x01;
+
+	rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0);
+	rd_clks &= 0x1C;
+
+	/*
+	 * Only if both go bit and the SCLK bit in VCFGEN0 are set
+	 * should we be using the AUX register. Remember, we also set the
+	 * GO bit to boot from the alternate bank on the on-board flash
+	 */
+
+	if (go_bit) {
+		if (rd_clks == 0x1c)
+			i = in8(PIXIS_BASE + PIXIS_AUX);
+		else
+			i = in8(PIXIS_BASE + PIXIS_SPD);
+	} else {
+		i = in8(PIXIS_BASE + PIXIS_SPD);
+	}
+
+	i &= 0x07;
+
+	switch (i) {
+	case 0:
+		val = 33333333;
+		break;
+	case 1:
+		val = 40000000;
+		break;
+	case 2:
+		val = 50000000;
+		break;
+	case 3:
+		val = 66666666;
+		break;
+	case 4:
+		val = 83000000;
+		break;
+	case 5:
+		val = 100000000;
+		break;
+	case 6:
+		val = 133333333;
+		break;
+	case 7:
+		val = 166666666;
+		break;
+	}
+
+	return val;
+}
+
+#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_board_setup(void *blob, bd_t *bd)
+{
+	u32 *p;
+	int len;
+
+	ft_cpu_setup(blob, bd);
+
+	p = ft_get_prop(blob, "/memory/reg", &len);
+	if (p != NULL) {
+		*p++ = cpu_to_be32(bd->bi_memstart);
+		*p = cpu_to_be32(bd->bi_memsize);
+	}
+}
+#endif

board/freescale/mpc8544ds/u-boot.lds

@@ -0,0 +1,148 @@
+/*
+ * Copyright 2007 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  .bootpg 0xFFFFF000 :
+  {
+    cpu/mpc85xx/start.o	(.bootpg)
+    board/freescale/mpc8544ds/init.o (.bootpg)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc85xx/start.o	(.text)
+    board/freescale/mpc8544ds/init.o (.text)
+    cpu/mpc85xx/traps.o (.text)
+    cpu/mpc85xx/interrupts.o (.text)
+    cpu/mpc85xx/cpu_init.o (.text)
+    cpu/mpc85xx/cpu.o (.text)
+    cpu/mpc85xx/speed.o (.text)
+    common/dlmalloc.o (.text)
+    lib_generic/crc32.o (.text)
+    lib_ppc/extable.o (.text)
+    lib_generic/zlib.o (.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+   }
+    _etext = .;
+    PROVIDE (etext = .);
+    .rodata    :
+   {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}

board/ixdp425/config.mk

@@ -1,4 +1,2 @@
+#
 TEXT_BASE = 0x00f80000
-
-# include NPE ethernet driver
-BOARDLIBS = $(obj)cpu/ixp/npe/libnpe.a

board/mpc8540ads/init.S

@@ -260,8 +260,8 @@ tlb1_entry:
 #define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
 #define LAWAR2	(LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
 
-#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff)
-#define LAWAR3	(LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M))
+#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
+#define LAWAR3	(LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_1M))
 
 /*
  * Rapid IO at 0xc000_0000 for 512 M

board/mpc8560ads/init.S

@@ -260,8 +260,8 @@ tlb1_entry:
 #define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
 #define LAWAR2	(LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
 
-#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff)
-#define LAWAR3	(LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M))
+#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
+#define LAWAR3	(LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_1M))
 
 /*
  * Rapid IO at 0xc000_0000 for 512 M

board/mpc8568mds/Makefile

@@ -0,0 +1,58 @@
+#
+# Copyright 2004-2007 Freescale Semiconductor.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= $(BOARD).o \
+	bcsr.o \
+	ft_board.o
+
+SOBJS	:= init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

board/mpc8568mds/bcsr.c

@@ -0,0 +1,49 @@
+/*
+ * Copyright 2007 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include "bcsr.h"
+
+void enable_8568mds_duart()
+{
+	volatile uint* duart_mux	= (uint *)(CFG_CCSRBAR + 0xe0060);
+	volatile uint* devices		= (uint *)(CFG_CCSRBAR + 0xe0070);
+	volatile u8 *bcsr		= (u8 *)(CFG_BCSR);
+
+	*duart_mux = 0x80000000;	/* Set the mux to Duart on PMUXCR */
+	*devices  = 0;			/* Enable all peripheral devices */
+	bcsr[5] |= 0x01;		/* Enable Duart in BCSR*/
+}
+
+void enable_8568mds_flash_write()
+{
+	volatile u8 *bcsr = (u8 *)(CFG_BCSR);
+
+	bcsr[9] |= 0x01;
+}
+
+void disable_8568mds_flash_write()
+{
+	volatile u8 *bcsr = (u8 *)(CFG_BCSR);
+
+	bcsr[9] &= ~(0x01);
+}

board/mpc8568mds/bcsr.h

@@ -0,0 +1,99 @@
+/*
+ * Copyright 2007 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __BCSR_H_
+#define __BCSR_H_
+
+#include <common.h>
+
+/* BCSR Bit definitions
+	* BCSR 0 *
+	0:3	ccb sys pll
+	4:6	cfg core pll
+	7	cfg boot seq
+
+	* BCSR 1 *
+	0:2 	cfg rom lock
+	3:5 	cfg host agent
+	6	PCI IO
+	7	cfg RIO size
+
+	* BCSR 2 *
+	0:4	QE PLL
+	5	QE clock
+	6	cfg PCI arbiter
+
+	* BCSR 3 *
+	0	TSEC1 reduce
+	1	TSEC2 reduce
+	2:3	TSEC1 protocol
+	4:5 	TSEC2 protocol
+	6	PHY1 slave
+	7	PHY2 slave
+
+	* BCSR 4 *
+	4	clock enable
+	5	boot EPROM
+	6	GETH transactive reset
+	7	BRD write potect
+
+	* BCSR 5 *
+	1:3	Leds 1-3
+	4	UPC1 enable
+	5	UPC2 enable
+	6	UPC2 pos
+	7	RS232 enable
+
+	* BCSR 6 *
+	0	CFG ver 0
+	1	CFG ver 1
+	6	Register config led
+	7	Power on reset
+
+	* BCSR 7 *
+	2 	board host mode indication
+	5 	enable TSEC1 PHY
+	6 	enable TSEC2 PHY
+
+	* BCSR 8 *
+	0	UCC GETH1 enable
+	1	UCC GMII enable
+	3	UCC TBI enable
+	5	UCC MII enable
+	7	Real time clock reset
+
+	* BCSR 9 *
+	0	UCC2 GETH enable
+	1	UCC2 GMII enable
+	3	UCC2 TBI enable
+	5	UCC2 MII enable
+	6	Ready only - indicate flash ready after burning
+	7	Flash write protect
+*/
+
+/*BCSR Utils functions*/
+
+void enable_8568mds_duart(void);
+void enable_8568mds_flash_write(void);
+void disable_8568mds_flash_write(void);
+
+#endif	/* __BCSR_H_ */

board/mpc8568mds/config.mk

@@ -0,0 +1,30 @@
+#
+# Copyright 2007 Freescale Semiconductor.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# mpc8568mds board
+#
+TEXT_BASE = 0xfff80000
+
+PLATFORM_CPPFLAGS += -DCONFIG_E500=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC8568=1

board/mpc8568mds/ft_board.c

@@ -0,0 +1,45 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#include <ft_build.h>
+
+extern void ft_cpu_setup(void *blob, bd_t *bd);
+
+#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_board_setup(void *blob, bd_t *bd)
+{
+	u32 *p;
+	int len;
+#ifdef CONFIG_PCI
+	ft_pci_setup(blob, bd);
+#endif
+	ft_cpu_setup(blob, bd);
+	p = ft_get_prop(blob, "/memory/reg", &len);
+	if (p != NULL) {
+		*p++ = cpu_to_be32(bd->bi_memstart);
+		*p = cpu_to_be32(bd->bi_memsize);
+	}
+}
+#endif /* CONFIG_OF_FLAT_TREE && CONFIG_OF_BOARD_SETUP */

board/mpc8568mds/init.S

@@ -0,0 +1,258 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor.
+ * Copyright 2002,2003, Motorola Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <config.h>
+#include <mpc85xx.h>
+
+
+/*
+ * TLB0 and TLB1 Entries
+ *
+ * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
+ * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
+ * these TLB entries are established.
+ *
+ * The TLB entries for DDR are dynamically setup in spd_sdram()
+ * and use TLB1 Entries 8 through 15 as needed according to the
+ * size of DDR memory.
+ *
+ * MAS0: tlbsel, esel, nv
+ * MAS1: valid, iprot, tid, ts, tsize
+ * MAS2: epn, sharen, x0, x1, w, i, m, g, e
+ * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
+ */
+#define	entry_start \
+	mflr	r1	;	\
+	bl	0f	;
+
+#define	entry_end \
+0:	mflr	r0	;	\
+	mtlr	r1	;	\
+	blr		;
+
+
+	.section	.bootpg, "ax"
+	.globl	tlb1_entry
+tlb1_entry:
+	entry_start
+
+	/*
+	 * Number of TLB0 and TLB1 entries in the following table
+	 */
+	.long (2f-1f)/16
+
+1:
+#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
+	/*
+	 * TLB0		4K	Non-cacheable, guarded
+	 * 0xff700000	4K	Initial CCSRBAR mapping
+	 *
+	 * This ends up at a TLB0 Index==0 entry, and must not collide
+	 * with other TLB0 Entries.
+	 */
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
+#else
+#error("Update the number of table entries in tlb1_entry")
+#endif
+
+	/*
+	 * TLB0		16K	Cacheable, non-guarded
+	 * 0xd001_0000	16K	Temporary Global data for initialization
+	 *
+	 * Use four 4K TLB0 entries.  These entries must be cacheable
+	 * as they provide the bootstrap memory before the memory
+	 * controler and real memory have been configured.
+	 *
+	 * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
+	 * and must not collide with other TLB0 entries.
+	 */
+
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR), 0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR), 0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
+			0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
+			0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
+			0,0,0,0,0,1,0,1,0,1)
+
+	/* TLB 1 Initializations */
+	/*
+	 * TLBe 0:	16M	Non-cacheable, guarded
+	 * 0xff000000	16M	FLASH (upper half)
+	 * Out of reset this entry is only 4K.
+	 */
+	.long TLB1_MAS0(1, 0, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE + 0x1000000),
+			0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE + 0x1000000),
+			0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLBe 1:	16M	Non-cacheable, guarded
+	 * 0xfe000000	16M	FLASH (lower half)
+	 */
+	.long TLB1_MAS0(1, 1, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLBe 2:	256M	Non-cacheable, guarded
+	 * 0x80000000	256M	PCI1 MEM
+	 */
+	.long TLB1_MAS0(1, 2, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLBe 3:	256M	Non-cacheable, guarded
+	 * 0xa0000000	256M	PCIe Mem
+	 */
+	.long TLB1_MAS0(1, 3, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_PEX_MEM_BASE), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_PEX_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLBe 4:	Reserved for future usage
+	 */
+
+	/*
+	 * TLBe 5:	64M	Non-cacheable, guarded
+	 * 0xe000_0000	1M	CCSRBAR
+	 * 0xe200_0000	8M	PCI1 IO
+	 * 0xe280_0000	8M	PCIe IO
+	 */
+	.long TLB1_MAS0(1, 5, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLBe 6:	64M	Cacheable, non-guarded
+	 * 0xf000_0000	64M	LBC SDRAM
+	 */
+	.long TLB1_MAS0(1, 6, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLBe 7:	256K	Non-cacheable, guarded
+	 * 0xf8000000	32K BCSR
+	 * 0xf8008000	32K PIB (CS4)
+	 * 0xf8010000	32K PIB (CS5)
+	 */
+	.long TLB1_MAS0(1, 7, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256K)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_BCSR_BASE), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_BCSR_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+2:
+	entry_end
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ *0)   0x0000_0000   0x7fff_ffff     DDR                     2G
+ *1)   0x8000_0000   0x9fff_ffff     PCI1 MEM                256MB
+ *2)   0xa000_0000   0xbfff_ffff     PCIe MEM                256MB
+ *5)   0xc000_0000   0xdfff_ffff     SRIO                    256MB
+ *-)   0xe000_0000   0xe00f_ffff     CCSR                    1M
+ *3)   0xe200_0000   0xe27f_ffff     PCI1 I/O                8M
+ *4)   0xe280_0000   0xe2ff_ffff     PCIe I/0                8M
+ *6.a) 0xf000_0000   0xf3ff_ffff     SDRAM                   64MB
+ *6.b) 0xf800_0000   0xf800_7fff     BCSR                    32KB
+ *6.c) 0xf800_8000   0xf800_ffff     PIB (CS4)		     32KB
+ *6.d) 0xf801_0000   0xf801_7fff     PIB (CS5)		     32KB
+ *6.e) 0xfe00_0000   0xffff_ffff     Flash                   32MB
+ *
+ *Notes:
+ *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ *
+ * The defines below are 1-off of the actual LAWAR0 usage.
+ * So LAWAR3 define uses the LAWAR4 register in the ECM.
+ */
+
+#define LAWBAR0 0
+#define LAWAR0  ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
+
+#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
+#define LAWAR1	(LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_256M))
+
+#define LAWBAR2 ((CFG_PEX_MEM_BASE>>12) & 0xfffff)
+#define LAWAR2	(LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_256M))
+
+#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
+#define LAWAR3	(LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_8M))
+
+#define LAWBAR4 ((CFG_PEX_IO_PHYS>>12) & 0xfffff)
+#define LAWAR4  (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_16M))
+
+
+#define LAWBAR5 ((CFG_SRIO_MEM_BASE>>12) & 0xfffff)
+#define LAWAR5	(LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_256M))
+
+/* LBC window - maps 256M.  That's SDRAM, BCSR, PIBs, and Flash */
+#define LAWBAR6 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
+#define LAWAR6	(LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
+
+	.section .bootpg, "ax"
+	.globl	law_entry
+
+law_entry:
+	entry_start
+	.long (4f-3f)/8
+3:
+	.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
+	.long LAWBAR4,LAWAR4,LAWBAR5,LAWAR5,LAWBAR6,LAWAR6
+4:
+	entry_end

board/mpc8568mds/mpc8568mds.c

@@ -0,0 +1,288 @@
+/*
+ * Copyright 2007 Freescale Semiconductor.
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <spd.h>
+
+#include "bcsr.h"
+
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+extern void ddr_enable_ecc(unsigned int dram_size);
+#endif
+
+extern long int spd_sdram(void);
+
+void local_bus_init(void);
+void sdram_init(void);
+
+int board_early_init_f (void)
+{
+	/*
+	 * Initialize local bus.
+	 */
+	local_bus_init ();
+
+	enable_8568mds_duart();
+	enable_8568mds_flash_write();
+
+	return 0;
+}
+
+int checkboard (void)
+{
+	printf ("Board: 8568 MDS\n");
+
+	return 0;
+}
+
+long int
+initdram(int board_type)
+{
+	long dram_size = 0;
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+
+	puts("Initializing\n");
+
+#if defined(CONFIG_DDR_DLL)
+	{
+		/*
+		 * Work around to stabilize DDR DLL MSYNC_IN.
+		 * Errata DDR9 seems to have been fixed.
+		 * This is now the workaround for Errata DDR11:
+		 *    Override DLL = 1, Course Adj = 1, Tap Select = 0
+		 */
+
+		volatile ccsr_gur_t *gur= &immap->im_gur;
+
+		gur->ddrdllcr = 0x81000000;
+		asm("sync;isync;msync");
+		udelay(200);
+	}
+#endif
+	dram_size = spd_sdram();
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+	/*
+	 * Initialize and enable DDR ECC.
+	 */
+	ddr_enable_ecc(dram_size);
+#endif
+	/*
+	 * SDRAM Initialization
+	 */
+	sdram_init();
+
+	puts("    DDR: ");
+	return dram_size;
+}
+
+/*
+ * Initialize Local Bus
+ */
+void
+local_bus_init(void)
+{
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile ccsr_gur_t *gur = &immap->im_gur;
+	volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+
+	uint clkdiv;
+	uint lbc_hz;
+	sys_info_t sysinfo;
+
+	get_sys_info(&sysinfo);
+	clkdiv = (lbc->lcrr & 0x0f) * 2;
+	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
+
+	gur->lbiuiplldcr1 = 0x00078080;
+	if (clkdiv == 16) {
+		gur->lbiuiplldcr0 = 0x7c0f1bf0;
+	} else if (clkdiv == 8) {
+		gur->lbiuiplldcr0 = 0x6c0f1bf0;
+	} else if (clkdiv == 4) {
+		gur->lbiuiplldcr0 = 0x5c0f1bf0;
+	}
+
+	lbc->lcrr |= 0x00030000;
+
+	asm("sync;isync;msync");
+}
+
+/*
+ * Initialize SDRAM memory on the Local Bus.
+ */
+void
+sdram_init(void)
+{
+#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
+
+	uint idx;
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+	uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
+	uint lsdmr_common;
+
+	puts("    SDRAM: ");
+
+	print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
+
+	/*
+	 * Setup SDRAM Base and Option Registers
+	 */
+	lbc->or2 = CFG_OR2_PRELIM;
+	asm("msync");
+
+	lbc->br2 = CFG_BR2_PRELIM;
+	asm("msync");
+
+	lbc->lbcr = CFG_LBC_LBCR;
+	asm("msync");
+
+
+	lbc->lsrt = CFG_LBC_LSRT;
+	lbc->mrtpr = CFG_LBC_MRTPR;
+	asm("msync");
+
+	/*
+	 * MPC8568 uses "new" 15-16 style addressing.
+	 */
+	lsdmr_common = CFG_LBC_LSDMR_COMMON;
+	lsdmr_common |= CFG_LBC_LSDMR_BSMA1516;
+
+	/*
+	 * Issue PRECHARGE ALL command.
+	 */
+	lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL;
+	asm("sync;msync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(100);
+
+	/*
+	 * Issue 8 AUTO REFRESH commands.
+	 */
+	for (idx = 0; idx < 8; idx++) {
+		lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH;
+		asm("sync;msync");
+		*sdram_addr = 0xff;
+		ppcDcbf((unsigned long) sdram_addr);
+		udelay(100);
+	}
+
+	/*
+	 * Issue 8 MODE-set command.
+	 */
+	lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW;
+	asm("sync;msync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(100);
+
+	/*
+	 * Issue NORMAL OP command.
+	 */
+	lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL;
+	asm("sync;msync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(200);    /* Overkill. Must wait > 200 bus cycles */
+
+#endif	/* enable SDRAM init */
+}
+
+#if defined(CFG_DRAM_TEST)
+int
+testdram(void)
+{
+	uint *pstart = (uint *) CFG_MEMTEST_START;
+	uint *pend = (uint *) CFG_MEMTEST_END;
+	uint *p;
+
+	printf("Testing DRAM from 0x%08x to 0x%08x\n",
+	       CFG_MEMTEST_START,
+	       CFG_MEMTEST_END);
+
+	printf("DRAM test phase 1:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0xaaaaaaaa;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0xaaaaaaaa) {
+			printf ("DRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("DRAM test phase 2:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0x55555555;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0x55555555) {
+			printf ("DRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("DRAM test passed.\n");
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_PCI)
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_mpc8568mds_config_table[] = {
+	{
+	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+	 pci_cfgfunc_config_device,
+	 {PCI_ENET0_IOADDR,
+	  PCI_ENET0_MEMADDR,
+	  PCI_COMMON_MEMORY | PCI_COMMAND_MASTER}
+	 },
+	{}
+};
+#endif
+
+static struct pci_controller hose[] = {
+#ifndef CONFIG_PCI_PNP
+	{ config_table: pci_mpc8568mds_config_table,},
+#endif
+#ifdef CONFIG_MPC85XX_PCI2
+	{},
+#endif
+};
+
+#endif	/* CONFIG_PCI */
+
+void
+pci_init_board(void)
+{
+#ifdef CONFIG_PCI
+	pci_mpc85xx_init(&hose);
+#endif
+}

board/mpc8568mds/u-boot.lds

@@ -0,0 +1,152 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+
+SECTIONS
+{
+ /* ELIOR - From RAM:  From FLASH: 0xFFFFFFFC*/
+  .resetvec 0xFFFFFFFC:
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  /*(ELIOR - From RAM:  From FLASH: 0xFFFFF000*/
+  .bootpg 0xFFFFF000:
+  {
+	cpu/mpc85xx/start.o	(.bootpg)
+	board/mpc8568mds/init.o (.bootpg)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc85xx/start.o	(.text)
+    board/mpc8568mds/init.o (.text)
+    cpu/mpc85xx/traps.o (.text)
+    cpu/mpc85xx/interrupts.o (.text)
+    cpu/mpc85xx/cpu_init.o (.text)
+    cpu/mpc85xx/cpu.o (.text)
+    cpu/mpc85xx/speed.o (.text)
+    cpu/mpc85xx/pci.o (.text)
+    common/dlmalloc.o (.text)
+    lib_generic/crc32.o (.text)
+    lib_ppc/extable.o (.text)
+    lib_generic/zlib.o (.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+   }
+    _etext = .;
+    PROVIDE (etext = .);
+    .rodata    :
+   {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}

board/mpc8641hpcn/init.S

@@ -59,7 +59,7 @@
 #define LAWAR2	(LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
 
 #define LAWBAR3 ((CFG_PCI2_MEM_BASE>>12) & 0xffffff)
-#define LAWAR3	(~LAWAR_EN & (LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)))
+#define LAWAR3	(LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M))
 
 /*
  * This is not so much the SDRAM map as it is the whole localbus map.
@@ -67,11 +67,11 @@
 #define LAWBAR4 ((0xf8100000>>12) & 0xffffff)
 #define LAWAR4	(LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_2M))
 
-#define LAWBAR5 ((CFG_PCI1_IO_BASE>>12) & 0xffffff)
+#define LAWBAR5 ((CFG_PCI1_IO_PHYS>>12) & 0xffffff)
 #define LAWAR5	(LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M))
 
-#define LAWBAR6 ((CFG_PCI2_IO_BASE>>12) & 0xffffff)
-#define LAWAR6	(~LAWAR_EN &( LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M)))
+#define LAWBAR6 ((CFG_PCI2_IO_PHYS>>12) & 0xffffff)
+#define LAWAR6	(LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M))
 
 #define LAWBAR7 ((0xfe000000 >>12) & 0xffffff)
 #define LAWAR7	(LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_32M))
@@ -84,7 +84,7 @@
 #define LAWAR8  ((LAWAR_TRGT_IF_DDR2 | (LAWAR_SIZE & LAWAR_SIZE_512M)) & ~LAWAR_EN)
 #endif
 
-#define LAWBAR9 ((CFG_RIO_MEM_BASE>>12) & 0xfffff)
+#define LAWBAR9 ((CFG_RIO_MEM_PHYS>>12) & 0xfffff)
 #define LAWAR9  (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
 
 	.section .bootpg, "ax"

board/prodrive/pdnb3/config.mk

@@ -1,4 +1,2 @@
+#
 TEXT_BASE = 0x01f00000
-
-# include NPE ethernet driver
-BOARDLIBS = $(obj)cpu/ixp/npe/libnpe.a

board/stxssa/Makefile

@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= $(BOARD).o
+SOBJS	:= init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

board/stxssa/config.mk

@@ -0,0 +1,34 @@
+# Modified by Xianghua Xiao, X.Xiao@motorola.com
+# (C) Copyright 2002,2003 Motorola Inc.
+#
+# Copied from ADS85xx for STx GP3 - Dan Malek
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# default CCARBAR is at 0xff700000
+# assume U-Boot is less than 0.5MB
+# U-Boot is less than 256K, so push
+# it further up into the flash
+#
+TEXT_BASE = 0xfffC0000
+
+PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
+PLATFORM_CPPFLAGS += -DCONFIG_E500=1

board/stxssa/init.S

@@ -0,0 +1,256 @@
+/*
+ * Copyright (C) 2005 Embedded Alley Solutions, Inc.
+ * Dan Malek <dan@embeddedalley.com>
+ * Copied from STx GP3.
+ * Updates for Silicon Tx GP3 SSA.  We only support 32-bit flash
+ * and DDR with SPD EEPROM configuration.
+ *
+ * Copyright 2004 Freescale Semiconductor.
+ * Copyright (C) 2002,2003, Motorola Inc.
+ * Xianghua Xiao <X.Xiao@motorola.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <config.h>
+#include <mpc85xx.h>
+
+
+/*
+ * TLB0 and TLB1 Entries
+ *
+ * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
+ * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
+ * these TLB entries are established.
+ *
+ * The TLB entries for DDR are dynamically setup in spd_sdram()
+ * and use TLB1 Entries 8 through 15 as needed according to the
+ * size of DDR memory.
+ *
+ * MAS0: tlbsel, esel, nv
+ * MAS1: valid, iprot, tid, ts, tsize
+ * MAS2: epn, sharen, x0, x1, w, i, m, g, e
+ * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
+ */
+
+#define	entry_start \
+	mflr	r1 	;	\
+	bl	0f 	;
+
+#define	entry_end \
+0:	mflr	r0	;	\
+	mtlr	r1	;	\
+	blr		;
+
+
+	.section	.bootpg, "ax"
+	.globl	tlb1_entry
+tlb1_entry:
+	entry_start
+
+	/*
+	 * Number of TLB0 and TLB1 entries in the following table
+	 */
+	.long 12
+
+#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
+	/*
+	 * TLB0		4K	Non-cacheable, guarded
+	 * 0xff700000	4K	Initial CCSRBAR mapping
+	 *
+	 * This ends up at a TLB0 Index==0 entry, and must not collide
+	 * with other TLB0 Entries.
+	 */
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
+#else
+#error("Update the number of table entries in tlb1_entry")
+#endif
+
+	/*
+	 * TLB0		16K	Cacheable, non-guarded
+	 * 0xd001_0000	16K	Temporary Global data for initialization
+	 *
+	 * Use four 4K TLB0 entries.  These entries must be cacheable
+	 * as they provide the bootstrap memory before the memory
+	 * controler and real memory have been configured.
+	 *
+	 * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
+	 * and must not collide with other TLB0 entries.
+	 */
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR), \
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR), \
+			0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024), \
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024), \
+			0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024), \
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024), \
+			0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024), \
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024), \
+			0,0,0,0,0,1,0,1,0,1)
+
+
+	/*
+	 * TLB 0:	64M	Non-cacheable, guarded
+	 * 0xfc000000	6M4	FLASH
+	 * Out of reset this entry is only 4K.
+	 */
+	.long TLB1_MAS0(1, 0, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 1:	256M	Non-cacheable, guarded
+	 * 0x80000000	256M	PCI1 MEM First half
+	 */
+	.long TLB1_MAS0(1, 1, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 2:	256M	Non-cacheable, guarded
+	 * 0x90000000	256M	PCI1 MEM Second half
+	 */
+	.long TLB1_MAS0(1, 2, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000), \
+			0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000), \
+			0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 3:	256M	Non-cacheable, guarded
+	 * 0xa0000000	256M	PCI2 MEM First half
+	 */
+	.long TLB1_MAS0(1, 3, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 4:	256M	Non-cacheable, guarded
+	 * 0xb0000000	256M	PCI2 MEM Second half
+	 */
+	.long TLB1_MAS0(1, 4, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE + 0x10000000), \
+			0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE + 0x10000000), \
+			0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 5:	64M	Non-cacheable, guarded
+	 * 0xe000_0000	1M	CCSRBAR
+	 * 0xe200_0000	16M	PCI1 IO
+	 * 0xe300_0000	16M	PCI2 IO
+	 */
+	.long TLB1_MAS0(1, 5, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 6:	256M	Non-cacheable, guarded
+	 * 0xf0000000		Local bus expansion option.
+	 * 0xfb000000		Configuration Latch register (one word)
+	 * 0xfc000000		Up to 64M flash
+	 */
+	.long TLB1_MAS0(1, 7, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_OPTION_BASE), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_OPTION_BASE), 0,0,0,0,0,1,0,1,0,1)
+	entry_end
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000     0x7fff_ffff     DDR                     2G
+ * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
+ * 0xa000_0000     0xbfff_ffff     PCI2 MEM                512M
+ * 0xe000_0000     0xe000_ffff     CCSR                    1M
+ * 0xe200_0000     0xe2ff_ffff     PCI1 IO                 16M
+ * 0xe300_0000     0xe3ff_ffff     PCI2 IO                 16M
+ * 0xf000_0000     0xfaff_ffff     Local bus               128M
+ * 0xfb00_0000     0xfb00_ffff     Config Latch            64K
+ * 0xfc00_0000     0xffff_ffff     FLASH (boot bank)       64M
+ *
+ * Notes:
+ *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+#if !defined(CONFIG_SPD_EEPROM)
+#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
+#define LAWAR0	(LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M))
+#else
+#define LAWBAR0 0
+#define LAWAR0  ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
+#endif
+
+#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
+#define LAWAR1 	(LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
+#define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff)
+#define LAWAR2 	(LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
+#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
+#define LAWAR3 	(LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M))
+
+#define LAWBAR4 ((CFG_PCI2_IO_PHYS>>12) & 0xfffff)
+#define LAWAR4 	(LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M))
+
+/* Map the whole localbus, including flash and reset latch.
+*/
+#define LAWBAR5 ((CFG_LBC_OPTION_BASE>>12) & 0xfffff)
+#define LAWAR5	(LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
+
+
+	.section .bootpg, "ax"
+	.globl	law_entry
+law_entry:
+	entry_start
+	.long 6
+	.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
+	.long LAWBAR4,LAWAR4,LAWBAR5,LAWAR5
+	entry_end

board/stxssa/stxssa.c

@@ -0,0 +1,398 @@
+/*
+ * (C) Copyright 2005, Embedded Alley Solutions, Inc.
+ * Dan Malek, <dan@embeddedalley.com>
+ * Copied from STx GP3.
+ * Updates for Silicon Tx GP3 SSA
+ *
+ * (C) Copyright 2003,Motorola Inc.
+ * Xianghua Xiao, (X.Xiao@motorola.com)
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+extern long int spd_sdram (void);
+
+#include <common.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <ioports.h>
+#include <asm/io.h>
+#include <spd.h>
+#include <miiphy.h>
+
+long int fixed_sdram (void);
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A configuration */
+    {   /*            conf ppar psor pdir podr pdat */
+	/* PA31 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxENB */
+	/* PA30 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 TxClav   */
+	/* PA29 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxSOC  */
+	/* PA28 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 RxENB */
+	/* PA27 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxSOC */
+	/* PA26 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxClav */
+	/* PA25 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[0] */
+	/* PA24 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[1] */
+	/* PA23 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[2] */
+	/* PA22 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[3] */
+	/* PA21 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[4] */
+	/* PA20 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[5] */
+	/* PA19 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[6] */
+	/* PA18 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[7] */
+	/* PA17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[7] */
+	/* PA16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[6] */
+	/* PA15 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[5] */
+	/* PA14 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[4] */
+	/* PA13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[3] */
+	/* PA12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[2] */
+	/* PA11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[1] */
+	/* PA10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[0] */
+	/* PA9  */ {   0,   1,   1,   1,   0,   0   }, /* FCC1 L1TXD */
+	/* PA8  */ {   0,   1,   1,   0,   0,   0   }, /* FCC1 L1RXD */
+	/* PA7  */ {   0,   0,   0,   1,   0,   0   }, /* PA7 */
+	/* PA6  */ {   0,   1,   1,   1,   0,   0   }, /* TDM A1 L1RSYNC */
+	/* PA5  */ {   0,   0,   0,   1,   0,   0   }, /* PA5 */
+	/* PA4  */ {   0,   0,   0,   1,   0,   0   }, /* PA4 */
+	/* PA3  */ {   0,   0,   0,   1,   0,   0   }, /* PA3 */
+	/* PA2  */ {   0,   0,   0,   1,   0,   0   }, /* PA2 */
+	/* PA1  */ {   1,   0,   0,   0,   0,   0   }, /* FREERUN */
+	/* PA0  */ {   0,   0,   0,   1,   0,   0   }  /* PA0 */
+    },
+
+    /* Port B configuration */
+    {   /*            conf ppar psor pdir podr pdat */
+	/* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
+	/* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
+	/* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
+	/* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
+	/* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
+	/* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
+	/* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
+	/* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
+	/* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
+	/* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
+	/* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
+	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
+	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
+	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
+	/* PB17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_DIV */
+	/* PB16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_ERR */
+	/* PB15 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_ERR */
+	/* PB14 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_EN */
+	/* PB13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:COL */
+	/* PB12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:CRS */
+	/* PB11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB9  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB8  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB7  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB6  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB5  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB4  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    },
+
+    /* Port C */
+    {   /*            conf ppar psor pdir podr pdat */
+	/* PC31 */ {   0,   0,   0,   1,   0,   0   }, /* PC31 */
+	/* PC30 */ {   0,   0,   0,   1,   0,   0   }, /* PC30 */
+	/* PC29 */ {   0,   1,   1,   0,   0,   0   }, /* SCC1 EN *CLSN */
+	/* PC28 */ {   0,   0,   0,   1,   0,   0   }, /* PC28 */
+	/* PC27 */ {   0,   0,   0,   1,   0,   0   }, /* UART Clock in */
+	/* PC26 */ {   0,   0,   0,   1,   0,   0   }, /* PC26 */
+	/* PC25 */ {   0,   0,   0,   1,   0,   0   }, /* PC25 */
+	/* PC24 */ {   0,   0,   0,   1,   0,   0   }, /* PC24 */
+	/* PC23 */ {   0,   1,   0,   1,   0,   0   }, /* ATMTFCLK */
+	/* PC22 */ {   0,   1,   0,   0,   0,   0   }, /* ATMRFCLK */
+	/* PC21 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN RXCLK */
+	/* PC20 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN TXCLK */
+	/* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK CLK13 */
+	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK14) */
+	/* PC17 */ {   0,   0,   0,   1,   0,   0   }, /* PC17 */
+	/* PC16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK16) */
+	/* PC15 */ {   0,   1,   0,   0,   0,   0   }, /* PC15 */
+	/* PC14 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN *CD */
+	/* PC13 */ {   0,   0,   0,   1,   0,   0   }, /* PC13 */
+	/* PC12 */ {   0,   1,   0,   1,   0,   0   }, /* PC12 */
+	/* PC11 */ {   0,   0,   0,   1,   0,   0   }, /* LXT971 transmit control */
+	/* PC10 */ {   0,   0,   0,   1,   0,   0   }, /* FETHMDC */
+	/* PC9  */ {   0,   0,   0,   0,   0,   0   }, /* FETHMDIO */
+	/* PC8  */ {   0,   0,   0,   1,   0,   0   }, /* PC8 */
+	/* PC7  */ {   0,   0,   0,   1,   0,   0   }, /* PC7 */
+	/* PC6  */ {   0,   0,   0,   1,   0,   0   }, /* PC6 */
+	/* PC5  */ {   0,   0,   0,   1,   0,   0   }, /* PC5 */
+	/* PC4  */ {   0,   0,   0,   1,   0,   0   }, /* PC4 */
+	/* PC3  */ {   0,   0,   0,   1,   0,   0   }, /* PC3 */
+	/* PC2  */ {   0,   0,   0,   1,   0,   1   }, /* ENET FDE */
+	/* PC1  */ {   0,   0,   0,   1,   0,   0   }, /* ENET DSQE */
+	/* PC0  */ {   0,   0,   0,   1,   0,   0   }, /* ENET LBK */
+    },
+
+    /* Port D */
+    {   /*            conf ppar psor pdir podr pdat */
+	/* PD31 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN RxD */
+	/* PD30 */ {   0,   1,   1,   1,   0,   0   }, /* SCC1 EN TxD */
+	/* PD29 */ {   0,   1,   0,   1,   0,   0   }, /* SCC1 EN TENA */
+	/* PD28 */ {   1,   1,   0,   0,   0,   0   }, /* SCC2 RxD */
+	/* PD27 */ {   1,   1,   0,   1,   0,   0   }, /* SCC2 TxD */
+	/* PD26 */ {   0,   0,   0,   1,   0,   0   }, /* PD26 */
+	/* PD25 */ {   0,   0,   0,   1,   0,   0   }, /* PD25 */
+	/* PD24 */ {   0,   0,   0,   1,   0,   0   }, /* PD24 */
+	/* PD23 */ {   0,   0,   0,   1,   0,   0   }, /* PD23 */
+	/* PD22 */ {   0,   0,   0,   1,   0,   0   }, /* PD22 */
+	/* PD21 */ {   0,   0,   0,   1,   0,   0   }, /* PD21 */
+	/* PD20 */ {   0,   0,   0,   1,   0,   0   }, /* PD20 */
+	/* PD19 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
+	/* PD18 */ {   0,   0,   0,   1,   0,   0   }, /* PD18 */
+	/* PD17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXPRTY */
+	/* PD16 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXPRTY */
+	/* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   1,   1,   1,   0,   0,   0   }, /* I2C CLK */
+	/* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
+	/* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
+	/* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
+	/* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
+	/* PD9  */ {   0,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
+	/* PD8  */ {   0,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
+	/* PD7  */ {   0,   0,   0,   1,   0,   1   }, /* PD7 */
+	/* PD6  */ {   0,   0,   0,   1,   0,   1   }, /* PD6 */
+	/* PD5  */ {   0,   0,   0,   1,   0,   1   }, /* PD5 */
+	/* PD4  */ {   0,   0,   0,   1,   0,   1   }, /* PD4 */
+	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    }
+};
+
+static	uint64_t	next_led_update;
+static	uint		led_bit;
+
+void
+reset_phy(void)
+{
+	volatile uint *blatch;
+#if 0
+	int	i;
+#endif
+	blatch = (volatile uint *)CFG_LBC_CFGLATCH_BASE;
+
+	/* reset Giga bit Ethernet port if needed here */
+
+#if 1
+	*blatch &= ~0x000000c0;
+	udelay(100);
+#else
+	*blatch = 0;
+	asm("eieio");
+	for (i=0; i<1000; i++)
+		udelay(1000);
+#endif
+	*blatch = 0x000000c1;	/* Light one led, too */
+	udelay(1000);
+
+#if 0	/* This is the port we really want to use for debugging. */
+	/* reset the CPM FEC port */
+#if (CONFIG_ETHER_INDEX == 2)
+	bcsr->bcsr2 &= ~FETH2_RST;
+	udelay(2);
+	bcsr->bcsr2 |=  FETH2_RST;
+	udelay(1000);
+#elif (CONFIG_ETHER_INDEX == 3)
+	bcsr->bcsr3 &= ~FETH3_RST;
+	udelay(2);
+	bcsr->bcsr3 |=  FETH3_RST;
+	udelay(1000);
+#endif
+#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
+	/* reset PHY */
+	miiphy_reset("FCC1 ETHERNET", 0x0);
+
+	/* change PHY address to 0x02 */
+	bb_miiphy_write(NULL, 0, PHY_MIPSCR, 0xf028);
+
+	bb_miiphy_write(NULL, 0x02, PHY_BMCR,
+			PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
+#endif /* CONFIG_MII */
+#endif
+}
+
+int
+board_early_init_f(void)
+{
+#if defined(CONFIG_PCI)
+    volatile immap_t *immr = (immap_t *)CFG_IMMR;
+    volatile ccsr_pcix_t *pci = &immr->im_pcix;
+
+    pci->peer &= 0xfffffffdf; /* disable master abort */
+#endif
+
+	/* Why is the phy reset done _after_ the ethernet
+	 * initialization in lib_ppc/board.c?
+	 * Do it here so it's done before the TSECs are used.
+	 */
+	reset_phy();
+
+	return 0;
+}
+
+int
+checkboard(void)
+{
+	printf ("Board: Silicon Tx GPPP SSA Board\n");
+	return (0);
+}
+
+/* Blinkin' LEDS for Robert.
+*/
+void
+show_activity(int flag)
+{
+	volatile uint *blatch;
+
+	if (next_led_update > get_ticks())
+		return;
+
+	blatch = (volatile uint *)CFG_LBC_CFGLATCH_BASE;
+
+	led_bit >>= 1;
+	if (led_bit == 0)
+		led_bit = 0x08;
+	*blatch = (0xc0 | led_bit);
+	eieio();
+	next_led_update += (get_tbclk() / 4);
+}
+
+long int
+initdram (int board_type)
+{
+	long dram_size = 0;
+	extern long spd_sdram (void);
+
+#if defined(CONFIG_DDR_DLL)
+	{
+		volatile immap_t *immap = (immap_t *)CFG_IMMR;
+		volatile ccsr_gur_t *gur= &immap->im_gur;
+		uint temp_ddrdll = 0;
+
+		/* Work around to stabilize DDR DLL */
+		temp_ddrdll = gur->ddrdllcr;
+		gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
+		asm("sync;isync;msync");
+	}
+#endif
+
+	dram_size = spd_sdram ();
+
+#if defined(CONFIG_DDR_ECC)
+	/* Initialize and enable DDR ECC.
+	*/
+	ddr_enable_ecc(dram_size);
+#endif
+
+	return dram_size;
+}
+
+
+#if defined(CFG_DRAM_TEST)
+int testdram (void)
+{
+	uint *pstart = (uint *) CFG_MEMTEST_START;
+	uint *pend = (uint *) CFG_MEMTEST_END;
+	uint *p;
+
+	printf("SDRAM test phase 1:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0xaaaaaaaa;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0xaaaaaaaa) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("SDRAM test phase 2:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0x55555555;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0x55555555) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("SDRAM test passed.\n");
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_PCI)
+
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_stxgp3_config_table[] = {
+    { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+      PCI_IDSEL_NUMBER, PCI_ANY_ID,
+      pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
+				   PCI_ENET0_MEMADDR,
+				   PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
+      } },
+    { }
+};
+#endif
+
+
+static struct pci_controller hose = {
+#ifndef CONFIG_PCI_PNP
+	config_table: pci_stxgp3_config_table,
+#endif
+};
+
+#endif	/* CONFIG_PCI */
+
+
+void
+pci_init_board(void)
+{
+#ifdef CONFIG_PCI
+	extern void pci_mpc85xx_init(struct pci_controller *hose);
+
+	pci_mpc85xx_init(&hose);
+#endif /* CONFIG_PCI */
+}

board/stxssa/u-boot.lds

@@ -0,0 +1,158 @@
+/*
+ * (C) Copyright 2005 Embedded Alley Solutions, Inc.
+ * Dan Malek, <dan@embeddedalley.com>
+ * Copied from STx GP3.
+ * Updates for Silicon Tx GP3 SSA.
+ *
+ * (C) Copyright 2002,2003,Motorola,Inc.
+ * Xianghua Xiao, X.Xiao@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  .bootpg 0xFFFFF000 :
+  {
+    cpu/mpc85xx/start.o	(.bootpg)
+    board/stxssa/init.o (.bootpg)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc85xx/start.o	(.text)
+    board/stxssa/init.o (.text)
+    cpu/mpc85xx/commproc.o (.text)
+    cpu/mpc85xx/traps.o (.text)
+    cpu/mpc85xx/interrupts.o (.text)
+    cpu/mpc85xx/serial_scc.o (.text)
+    cpu/mpc85xx/ether_fcc.o (.text)
+    cpu/mpc85xx/cpu_init.o (.text)
+    cpu/mpc85xx/cpu.o (.text)
+    cpu/mpc85xx/speed.o (.text)
+    cpu/mpc85xx/spd_sdram.o (.text)
+    common/dlmalloc.o (.text)
+    lib_generic/crc32.o (.text)
+    lib_ppc/extable.o (.text)
+    lib_generic/zlib.o (.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+   }
+    _etext = .;
+    PROVIDE (etext = .);
+    .rodata    :
+   {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}

common/cmd_bootm.c

@@ -779,9 +779,8 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
 
 			checksum = ntohl(hdr->ih_dcrc);
 			addr = (ulong)((uchar *)(hdr) + sizeof(image_header_t));
-			len = ntohl(hdr->ih_size);
 
-			if(checksum != crc32(0, (uchar *)addr, len)) {
+			if(checksum != crc32(0, (uchar *)addr, ntohl(hdr->ih_size))) {
 				printf("ERROR: Flat Device Tree checksum is invalid\n");
 				return;
 			}

common/cmd_nvedit.c

@@ -391,7 +391,10 @@ int _do_setenv (int flag, int argc, char *argv[])
 void setenv (char *varname, char *varvalue)
 {
 	char *argv[4] = { "setenv", varname, varvalue, NULL };
-	_do_setenv (0, 3, argv);
+	if (varvalue == NULL)
+		_do_setenv (0, 2, argv);
+	else
+		_do_setenv (0, 3, argv);
 }
 
 int do_setenv ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])

common/console.c

@@ -494,13 +494,7 @@ int console_init_r (void)
 	/* suppress all output if splash screen is enabled and we have
 	   a bmp to display                                            */
 	if (getenv("splashimage") != NULL)
-		outputdev = search_device (DEV_FLAGS_OUTPUT, "nulldev");
-#endif
-
-#ifdef CONFIG_SILENT_CONSOLE
-	/* Suppress all output if "silent" mode requested		*/
-	if (gd->flags & GD_FLG_SILENT)
-		outputdev = search_device (DEV_FLAGS_OUTPUT, "nulldev");
+		gd->flags |= GD_FLG_SILENT;
 #endif
 
 	/* Scan devices looking for input and output devices */

common/main.c

@@ -112,14 +112,6 @@ static __inline__ int abortboot(int bootdelay)
 	u_int presskey_max = 0;
 	u_int i;
 
-#ifdef CONFIG_SILENT_CONSOLE
-	if (gd->flags & GD_FLG_SILENT) {
-		/* Restore serial console */
-		console_assign (stdout, "serial");
-		console_assign (stderr, "serial");
-	}
-#endif
-
 #  ifdef CONFIG_AUTOBOOT_PROMPT
 	printf (CONFIG_AUTOBOOT_PROMPT, bootdelay);
 #  endif
@@ -199,14 +191,8 @@ static __inline__ int abortboot(int bootdelay)
 #  endif
 
 #ifdef CONFIG_SILENT_CONSOLE
-	if (abort) {
-		/* permanently enable normal console output */
-		gd->flags &= ~(GD_FLG_SILENT);
-	} else if (gd->flags & GD_FLG_SILENT) {
-		/* Restore silent console */
-		console_assign (stdout, "nulldev");
-		console_assign (stderr, "nulldev");
-	}
+	if (abort)
+		gd->flags &= ~GD_FLG_SILENT;
 #endif
 
 	return abort;
@@ -222,14 +208,6 @@ static __inline__ int abortboot(int bootdelay)
 {
 	int abort = 0;
 
-#ifdef CONFIG_SILENT_CONSOLE
-	if (gd->flags & GD_FLG_SILENT) {
-		/* Restore serial console */
-		console_assign (stdout, "serial");
-		console_assign (stderr, "serial");
-	}
-#endif
-
 #ifdef CONFIG_MENUPROMPT
 	printf(CONFIG_MENUPROMPT, bootdelay);
 #else
@@ -245,7 +223,7 @@ static __inline__ int abortboot(int bootdelay)
 		if (tstc()) {	/* we got a key press	*/
 			(void) getc();  /* consume input	*/
 			puts ("\b\b\b 0");
-			abort = 1; 	/* don't auto boot	*/
+			abort = 1;	/* don't auto boot	*/
 		}
 	}
 #endif
@@ -275,14 +253,8 @@ static __inline__ int abortboot(int bootdelay)
 	putc ('\n');
 
 #ifdef CONFIG_SILENT_CONSOLE
-	if (abort) {
-		/* permanently enable normal console output */
-		gd->flags &= ~(GD_FLG_SILENT);
-	} else if (gd->flags & GD_FLG_SILENT) {
-		/* Restore silent console */
-		console_assign (stdout, "nulldev");
-		console_assign (stderr, "nulldev");
-	}
+	if (abort)
+		gd->flags &= ~GD_FLG_SILENT;
 #endif
 
 	return abort;

cpu/ixp/npe/Makefile

@@ -87,7 +87,7 @@ START	:= $(addprefix $(obj),$(START))
 
 all:	$(LIB)
 
-$(LIB):	$(obj).depend $(OBJS)
+$(LIB):	$(OBJS)
 	$(AR) $(ARFLAGS) $@ $(OBJS)
 
 #########################################################################

cpu/mpc5xxx/cpu.c

@@ -53,12 +53,16 @@ int checkcpu (void)
 #else
 	svr = get_svr();
 	pvr = get_pvr();
-	switch (SVR_VER (svr)) {
-	case SVR_MPC5200:
-		printf ("MPC5200");
+
+	switch (pvr) {
+	case PVR_5200:
+		printf("MPC5200");
+		break;
+	case PVR_5200B:
+		printf("MPC5200B");
 		break;
 	default:
-		printf ("MPC52??  (SVR %08x)", svr);
+		printf("Unknown MPC5xxx");
 		break;
 	}
 
@@ -127,5 +131,9 @@ ft_cpu_setup(void *blob, bd_t *bd)
 	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@3000/mac-address", &len);
 	if (p != NULL)
 		memcpy(p, bd->bi_enetaddr, 6);
+
+	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@3000/local-mac-address", &len);
+	if (p != NULL)
+		memcpy(p, bd->bi_enetaddr, 6);
 }
 #endif

cpu/mpc85xx/cpu.c

@@ -1,5 +1,5 @@
 /*
- * Copyright 2004 Freescale Semiconductor.
+ * Copyright 2004,2007 Freescale Semiconductor, Inc.
  * (C) Copyright 2002, 2003 Motorola Inc.
  * Xianghua Xiao (X.Xiao@motorola.com)
  *
@@ -70,6 +70,15 @@ int checkcpu (void)
 	case SVR_8548_E:
 		puts("8548_E");
 		break;
+	case SVR_8544:
+		puts("8544");
+		break;
+	case SVR_8544_E:
+		puts("8544_E");
+		break;
+	case SVR_8568_E:
+		puts("8568_E");
+		break;
 	default:
 		puts("Unknown");
 		break;
@@ -112,7 +121,7 @@ int checkcpu (void)
 #endif
 	clkdiv = lcrr & 0x0f;
 	if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
-#ifdef CONFIG_MPC8548
+#if defined(CONFIG_MPC8548) || defined(CONFIG_MPC8544)
 		/*
 		 * Yes, the entire PQ38 family use the same
 		 * bit-representation for twice the clock divider values.
@@ -140,16 +149,25 @@ int checkcpu (void)
 
 int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
 {
+	uint pvr;
+	uint ver;
+	pvr = get_pvr();
+	ver = PVR_VER(pvr);
+	if (ver & 1){
+	/* e500 v2 core has reset control register */
+		volatile unsigned int * rstcr;
+		rstcr = (volatile unsigned int *)(CFG_IMMR + 0xE00B0);
+		*rstcr = 0x2;		/* HRESET_REQ */
+	}else{
 	/*
 	 * Initiate hard reset in debug control register DBCR0
 	 * Make sure MSR[DE] = 1
 	 */
-	unsigned long val;
-
-	val = mfspr(DBCR0);
-	val |= 0x70000000;
-	mtspr(DBCR0,val);
-
+		unsigned long val;
+		val = mfspr(DBCR0);
+		val |= 0x70000000;
+		mtspr(DBCR0,val);
+	}
 	return 1;
 }
 
@@ -183,9 +201,9 @@ reset_85xx_watchdog(void)
 	 * Clear TSR(WIS) bit by writing 1
 	 */
 	unsigned long val;
-	val = mfspr(tsr);
-	val |= 0x40000000;
-	mtspr(tsr, val);
+	val = mfspr(SPRN_TSR);
+	val |= TSR_WIS;
+	mtspr(SPRN_TSR, val);
 }
 #endif	/* CONFIG_WATCHDOG */
 
@@ -196,6 +214,7 @@ void dma_init(void) {
 
 	dma->satr0 = 0x02c40000;
 	dma->datr0 = 0x02c40000;
+	dma->sr0 = 0xfffffff; /* clear any errors */
 	asm("sync; isync; msync");
 	return;
 }
@@ -210,6 +229,10 @@ uint dma_check(void) {
 		status = dma->sr0;
 	}
 
+	/* clear MR0[CS] channel start bit */
+	dma->mr0 &= 0x00000001;
+	asm("sync;isync;msync");
+
 	if (status != 0) {
 		printf ("DMA Error: status = %x\n", status);
 	}
@@ -245,6 +268,10 @@ ft_cpu_setup(void *blob, bd_t *bd)
 	if (p != NULL)
 		*p = cpu_to_be32(clock);
 
+	p = ft_get_prop(blob, "/qe@e0080000/" OF_CPU "/bus-frequency", &len);
+	if (p != NULL)
+		*p = cpu_to_be32(clock);
+
 	p = ft_get_prop(blob, "/" OF_SOC "/serial@4500/clock-frequency", &len);
 	if (p != NULL)
 		*p = cpu_to_be32(clock);
@@ -255,21 +282,41 @@ ft_cpu_setup(void *blob, bd_t *bd)
 
 #if defined(CONFIG_MPC85XX_TSEC1)
 	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len);
+	if (p)
+		memcpy(p, bd->bi_enetaddr, 6);
+
+	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/local-mac-address", &len);
+	if (p)
 		memcpy(p, bd->bi_enetaddr, 6);
 #endif
 
 #if defined(CONFIG_HAS_ETH1)
 	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/mac-address", &len);
+	if (p)
+		memcpy(p, bd->bi_enet1addr, 6);
+
+	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/local-mac-address", &len);
+	if (p)
 		memcpy(p, bd->bi_enet1addr, 6);
 #endif
 
 #if defined(CONFIG_HAS_ETH2)
 	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/mac-address", &len);
+	if (p)
+		memcpy(p, bd->bi_enet2addr, 6);
+
+	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/local-mac-address", &len);
+	if (p)
 		memcpy(p, bd->bi_enet2addr, 6);
 #endif
 
 #if defined(CONFIG_HAS_ETH3)
 	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/mac-address", &len);
+	if (p)
+		memcpy(p, bd->bi_enet3addr, 6);
+
+	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/local-mac-address", &len);
+	if (p)
 		memcpy(p, bd->bi_enet3addr, 6);
 #endif
 

cpu/mpc85xx/cpu_init.c

@@ -143,12 +143,10 @@ void cpu_init_f (void)
 	memctl->br1 = CFG_BR1_PRELIM;
 #endif
 
-#if !defined(CONFIG_MPC85xx)
 #if defined(CFG_BR2_PRELIM) && defined(CFG_OR2_PRELIM)
 	memctl->or2 = CFG_OR2_PRELIM;
 	memctl->br2 = CFG_BR2_PRELIM;
 #endif
-#endif
 
 #if defined(CFG_BR3_PRELIM) && defined(CFG_OR3_PRELIM)
 	memctl->or3 = CFG_OR3_PRELIM;

cpu/mpc85xx/pci.c

@@ -90,14 +90,14 @@ pci_mpc85xx_init(struct pci_controller *board_hose)
 	pcix->powbar1  = (CFG_PCI1_MEM_PHYS >> 12) & 0x000fffff;
 	pcix->powbear1 = 0x00000000;
 	pcix->powar1 = (POWAR_EN | POWAR_MEM_READ |
-			POWAR_MEM_WRITE | POWAR_MEM_512M);
+			POWAR_MEM_WRITE | (__ilog2(CFG_PCI1_MEM_SIZE) - 1));
 
 	pcix->potar2  = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff;
 	pcix->potear2  = 0x00000000;
 	pcix->powbar2  = (CFG_PCI1_IO_PHYS >> 12) & 0x000fffff;
 	pcix->powbear2 = 0x00000000;
 	pcix->powar2 = (POWAR_EN | POWAR_IO_READ |
-			POWAR_IO_WRITE | POWAR_IO_1M);
+			POWAR_IO_WRITE | (__ilog2(CFG_PCI1_IO_SIZE) - 1));
 
 	pcix->pitar1 = 0x00000000;
 	pcix->piwbar1 = 0x00000000;
@@ -175,14 +175,14 @@ pci_mpc85xx_init(struct pci_controller *board_hose)
 	pcix2->powbar1  = (CFG_PCI2_MEM_PHYS >> 12) & 0x000fffff;
 	pcix2->powbear1 = 0x00000000;
 	pcix2->powar1 = (POWAR_EN | POWAR_MEM_READ |
-			POWAR_MEM_WRITE | POWAR_MEM_512M);
+			POWAR_MEM_WRITE | (__ilog2(CFG_PCI2_MEM_SIZE) - 1));
 
 	pcix2->potar2  = (CFG_PCI2_IO_BASE >> 12) & 0x000fffff;
 	pcix2->potear2  = 0x00000000;
 	pcix2->powbar2  = (CFG_PCI2_IO_PHYS >> 12) & 0x000fffff;
 	pcix2->powbear2 = 0x00000000;
 	pcix2->powar2 = (POWAR_EN | POWAR_IO_READ |
-			POWAR_IO_WRITE | POWAR_IO_1M);
+			POWAR_IO_WRITE | (__ilog2(CFG_PCI2_IO_SIZE) - 1));
 
 	pcix2->pitar1 = 0x00000000;
 	pcix2->piwbar1 = 0x00000000;

cpu/mpc85xx/spd_sdram.c

@@ -263,13 +263,14 @@ spd_sdram(void)
 	}
 
 	/*
-	 * Adjust DDR II IO voltage biasing.  It just makes it work.
+	 * Adjust DDR II IO voltage biasing.
+	 * Only 8548 rev 1 needs the fix
 	 */
-	if (spd.mem_type == SPD_MEMTYPE_DDR2) {
-		gur->ddrioovcr = (0
-				  | 0x80000000		/* Enable */
-				  | 0x10000000		/* VSEL to 1.8V */
-				  );
+	if ((SVR_VER(get_svr()) == SVR_8548_E) &&
+			(SVR_MJREV(get_svr()) == 1) &&
+			(spd.mem_type == SPD_MEMTYPE_DDR2)) {
+		gur->ddrioovcr = (0x80000000	/* Enable */
+				  | 0x10000000);/* VSEL to 1.8V */
 	}
 
 	/*
@@ -786,14 +787,17 @@ spd_sdram(void)
 	 * Is this an ECC DDR chip?
 	 * But don't mess with it if the DDR controller will init mem.
 	 */
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+#ifdef CONFIG_DDR_ECC
 	if (spd.config == 0x02) {
+#ifndef CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 		ddr->err_disable = 0x0000000d;
+#endif
 		ddr->err_sbe = 0x00ff0000;
 	}
+
 	debug("DDR: err_disable = 0x%08x\n", ddr->err_disable);
 	debug("DDR: err_sbe = 0x%08x\n", ddr->err_sbe);
-#endif
+#endif /* CONFIG_DDR_ECC */
 
 	asm("sync;isync;msync");
 	udelay(500);
@@ -991,17 +995,24 @@ setup_laws_and_tlbs(unsigned int memsize)
 		break;
 	case 256:
 	case 512:
+		tlb_size = BOOKE_PAGESZ_256M;
+		break;
 	case 1024:
 	case 2048:
-		tlb_size = BOOKE_PAGESZ_256M;
+		if (PVR_VER(get_pvr()) > PVR_VER(PVR_85xx))
+			tlb_size = BOOKE_PAGESZ_1G;
+		else
+			tlb_size = BOOKE_PAGESZ_256M;
 		break;
 	default:
 		puts("DDR: only 16M,32M,64M,128M,256M,512M,1G and 2G are supported.\n");
 
 		/*
 		 * The memory was not able to be mapped.
+		 * Default to a small size.
 		 */
-		return 0;
+		tlb_size = BOOKE_PAGESZ_64M;
+		memsize=64;
 		break;
 	}
 

cpu/mpc85xx/speed.c

@@ -37,49 +37,21 @@ void get_sys_info (sys_info_t * sysInfo)
 {
 	volatile immap_t    *immap = (immap_t *)CFG_IMMR;
 	volatile ccsr_gur_t *gur = &immap->im_gur;
-	uint plat_ratio,e500_ratio;
+	uint plat_ratio,e500_ratio,half_freqSystemBus;
 
 	plat_ratio = (gur->porpllsr) & 0x0000003e;
 	plat_ratio >>= 1;
-	switch(plat_ratio) {
-	case 0x02:
-	case 0x03:
-	case 0x04:
-	case 0x05:
-	case 0x06:
-	case 0x08:
-	case 0x09:
-	case 0x0a:
-	case 0x0c:
-	case 0x10:
-		sysInfo->freqSystemBus = plat_ratio * CONFIG_SYS_CLK_FREQ;
-		break;
-	default:
-		sysInfo->freqSystemBus = 0;
-		break;
-	}
-
+	sysInfo->freqSystemBus = plat_ratio * CONFIG_SYS_CLK_FREQ;
 	e500_ratio = (gur->porpllsr) & 0x003f0000;
 	e500_ratio >>= 16;
-	switch(e500_ratio) {
-	case 0x04:
-		sysInfo->freqProcessor = 2*sysInfo->freqSystemBus;
-		break;
-	case 0x05:
-		sysInfo->freqProcessor = 5*sysInfo->freqSystemBus/2;
-		break;
-	case 0x06:
-		sysInfo->freqProcessor = 3*sysInfo->freqSystemBus;
-		break;
-	case 0x07:
-		sysInfo->freqProcessor = 7*sysInfo->freqSystemBus/2;
-		break;
-	default:
-		sysInfo->freqProcessor = 0;
-		break;
-	}
+
+	/* Divide before multiply to avoid integer
+	 * overflow for processor speeds above 2GHz */
+	half_freqSystemBus = sysInfo->freqSystemBus/2;
+	sysInfo->freqProcessor = e500_ratio*half_freqSystemBus;
 }
 
+
 int get_clocks (void)
 {
 	sys_info_t sys_info;

cpu/mpc85xx/start.S

@@ -251,13 +251,10 @@ _start_e500:
 	 */
 	bl	tlb1_entry
 	mr	r5,r0
-	li	r1,0x0020	/* max 16 TLB1 plus some TLB0 entries */
-	mtctr	r1
 	lwzu	r4,0(r5)	/* how many TLB1 entries we actually use */
+	mtctr	r4
 
-0:	cmpwi	r4,0
-	beq	1f
-	lwzu	r0,4(r5)
+0:	lwzu	r0,4(r5)
 	lwzu	r1,4(r5)
 	lwzu	r2,4(r5)
 	lwzu	r3,4(r5)
@@ -269,7 +266,6 @@ _start_e500:
 	msync
 	tlbwe
 	isync
-	addi	r4,r4,-1
 	bdnz	0b
 
 1:
@@ -301,20 +297,16 @@ _start_e500:
 
 	bl	law_entry
 	mr	r6,r0
-	li	r1,0x0007	/* 8 LAWs, but reserve one for boot-over-rio-or-pci */
-	mtctr	r1
 	lwzu	r5,0(r6)	/* how many windows we actually use */
+	mtctr	r5
 
 	li	r2,0x0c28	/* the first pair is reserved for boot-over-rio-or-pci */
 	li	r1,0x0c30
 
-0:	cmpwi	r5,0
-	beq	1f
-	lwzu	r4,4(r6)
+0:	lwzu	r4,4(r6)
 	lwzu	r3,4(r6)
 	stwx	r4,r7,r2
 	stwx	r3,r7,r1
-	addi	r5,r5,-1
 	addi	r2,r2,0x0020
 	addi	r1,r1,0x0020
 	bdnz	0b

cpu/mpc86xx/cpu.c

@@ -280,22 +280,38 @@ ft_cpu_setup(void *blob, bd_t *bd)
 
 #if defined(CONFIG_MPC86XX_TSEC1)
 	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len);
-	memcpy(p, bd->bi_enetaddr, 6);
+	if (p != NULL)
+		memcpy(p, bd->bi_enetaddr, 6);
+	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/local-mac-address", &len);
+	if (p)
+		memcpy(p, bd->bi_enetaddr, 6);
 #endif
 
 #if defined(CONFIG_MPC86XX_TSEC2)
 	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/mac-address", &len);
-	memcpy(p, bd->bi_enet1addr, 6);
+	if (p != NULL)
+		memcpy(p, bd->bi_enet1addr, 6);
+	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/local-mac-address", &len);
+	if (p != NULL)
+		memcpy(p, bd->bi_enet1addr, 6);
 #endif
 
 #if defined(CONFIG_MPC86XX_TSEC3)
 	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/mac-address", &len);
-	memcpy(p, bd->bi_enet2addr, 6);
+	if (p != NULL)
+		memcpy(p, bd->bi_enet2addr, 6);
+	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/local-mac-address", &len);
+	if (p != NULL)
+		memcpy(p, bd->bi_enet2addr, 6);
 #endif
 
 #if defined(CONFIG_MPC86XX_TSEC4)
 	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/mac-address", &len);
-	memcpy(p, bd->bi_enet3addr, 6);
+	if (p != NULL)
+		memcpy(p, bd->bi_enet3addr, 6);
+	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/local-mac-address", &len);
+	if (p != NULL)
+		memcpy(p, bd->bi_enet3addr, 6);
 #endif
 
 }

cpu/mpc86xx/spd_sdram.c

@@ -51,20 +51,32 @@ extern int dma_xfer(void *dest, uint count, void *src);
 #define CFG_SUPER_BANK_INTERLEAVING	0
 
 /*
- * Convert picoseconds into clock cycles (rounding up if needed).
+ * Convert picoseconds into DRAM clock cycles (rounding up if needed).
  */
 
-int
-picos_to_clk(int picos)
+static unsigned int
+picos_to_clk(unsigned int picos)
 {
-	int clks;
-
-	clks = picos / (2000000000 / (get_bus_freq(0) / 1000));
-	if (picos % (2000000000 / (get_bus_freq(0) / 1000)) != 0) {
+	/* use unsigned long long to avoid rounding errors */
+	const unsigned long long ULL_2e12 = 2000000000000ULL;
+	unsigned long long clks;
+	unsigned long long clks_temp;
+
+	if (! picos)
+	    return 0;
+
+	clks = get_bus_freq(0) * (unsigned long long) picos;
+	clks_temp = clks;
+	clks = clks / ULL_2e12;
+	if (clks_temp % ULL_2e12) {
 		clks++;
 	}
 
-	return clks;
+	if (clks > 0xFFFFFFFFULL) {
+		clks = 0xFFFFFFFFULL;
+	}
+
+	return (unsigned int) clks;
 }
 
 

cpu/mpc86xx/start.S

@@ -241,26 +241,40 @@ in_flash:
 	bl	setup_ccsrbar
 #endif
 
-	/* Fix for SMP linux - Changing arbitration to round-robin */
-	lis	r3, CFG_CCSRBAR@h
-	ori	r3, r3, 0x1000
-	xor	r4, r4, r4
-	li	r4, 0x1000
-	stw	r4, 0(r3)
 
-	/* setup the law entries */
-	bl	law_entry
+	/* -- MPC8641 Rev 1.0 MCM Errata fixups -- */
+
+	/* skip fixups if not Rev 1.0 */
+	mfspr	r4, SVR
+	rlwinm	r4,r4,0,24,31
+	cmpwi	r4,0x10
+	bne	1f
+
+	lis	r3,MCM_ABCR@ha
+	lwz	r4,MCM_ABCR@l(r3)	/* ABCR -> r4 */
+
+	/* set ABCR[A_STRM_CNT] = 0 */
+	rlwinm	r4,r4,0,0,29
+
+	/* set ABCR[ARB_POLICY] to 0x1 (round-robin) */
+	addi	r0,r0,1
+	rlwimi	r4,r0,12,18,19
+
+	stw	r4,MCM_ABCR@l(r3)	/* r4 -> ABCR */
 	sync
 
-	/* Don't use this feature due to bug in 8641D PD4 */
-	/* Disable ERD_DIS */
-	lis	r3, CFG_CCSRBAR@h
-	ori	r3, r3, 0x1008
-	lwz	r4, 0(r3)
+	/* Set DBCR[ERD_DIS] */
+	lis	r3,MCM_DBCR@ha
+	lwz	r4,MCM_DBCR@l(r3)
 	oris	r4, r4, 0x4000
-	stw	r4, 0(r3)
+	stw	r4,MCM_DBCR@l(r3)
+	sync
+1:
+	/* setup the law entries */
+	bl	law_entry
 	sync
 
+
 #if (EMULATOR_RUN == 1)
 	/* On the emulator we want to adjust these ASAP */
 	/* otherwise things are sloooow */

cpu/ppc4xx/4xx_enet.c

@@ -339,29 +339,41 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
 int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
 {
 	unsigned long zmiifer=0x0;
+	unsigned long pfc1;
 
-	/*
-	 * Right now only 2*RGMII is supported. Please extend when needed.
-	 * sr - 2006-08-29
-	 */
-	switch (1) {
-	case 0:
+	mfsdr(sdr_pfc1, pfc1);
+	pfc1 &= SDR0_PFC1_SELECT_MASK;
+
+	switch (pfc1) {
+	case SDR0_PFC1_SELECT_CONFIG_2:
 		/* 1 x GMII port */
 		out32 (ZMII_FER, 0x00);
 		out32 (RGMII_FER, 0x00000037);
 		bis->bi_phymode[0] = BI_PHYMODE_GMII;
 		bis->bi_phymode[1] = BI_PHYMODE_NONE;
 		break;
-	case 1:
+	case SDR0_PFC1_SELECT_CONFIG_4:
 		/* 2 x RGMII ports */
 		out32 (ZMII_FER, 0x00);
 		out32 (RGMII_FER, 0x00000055);
 		bis->bi_phymode[0] = BI_PHYMODE_RGMII;
 		bis->bi_phymode[1] = BI_PHYMODE_RGMII;
 		break;
-	case 2:
+	case SDR0_PFC1_SELECT_CONFIG_6:
 		/* 2 x SMII ports */
-
+		out32 (ZMII_FER,
+		       ((ZMII_FER_SMII) << ZMII_FER_V(0)) |
+		       ((ZMII_FER_SMII) << ZMII_FER_V(1)));
+		out32 (RGMII_FER, 0x00000000);
+		bis->bi_phymode[0] = BI_PHYMODE_SMII;
+		bis->bi_phymode[1] = BI_PHYMODE_SMII;
+		break;
+	case SDR0_PFC1_SELECT_CONFIG_1_2:
+		/* only 1 x MII supported */
+		out32 (ZMII_FER, (ZMII_FER_MII) << ZMII_FER_V(0));
+		out32 (RGMII_FER, 0x00000000);
+		bis->bi_phymode[0] = BI_PHYMODE_MII;
+		bis->bi_phymode[1] = BI_PHYMODE_NONE;
 		break;
 	default:
 		break;

doc/README.nand

@@ -192,12 +192,7 @@ The old NAND handling code has been re-factored and is now confined
 to only board-specific files and - unfortunately - to the DoC code
 (see below). A new configuration variable has been introduced:
 CFG_NAND_LEGACY, which has to be defined in the board config file if
-that board uses legacy code. If CFG_NAND_LEGACY is defined, the board
-specific config.mk file should also have "BOARDLIBS =
-drivers/nand_legacy/libnand_legacy.a". For boards using the new NAND
-approach (PPChameleon and netstar at the moment) no variable is
-necessary, but the config.mk should have "BOARDLIBS =
-drivers/nand/libnand.a".
+that board uses legacy code.
 
 The necessary changes have been made to all affected boards, and no
 build breakage has been introduced, except for NETTA and NETTA_ISDN

drivers/nand/nand_base.c

@@ -427,8 +427,9 @@ static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
 	struct nand_chip *this = mtd->priv;
 	u16 bad;
 
+	page = (int)(ofs >> this->page_shift) & this->pagemask;
+
 	if (getchip) {
-		page = (int)(ofs >> this->page_shift);
 		chipnr = (int)(ofs >> this->chip_shift);
 
 		/* Grab the lock and see if the device is available */
@@ -436,18 +437,17 @@ static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
 
 		/* Select the NAND device */
 		this->select_chip(mtd, chipnr);
-	} else
-		page = (int) ofs;
+	}
 
 	if (this->options & NAND_BUSWIDTH_16) {
-		this->cmdfunc (mtd, NAND_CMD_READOOB, this->badblockpos & 0xFE, page & this->pagemask);
+		this->cmdfunc (mtd, NAND_CMD_READOOB, this->badblockpos & 0xFE, page);
 		bad = cpu_to_le16(this->read_word(mtd));
 		if (this->badblockpos & 0x1)
 			bad >>= 1;
 		if ((bad & 0xFF) != 0xff)
 			res = 1;
 	} else {
-		this->cmdfunc (mtd, NAND_CMD_READOOB, this->badblockpos, page & this->pagemask);
+		this->cmdfunc (mtd, NAND_CMD_READOOB, this->badblockpos, page);
 		if (this->read_byte(mtd) != 0xff)
 			res = 1;
 	}

drivers/pci_auto.c

@@ -34,7 +34,12 @@
 
 void pciauto_region_init(struct pci_region* res)
 {
-	res->bus_lower = res->bus_start;
+	/*
+	 * Avoid allocating PCI resources from address 0 -- this is illegal
+	 * according to PCI 2.1 and moreover, this is known to cause Linux IDE
+	 * drivers to fail. Use a reasonable starting value of 0x1000 instead.
+	 */
+	res->bus_lower = res->bus_start ? res->bus_start : 0x1000;
 }
 
 void pciauto_region_align(struct pci_region *res, unsigned long size)

drivers/smc91111.c

@@ -1538,9 +1538,9 @@ int eth_send(volatile void *packet, int length) {
 int smc_get_ethaddr (bd_t * bd)
 {
 	int env_size, rom_valid, env_present = 0, reg;
-	char *s = NULL, *e, *v_mac, es[] = "11:22:33:44:55:66";
+	char *s = NULL, *e, es[] = "11:22:33:44:55:66";
 	char s_env_mac[64];
-	uchar v_env_mac[6], v_rom_mac[6];
+	uchar v_env_mac[6], v_rom_mac[6], *v_mac;
 
 	env_size = getenv_r ("ethaddr", s_env_mac, sizeof (s_env_mac));
 	if ((env_size > 0) && (env_size < sizeof (es))) {	/* exit if env is bad */
@@ -1563,7 +1563,7 @@ int smc_get_ethaddr (bd_t * bd)
 
 	if (!env_present) {	/* if NO env */
 		if (rom_valid) {	/* but ROM is valid */
-			v_mac = (char *)v_rom_mac;
+			v_mac = v_rom_mac;
 			sprintf (s_env_mac, "%02X:%02X:%02X:%02X:%02X:%02X",
 				 v_mac[0], v_mac[1], v_mac[2], v_mac[3],
 				 v_mac[4], v_mac[5]);
@@ -1573,7 +1573,7 @@ int smc_get_ethaddr (bd_t * bd)
 			return (-1);
 		}
 	} else {		/* good env, don't care ROM */
-		v_mac = (char *)v_env_mac;	/* always use a good env over a ROM */
+		v_mac = v_env_mac;	/* always use a good env over a ROM */
 	}
 
 	if (env_present && rom_valid) { /* if both env and ROM are good */

drivers/tsec.c

@@ -5,7 +5,7 @@
  * terms of the GNU Public License, Version 2, incorporated
  * herein by reference.
  *
- * Copyright 2004 Freescale Semiconductor.
+ * Copyright 2004, 2007 Freescale Semiconductor, Inc.
  * (C) Copyright 2003, Motorola, Inc.
  * author Andy Fleming
  *
@@ -66,7 +66,11 @@ struct tsec_info_struct {
  */
 static struct tsec_info_struct tsec_info[] = {
 #if defined(CONFIG_MPC85XX_TSEC1) || defined(CONFIG_MPC83XX_TSEC1)
+#if defined(CONFIG_MPC8544DS)
+	{TSEC1_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC1_PHYIDX},
+#else
 	{TSEC1_PHY_ADDR, TSEC_GIGABIT, TSEC1_PHYIDX},
+#endif
 #elif defined(CONFIG_MPC86XX_TSEC1)
 	{TSEC1_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC1_PHYIDX},
 #else
@@ -381,6 +385,76 @@ uint mii_parse_sr(uint mii_reg, struct tsec_private * priv)
 	return 0;
 }
 
+/* Generic function which updates the speed and duplex.  If
+ * autonegotiation is enabled, it uses the AND of the link
+ * partner's advertised capabilities and our advertised
+ * capabilities.  If autonegotiation is disabled, we use the
+ * appropriate bits in the control register.
+ *
+ * Stolen from Linux's mii.c and phy_device.c
+ */
+uint mii_parse_link(uint mii_reg, struct tsec_private *priv)
+{
+	/* We're using autonegotiation */
+	if (mii_reg & PHY_BMSR_AUTN_ABLE) {
+		uint lpa = 0;
+		uint gblpa = 0;
+
+		/* Check for gigabit capability */
+		if (mii_reg & PHY_BMSR_EXT) {
+			/* We want a list of states supported by
+			 * both PHYs in the link
+			 */
+			gblpa = read_phy_reg(priv, PHY_1000BTSR);
+			gblpa &= read_phy_reg(priv, PHY_1000BTCR) << 2;
+		}
+
+		/* Set the baseline so we only have to set them
+		 * if they're different
+		 */
+		priv->speed = 10;
+		priv->duplexity = 0;
+
+		/* Check the gigabit fields */
+		if (gblpa & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) {
+			priv->speed = 1000;
+
+			if (gblpa & PHY_1000BTSR_1000FD)
+				priv->duplexity = 1;
+
+			/* We're done! */
+			return 0;
+		}
+
+		lpa = read_phy_reg(priv, PHY_ANAR);
+		lpa &= read_phy_reg(priv, PHY_ANLPAR);
+
+		if (lpa & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX)) {
+			priv->speed = 100;
+
+			if (lpa & PHY_ANLPAR_TXFD)
+				priv->duplexity = 1;
+
+		} else if (lpa & PHY_ANLPAR_10FD)
+			priv->duplexity = 1;
+	} else {
+		uint bmcr = read_phy_reg(priv, PHY_BMCR);
+
+		priv->speed = 10;
+		priv->duplexity = 0;
+
+		if (bmcr & PHY_BMCR_DPLX)
+			priv->duplexity = 1;
+
+		if (bmcr & PHY_BMCR_1000_MBPS)
+			priv->speed = 1000;
+		else if (bmcr & PHY_BMCR_100_MBPS)
+			priv->speed = 100;
+	}
+
+	return 0;
+}
+
 /*
  * Parse the BCM54xx status register for speed and duplex information.
  * The linux sungem_phy has this information, but in a table format.
@@ -718,6 +792,7 @@ static void startup_tsec(struct eth_device *dev)
 	/* Start up the PHY */
 	if(priv->phyinfo)
 		phy_run_commands(priv, priv->phyinfo->startup);
+
 	adjust_link(dev);
 
 	/* Enable Transmit and Receive */
@@ -1088,6 +1163,27 @@ struct phy_info phy_info_dm9161 = {
 			   {miim_end,}
 			   },
 };
+/* a generic flavor.  */
+struct phy_info phy_info_generic =  {
+	0,
+	"Unknown/Generic PHY",
+	32,
+	(struct phy_cmd[]) { /* config */
+		{PHY_BMCR, PHY_BMCR_RESET, NULL},
+		{PHY_BMCR, PHY_BMCR_AUTON|PHY_BMCR_RST_NEG, NULL},
+		{miim_end,}
+	},
+	(struct phy_cmd[]) { /* startup */
+		{PHY_BMSR, miim_read, NULL},
+		{PHY_BMSR, miim_read, &mii_parse_sr},
+		{PHY_BMSR, miim_read, &mii_parse_link},
+		{miim_end,}
+	},
+	(struct phy_cmd[]) { /* shutdown */
+		{miim_end,}
+	}
+};
+
 
 uint mii_parse_lxt971_sr2(uint mii_reg, struct tsec_private *priv)
 {
@@ -1203,6 +1299,7 @@ struct phy_info *phy_info[] = {
 	&phy_info_lxt971,
 	&phy_info_VSC8244,
 	&phy_info_dp83865,
+	&phy_info_generic,
 	NULL
 };
 

drivers/tsec.h

@@ -7,7 +7,7 @@
  *  terms of the GNU Public License, Version 2, incorporated
  *  herein by reference.
  *
- * Copyright 2004 Freescale Semiconductor.
+ * Copyright 2004, 2007 Freescale Semiconductor, Inc.
  * (C) Copyright 2003, Motorola, Inc.
  * maintained by Xianghua Xiao (x.xiao@motorola.com)
  * author Andy Fleming
@@ -65,6 +65,7 @@
 #define ECNTRL_INIT_SETTINGS	0x00001000
 #define ECNTRL_TBI_MODE         0x00000020
 #define ECNTRL_R100		0x00000008
+#define ECNTRL_SGMII_MODE	0x00000002
 
 #define miim_end -2
 #define miim_read -1

include/asm-ppc/mmu.h

@@ -396,8 +396,8 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower);
 #define BOOKE_PAGESZ_16M        7
 #define BOOKE_PAGESZ_64M        8
 #define BOOKE_PAGESZ_256M       9
-#define BOOKE_PAGESZ_1GB        10
-#define BOOKE_PAGESZ_4GB        11
+#define BOOKE_PAGESZ_1G		10
+#define BOOKE_PAGESZ_4G		11
 
 #if defined(CONFIG_MPC86xx)
 #define LAWBAR_BASE_ADDR	0x00FFFFFF
@@ -413,6 +413,7 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower);
 #define LAWAR_TRGT_IF_PCI1	0x00000000
 #define LAWAR_TRGT_IF_PCIX	0x00000000
 #define LAWAR_TRGT_IF_PCI2	0x00100000
+#define LAWAR_TRGT_IF_PEX	0x00200000
 #define LAWAR_TRGT_IF_LBC	0x00400000
 #define LAWAR_TRGT_IF_CCSR	0x00800000
 #define LAWAR_TRGT_IF_DDR_INTERLEAVED 0x00B00000

include/asm-ppc/processor.h

@@ -232,6 +232,9 @@
 #define   HID0_BHTE	(1<<2)		/* Branch History Table Enable */
 #define   HID0_BTCD	(1<<1)		/* Branch target cache disable */
 #define SPRN_HID1	0x3F1	/* Hardware Implementation Register 1 */
+#define	  HID1_RFXE	(1<<17)		/* Read Fault Exception Enable */
+#define	  HID1_ASTME	(1<<13)		/* Address bus streaming mode */
+#define	  HID1_ABE	(1<<12)		/* Address broadcast enable */
 #define SPRN_IABR	0x3F2	/* Instruction Address Breakpoint Register */
 #ifndef CONFIG_BOOKE
 #define SPRN_IAC1	0x3F4	/* Instruction Address Compare 1 */
@@ -415,10 +418,12 @@
 #define SPRN_IVOR15	0x19f	/* Interrupt Vector Offset Register 15 */
 
 /* e500 definitions */
-#define SPRN_L1CSR0     0x3f2   /* L1 Cache Control and Status Register 0 */
+#define SPRN_L1CSR0     0x3f2   /* L1 Data Cache Control and Status Register 0 */
+#define   L1CSR0_CPE            0x00010000	/* Data Cache Parity Enable */
 #define   L1CSR0_DCFI           0x00000002      /* Data Cache Flash Invalidate */
 #define   L1CSR0_DCE            0x00000001      /* Data Cache Enable */
-#define SPRN_L1CSR1     0x3f3   /* L1 Cache Control and Status Register 1 */
+#define SPRN_L1CSR1     0x3f3   /* L1 Instruction Cache Control and Status Register 1 */
+#define   L1CSR1_CPE            0x00010000	/* Instruction Cache Parity Enable */
 #define   L1CSR1_ICFI           0x00000002      /* Instruction Cache Flash Invalidate */
 #define   L1CSR1_ICE            0x00000001      /* Instruction Cache Enable */
 
@@ -701,8 +706,6 @@
 #define SVR_MJREV(svr)	(((svr) >>  4) & 0x0F)   /* Major SOC design revision indicator */
 #define SVR_MNREV(svr)	(((svr) >>  0) & 0x0F)   /* Minor SOC design revision indicator */
 
-/* System-On-Chip Version Numbers (version field only) */
-#define SVR_MPC5200	0x8011
 
 /* Processor Version Register */
 
@@ -813,6 +816,12 @@
 #define PVR_8260_HIP7R1 0x80822013
 #define PVR_8260_HIP7RA	0x80822014
 
+/*
+ * MPC 52xx
+ */
+#define PVR_5200	0x80822011
+#define PVR_5200B	0x80822014
+
 
 /*
  * System Version Register
@@ -840,9 +849,12 @@
 #define SVR_8560	0x8070
 #define SVR_8555	0x8079
 #define SVR_8541	0x807A
+#define SVR_8544	0x8034
+#define SVR_8544_E	0x803C
 #define SVR_8548	0x8031
 #define SVR_8548_E	0x8039
 #define SVR_8641	0x8090
+#define SVR_8568_E	0x807D
 
 
 /* I am just adding a single entry for 8260 boards.  I think we may be

include/configs/MPC8540ADS.h

@@ -330,13 +330,12 @@
 
 /*
  * General PCI
- * Addresses are mapped 1-1.
+ * Memory space is mapped 1-1, but I/O space must start from 0.
  */
 #define CFG_PCI1_MEM_BASE	0x80000000
 #define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
 #define CFG_PCI1_MEM_SIZE	0x20000000	/* 512M */
-
-#define CFG_PCI1_IO_BASE	0x0
+#define CFG_PCI1_IO_BASE	0x00000000
 #define CFG_PCI1_IO_PHYS	0xe2000000
 #define CFG_PCI1_IO_SIZE	0x100000	/* 1M */
 

include/configs/MPC8541CDS.h

@@ -334,7 +334,7 @@ extern unsigned long get_clock_freq(void);
 
 /*
  * General PCI
- * Addresses are mapped 1-1.
+ * Memory space is mapped 1-1, but I/O space must start from 0.
  */
 #define CFG_PCI1_MEM_BASE	0x80000000
 #define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE

include/configs/MPC8544DS.h

@@ -0,0 +1,591 @@
+/*
+ * Copyright 2007 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * mpc8544ds board configuration file
+ *
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE		1	/* BOOKE */
+#define CONFIG_E500		1	/* BOOKE e500 family */
+#define CONFIG_MPC85xx		1	/* MPC8540/60/55/41/48 */
+#define CONFIG_MPC8544		1
+#define CONFIG_MPC8544DS	1
+
+#undef CONFIG_PCI			/* Enable PCI/PCIE */
+#undef CONFIG_PCI1			/* PCI controller 1 */
+#undef CONFIG_PCIE1			/* PCIE controler 1 (slot 1) */
+#undef CONFIG_PCIE2			/* PCIE controler 2 (slot 2) */
+#undef CONFIG_PCIE3			/* PCIE controler 3 (ULI bridge) */
+#undef CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
+
+#define CONFIG_TSEC_ENET 		/* tsec ethernet support */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
+#undef CONFIG_DDR_DLL
+#define CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
+
+#define CONFIG_DDR_ECC			/* only for ECC DDR module */
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
+#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
+
+#define CONFIG_DDR_ECC_CMD
+
+/*
+ * When initializing flash, if we cannot find the manufacturer ID,
+ * assume this is the AMD flash associated with the CDS board.
+ * This allows booting from a promjet.
+ */
+#define CONFIG_ASSUME_AMD_FLASH
+
+#define MPC85xx_DDR_SDRAM_CLK_CNTL	/* 85xx has clock control reg */
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_board_sys_clk(unsigned long dummy);
+#endif
+#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0) /* sysclk for MPC85xx */
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE			/* toggle L2 cache 	*/
+#define CONFIG_BTB			/* toggle branch predition */
+#define CONFIG_ADDR_STREAMING		/* toggle addr streaming */
+#define CONFIG_CLEAR_LAW0		/* Clear LAW0 in cpu_init_r */
+
+/*
+ * Only possible on E500 Version 2 or newer cores.
+ */
+#define CONFIG_ENABLE_36BIT_PHYS	1
+
+#define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */
+
+#undef	CFG_DRAM_TEST			/* memory test, takes time */
+#define CFG_MEMTEST_START	0x00200000	/* memtest works on */
+#define CFG_MEMTEST_END		0x00400000
+#define CFG_ALT_MEMTEST
+#define CONFIG_PANIC_HANG 	/* do not reset board on panic */
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default */
+#define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
+#define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
+
+#define CFG_PCI1_ADDR		(CFG_CCSRBAR+0x8000)
+#define CFG_PCIE1_ADDR		(CFG_CCSRBAR+0xa000)
+#define CFG_PCIE2_ADDR		(CFG_CCSRBAR+0x9000)
+#define CFG_PCIE3_ADDR		(CFG_CCSRBAR+0xb000)
+
+/*
+ * DDR Setup
+ */
+#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
+#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
+
+#define SPD_EEPROM_ADDRESS	0x51		/* DDR DIMM */
+
+/*
+ * Make sure required options are set
+ */
+#ifndef CONFIG_SPD_EEPROM
+#error ("CONFIG_SPD_EEPROM is required")
+#endif
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+/*
+ * Memory map
+ *
+ * 0x0000_0000	0x7fff_ffff	DDR			2G Cacheable
+ *
+ * 0x8000_0000	0xbfff_ffff	PCI Express Mem		1G non-cacheable
+ *
+ * 0xc000_0000	0xdfff_ffff	PCI			512M non-cacheable
+ *
+ * 0xe000_0000	0xe00f_ffff	CCSR			1M non-cacheable
+ * 0xe100_0000	0xe3ff_ffff	PCI IO range		4M non-cacheable
+ *
+ * Localbus cacheable
+ *
+ * 0xf000_0000	0xf3ff_ffff	SDRAM			64M Cacheable
+ * 0xf401_0000	0xf401_3fff	L1 for stack		4K Cacheable TLB0
+ *
+ * Localbus non-cacheable
+ *
+ * 0xf800_0000	0xf80f_ffff	NVRAM/CADMUS (*)	1M non-cacheable
+ * 0xff00_0000	0xff7f_ffff	FLASH (2nd bank)	8M non-cacheable
+ * 0xff80_0000	0xffff_ffff	FLASH (boot bank)	8M non-cacheable
+ *
+ */
+
+/*
+ * Local Bus Definitions
+ */
+#define CFG_BOOT_BLOCK		0xfc000000	/* boot TLB */
+
+#define CFG_LBC_CACHE_BASE	0xf0000000	/* Localbus cacheable */
+
+#define CFG_FLASH_BASE		0xff800000	/* start of FLASH 8M */
+
+#define CFG_BR0_PRELIM		0xff801001
+#define CFG_BR1_PRELIM		0xfe801001
+
+#define CFG_OR0_PRELIM		0xff806e65
+#define CFG_OR1_PRELIM		0xff806e65
+
+#define CFG_FLASH_BANKS_LIST	{0xfe800000,CFG_FLASH_BASE}
+
+#define CFG_MAX_FLASH_BANKS	2		/* number of banks */
+#define CFG_MAX_FLASH_SECT	128		/* sectors per device */
+#undef	CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT	60000		/* Flash Erase Timeout (ms) */
+#define CFG_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */
+
+#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor */
+
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_FLASH_CFI
+#define CFG_FLASH_EMPTY_INFO
+
+#define CFG_LBC_NONCACHE_BASE	0xf8000000
+
+#define CFG_BR2_PRELIM		0xf8201001	/* port size 16bit */
+#define CFG_OR2_PRELIM		0xfff06ff7	/* 1MB Compact Flash area*/
+
+#define CFG_BR3_PRELIM		0xf8100801	/* port size 8bit */
+#define CFG_OR3_PRELIM		0xfff06ff7	/* 1MB PIXIS area*/
+
+#define PIXIS_BASE	0xf8100000	/* PIXIS registers */
+#define PIXIS_ID		0x0	/* Board ID at offset 0 */
+#define PIXIS_VER		0x1	/* Board version at offset 1 */
+#define PIXIS_PVER		0x2	/* PIXIS FPGA version at offset 2 */
+#define PIXIS_RST		0x4	/* PIXIS Reset Control register */
+#define PIXIS_AUX		0x6	/* PIXIS Auxiliary register; Scratch
+					 * register */
+#define PIXIS_SPD		0x7	/* Register for SYSCLK speed */
+#define PIXIS_VCTL		0x10	/* VELA Control Register */
+#define PIXIS_VCFGEN0		0x12	/* VELA Config Enable 0 */
+#define PIXIS_VCFGEN1		0x13	/* VELA Config Enable 1 */
+#define PIXIS_VBOOT		0x16	/* VELA VBOOT Register */
+#define PIXIS_VSPEED0		0x17	/* VELA VSpeed 0 */
+#define PIXIS_VSPEED1		0x18	/* VELA VSpeed 1 */
+#define PIXIS_VCLKH		0x19	/* VELA VCLKH register */
+#define PIXIS_VCLKL		0x1A	/* VELA VCLKL register */
+
+
+/* define to use L1 as initial stack */
+#define CONFIG_L1_INIT_RAM	1
+#define CFG_INIT_L1_LOCK	1
+#define CFG_INIT_L1_ADDR	0xf4010000	/* Initial L1 address */
+#define CFG_INIT_L1_END		0x00004000	/* End of used area in RAM */
+
+/* define to use L2SRAM as initial stack */
+#undef CONFIG_L2_INIT_RAM
+#define CFG_INIT_L2_ADDR	0xf8fc0000
+#define CFG_INIT_L2_END		0x00040000	/* End of used area in RAM */
+
+#ifdef CONFIG_L1_INIT_RAM
+#define CFG_INIT_RAM_ADDR	CFG_INIT_L1_ADDR
+#define CFG_INIT_RAM_END	CFG_INIT_L1_END
+#else
+#define CFG_INIT_RAM_ADDR	CFG_INIT_L2_ADDR
+#define CFG_INIT_RAM_END	CFG_INIT_L2_END
+#endif
+
+#define CFG_GBL_DATA_SIZE	128	/* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserved for malloc */
+
+/* Serial Port - controlled on board with jumper J8
+ * open - index 2
+ * shorted - index 1
+ */
+#define CONFIG_CONS_INDEX	1
+#undef	CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE	1
+#define CFG_NS16550_CLK		get_bus_freq(0)
+
+#define CFG_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CFG_NS16550_COM1	(CFG_CCSRBAR+0x4500)
+#define CFG_NS16550_COM2	(CFG_CCSRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CFG_HUSH_PARSER
+#ifdef	CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_FLAT_TREE	1
+#define CONFIG_OF_BOARD_SETUP	1
+
+/* maximum size of the flat tree (8K) */
+#define OF_FLAT_TREE_MAX_SIZE	8192
+
+#define OF_CPU			"PowerPC,8544@0"
+#define OF_SOC			"soc8544@e0000000"
+#define OF_TBCLK		(bd->bi_busfreq / 8)
+#define OF_STDOUT_PATH		"/soc8544@e0000000/serial@4500"
+
+/* I2C */
+#define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C		/* I2C with hardware support */
+#undef	CONFIG_SOFT_I2C		/* I2C bit-banged */
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CFG_I2C_EEPROM_ADDR	0x57
+#define CFG_I2C_SLAVE		0x7F
+#define CFG_I2C_NOPROBES	{0x69}	/* Don't probe these addrs */
+#define CFG_I2C_OFFSET		0x3100
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+#define CFG_PCIE_PHYS		0x80000000	/* 1G PCIE TLB */
+#define CFG_PCI_PHYS		0xc0000000	/* 512M PCI TLB */
+
+#define CFG_PCI1_MEM_BASE	0xc0000000
+#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
+#define CFG_PCI1_MEM_SIZE	0x20000000	/* 512M */
+#define CFG_PCI1_IO_BASE	0x00000000
+#define CFG_PCI1_IO_PHYS	0xe1000000
+#define CFG_PCI1_IO_SIZE	0x00100000	/* 1M */
+
+/* PCI view of System Memory */
+#define CFG_PCI_MEMORY_BUS	0x00000000
+#define CFG_PCI_MEMORY_PHYS	0x00000000
+#define CFG_PCI_MEMORY_SIZE	0x80000000
+
+/* controller 2, Slot 1, tgtid 1, Base address 9000 */
+#define CFG_PCIE2_MEM_BASE	0x80000000
+#define CFG_PCIE2_MEM_PHYS	CFG_PCIE2_MEM_BASE
+#define CFG_PCIE2_MEM_SIZE	0x20000000	/* 512M */
+#define CFG_PCIE2_IO_BASE	0x00000000
+#define CFG_PCIE2_IO_PHYS	0xe2000000
+#define CFG_PCIE2_IO_SIZE	0x00100000	/* 1M */
+
+/* controller 1, Slot 2,tgtid 2, Base address a000 */
+#define CFG_PCIE1_MEM_BASE	0xa0000000
+#define CFG_PCIE1_MEM_PHYS	CFG_PCIE1_MEM_BASE
+#define CFG_PCIE1_MEM_SIZE	0x08000000	/* 128M */
+#define CFG_PCIE1_MEM_BASE2	0xa8000000
+#define CFG_PCIE1_MEM_PHYS2	CFG_PCIE1_MEM_BASE2
+#define CFG_PCIE1_MEM_SIZE2	0x04000000	/* 64M */
+#define CFG_PCIE1_IO_BASE	0x00000000	/* reuse mem LAW */
+#define CFG_PCIE1_IO_PHYS	0xaf000000
+#define CFG_PCIE1_IO_SIZE	0x00100000	/* 1M */
+
+/* controller 3, direct to uli, tgtid 3, Base address b000 */
+#define CFG_PCIE3_MEM_BASE	0xb0000000
+#define CFG_PCIE3_MEM_PHYS	CFG_PCIE3_MEM_BASE
+#define CFG_PCIE3_MEM_SIZE	0x10000000	/* 256M */
+#define CFG_PCIE3_IO_BASE	0x00000000
+#define CFG_PCIE3_IO_PHYS	0xe3000000
+#define CFG_PCIE3_IO_SIZE	0x00100000	/* 1M */
+
+#if defined(CONFIG_PCI)
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+#define CONFIG_RTL8139
+
+#ifdef CONFIG_RTL8139
+/* This macro is used by RTL8139 but not defined in PPC architecture */
+#define KSEG1ADDR(x)		(x)
+#define _IO_BASE	0x00000000
+#endif
+
+#ifndef CONFIG_PCI_PNP
+	#define PCI_ENET0_IOADDR	CFG_PCI1_IO_BASE
+	#define PCI_ENET0_MEMADDR	CFG_PCI1_IO_BASE
+	#define PCI_IDSEL_NUMBER	0x11	/* IDSEL = AD11 */
+#endif
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SCSI_AHCI
+
+#ifdef CONFIG_SCSI_AHCI
+#define CONFIG_SATA_ULI5288
+#define CFG_SCSI_MAX_SCSI_ID	4
+#define CFG_SCSI_MAX_LUN	1
+#define CFG_SCSI_MAX_DEVICE 	(CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN)
+#define CFG_SCSI_MAXDEVICE	CFG_SCSI_MAX_DEVICE
+#endif /* SCSCI */
+
+#endif	/* CONFIG_PCI */
+
+
+#if defined(CONFIG_TSEC_ENET)
+
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI 	1
+#endif
+
+#define CONFIG_MII		1	/* MII PHY management */
+#define CONFIG_MII_DEFAULT_TSEC	1	/* Allow unregistered phys */
+#define CONFIG_MPC85XX_TSEC1	1
+#define CONFIG_MPC85XX_TSEC1_NAME	"eTSEC1"
+#define CONFIG_MPC85XX_TSEC3	1
+#define CONFIG_MPC85XX_TSEC3_NAME	"eTSEC3"
+#undef CONFIG_MPC85XX_FEC
+
+#define TSEC1_PHY_ADDR		0
+#define TSEC3_PHY_ADDR		1
+
+#define TSEC1_PHYIDX		0
+#define TSEC3_PHYIDX		0
+
+#define CONFIG_ETHPRIME		"eTSEC1"
+
+#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
+
+#endif	/* CONFIG_TSEC_ENET */
+
+/*
+ * Environment
+ */
+#define CFG_ENV_IS_IN_FLASH	1
+#if CFG_MONITOR_BASE > 0xfff80000
+#define CFG_ENV_ADDR		0xfff80000
+#else
+#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
+#endif
+#define CFG_ENV_SIZE		0x2000
+#define CFG_ENV_SECT_SIZE	0x10000 /* 64K (one sector) */
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+#if defined(CONFIG_PCI)
+#define	CONFIG_COMMANDS	(CONFIG_CMD_DFL \
+				| CFG_CMD_PCI \
+				| CFG_CMD_PING \
+				| CFG_CMD_I2C \
+				| CFG_CMD_MII \
+				| CFG_CMD_BEDBUG \
+				| CFG_CMD_NET)
+#else
+#define	CONFIG_COMMANDS	(CONFIG_CMD_DFL \
+				| CFG_CMD_PING \
+				| CFG_CMD_I2C \
+				| CFG_CMD_MII)
+#endif
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory	*/
+#define CFG_LOAD_ADDR	0x2000000	/* default load address */
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args */
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
+#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ	(8 << 20) 	/* Initial Memory map for Linux*/
+
+/* Cache Configuration */
+#define CFG_DCACHE_SIZE	32768
+#define CFG_CACHELINE_SIZE	32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/*log base 2 of the above value*/
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02		/* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+/* The mac addresses for all ethernet interface */
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_ETHADDR	00:E0:0C:02:00:FD
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR	00:E0:0C:02:01:FD
+#define CONFIG_HAS_ETH2
+#define CONFIG_ETH2ADDR	00:E0:0C:02:02:FD
+#define CONFIG_HAS_ETH3
+#define CONFIG_ETH3ADDR	00:E0:0C:02:03:FD
+#endif
+
+#define CONFIG_IPADDR	192.168.1.251
+
+#define CONFIG_HOSTNAME	8544ds_unknown
+#define CONFIG_ROOTPATH	/nfs/mpc85xx
+#define CONFIG_BOOTFILE	8544ds_tmt/uImage.uboot
+
+#define CONFIG_SERVERIP	192.168.0.1
+#define CONFIG_GATEWAYIP 192.168.0.1
+#define CONFIG_NETMASK	255.255.0.0
+
+#define CONFIG_LOADADDR	1000000	/*default location for tftp and bootm*/
+
+#define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
+#undef	CONFIG_BOOTARGS	/* the boot command will set bootargs*/
+
+#define CONFIG_BAUDRATE	115200
+
+#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || defined(CONFIG_PCIE3)
+#define PCIE_ENV \
+ "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \
+	"echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \
+ "pcie1regs=setenv a e000a; run pciereg\0"	\
+ "pcie2regs=setenv a e0009; run pciereg\0"	\
+ "pcie3regs=setenv a e000b; run pciereg\0"	\
+ "pcieerr=md ${a}020 1; md ${a}e00;"		\
+	"pci d.b $b.0 7 1; pci d.w $b.0 1e 1;"	\
+	"pci d.w $b.0 56 1;"			\
+	"pci d $b.0 104 1;pci d $b.0 110 1;pci d $b.0 130 1\0" \
+ "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff;"	\
+	"pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff;" \
+	"pci w $b.0 104 ffffffff; pci w $b.0 110 ffffffff;" \
+	"pci w $b.0 130 ffffffff\0" \
+ "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0"	\
+ "pcie1err=setenv a e000a; run pcieerr\0"	\
+ "pcie2err=setenv a e0009; run pcieerr\0"	\
+ "pcie3err=setenv a e000b; run pcieerr\0"	\
+ "pcie1errc=setenv a e000a; run pcieerrc\0"	\
+ "pcie2errc=setenv a e0009; run pcieerrc\0"	\
+ "pcie3errc=setenv a e000b; run pcieerrc\0"
+#else
+#define	PCIE_ENV ""
+#endif
+
+#if defined(CONFIG_PCI1)
+#define PCI_ENV \
+ "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \
+	"echo e;md ${a}e00 9\0" 		\
+ "pci1regs=setenv a e0008; run pcireg\0"	\
+ "pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \
+	"pci d.w $b.0 56 1\0"			\
+ "pcierrc=mw ${a}e00 ffffffff; pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff;" \
+	"pci w.w $b.0 56 ffff\0"		\
+ "pci1err=setenv a e0008; run pcierr\0"		\
+ "pci1errc=setenv a e0008; run pcierrc\0"
+#else
+#define	PCI_ENV ""
+#endif
+
+#if defined(CONFIG_TSEC_ENET)
+#define ENET_ENV \
+ "enetreg1=md ${a}000 2; md ${a}010 9; md ${a}050 4; md ${a}08c 1;" \
+	"md ${a}098 2\0" \
+ "enetregt=echo t;md ${a}100 6; md ${a}140 2; md ${a}180 10; md ${a}200 10\0" \
+ "enetregr=echo r;md ${a}300 6; md ${a}330 5; md ${a}380 10; md ${a}400 10\0" \
+ "enetregm=echo mac;md ${a}500 5; md ${a}520 28;echo fifo;md ${a}a00 1;" \
+	"echo mib;md ${a}680 31\0" \
+ "enetreg=run enetreg1; run enetregm; run enetregt; run enetregr\0" \
+ "enet1regs=setenv a e0024; run enetreg\0" \
+ "enet3regs=setenv a e0026; run enetreg\0"
+#else
+#define ENET_ENV ""
+#endif
+
+#define	CONFIG_EXTRA_ENV_SETTINGS		\
+ "netdev=eth0\0"				\
+ "consoledev=ttyS0\0"				\
+ "ramdiskaddr=2000000\0"			\
+ "ramdiskfile=8544ds_tmt/ramdisk.uboot\0"	\
+ "fdtaddr=400000\0"				\
+ "fdtfile=8544ds_tmt/mpc8544ds.dtb\0"		\
+ "eoi=mw e00400b0 0\0" 				\
+ "iack=md e00400a0 1\0" 			\
+ "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4; md ${a}bf0 4;" \
+	"md ${a}e00 3; md ${a}e20 3; md ${a}e40 7; md ${a}f00 5\0" \
+ "ddrregs=setenv a e0002; run ddrreg\0" 	\
+ "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}b20 3;" \
+	"md ${a}e00 1; md ${a}e60 1; md ${a}ef0 15\0" 	\
+ "guregs=setenv a e00e0; run gureg\0" 		\
+ "ecmreg=md ${a}000 1; md ${a}010 1; md ${a}bf8 2; md ${a}e00 6\0" \
+ "ecmregs=setenv a e0001; run ecmreg\0" 	\
+ PCIE_ENV 	\
+ PCI_ENV 	\
+ ENET_ENV
+
+
+#define CONFIG_NFSBOOTCOMMAND		\
+ "setenv bootargs root=/dev/nfs rw "	\
+ "nfsroot=$serverip:$rootpath "		\
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;"	\
+ "tftp $loadaddr $bootfile;"		\
+ "tftp $fdtaddr $fdtfile;"		\
+ "bootm $loadaddr - $fdtaddr"
+
+
+#define CONFIG_RAMBOOTCOMMAND 		\
+ "setenv bootargs root=/dev/ram rw "	\
+ "console=$consoledev,$baudrate $othbootargs;"	\
+ "tftp $ramdiskaddr $ramdiskfile;"	\
+ "tftp $loadaddr $bootfile;"		\
+ "tftp $fdtaddr $fdtfile;"		\
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND 		\
+ "setenv bootargs root=/dev/sda3 rw "	\
+ "console=$consoledev,$baudrate $othbootargs;"	\
+ "tftp $loadaddr $bootfile;"		\
+ "tftp $fdtaddr $fdtfile;"		\
+ "bootm $loadaddr - $fdtaddr"
+
+#endif	/* __CONFIG_H */

include/configs/MPC8548CDS.h

@@ -36,12 +36,12 @@
 #define CONFIG_MPC8548		1	/* MPC8548 specific */
 #define CONFIG_MPC8548CDS	1	/* MPC8548CDS board specific */
 
-#undef CONFIG_PCI
+#define CONFIG_PCI
 #define CONFIG_TSEC_ENET 		/* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
 #define CONFIG_DDR_DLL			/* possible DLL fix needed */
-#define CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
+#undef CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
 
 #define CONFIG_DDR_ECC			/* only for ECC DDR module */
 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
@@ -340,22 +340,34 @@ extern unsigned long get_clock_freq(void);
 
 /*
  * General PCI
- * Addresses are mapped 1-1.
+ * Memory space is mapped 1-1, but I/O space must start from 0.
  */
 #define CFG_PCI1_MEM_BASE	0x80000000
 #define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
-#define CFG_PCI1_MEM_SIZE	0x20000000	/* 512M */
+#define CFG_PCI1_MEM_SIZE	0x10000000	/* 256M */
 #define CFG_PCI1_IO_BASE	0x00000000
 #define CFG_PCI1_IO_PHYS	0xe2000000
-#define CFG_PCI1_IO_SIZE	0x00100000	/* 1M */
+#define CFG_PCI1_IO_SIZE	0x00800000	/* 8M */
 
-#define CFG_PCI2_MEM_BASE	0xa0000000
+#define CFG_PCI2_MEM_BASE	0x90000000
 #define CFG_PCI2_MEM_PHYS	CFG_PCI2_MEM_BASE
-#define CFG_PCI2_MEM_SIZE	0x20000000	/* 512M */
+#define CFG_PCI2_MEM_SIZE	0x10000000	/* 256M */
 #define CFG_PCI2_IO_BASE	0x00000000
-#define CFG_PCI2_IO_PHYS	0xe2100000
-#define CFG_PCI2_IO_SIZE	0x00100000	/* 1M */
+#define CFG_PCI2_IO_PHYS	0xe2800000
+#define CFG_PCI2_IO_SIZE	0x00800000	/* 8M */
 
+#define CFG_PEX_MEM_BASE	0xa0000000
+#define CFG_PEX_MEM_PHYS	CFG_PEX_MEM_BASE
+#define CFG_PEX_MEM_SIZE	0x20000000	/* 512M */
+#define CFG_PEX_IO_BASE		0x00000000
+#define CFG_PEX_IO_PHYS		0xe3000000
+#define CFG_PEX_IO_SIZE		0x01000000	/* 16M */
+
+/*
+ * RapidIO MMU
+ */
+#define CFG_RIO_MEM_BASE	0xC0000000
+#define CFG_RIO_MEM_SIZE	0x20000000	/* 512M */
 
 #if defined(CONFIG_PCI)
 

include/configs/MPC8560ADS.h

@@ -320,14 +320,14 @@
 
 /*
  * General PCI
- * Addresses are mapped 1-1.
+ * Memory space is mapped 1-1, but I/O space must start from 0.
  */
 #define CFG_PCI1_MEM_BASE	0x80000000
 #define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
 #define CFG_PCI1_MEM_SIZE	0x20000000	/* 512M */
-#define CFG_PCI1_IO_BASE	0xe2000000
-#define CFG_PCI1_IO_PHYS	CFG_PCI1_IO_BASE
-#define CFG_PCI1_IO_SIZE	0x1000000	/* 16M */
+#define CFG_PCI1_IO_BASE	0x00000000
+#define CFG_PCI1_IO_PHYS	0xe2000000
+#define CFG_PCI1_IO_SIZE	0x100000	/* 1M */
 
 #if defined(CONFIG_PCI)
 

include/configs/MPC8568MDS.h

@@ -0,0 +1,505 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * mpc8568mds board configuration file
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE		1	/* BOOKE */
+#define CONFIG_E500			1	/* BOOKE e500 family */
+#define CONFIG_MPC85xx		1	/* MPC8540/60/55/41/48/68 */
+#define CONFIG_MPC8568		1	/* MPC8568 specific */
+#define CONFIG_MPC8568MDS	1	/* MPC8568MDS board specific */
+
+#undef CONFIG_PCI
+#define CONFIG_TSEC_ENET 		/* tsec ethernet support */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
+#define CONFIG_DDR_DLL			/* possible DLL fix needed */
+/*#define CONFIG_DDR_2T_TIMING		 Sets the 2T timing bit */
+
+/*#define CONFIG_DDR_ECC*/			/* only for ECC DDR module */
+/*#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER*/	/* 	 DDR controller or DMA? */
+#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
+
+
+/*
+ * When initializing flash, if we cannot find the manufacturer ID,
+ * assume this is the AMD flash associated with the MDS board.
+ * This allows booting from a promjet.
+ */
+#define CONFIG_ASSUME_AMD_FLASH
+
+#define MPC85xx_DDR_SDRAM_CLK_CNTL	/* 85xx has clock control reg */
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_clock_freq(void);
+#endif						  /*Replace a call to get_clock_freq (after it is implemented)*/
+#define CONFIG_SYS_CLK_FREQ	66000000 /*TODO: restore if wanting to read from BCSR: get_clock_freq()*/ /* sysclk for MPC85xx */
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+/*#define CONFIG_L2_CACHE*/		    	    /* toggle L2 cache 	*/
+#define CONFIG_BTB						/* toggle branch predition */
+#define CONFIG_ADDR_STREAMING		    /* toggle addr streaming   */
+
+/*
+ * Only possible on E500 Version 2 or newer cores.
+ */
+#define CONFIG_ENABLE_36BIT_PHYS	1
+
+
+#define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */
+
+#undef	CFG_DRAM_TEST			/* memory test, takes time */
+#define CFG_MEMTEST_START	0x00200000	/* memtest works on */
+#define CFG_MEMTEST_END		0x00400000
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default */
+#define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
+#define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
+
+/*
+ * DDR Setup
+ */
+#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
+#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
+
+#define SPD_EEPROM_ADDRESS	0x51		/* DDR DIMM */
+
+/*
+ * Make sure required options are set
+ */
+#ifndef CONFIG_SPD_EEPROM
+#error ("CONFIG_SPD_EEPROM is required")
+#endif
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+
+/*
+ * Local Bus Definitions
+ */
+
+/*
+ * FLASH on the Local Bus
+ * Two banks, 8M each, using the CFI driver.
+ * Boot from BR0/OR0 bank at 0xff00_0000
+ * Alternate BR1/OR1 bank at 0xff80_0000
+ *
+ * BR0, BR1:
+ *    Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
+ *    Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
+ *    Port Size = 16 bits = BRx[19:20] = 10
+ *    Use GPCM = BRx[24:26] = 000
+ *    Valid = BRx[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001    BR0
+ * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001    BR1
+ *
+ * OR0, OR1:
+ *    Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
+ *    Reserved ORx[17:18] = 11, confusion here?
+ *    CSNT = ORx[20] = 1
+ *    ACS = half cycle delay = ORx[21:22] = 11
+ *    SCY = 6 = ORx[24:27] = 0110
+ *    TRLX = use relaxed timing = ORx[29] = 1
+ *    EAD = use external address latch delay = OR[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    ORx
+ */
+#define CFG_BCSR_BASE		0xf8000000
+
+#define CFG_FLASH_BASE		0xfe000000	/* start of FLASH 32M */
+
+/*Chip select 0 - Flash*/
+#define CFG_BR0_PRELIM		0xfe001001
+#define	CFG_OR0_PRELIM		0xfe006ff7
+
+/*Chip slelect 1 - BCSR*/
+#define CFG_BR1_PRELIM		0xf8000801
+#define	CFG_OR1_PRELIM		0xffffe9f7
+
+/*#define CFG_FLASH_BANKS_LIST	{0xff800000, CFG_FLASH_BASE} */
+#define CFG_MAX_FLASH_BANKS		1		/* number of banks */
+#define CFG_MAX_FLASH_SECT		512		/* sectors per device */
+#undef	CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CFG_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */
+
+#define CFG_MONITOR_BASE    	TEXT_BASE	/* start of monitor */
+
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_FLASH_CFI
+#define CFG_FLASH_EMPTY_INFO
+
+
+/*
+ * SDRAM on the LocalBus
+ */
+#define CFG_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM	 */
+#define CFG_LBC_SDRAM_SIZE	64			/* LBC SDRAM is 64MB */
+
+
+/*Chip select 2 - SDRAM*/
+#define CFG_BR2_PRELIM      0xf0001861
+#define CFG_OR2_PRELIM		0xfc006901
+
+#define CFG_LBC_LCRR		0x00030004    	/* LB clock ratio reg */
+#define CFG_LBC_LBCR		0x00000000    	/* LB config reg */
+#define CFG_LBC_LSRT		0x20000000  	/* LB sdram refresh timer */
+#define CFG_LBC_MRTPR		0x00000000  	/* LB refresh timer prescal*/
+
+/*
+ * LSDMR masks
+ */
+#define CFG_LBC_LSDMR_RFEN	(1 << (31 -  1))
+#define CFG_LBC_LSDMR_BSMA1516	(3 << (31 - 10))
+#define CFG_LBC_LSDMR_BSMA1617	(4 << (31 - 10))
+#define CFG_LBC_LSDMR_RFCR16	(7 << (31 - 16))
+#define CFG_LBC_LSDMR_PRETOACT7	(7 << (31 - 19))
+#define CFG_LBC_LSDMR_ACTTORW7	(7 << (31 - 22))
+#define CFG_LBC_LSDMR_ACTTORW6	(6 << (31 - 22))
+#define CFG_LBC_LSDMR_BL8	(1 << (31 - 23))
+#define CFG_LBC_LSDMR_WRC4	(0 << (31 - 27))
+#define CFG_LBC_LSDMR_CL3	(3 << (31 - 31))
+
+#define CFG_LBC_LSDMR_OP_NORMAL	(0 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_ARFRSH	(1 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_SRFRSH	(2 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_PCHALL	(5 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_ACTBNK	(6 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))
+
+/*
+ * Common settings for all Local Bus SDRAM commands.
+ * At run time, either BSMA1516 (for CPU 1.1)
+ *                  or BSMA1617 (for CPU 1.0) (old)
+ * is OR'ed in too.
+ */
+#define CFG_LBC_LSDMR_COMMON	( CFG_LBC_LSDMR_RFCR16		\
+				| CFG_LBC_LSDMR_PRETOACT7	\
+				| CFG_LBC_LSDMR_ACTTORW7	\
+				| CFG_LBC_LSDMR_BL8		\
+				| CFG_LBC_LSDMR_WRC4		\
+				| CFG_LBC_LSDMR_CL3		\
+				| CFG_LBC_LSDMR_RFEN		\
+				)
+
+/*
+ * The bcsr registers are connected to CS3 on MDS.
+ * The new memory map places bcsr at 0xf8000000.
+ *
+ * For BR3, need:
+ *    Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
+ *    port-size = 8-bits  = BR[19:20] = 01
+ *    no parity checking  = BR[21:22] = 00
+ *    GPMC for MSEL       = BR[24:26] = 000
+ *    Valid               = BR[31]    = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
+ *
+ * For OR3, need:
+ *    1 MB mask for AM,   OR[0:16]  = 1111 1111 1111 0000 0
+ *    disable buffer ctrl OR[19]    = 0
+ *    CSNT                OR[20]    = 1
+ *    ACS                 OR[21:22] = 11
+ *    XACS                OR[23]    = 1
+ *    SCY 15 wait states  OR[24:27] = 1111	max is suboptimal but safe
+ *    SETA                OR[28]    = 0
+ *    TRLX                OR[29]    = 1
+ *    EHTR                OR[30]    = 1
+ *    EAD extra time      OR[31]    = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
+ */
+#define CFG_BCSR (0xf8000000)
+
+/*Chip slelect 4 - PIB*/
+#define CFG_BR4_PRELIM   0xf8008801
+#define CFG_OR4_PRELIM   0xffffe9f7
+
+/*Chip select 5 - PIB*/
+#define CFG_BR5_PRELIM	 0xf8010801
+#define CFG_OR5_PRELIM	 0xffff69f7
+
+#define CONFIG_L1_INIT_RAM
+#define CFG_INIT_RAM_LOCK 	1
+#define CFG_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
+#define CFG_INIT_RAM_END    	0x4000	    /* End of used area in RAM */
+
+#define CFG_GBL_DATA_SIZE  	128	    /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN	    	(256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN	    	(128 * 1024)	/* Reserved for malloc */
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX		1
+#undef	CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE    1
+#define CFG_NS16550_CLK		get_bus_freq(0)
+
+#define CFG_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CFG_NS16550_COM1        (CFG_CCSRBAR+0x4500)
+#define CFG_NS16550_COM2        (CFG_CCSRBAR+0x4600)
+
+/* Use the HUSH parser*/
+#define CFG_HUSH_PARSER
+#ifdef  CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_FLAT_TREE	1
+#define CONFIG_OF_BOARD_SETUP	1
+
+/* maximum size of the flat tree (8K) */
+#define OF_FLAT_TREE_MAX_SIZE	8192
+
+#define OF_CPU			"PowerPC,8568@0"
+#define OF_SOC			"soc8568@e0000000"
+#define OF_TBCLK		(bd->bi_busfreq / 8)
+#define OF_STDOUT_PATH		"/soc8568@e0000000/serial@4600"
+
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C		/* I2C with hardware support*/
+#undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CFG_I2C_EEPROM_ADDR	0x57
+#define CFG_I2C_SLAVE		0x7F
+#define CFG_I2C_NOPROBES        {0x69}	/* Don't probe these addrs */
+#define CFG_I2C_OFFSET		0x3000
+
+/*
+ * General PCI
+ * Memory Addresses are mapped 1-1. I/O is mapped from 0
+ */
+#define CFG_PCI1_MEM_BASE	0x80000000
+#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
+#define CFG_PCI1_MEM_SIZE	0x10000000	/* 256M */
+#define CFG_PCI1_IO_BASE	0x00000000
+#define CFG_PCI1_IO_PHYS	0xe2000000
+#define CFG_PCI1_IO_SIZE	0x00800000	/* 8M */
+
+#define CFG_PEX_MEM_BASE	0xa0000000
+#define CFG_PEX_MEM_PHYS	CFG_PEX_MEM_BASE
+#define CFG_PEX_MEM_SIZE	0x10000000	/* 256M */
+#define CFG_PEX_IO_BASE		0x00000000
+#define CFG_PEX_IO_PHYS		0xe2800000
+#define CFG_PEX_IO_SIZE		0x00800000	/* 8M */
+
+#define CFG_SRIO_MEM_BASE	0xc0000000
+
+#if defined(CONFIG_PCI)
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP	               	/* do pci plug-and-play */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
+
+#endif	/* CONFIG_PCI */
+
+
+#if defined(CONFIG_TSEC_ENET)
+
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI 	1
+#endif
+
+#define CONFIG_MII		1	/* MII PHY management */
+#define CONFIG_MPC85XX_TSEC1	1
+#define CONFIG_MPC85XX_TSEC1_NAME	"eTSEC0"
+#define CONFIG_MPC85XX_TSEC2	1
+#define CONFIG_MPC85XX_TSEC2_NAME	"eTSEC1"
+#undef  CONFIG_MPC85XX_TSEC3
+#undef  CONFIG_MPC85XX_TSEC4
+#undef  CONFIG_MPC85XX_FEC
+
+#define TSEC1_PHY_ADDR		2
+#define TSEC2_PHY_ADDR		3
+
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+
+/* Options are: eTSEC[0-3] */
+#define CONFIG_ETHPRIME		"eTSEC0"
+
+#endif	/* CONFIG_TSEC_ENET */
+
+/*
+ * Environment
+ */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
+#define CFG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
+#define CFG_ENV_SIZE		0x2000
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+#if defined(CONFIG_PCI)
+#define  CONFIG_COMMANDS	(CONFIG_CMD_DFL \
+				| CFG_CMD_PCI \
+				| CFG_CMD_PING \
+				| CFG_CMD_I2C \
+				| CFG_CMD_MII)
+#else
+#define  CONFIG_COMMANDS	(CONFIG_CMD_DFL \
+				| CFG_CMD_PING \
+				| CFG_CMD_I2C \
+				| CFG_CMD_MII)
+#endif
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory	*/
+#define CFG_LOAD_ADDR	0x2000000	/* default load address */
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE	256			/* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args */
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
+#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ	(8 << 20) 	/* Initial Memory map for Linux*/
+
+/* Cache Configuration */
+#define CFG_DCACHE_SIZE	32768
+#define CFG_CACHELINE_SIZE	32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/*log base 2 of the above value*/
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02		/* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+/* The mac addresses for all ethernet interface */
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_ETHADDR   00:E0:0C:00:00:FD
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR  00:E0:0C:00:01:FD
+#define CONFIG_HAS_ETH2
+#define CONFIG_ETH2ADDR  00:E0:0C:00:02:FD
+#endif
+
+#define CONFIG_IPADDR    192.168.1.253
+
+#define CONFIG_HOSTNAME  unknown
+#define CONFIG_ROOTPATH  /nfsroot
+#define CONFIG_BOOTFILE  your.uImage
+
+#define CONFIG_SERVERIP  192.168.1.1
+#define CONFIG_GATEWAYIP 192.168.1.1
+#define CONFIG_NETMASK   255.255.255.0
+
+#define CONFIG_LOADADDR  200000   /*default location for tftp and bootm*/
+
+#define CONFIG_BOOTDELAY 10       /* -1 disables auto-boot */
+#undef  CONFIG_BOOTARGS           /* the boot command will set bootargs*/
+
+#define CONFIG_BAUDRATE	115200
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				        \
+   "netdev=eth0\0"                                                      \
+   "consoledev=ttyS0\0"                                                 \
+   "ramdiskaddr=600000\0"                                               \
+   "ramdiskfile=your.ramdisk.u-boot\0"					\
+   "fdtaddr=400000\0"							\
+   "fdtfile=your.fdt.dtb\0"						\
+   "nfsargs=setenv bootargs root=/dev/nfs rw "				\
+      "nfsroot=$serverip:$rootpath "					\
+      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+      "console=$consoledev,$baudrate $othbootargs\0"			\
+   "ramargs=setenv bootargs root=/dev/ram rw "				\
+      "console=$consoledev,$baudrate $othbootargs\0"			\
+
+
+#define CONFIG_NFSBOOTCOMMAND	                                        \
+   "run nfsargs;"							\
+   "tftp $loadaddr $bootfile;"                                          \
+   "tftp $fdtaddr $fdtfile;"						\
+   "bootm $loadaddr - $fdtaddr"
+
+
+#define CONFIG_RAMBOOTCOMMAND \
+   "run ramargs;"							\
+   "tftp $ramdiskaddr $ramdiskfile;"                                    \
+   "tftp $loadaddr $bootfile;"                                          \
+   "bootm $loadaddr $ramdiskaddr"
+
+#define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
+
+#endif	/* __CONFIG_H */

include/configs/bamboo.h

@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2005-2006
+ * (C) Copyright 2005-2007
  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -43,7 +43,6 @@
  * 2nd ethernet port you have to "undef" the following define.
  */
 #define CONFIG_BAMBOO_NAND      1       /* enable nand flash support    */
-#define CFG_NAND_LEGACY
 
 /*-----------------------------------------------------------------------
  * Base addresses -- Note these are effective addresses where the
@@ -143,65 +142,13 @@
 #endif /* CFG_ENV_IS_IN_FLASH */
 
 /*-----------------------------------------------------------------------
- * NAND-FLASH related
+ * NAND FLASH
  *----------------------------------------------------------------------*/
-#define NAND_CMD_REG   (0x00) /* NandFlash Command Register */
-#define NAND_ADDR_REG  (0x04) /* NandFlash Address Register */
-#define NAND_DATA_REG  (0x08) /* NandFlash Data Register */
-#define NAND_ECC0_REG  (0x10) /* NandFlash ECC Register0 */
-#define NAND_ECC1_REG  (0x14) /* NandFlash ECC Register1 */
-#define NAND_ECC2_REG  (0x18) /* NandFlash ECC Register2 */
-#define NAND_ECC3_REG  (0x1C) /* NandFlash ECC Register3 */
-#define NAND_ECC4_REG  (0x20) /* NandFlash ECC Register4 */
-#define NAND_ECC5_REG  (0x24) /* NandFlash ECC Register5 */
-#define NAND_ECC6_REG  (0x28) /* NandFlash ECC Register6 */
-#define NAND_ECC7_REG  (0x2C) /* NandFlash ECC Register7 */
-#define NAND_CR0_REG   (0x30) /* NandFlash Device Bank0 Config Register */
-#define NAND_CR1_REG   (0x34) /* NandFlash Device Bank1 Config Register */
-#define NAND_CR2_REG   (0x38) /* NandFlash Device Bank2 Config Register */
-#define NAND_CR3_REG   (0x3C) /* NandFlash Device Bank3 Config Register */
-#define NAND_CCR_REG   (0x40) /* NandFlash Core Configuration Register */
-#define NAND_STAT_REG  (0x44) /* NandFlash Device Status Register */
-#define NAND_HWCTL_REG (0x48) /* NandFlash Direct Hwd Control Register */
-#define NAND_REVID_REG (0x50) /* NandFlash Core Revision Id Register */
-
-/* Nand Flash K9F1208U0A Command Set => Nand Flash 0 */
-#define NAND0_CMD_READ1_HALF1     0x00     /* Starting addr for 1rst half of registers */
-#define NAND0_CMD_READ1_HALF2     0x01     /* Starting addr for 2nd half of registers */
-#define NAND0_CMD_READ2           0x50
-#define NAND0_CMD_READ_ID         0x90
-#define NAND0_CMD_READ_STATUS     0x70
-#define NAND0_CMD_RESET           0xFF
-#define NAND0_CMD_PAGE_PROG       0x80
-#define NAND0_CMD_PAGE_PROG_TRUE  0x10
-#define NAND0_CMD_PAGE_PROG_DUMMY 0x11
-#define NAND0_CMD_BLOCK_ERASE     0x60
-#define NAND0_CMD_BLOCK_ERASE_END 0xD0
-
-#define CFG_MAX_NAND_DEVICE     1	/* Max number of NAND devices */
-#define SECTORSIZE              512
-
-#define ADDR_COLUMN             1
-#define ADDR_PAGE               2
-#define ADDR_COLUMN_PAGE        3
-
-#define NAND_ChipID_UNKNOWN     0x00
-#define NAND_MAX_FLOORS         1
-#define NAND_MAX_CHIPS          1
-
-#define WRITE_NAND_COMMAND(d, adr) do {*(volatile u8 *)((ulong)adr+NAND_CMD_REG) = d;} while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do {*(volatile u8 *)((ulong)adr+NAND_ADDR_REG) = d;} while(0)
-#define WRITE_NAND(d, adr)      do {*(volatile u8 *)((ulong)adr+NAND_DATA_REG) = d;} while(0)
-#define READ_NAND(adr)          (*(volatile u8 *)((ulong)adr+NAND_DATA_REG))
-#define NAND_WAIT_READY(nand)   while (!(*(volatile u8 *)((ulong)nand->IO_ADDR+NAND_STAT_REG) & 0x01))
-
-/* not needed with 440EP NAND controller */
-#define NAND_CTL_CLRALE(nandptr)
-#define NAND_CTL_SETALE(nandptr)
-#define NAND_CTL_CLRCLE(nandptr)
-#define NAND_CTL_SETCLE(nandptr)
-#define NAND_DISABLE_CE(nand)
-#define NAND_ENABLE_CE(nand)
+#define CFG_MAX_NAND_DEVICE	1
+#define NAND_MAX_CHIPS		1
+#define CFG_NAND_CS		1
+#define CFG_NAND_BASE		(CFG_NAND_ADDR + CFG_NAND_CS)
+#define CFG_NAND_SELECT_DEVICE  1	/* nand driver supports mutipl. chips	*/
 
 /*-----------------------------------------------------------------------
  * DDR SDRAM

include/configs/delta.h

@@ -202,7 +202,6 @@
 /*
  * NAND Flash
  */
-/* Use the new NAND code. (BOARDLIBS = drivers/nand/libnand.a required) */
 #undef CFG_NAND_LEGACY
 
 #define CFG_NAND0_BASE		0x0 /* 0x43100040 */ /* 0x10000000 */

include/configs/katmai.h

@@ -360,7 +360,19 @@
 				 EBC_BXCR_BW_16BIT)
 
 /* Memory Bank 1 (Xilinx System ACE controller) initialization		*/
-#define CFG_EBC_PB1AP		0x7F8FFE80
+#define CFG_EBC_PB1AP		(EBC_BXAP_BME_DISABLED      |		\
+				 EBC_BXAP_TWT_ENCODE(4)     |		\
+				 EBC_BXAP_BCE_DISABLE       |		\
+				 EBC_BXAP_BCT_2TRANS        |		\
+				 EBC_BXAP_CSN_ENCODE(0)     |		\
+				 EBC_BXAP_OEN_ENCODE(0)     |		\
+				 EBC_BXAP_WBN_ENCODE(0)     |		\
+				 EBC_BXAP_WBF_ENCODE(0)     |		\
+				 EBC_BXAP_TH_ENCODE(0)      |		\
+				 EBC_BXAP_RE_DISABLED       |		\
+				 EBC_BXAP_SOR_NONDELAYED    |		\
+				 EBC_BXAP_BEM_WRITEONLY     |		\
+				 EBC_BXAP_PEN_DISABLED)
 #define CFG_EBC_PB1CR		(EBC_BXCR_BAS_ENCODE(CFG_ACE_BASE)  |	\
 				 EBC_BXCR_BS_1MB                    |	\
 				 EBC_BXCR_BU_RW                     |	\

include/configs/sequoia.h

@@ -38,7 +38,9 @@
 #define CONFIG_440GRX		1		/* Specific PPC440GRx	*/
 #endif
 #define CONFIG_4xx		1		/* ... PPC4xx family	*/
-#define CONFIG_SYS_CLK_FREQ	33000000	/* external freq to pll	*/
+/* Detect Sequoia PLL input clock automatically via CPLD bit		*/
+#define CONFIG_SYS_CLK_FREQ    ((in8(CFG_BCSR_BASE + 3) & 0x80) ? \
+				3333333 : 33000000)
 
 #define CONFIG_BOARD_EARLY_INIT_F 1		/* Call board_early_init_f */
 #define CONFIG_MISC_INIT_R	1		/* Call misc_init_r	*/

include/configs/stxssa.h

@@ -0,0 +1,465 @@
+/*
+ * (C) Copyright 2005 Embedded Alley Solutions, Inc.
+ * Dan Malek <dan@embeddedalley.com>
+ * Copied from STx GP3.
+ * Updates for Silicon Tx GP3 SSA board.
+ *
+ * (C) Copyright 2002,2003 Motorola,Inc.
+ * Xianghua Xiao <X.Xiao@motorola.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* mpc8560ads board configuration file */
+/* please refer to doc/README.mpc85xx for more info */
+/* make sure you change the MAC address and other network params first,
+ * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE		1	/* BOOKE		*/
+#define CONFIG_E500		1	/* BOOKE e500 family	*/
+#define CONFIG_MPC85xx		1	/* MPC8540/MPC8560	*/
+#define CONFIG_CPM2		1	/* has CPM2 */
+#define CONFIG_STXSSA		1	/* Silicon Tx GPPP SSA board specific*/
+
+#undef  CONFIG_PCI	         	/* pci ethernet support	*/
+#define CONFIG_TSEC_ENET 		/* tsec ethernet support*/
+#undef CONFIG_ETHER_ON_FCC             /* cpm FCC ethernet support */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
+#undef  CONFIG_DDR_ECC			/* only for ECC DDR module */
+#undef CONFIG_DDR_DLL                  /* possible DLL fix needed */
+#define CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
+
+
+/* sysclk for MPC85xx
+ */
+
+#define CONFIG_SYS_CLK_FREQ     33000000 /* most pci cards are 33Mhz */
+
+/* Blinkin' LEDs for Robert :-)
+*/
+#define CONFIG_SHOW_ACTIVITY 1
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE                     /* toggle L2 cache         */
+#define  CONFIG_BTB                          /* toggle branch predition */
+#define  CONFIG_ADDR_STREAMING               /* toggle addr streaming   */
+
+#define CONFIG_BOARD_EARLY_INIT_F   1        /* Call board_pre_init      */
+
+#undef  CFG_DRAM_TEST                       /* memory test, takes time  */
+#define CFG_MEMTEST_START       0x00200000  /* memtest region */
+#define CFG_MEMTEST_END         0x00400000
+
+
+/* Localbus connector.  There are many options that can be
+ * connected here, including sdram or lots of flash.
+ * This address, however, is used to configure a 256M local bus
+ * window that includes the Config latch below.
+ */
+#define CFG_LBC_OPTION_BASE	0xf0000000      /* Localbus Extension */
+#define CFG_LBC_OPTION_SIZE	256		/* 256MB */
+
+/* There are various flash options used, we configure for the largest,
+ * which is 64Mbytes.  The CFI works fine and will discover the proper
+ * sizes.
+ */
+#define CFG_FLASH_BASE		0xFC000000      /* start of FLASH 64M    */
+#define CFG_BR0_PRELIM		0xFC001801	/* port size 32bit      */
+#define CFG_OR0_PRELIM		0xFC000FF7	/* 64 MB Flash           */
+
+#define CFG_FLASH_CFI		1
+#define CFG_FLASH_CFI_DRIVER	1
+#undef CFG_FLASH_USE_BUFFER_WRITE 	/* use buffered writes (20x faster) */
+#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks	*/
+
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
+
+#define CFG_FLASH_PROTECTION
+
+/* The configuration latch is Chip Select 1.
+ * It's an 8-bit latch in the lower 8 bits of the word.
+ */
+#define CFG_LBC_CFGLATCH_BASE	0xfb000000	/* Base of config latch */
+#define CFG_BR1_PRELIM		0xfb001801	/* 32-bit port */
+#define CFG_OR1_PRELIM		0xffff0ff7      /* 64K is enough */
+
+#define CFG_MONITOR_BASE    	TEXT_BASE	/* start of monitor	*/
+
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#define CFG_RAMBOOT
+#else
+#undef  CFG_RAMBOOT
+#endif
+
+#ifdef CFG_RAMBOOT
+#define CFG_CCSRBAR_DEFAULT 	0x40000000	/* CCSRBAR by BDI cfg	*/
+#else
+#define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default	*/
+#endif
+#define CFG_CCSRBAR             0xe0000000      /* relocated CCSRBAR    */
+#define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR	*/
+
+
+/*
+ * DDR Setup
+ */
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory  */
+#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
+
+#define SPD_EEPROM_ADDRESS 	0x54     	/*  DDR DIMM */
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+/* local bus definitions */
+#define CFG_BR2_PRELIM		0xf8001861	/* 64MB localbus SDRAM  */
+#define CFG_OR2_PRELIM		0xfc006901
+#define CFG_LBC_LCRR		0x00030004	/* local bus freq 	*/
+#define CFG_LBC_LBCR		0x00000000
+#define CFG_LBC_LSRT		0x20000000
+#define CFG_LBC_MRTPR		0x20000000
+#define CFG_LBC_LSDMR_1		0x2861b723
+#define CFG_LBC_LSDMR_2		0x0861b723
+#define CFG_LBC_LSDMR_3		0x0861b723
+#define CFG_LBC_LSDMR_4		0x1861b723
+#define CFG_LBC_LSDMR_5		0x4061b723
+
+#define CONFIG_L1_INIT_RAM
+#define CFG_INIT_RAM_LOCK 	1
+#define CFG_INIT_RAM_ADDR       0x60000000      /* Initial RAM address  */
+#define CFG_INIT_RAM_END    	0x4000	    	/* End of used area in RAM */
+
+#define CFG_GBL_DATA_SIZE  	128		/* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN	    	(256 * 1024)    /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN	    	(512 * 1024)    /* Reserved for malloc */
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX     2
+#undef	CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE    1
+#define CFG_NS16550_CLK		get_bus_freq(0)
+
+#define CFG_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CFG_NS16550_COM1        (CFG_CCSRBAR+0x4500)
+#define CFG_NS16550_COM2        (CFG_CCSRBAR+0x4600)
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CFG_HUSH_PARSER		1	/* Use the HUSH parser		*/
+#ifdef  CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+/* I2C */
+#define CONFIG_FSL_I2C			/* Use FSL common I2C driver */
+#define  CONFIG_HARD_I2C    		/* I2C with hardware support*/
+#undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CFG_I2C_SLAVE		0x7F
+#if 0
+#define CFG_I2C_NOPROBES        {0x00}  /* Don't probe these addrs */
+#else
+/* I did the 'if 0' so we could keep the syntax above if ever needed. */
+#undef CFG_I2C_NOPROBES
+#endif
+#define CFG_I2C_OFFSET		0x3000
+
+/* I2C EEPROM.  AT24C32, we keep our environment in here.
+*/
+#define CFG_I2C_EEPROM_ADDR		0x51	/* 1010001x		*/
+#define CFG_I2C_EEPROM_ADDR_LEN		2
+#define CFG_EEPROM_PAGE_WRITE_BITS	5	/* =32 Bytes per write	*/
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	20
+
+/*
+ * Standard 8555 PCI mapping.
+ * Addresses are mapped 1-1.
+ */
+#define CFG_PCI1_MEM_BASE	0x80000000
+#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
+#define CFG_PCI1_MEM_SIZE	0x20000000	/* 512M */
+#define CFG_PCI1_IO_BASE	0x00000000
+#define CFG_PCI1_IO_PHYS	0xe2000000
+#define CFG_PCI1_IO_SIZE	0x01000000	/* 16M */
+
+#define CFG_PCI2_MEM_BASE	0xa0000000
+#define CFG_PCI2_MEM_PHYS	CFG_PCI2_MEM_BASE
+#define CFG_PCI2_MEM_SIZE	0x20000000	/* 512M */
+#define CFG_PCI2_IO_BASE	0x00000000
+#define CFG_PCI2_IO_PHYS	0xe3000000
+#define CFG_PCI2_IO_SIZE	0x01000000	/* 16M */
+
+#if defined(CONFIG_PCI) 		/* PCI Ethernet card */
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP	               	/* do pci plug-and-play */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#if !defined(CONFIG_PCI_PNP)
+  #define PCI_ENET0_IOADDR    	0xe0000000
+  #define PCI_ENET0_MEMADDR     0xe0000000
+  #define PCI_IDSEL_NUMBER      0x0c 	/* slot0->3(IDSEL)=12->15 */
+#endif
+
+#undef CONFIG_PCI_SCAN_SHOW
+#define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
+
+#endif /* CONFIG_PCI */
+
+#if defined(CONFIG_TSEC_ENET)
+
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI 	1
+#endif
+
+#define CONFIG_MII		1	/* MII PHY management		*/
+
+#define CONFIG_MPC85XX_TSEC1	1
+#define CONFIG_MPC85XX_TSEC1_NAME	"TSEC0"
+#define CONFIG_MPC85XX_TSEC2	1
+#define CONFIG_MPC85XX_TSEC2_NAME	"TSEC1"
+#undef CONFIG_MPS85XX_FEC
+
+#define TSEC1_PHY_ADDR		2
+#define TSEC2_PHY_ADDR		4
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+#define CONFIG_ETHPRIME		"TSEC0"
+
+#elif defined(CONFIG_ETHER_ON_FCC)	/* CPM FCC Ethernet */
+
+#define CONFIG_ETHER_ON_FCC2             /* define if ether on FCC   */
+#undef  CONFIG_ETHER_NONE               /* define if ether on something else */
+#define CONFIG_ETHER_INDEX      2       /* which channel for ether  */
+
+#if (CONFIG_ETHER_INDEX == 2)
+  /*
+   * - Rx-CLK is CLK13
+   * - Tx-CLK is CLK14
+   * - Select bus for bd/buffers
+   * - Full duplex
+   */
+  #define CFG_CMXFCR_MASK       (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
+  #define CFG_CMXFCR_VALUE      (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
+  #define CFG_CPMFCR_RAMTYPE    0
+#if 0
+  #define CFG_FCC_PSMR          (FCC_PSMR_FDE)
+#else
+  #define CFG_FCC_PSMR          0
+#endif
+  #define FETH2_RST		0x01
+#elif (CONFIG_ETHER_INDEX == 3)
+  /* need more definitions here for FE3 */
+  #define FETH3_RST		0x80
+#endif  				/* CONFIG_ETHER_INDEX */
+
+/* MDIO is done through the TSEC0 control.
+*/
+#define CONFIG_MII			/* MII PHY management */
+#undef CONFIG_BITBANGMII		/* bit-bang MII PHY management	*/
+
+#endif
+
+/* Environment - default config is in flash, see below */
+#if 0	/* in EEPROM */
+#define CFG_ENV_IS_IN_EEPROM	1
+#define CFG_ENV_OFFSET		0
+#define CFG_ENV_SIZE		2048
+#else	/* in flash */
+#define	CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_SECT_SIZE	0x40000
+
+#define	CFG_ENV_ADDR		(CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE)
+#define	CFG_ENV_SIZE		0x4000
+#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR - CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+#endif
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define	CONFIG_TIMESTAMP		/* Print image info with ts	*/
+
+#if defined(CFG_RAMBOOT)
+  #if defined(CONFIG_PCI)
+  #define  CONFIG_COMMANDS	((CONFIG_CMD_DFL | CFG_CMD_PCI | \
+				CFG_CMD_PING | CFG_CMD_I2C) & \
+				 ~(CFG_CMD_ENV | \
+				  CFG_CMD_LOADS ))
+  #elif defined(CONFIG_TSEC_ENET)
+  #define  CONFIG_COMMANDS	((CONFIG_CMD_DFL | CFG_CMD_PING | \
+				CFG_CMD_MII | CFG_CMD_I2C ) & \
+				~(CFG_CMD_ENV))
+  #elif defined(CONFIG_ETHER_ON_FCC)
+  #define  CONFIG_COMMANDS	((CONFIG_CMD_DFL | CFG_CMD_MII | \
+				CFG_CMD_PING | CFG_CMD_I2C) & \
+				~(CFG_CMD_ENV))
+  #endif
+#else
+  #if defined(CONFIG_PCI)
+  #define  CONFIG_COMMANDS	(CONFIG_CMD_DFL | CFG_CMD_PCI | \
+				CFG_CMD_ELF | CFG_CMD_PING | CFG_CMD_I2C)
+  #elif defined(CONFIG_TSEC_ENET)
+  #define  CONFIG_COMMANDS	(CONFIG_CMD_DFL | CFG_CMD_PING | \
+				CFG_CMD_ELF | CFG_CMD_MII | CFG_CMD_I2C)
+  #elif defined(CONFIG_ETHER_ON_FCC)
+  #define  CONFIG_COMMANDS	(CONFIG_CMD_DFL | CFG_CMD_MII | \
+				CFG_CMD_ELF | CFG_CMD_PING | CFG_CMD_I2C)
+  #endif
+#endif
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"SSA=> "	/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CFG_LOAD_ADDR	0x1000000	/* default load address */
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
+
+/* Cache Configuration */
+#define CFG_DCACHE_SIZE		32768
+#define CFG_CACHELINE_SIZE	32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02		/* Software reboot		*/
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+/*Note: change below for your network setting!!! */
+#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
+#define CONFIG_ETHADDR	 00:e0:0c:07:9b:8a
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR  00:e0:0c:07:9b:8b
+#define CONFIG_HAS_ETH2
+#define CONFIG_ETH2ADDR  00:e0:0c:07:9b:8c
+#endif
+
+/*
+ * Environment in EEPROM is compatible with different flash sector sizes,
+ * but only little space is available, so we use a very simple setup.
+ * With environment in flash, we use a more powerful default configuration.
+ */
+#ifdef CFG_ENV_IS_IN_EEPROM		/* use restricted "standard" environment */
+
+#define CONFIG_BAUDRATE	 	38400
+
+#define CONFIG_BOOTDELAY	3	/* -1 disable autoboot */
+#define CONFIG_BOOTCOMMAND	"bootm 0xffc00000 0xffd00000"
+#define CONFIG_BOOTARGS		"root=/dev/nfs rw ip=any console=ttyS1,$baudrate"
+#define CONFIG_SERVERIP 	192.168.85.1
+#define CONFIG_IPADDR  		192.168.85.60
+#define CONFIG_GATEWAYIP	192.168.85.1
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_HOSTNAME 	STX_SSA
+#define CONFIG_ROOTPATH 	/gppproot
+#define CONFIG_BOOTFILE 	uImage
+#define CONFIG_LOADADDR		0x1000000
+
+#else /* ENV IS IN FLASH		-- use a full-blown envionment */
+
+#define CONFIG_BAUDRATE	 	115200
+
+#define CONFIG_BOOTDELAY	5	/* -1 disable autoboot */
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS		/* the boot command will set bootargs	*/
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"hostname=gp3ssa\0"						\
+	"bootfile=/tftpboot/gp3ssa/uImage\0"				\
+	"loadaddr=400000\0"						\
+	"netdev=eth0\0"							\
+	"consdev=ttyS1\0"						\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=$serverip:$rootpath\0"				\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs $bootargs "				\
+		"ip=$ipaddr:$serverip:$gatewayip:$netmask"		\
+		":$hostname:$netdev:off panic=1\0"			\
+	"addcons=setenv bootargs $bootargs "				\
+		"console=$consdev,$baudrate\0"				\
+	"flash_nfs=run nfsargs addip addcons;"				\
+		"bootm $kernel_addr\0"					\
+	"flash_self=run ramargs addip addcons;"				\
+		"bootm $kernel_addr $ramdisk_addr\0"			\
+	"net_nfs=tftp $loadaddr $bootfile;"				\
+		"run nfsargs addip addcons;bootm\0"			\
+	"rootpath=/opt/eldk/ppc_85xx\0"					\
+	"kernel_addr=FC000000\0"					\
+	"ramdisk_addr=FC200000\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#endif	/* CFG_ENV_IS_IN_EEPROM */
+
+#endif	/* __CONFIG_H */

include/configs/zylonite.h

@@ -174,7 +174,6 @@
 /*
  * NAND Flash
  */
-/* Use the new NAND code. (BOARDLIBS = drivers/nand/libnand.a required) */
 #define CONFIG_NEW_NAND_CODE
 #define CFG_NAND0_BASE		0x0
 #undef CFG_NAND1_BASE

include/mpc86xx.h

@@ -9,6 +9,15 @@
 
 #define EXC_OFF_SYS_RESET	0x0100	/* System reset	offset */
 
+
+/*
+ * platform register addresses
+ */
+
+#define GUTS_SVR	(CFG_CCSRBAR + 0xE00A4)
+#define MCM_ABCR	(CFG_CCSRBAR + 0x01000)
+#define MCM_DBCR	(CFG_CCSRBAR + 0x01008)
+
 /*
  * l2cr values.  Look in config_<BOARD>.h for the actual setup
  */

nand_spl/board/amcc/sequoia/Makefile

@@ -30,7 +30,7 @@ AFLAGS	+= -DCONFIG_NAND_SPL
 CFLAGS	+= -DCONFIG_NAND_SPL
 
 SOBJS	= start.o init.o resetvec.o
-COBJS	= nand_boot.o ndfc.o sdram.o speed.o
+COBJS	= nand_boot.o ndfc.o sdram.o
 
 SRCS	:= $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
@@ -69,10 +69,6 @@ $(obj)start.S:
 	@rm -f $(obj)start.S
 	ln -s $(SRCTREE)/cpu/ppc4xx/start.S $(obj)start.S
 
-$(obj)speed.c:
-	@rm -f $(obj)speed.c
-	ln -s $(SRCTREE)/cpu/ppc4xx/speed.c $(obj)speed.c
-
 # from board directory
 $(obj)init.S:
 	@rm -f $(obj)init.S