arm: update co-processor 15 access

import system.h from linux

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

cpu/arm1136/cpu.c

@@ -33,36 +33,12 @@
 
 #include <common.h>
 #include <command.h>
+#include <asm/system.h>
 
 #ifdef CONFIG_USE_IRQ
 DECLARE_GLOBAL_DATA_PTR;
 #endif
 
-/* read co-processor 15, register #1 (control register) */
-static unsigned long read_p15_c1 (void)
-{
-	unsigned long value;
-
-	__asm__ __volatile__(
-				"mrc	p15, 0, %0, c1, c0, 0   @ read control reg\n"
-				: "=r" (value)
-				:
-				: "memory");
-	return value;
-}
-
-/* write to co-processor 15, register #1 (control register) */
-static void write_p15_c1 (unsigned long value)
-{
-	__asm__ __volatile__(
-						"mcr	p15, 0, %0, c1, c0, 0   @ write it back\n"
-						:
-						: "r" (value)
-						: "memory");
-
-	read_p15_c1 ();
-}
-
 static void cp_delay (void)
 {
 	volatile int i;
@@ -71,18 +47,6 @@ static void cp_delay (void)
 	for (i = 0; i < 100; i++);
 }
 
-/* See also ARM Ref. Man. */
-#define C1_MMU		(1<<0)		/* mmu off/on */
-#define C1_ALIGN	(1<<1)		/* alignment faults off/on */
-#define C1_DC		(1<<2)		/* dcache off/on */
-#define C1_WB		(1<<3)		/* merging write buffer on/off */
-#define C1_BIG_ENDIAN	(1<<7)	/* big endian off/on */
-#define C1_SYS_PROT	(1<<8)		/* system protection */
-#define C1_ROM_PROT	(1<<9)		/* ROM protection */
-#define C1_IC		(1<<12)		/* icache off/on */
-#define C1_HIGH_VECTORS	(1<<13)	/* location of vectors: low/high addresses */
-#define RESERVED_1	(0xf << 3)	/* must be 111b for R/W */
-
 int cpu_init (void)
 {
 	/*
@@ -120,7 +84,7 @@ int cleanup_before_linux (void)
 
 	/* turn off I/D-cache */
 	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
-	i &= ~(C1_DC | C1_IC);
+	i &= ~(CR_C | CR_I);
 	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 
 	/* flush I/D-cache */
@@ -142,21 +106,21 @@ void icache_enable (void)
 {
 	ulong reg;
 
-	reg = read_p15_c1 ();	/* get control reg. */
+	reg = get_cr ();	/* get control reg. */
 	cp_delay ();
-	write_p15_c1 (reg | C1_IC);
+	set_cr (reg | CR_I);
 }
 
 void icache_disable (void)
 {
 	ulong reg;
 
-	reg = read_p15_c1 ();
+	reg = get_cr ();
 	cp_delay ();
-	write_p15_c1 (reg & ~C1_IC);
+	set_cr (reg & ~CR_I);
 }
 
 int icache_status (void)
 {
-	return(read_p15_c1 () & C1_IC) != 0;
+	return(get_cr () & CR_I) != 0;
 }

cpu/arm1176/cpu.c

@@ -34,34 +34,10 @@
 #include <common.h>
 #include <command.h>
 #include <s3c6400.h>
+#include <asm/system.h>
 
 static void cache_flush (void);
 
-/* read co-processor 15, register #1 (control register) */
-static unsigned long read_p15_c1 (void)
-{
-	unsigned long value;
-
-	__asm__ __volatile__(
-		"mrc	p15, 0, %0, c1, c0, 0   @ read control reg\n"
-		: "=r" (value)
-		:
-		: "memory");
-	return value;
-}
-
-/* write to co-processor 15, register #1 (control register) */
-static void write_p15_c1 (unsigned long value)
-{
-	__asm__ __volatile__(
-		"mcr	p15, 0, %0, c1, c0, 0   @ write it back\n"
-		:
-		: "r" (value)
-		: "memory");
-
-	read_p15_c1();
-}
-
 static void cp_delay (void)
 {
 	volatile int i;
@@ -71,18 +47,6 @@ static void cp_delay (void)
 		__asm__ __volatile__("nop\n");
 }
 
-/* See also ARM Ref. Man. */
-#define C1_MMU		(1 << 0)	/* mmu off/on */
-#define C1_ALIGN	(1 << 1)	/* alignment faults off/on */
-#define C1_DC		(1 << 2)	/* dcache off/on */
-#define C1_WB		(1 << 3)	/* merging write buffer on/off */
-#define C1_BIG_ENDIAN	(1 << 7)	/* big endian off/on */
-#define C1_SYS_PROT	(1 << 8)	/* system protection */
-#define C1_ROM_PROT	(1 << 9)	/* ROM protection */
-#define C1_IC		(1 << 12)	/* icache off/on */
-#define C1_HIGH_VECTORS	(1 << 13)	/* location of vectors: low/high */
-#define RESERVED_1	(0xf << 3)	/* must be 111b for R/W */
-
 int cpu_init (void)
 {
 	return 0;
@@ -135,23 +99,23 @@ void icache_enable (void)
 {
 	ulong reg;
 
-	reg = read_p15_c1 ();	/* get control reg. */
+	reg = get_cr ();	/* get control reg. */
 	cp_delay ();
-	write_p15_c1 (reg | C1_IC);
+	set_cr (reg | CR_I);
 }
 
 void icache_disable (void)
 {
 	ulong reg;
 
-	reg = read_p15_c1 ();
+	reg = get_cr ();
 	cp_delay ();
-	write_p15_c1 (reg & ~C1_IC);
+	set_cr (reg & ~CR_I);
 }
 
 int icache_status (void)
 {
-	return (read_p15_c1 () & C1_IC) != 0;
+	return (get_cr () & CR_I) != 0;
 }
 
 /* It makes no sense to use the dcache if the MMU is not enabled */
@@ -159,23 +123,23 @@ void dcache_enable (void)
 {
 	ulong reg;
 
-	reg = read_p15_c1 ();
+	reg = get_cr ();
 	cp_delay ();
-	write_p15_c1 (reg | C1_DC);
+	set_cr (reg | CR_C);
 }
 
 void dcache_disable (void)
 {
 	ulong reg;
 
-	reg = read_p15_c1 ();
+	reg = get_cr ();
 	cp_delay ();
-	write_p15_c1 (reg & ~C1_DC);
+	set_cr (reg & ~CR_C);
 }
 
 int dcache_status (void)
 {
-	return (read_p15_c1 () & C1_DC) != 0;
+	return (get_cr () & CR_C) != 0;
 }
 
 /* flush I/D-cache */

cpu/arm720t/cpu.c

@@ -34,6 +34,7 @@
 #include <command.h>
 #include <clps7111.h>
 #include <asm/hardware.h>
+#include <asm/system.h>
 
 int cpu_init (void)
 {
@@ -98,33 +99,6 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
  */
 
 #if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_NETARM) || defined(CONFIG_ARMADILLO)
-/* read co-processor 15, register #1 (control register) */
-static unsigned long read_p15_c1(void)
-{
-	unsigned long value;
-
-	__asm__ __volatile__(
-		"mrc     p15, 0, %0, c1, c0, 0   @ read control reg\n"
-		: "=r" (value)
-		:
-		: "memory");
-	/* printf("p15/c1 is = %08lx\n", value); */
-	return value;
-}
-
-/* write to co-processor 15, register #1 (control register) */
-static void write_p15_c1(unsigned long value)
-{
-	/* printf("write %08lx to p15/c1\n", value); */
-	__asm__ __volatile__(
-		"mcr     p15, 0, %0, c1, c0, 0   @ write it back\n"
-		:
-		: "r" (value)
-		: "memory");
-
-	read_p15_c1();
-}
-
 static void cp_delay (void)
 {
 	volatile int i;
@@ -133,60 +107,50 @@ static void cp_delay (void)
 	for (i = 0; i < 100; i++);
 }
 
-/* See also ARM Ref. Man. */
-#define C1_MMU		(1<<0)	/* mmu off/on */
-#define C1_ALIGN	(1<<1)	/* alignment faults off/on */
-#define C1_IDC		(1<<2)	/* icache and/or dcache off/on */
-#define C1_WRITE_BUFFER	(1<<3)	/* write buffer off/on */
-#define C1_BIG_ENDIAN	(1<<7)	/* big endian off/on */
-#define C1_SYS_PROT	(1<<8)	/* system protection */
-#define C1_ROM_PROT	(1<<9)	/* ROM protection */
-#define C1_HIGH_VECTORS	(1<<13)	/* location of vectors: low/high addresses */
-
 void icache_enable (void)
 {
 	ulong reg;
 
-	reg = read_p15_c1 ();
+	reg = get_cr ();
 	cp_delay ();
-	write_p15_c1 (reg | C1_IDC);
+	set_cr (reg | CR_C);
 }
 
 void icache_disable (void)
 {
 	ulong reg;
 
-	reg = read_p15_c1 ();
+	reg = get_cr ();
 	cp_delay ();
-	write_p15_c1 (reg & ~C1_IDC);
+	set_cr (reg & ~CR_C);
 }
 
 int icache_status (void)
 {
-	return (read_p15_c1 () & C1_IDC) != 0;
+	return (get_cr () & CR_C) != 0;
 }
 
 void dcache_enable (void)
 {
 	ulong reg;
 
-	reg = read_p15_c1 ();
+	reg = get_cr ();
 	cp_delay ();
-	write_p15_c1 (reg | C1_IDC);
+	set_cr (reg | CR_C);
 }
 
 void dcache_disable (void)
 {
 	ulong reg;
 
-	reg = read_p15_c1 ();
+	reg = get_cr ();
 	cp_delay ();
-	write_p15_c1 (reg & ~C1_IDC);
+	set_cr (reg & ~CR_C);
 }
 
 int dcache_status (void)
 {
-	return (read_p15_c1 () & C1_IDC) != 0;
+	return (get_cr () & CR_C) != 0;
 }
 #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
 	/* No specific cache setup for IntegratorAP/CM720T as yet */

cpu/arm920t/cpu.c

@@ -32,43 +32,12 @@
 #include <common.h>
 #include <command.h>
 #include <arm920t.h>
+#include <asm/system.h>
 
 #ifdef CONFIG_USE_IRQ
 DECLARE_GLOBAL_DATA_PTR;
 #endif
 
-/* read co-processor 15, register #1 (control register) */
-static unsigned long read_p15_c1 (void)
-{
-	unsigned long value;
-
-	__asm__ __volatile__(
-		"mrc	p15, 0, %0, c1, c0, 0   @ read control reg\n"
-		: "=r" (value)
-		:
-		: "memory");
-
-#ifdef MMU_DEBUG
-	printf ("p15/c1 is = %08lx\n", value);
-#endif
-	return value;
-}
-
-/* write to co-processor 15, register #1 (control register) */
-static void write_p15_c1 (unsigned long value)
-{
-#ifdef MMU_DEBUG
-	printf ("write %08lx to p15/c1\n", value);
-#endif
-	__asm__ __volatile__(
-		"mcr	p15, 0, %0, c1, c0, 0   @ write it back\n"
-		:
-		: "r" (value)
-		: "memory");
-
-	read_p15_c1 ();
-}
-
 static void cp_delay (void)
 {
 	volatile int i;
@@ -77,18 +46,6 @@ static void cp_delay (void)
 	for (i = 0; i < 100; i++);
 }
 
-/* See also ARM920T    Technical reference Manual */
-#define C1_MMU		(1<<0)		/* mmu off/on */
-#define C1_ALIGN	(1<<1)		/* alignment faults off/on */
-#define C1_DC		(1<<2)		/* dcache off/on */
-
-#define C1_BIG_ENDIAN	(1<<7)		/* big endian off/on */
-#define C1_SYS_PROT	(1<<8)		/* system protection */
-#define C1_ROM_PROT	(1<<9)		/* ROM protection */
-#define C1_IC		(1<<12)		/* icache off/on */
-#define C1_HIGH_VECTORS	(1<<13)		/* location of vectors: low/high addresses */
-
-
 int cpu_init (void)
 {
 	/*
@@ -116,7 +73,7 @@ int cleanup_before_linux (void)
 
 	/* turn off I/D-cache */
 	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
-	i &= ~(C1_DC | C1_IC);
+	i &= ~(CR_C | CR_I);
 	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 
 	/* flush I/D-cache */
@@ -138,23 +95,23 @@ void icache_enable (void)
 {
 	ulong reg;
 
-	reg = read_p15_c1 ();		/* get control reg. */
+	reg = get_cr ();		/* get control reg. */
 	cp_delay ();
-	write_p15_c1 (reg | C1_IC);
+	set_cr (reg | CR_I);
 }
 
 void icache_disable (void)
 {
 	ulong reg;
 
-	reg = read_p15_c1 ();
+	reg = get_cr ();
 	cp_delay ();
-	write_p15_c1 (reg & ~C1_IC);
+	set_cr (reg & ~CR_I);
 }
 
 int icache_status (void)
 {
-	return (read_p15_c1 () & C1_IC) != 0;
+	return (get_cr () & CR_I) != 0;
 }
 
 #ifdef USE_920T_MMU
@@ -163,23 +120,23 @@ void dcache_enable (void)
 {
 	ulong reg;
 
-	reg = read_p15_c1 ();
+	reg = get_cr ();
 	cp_delay ();
-	write_p15_c1 (reg | C1_DC);
+	set_cr (reg | CR_C);
 }
 
 void dcache_disable (void)
 {
 	ulong reg;
 
-	reg = read_p15_c1 ();
+	reg = get_cr ();
 	cp_delay ();
-	reg &= ~C1_DC;
-	write_p15_c1 (reg);
+	reg &= ~CR_C;
+	set_cr (reg);
 }
 
 int dcache_status (void)
 {
-	return (read_p15_c1 () & C1_DC) != 0;
+	return (get_cr () & CR_C) != 0;
 }
 #endif

cpu/arm925t/cpu.c

@@ -32,43 +32,12 @@
 #include <common.h>
 #include <command.h>
 #include <arm925t.h>
+#include <asm/system.h>
 
 #ifdef CONFIG_USE_IRQ
 DECLARE_GLOBAL_DATA_PTR;
 #endif
 
-/* read co-processor 15, register #1 (control register) */
-static unsigned long read_p15_c1 (void)
-{
-	unsigned long value;
-
-	__asm__ __volatile__(
-		"mrc	p15, 0, %0, c1, c0, 0   @ read control reg\n"
-		: "=r" (value)
-		:
-		: "memory");
-
-#ifdef MMU_DEBUG
-	printf ("p15/c1 is = %08lx\n", value);
-#endif
-	return value;
-}
-
-/* write to co-processor 15, register #1 (control register) */
-static void write_p15_c1 (unsigned long value)
-{
-#ifdef MMU_DEBUG
-	printf ("write %08lx to p15/c1\n", value);
-#endif
-	__asm__ __volatile__(
-		"mcr	p15, 0, %0, c1, c0, 0   @ write it back\n"
-		:
-		: "r" (value)
-		: "memory");
-
-	read_p15_c1 ();
-}
-
 static void cp_delay (void)
 {
 	volatile int i;
@@ -77,18 +46,6 @@ static void cp_delay (void)
 	for (i = 0; i < 100; i++);
 }
 
-/* See also ARM Ref. Man. */
-#define C1_MMU		(1<<0)		/* mmu off/on */
-#define C1_ALIGN	(1<<1)		/* alignment faults off/on */
-#define C1_DC		(1<<2)		/* dcache off/on */
-#define C1_WB		(1<<3)		/* merging write buffer on/off */
-#define C1_BIG_ENDIAN	(1<<7)	/* big endian off/on */
-#define C1_SYS_PROT	(1<<8)		/* system protection */
-#define C1_ROM_PROT	(1<<9)		/* ROM protection */
-#define C1_IC		(1<<12)		/* icache off/on */
-#define C1_HIGH_VECTORS	(1<<13)	/* location of vectors: low/high addresses */
-#define RESERVED_1	(0xf << 3)	/* must be 111b for R/W */
-
 int cpu_init (void)
 {
 	/*
@@ -116,7 +73,7 @@ int cleanup_before_linux (void)
 
 	/* turn off I/D-cache */
 	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
-	i &= ~(C1_DC | C1_IC);
+	i &= ~(CR_C | CR_I);
 	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 
 	/* flush I/D-cache */
@@ -137,21 +94,21 @@ void icache_enable (void)
 {
 	ulong reg;
 
-	reg = read_p15_c1 ();		/* get control reg. */
+	reg = get_cr ();		/* get control reg. */
 	cp_delay ();
-	write_p15_c1 (reg | C1_IC);
+	set_cr (reg | CR_I);
 }
 
 void icache_disable (void)
 {
 	ulong reg;
 
-	reg = read_p15_c1 ();
+	reg = get_cr ();
 	cp_delay ();
-	write_p15_c1 (reg & ~C1_IC);
+	set_cr (reg & ~CR_I);
 }
 
 int icache_status (void)
 {
-	return (read_p15_c1 () & C1_IC) != 0;
+	return (get_cr () & CR_I) != 0;
 }

cpu/arm926ejs/cpu.c

@@ -32,43 +32,12 @@
 #include <common.h>
 #include <command.h>
 #include <arm926ejs.h>
+#include <asm/system.h>
 
 #ifdef CONFIG_USE_IRQ
 DECLARE_GLOBAL_DATA_PTR;
 #endif
 
-/* read co-processor 15, register #1 (control register) */
-static unsigned long read_p15_c1 (void)
-{
-	unsigned long value;
-
-	__asm__ __volatile__(
-		"mrc	p15, 0, %0, c1, c0, 0   @ read control reg\n"
-		: "=r" (value)
-		:
-		: "memory");
-
-#ifdef MMU_DEBUG
-	printf ("p15/c1 is = %08lx\n", value);
-#endif
-	return value;
-}
-
-/* write to co-processor 15, register #1 (control register) */
-static void write_p15_c1 (unsigned long value)
-{
-#ifdef MMU_DEBUG
-	printf ("write %08lx to p15/c1\n", value);
-#endif
-	__asm__ __volatile__(
-		"mcr	p15, 0, %0, c1, c0, 0   @ write it back\n"
-		:
-		: "r" (value)
-		: "memory");
-
-	read_p15_c1 ();
-}
-
 static void cp_delay (void)
 {
 	volatile int i;
@@ -77,18 +46,6 @@ static void cp_delay (void)
 	for (i = 0; i < 100; i++);
 }
 
-/* See also ARM926EJ-S Technical Reference Manual */
-#define C1_MMU		(1<<0)		/* mmu off/on */
-#define C1_ALIGN	(1<<1)		/* alignment faults off/on */
-#define C1_DC		(1<<2)		/* dcache off/on */
-
-#define C1_BIG_ENDIAN	(1<<7)		/* big endian off/on */
-#define C1_SYS_PROT	(1<<8)		/* system protection */
-#define C1_ROM_PROT	(1<<9)		/* ROM protection */
-#define C1_IC		(1<<12)		/* icache off/on */
-#define C1_HIGH_VECTORS	(1<<13)		/* location of vectors: low/high addresses */
-
-
 int cpu_init (void)
 {
 	/*
@@ -116,7 +73,7 @@ int cleanup_before_linux (void)
 
 	/* turn off I/D-cache */
 	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
-	i &= ~(C1_DC | C1_IC);
+	i &= ~(CR_C | CR_I);
 	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 
 	/* flush I/D-cache */
@@ -134,52 +91,52 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	return (0);
 }
 
-/* cache_bit must be either C1_IC or C1_DC */
+/* cache_bit must be either CR_I or CR_C */
 static void cache_enable(uint32_t cache_bit)
 {
 	uint32_t reg;
 
-	reg = read_p15_c1();	/* get control reg. */
+	reg = get_cr();	/* get control reg. */
 	cp_delay();
-	write_p15_c1(reg | cache_bit);
+	set_cr(reg | cache_bit);
 }
 
-/* cache_bit must be either C1_IC or C1_DC */
+/* cache_bit must be either CR_I or CR_C */
 static void cache_disable(uint32_t cache_bit)
 {
 	uint32_t reg;
 
-	reg = read_p15_c1();
+	reg = get_cr();
 	cp_delay();
-	write_p15_c1(reg & ~cache_bit);
+	set_cr(reg & ~cache_bit);
 }
 
 void icache_enable(void)
 {
-	cache_enable(C1_IC);
+	cache_enable(CR_I);
 }
 
 void icache_disable(void)
 {
-	cache_disable(C1_IC);
+	cache_disable(CR_I);
 }
 
 int icache_status(void)
 {
-	return (read_p15_c1() & C1_IC) != 0;
+	return (get_cr() & CR_I) != 0;
 }
 
 void dcache_enable(void)
 {
-	cache_enable(C1_DC);
+	cache_enable(CR_C);
 }
 
 void dcache_disable(void)
 {
-	cache_disable(C1_DC);
+	cache_disable(CR_C);
 }
 
 int dcache_status(void)
 {
-	return (read_p15_c1() & C1_DC) != 0;
+	return (get_cr() & CR_C) != 0;
 }

cpu/arm946es/cpu.c

@@ -32,43 +32,12 @@
 #include <common.h>
 #include <command.h>
 #include <arm946es.h>
+#include <asm/system.h>
 
 #ifdef CONFIG_USE_IRQ
 DECLARE_GLOBAL_DATA_PTR;
 #endif
 
-/* read co-processor 15, register #1 (control register) */
-static unsigned long read_p15_c1 (void)
-{
-	unsigned long value;
-
-	__asm__ __volatile__(
-		"mrc	p15, 0, %0, c1, c0, 0	@ read control reg\n"
-		: "=r" (value)
-		:
-		: "memory");
-
-#ifdef MMU_DEBUG
-	printf ("p15/c1 is = %08lx\n", value);
-#endif
-	return value;
-}
-
-/* write to co-processor 15, register #1 (control register) */
-static void write_p15_c1 (unsigned long value)
-{
-#ifdef MMU_DEBUG
-	printf ("write %08lx to p15/c1\n", value);
-#endif
-	__asm__ __volatile__(
-		"mcr	p15, 0, %0, c1, c0, 0	@ write it back\n"
-		:
-		: "r" (value)
-		: "memory");
-
-	read_p15_c1 ();
-}
-
 static void cp_delay (void)
 {
 	volatile int i;
@@ -77,18 +46,6 @@ static void cp_delay (void)
 	for (i = 0; i < 100; i++);
 }
 
-/* See also ARM946E-S  Technical Reference Manual */
-#define C1_MMU		(1<<0)		/* mmu off/on */
-#define C1_ALIGN	(1<<1)		/* alignment faults off/on */
-#define C1_DC		(1<<2)		/* dcache off/on */
-
-#define C1_BIG_ENDIAN	(1<<7)		/* big endian off/on */
-#define C1_SYS_PROT	(1<<8)		/* system protection */
-#define C1_ROM_PROT	(1<<9)		/* ROM protection */
-#define C1_IC		(1<<12)		/* icache off/on */
-#define C1_HIGH_VECTORS (1<<13)		/* location of vectors: low/high addresses */
-
-
 int cpu_init (void)
 {
 	/*
@@ -120,7 +77,7 @@ int cleanup_before_linux (void)
 	 */
 	/* turn off I/D-cache */
 	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
-	i &= ~(C1_DC | C1_IC);
+	i &= ~(CR_C | CR_I);
 	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 
 	/* flush I/D-cache */
@@ -145,21 +102,21 @@ void icache_enable (void)
 {
 	ulong reg;
 
-	reg = read_p15_c1 ();		/* get control reg. */
+	reg = get_cr ();		/* get control reg. */
 	cp_delay ();
-	write_p15_c1 (reg | C1_IC);
+	set_cr (reg | CR_I);
 }
 
 void icache_disable (void)
 {
 	ulong reg;
 
-	reg = read_p15_c1 ();
+	reg = get_cr ();
 	cp_delay ();
-	write_p15_c1 (reg & ~C1_IC);
+	set_cr (reg & ~CR_I);
 }
 
 int icache_status (void)
 {
-	return (read_p15_c1 () & C1_IC) != 0;
+	return (get_cr () & CR_I) != 0;
 }

cpu/arm_cortexa8/cpu.c

@@ -34,6 +34,7 @@
 #include <common.h>
 #include <command.h>
 #include <asm/arch/sys_proto.h>
+#include <asm/system.h>
 
 #ifdef CONFIG_USE_IRQ
 DECLARE_GLOBAL_DATA_PTR;
@@ -45,27 +46,6 @@ void l2cache_disable(void);
 
 static void cache_flush(void);
 
-/* read co-processor 15, register #1 (control register) */
-static unsigned long read_p15_c1(void)
-{
-	unsigned long value;
-
-	__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 0\
-			     @ read control reg\n":"=r"(value)
-			     ::"memory");
-	return value;
-}
-
-/* write to co-processor 15, register #1 (control register) */
-static void write_p15_c1(unsigned long value)
-{
-	__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 0\
-			     @ write it back\n"::"r"(value)
-			     : "memory");
-
-	read_p15_c1();
-}
-
 static void cp_delay(void)
 {
 	/* Many OMAP regs need at least 2 nops */
@@ -73,18 +53,6 @@ static void cp_delay(void)
 	asm("nop");
 }
 
-/* See also ARM Ref. Man. */
-#define C1_MMU		(1<<0)	/* mmu off/on */
-#define C1_ALIGN	(1<<1)	/* alignment faults off/on */
-#define C1_DC		(1<<2)	/* dcache off/on */
-#define C1_WB		(1<<3)	/* merging write buffer on/off */
-#define C1_BIG_ENDIAN	(1<<7)	/* big endian off/on */
-#define C1_SYS_PROT	(1<<8)	/* system protection */
-#define C1_ROM_PROT	(1<<9)	/* ROM protection */
-#define C1_IC		(1<<12)	/* icache off/on */
-#define C1_HIGH_VECTORS	(1<<13)	/* location of vectors: low/high addresses */
-#define RESERVED_1	(0xf << 3)	/* must be 111b for R/W */
-
 int cpu_init(void)
 {
 	/*
@@ -147,27 +115,27 @@ void icache_enable(void)
 {
 	ulong reg;
 
-	reg = read_p15_c1();	/* get control reg. */
+	reg = get_cr();	/* get control reg. */
 	cp_delay();
-	write_p15_c1(reg | C1_IC);
+	set_cr(reg | CR_I);
 }
 
 void icache_disable(void)
 {
 	ulong reg;
 
-	reg = read_p15_c1();
+	reg = get_cr();
 	cp_delay();
-	write_p15_c1(reg & ~C1_IC);
+	set_cr(reg & ~CR_I);
 }
 
 void dcache_disable (void)
 {
 	ulong reg;
 
-	reg = read_p15_c1 ();
+	reg = get_cr ();
 	cp_delay ();
-	write_p15_c1 (reg & ~C1_DC);
+	set_cr (reg & ~CR_C);
 }
 
 void l2cache_enable()
@@ -231,7 +199,7 @@ void l2cache_disable()
 
 int icache_status(void)
 {
-	return (read_p15_c1() & C1_IC) != 0;
+	return (get_cr() & CR_I) != 0;
 }
 
 static void cache_flush(void)

cpu/ixp/cpu.c

@@ -34,6 +34,7 @@
 #include <command.h>
 #include <netdev.h>
 #include <asm/arch/ixp425.h>
+#include <asm/system.h>
 
 ulong loops_per_jiffy;
 
@@ -125,47 +126,39 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	return (0);
 }
 
-/* taken from blob */
-void icache_enable (void)
+/* cache_bit must be either CR_I or CR_C */
+static void cache_enable(uint32_t cache_bit)
 {
-	register u32 i;
+	uint32_t reg;
 
-	/* read control register */
-	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
-
-	/* set i-cache */
-	i |= 0x1000;
-
-	/* write back to control register */
-	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+	reg = get_cr();	/* get control reg. */
+	cp_delay();
+	set_cr(reg | cache_bit);
 }
 
-void icache_disable (void)
+/* cache_bit must be either CR_I or CR_C */
+static void cache_disable(uint32_t cache_bit)
 {
-	register u32 i;
-
-	/* read control register */
-	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
-
-	/* clear i-cache */
-	i &= ~0x1000;
+	uint32_t reg;
 
-	/* write back to control register */
-	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
-
-	/* flush i-cache */
-	asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
+	reg = get_cr();
+	cp_delay();
+	set_cr(reg & ~cache_bit);
 }
 
-int icache_status (void)
+void icache_enable(void)
 {
-	register u32 i;
+	cache_enable(CR_I);
+}
 
-	/* read control register */
-	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+void icache_disable(void)
+{
+	cache_disable(CR_I);
+}
 
-	/* return bit */
-	return (i & 0x1000);
+int icache_status(void)
+{
+	return (get_cr() & CR_I) != 0;
 }
 
 /* we will never enable dcache, because we have to setup MMU first */

cpu/lh7a40x/cpu.c

@@ -32,43 +32,12 @@
 #include <common.h>
 #include <command.h>
 #include <arm920t.h>
+#include <asm/system.h>
 
 #ifdef CONFIG_USE_IRQ
 DECLARE_GLOBAL_DATA_PTR;
 #endif
 
-/* read co-processor 15, register #1 (control register) */
-static unsigned long read_p15_c1 (void)
-{
-	unsigned long value;
-
-	__asm__ __volatile__(
-		"mrc     p15, 0, %0, c1, c0, 0   @ read control reg\n"
-		: "=r" (value)
-		:
-		: "memory");
-
-#ifdef MMU_DEBUG
-	printf ("p15/c1 is = %08lx\n", value);
-#endif
-	return value;
-}
-
-/* write to co-processor 15, register #1 (control register) */
-static void write_p15_c1 (unsigned long value)
-{
-#ifdef MMU_DEBUG
-	printf ("write %08lx to p15/c1\n", value);
-#endif
-	__asm__ __volatile__(
-		"mcr     p15, 0, %0, c1, c0, 0   @ write it back\n"
-		:
-		: "r" (value)
-		: "memory");
-
-	read_p15_c1 ();
-}
-
 static void cp_delay (void)
 {
 	volatile int i;
@@ -77,17 +46,6 @@ static void cp_delay (void)
 	for (i = 0; i < 100; i++);
 }
 
-/* See also ARM Ref. Man. */
-#define C1_MMU		(1<<0)		/* mmu off/on */
-#define C1_ALIGN	(1<<1)		/* alignment faults off/on */
-#define C1_DC		(1<<2)		/* dcache off/on */
-#define C1_BIG_ENDIAN	(1<<7)	/* big endian off/on */
-#define C1_SYS_PROT	(1<<8)		/* system protection */
-#define C1_ROM_PROT	(1<<9)		/* ROM protection */
-#define C1_IC		(1<<12)		/* icache off/on */
-#define C1_HIGH_VECTORS	(1<<13)	/* location of vectors: low/high addresses */
-#define RESERVED_1	(0xf << 3)	/* must be 111b for R/W */
-
 int cpu_init (void)
 {
 	/*
@@ -115,7 +73,7 @@ int cleanup_before_linux (void)
 
 	/* turn off I/D-cache */
 	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
-	i &= ~(C1_DC | C1_IC);
+	i &= ~(CR_C | CR_I);
 	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 
 	/* flush I/D-cache */
@@ -136,23 +94,23 @@ void icache_enable (void)
 {
 	ulong reg;
 
-	reg = read_p15_c1 ();
+	reg = get_cr ();
 	cp_delay ();
-	write_p15_c1 (reg | C1_IC);
+	set_cr (reg | CR_I);
 }
 
 void icache_disable (void)
 {
 	ulong reg;
 
-	reg = read_p15_c1 ();
+	reg = get_cr ();
 	cp_delay ();
-	write_p15_c1 (reg & ~C1_IC);
+	set_cr (reg & ~CR_I);
 }
 
 int icache_status (void)
 {
-	return (read_p15_c1 () & C1_IC) != 0;
+	return (get_cr () & CR_I) != 0;
 }
 
 #ifdef USE_920T_MMU
@@ -161,23 +119,23 @@ void dcache_enable (void)
 {
 	ulong reg;
 
-	reg = read_p15_c1 ();
+	reg = get_cr ();
 	cp_delay ();
-	write_p15_c1 (reg | C1_DC);
+	set_cr (reg | CR_C);
 }
 
 void dcache_disable (void)
 {
 	ulong reg;
 
-	reg = read_p15_c1 ();
+	reg = get_cr ();
 	cp_delay ();
-	reg &= ~C1_DC;
-	write_p15_c1 (reg);
+	reg &= ~CR_C;
+	set_cr (reg);
 }
 
 int dcache_status (void)
 {
-	return (read_p15_c1 () & C1_DC) != 0;
+	return (get_cr () & CR_C) != 0;
 }
 #endif

cpu/pxa/cpu.c

@@ -33,6 +33,7 @@
 #include <common.h>
 #include <command.h>
 #include <asm/arch/pxa-regs.h>
+#include <asm/system.h>
 
 #ifdef CONFIG_USE_IRQ
 DECLARE_GLOBAL_DATA_PTR;
@@ -86,47 +87,39 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	return (0);
 }
 
-/* taken from blob */
-void icache_enable (void)
+/* cache_bit must be either CR_I or CR_C */
+static void cache_enable(uint32_t cache_bit)
 {
-	register u32 i;
+	uint32_t reg;
 
-	/* read control register */
-	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
-
-	/* set i-cache */
-	i |= 0x1000;
-
-	/* write back to control register */
-	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+	reg = get_cr();	/* get control reg. */
+	cp_delay();
+	set_cr(reg | cache_bit);
 }
 
-void icache_disable (void)
+/* cache_bit must be either CR_I or CR_C */
+static void cache_disable(uint32_t cache_bit)
 {
-	register u32 i;
-
-	/* read control register */
-	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
-
-	/* clear i-cache */
-	i &= ~0x1000;
+	uint32_t reg;
 
-	/* write back to control register */
-	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
-
-	/* flush i-cache */
-	asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
+	reg = get_cr();
+	cp_delay();
+	set_cr(reg & ~cache_bit);
 }
 
-int icache_status (void)
+void icache_enable(void)
 {
-	register u32 i;
+	cache_enable(CR_I);
+}
 
-	/* read control register */
-	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+void icache_disable(void)
+{
+	cache_disable(CR_I);
+}
 
-	/* return bit */
-	return (i & 0x1000);
+int icache_status(void)
+{
+	return (get_cr() & CR_I) != 0;
 }
 
 /* we will never enable dcache, because we have to setup MMU first */

cpu/sa1100/cpu.c

@@ -32,6 +32,7 @@
 
 #include <common.h>
 #include <command.h>
+#include <asm/system.h>
 
 #ifdef CONFIG_USE_IRQ
 DECLARE_GLOBAL_DATA_PTR;
@@ -85,47 +86,35 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	return (0);
 }
 
-/* taken from blob */
-void icache_enable (void)
+static void cp_delay (void)
 {
-	register u32 i;
+	volatile int i;
 
-	/* read control register */
-	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+	/* copro seems to need some delay between reading and writing */
+	for (i = 0; i < 100; i++);
+}
 
-	/* set i-cache */
-	i |= 0x1000;
+void icache_enable (void)
+{
+	ulong reg;
 
-	/* write back to control register */
-	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+	reg = get_cr ();
+	cp_delay ();
+	set_cr (reg | CR_C);
 }
 
 void icache_disable (void)
 {
-	register u32 i;
-
-	/* read control register */
-	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+	ulong reg;
 
-	/* clear i-cache */
-	i &= ~0x1000;
-
-	/* write back to control register */
-	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
-
-	/* flush i-cache */
-	asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
+	reg = get_cr ();
+	cp_delay ();
+	set_cr (reg & ~CR_C);
 }
 
 int icache_status (void)
 {
-	register u32 i;
-
-	/* read control register */
-	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
-
-	/* return bit */
-	return (i & 0x1000);
+	return (get_cr () & CR_C) != 0;
 }
 
 /* we will never enable dcache, because we have to setup MMU first */

include/asm-arm/system.h

@@ -0,0 +1,84 @@
+#ifndef __ASM_ARM_SYSTEM_H
+#define __ASM_ARM_SYSTEM_H
+
+#ifdef __KERNEL__
+
+#define CPU_ARCH_UNKNOWN	0
+#define CPU_ARCH_ARMv3		1
+#define CPU_ARCH_ARMv4		2
+#define CPU_ARCH_ARMv4T		3
+#define CPU_ARCH_ARMv5		4
+#define CPU_ARCH_ARMv5T		5
+#define CPU_ARCH_ARMv5TE	6
+#define CPU_ARCH_ARMv5TEJ	7
+#define CPU_ARCH_ARMv6		8
+#define CPU_ARCH_ARMv7		9
+
+/*
+ * CR1 bits (CP#15 CR1)
+ */
+#define CR_M	(1 << 0)	/* MMU enable				*/
+#define CR_A	(1 << 1)	/* Alignment abort enable		*/
+#define CR_C	(1 << 2)	/* Dcache enable			*/
+#define CR_W	(1 << 3)	/* Write buffer enable			*/
+#define CR_P	(1 << 4)	/* 32-bit exception handler		*/
+#define CR_D	(1 << 5)	/* 32-bit data address range		*/
+#define CR_L	(1 << 6)	/* Implementation defined		*/
+#define CR_B	(1 << 7)	/* Big endian				*/
+#define CR_S	(1 << 8)	/* System MMU protection		*/
+#define CR_R	(1 << 9)	/* ROM MMU protection			*/
+#define CR_F	(1 << 10)	/* Implementation defined		*/
+#define CR_Z	(1 << 11)	/* Implementation defined		*/
+#define CR_I	(1 << 12)	/* Icache enable			*/
+#define CR_V	(1 << 13)	/* Vectors relocated to 0xffff0000	*/
+#define CR_RR	(1 << 14)	/* Round Robin cache replacement	*/
+#define CR_L4	(1 << 15)	/* LDR pc can set T bit			*/
+#define CR_DT	(1 << 16)
+#define CR_IT	(1 << 18)
+#define CR_ST	(1 << 19)
+#define CR_FI	(1 << 21)	/* Fast interrupt (lower latency mode)	*/
+#define CR_U	(1 << 22)	/* Unaligned access operation		*/
+#define CR_XP	(1 << 23)	/* Extended page tables			*/
+#define CR_VE	(1 << 24)	/* Vectored interrupts			*/
+#define CR_EE	(1 << 25)	/* Exception (Big) Endian		*/
+#define CR_TRE	(1 << 28)	/* TEX remap enable			*/
+#define CR_AFE	(1 << 29)	/* Access flag enable			*/
+#define CR_TE	(1 << 30)	/* Thumb exception enable		*/
+
+/*
+ * This is used to ensure the compiler did actually allocate the register we
+ * asked it for some inline assembly sequences.  Apparently we can't trust
+ * the compiler from one version to another so a bit of paranoia won't hurt.
+ * This string is meant to be concatenated with the inline asm string and
+ * will cause compilation to stop on mismatch.
+ * (for details, see gcc PR 15089)
+ */
+#define __asmeq(x, y)  ".ifnc " x "," y " ; .err ; .endif\n\t"
+
+#ifndef __ASSEMBLY__
+
+#define isb() __asm__ __volatile__ ("" : : : "memory")
+
+#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
+
+static inline unsigned int get_cr(void)
+{
+	unsigned int val;
+	asm("mrc p15, 0, %0, c1, c0, 0	@ get CR" : "=r" (val) : : "cc");
+	return val;
+}
+
+static inline void set_cr(unsigned int val)
+{
+	asm volatile("mcr p15, 0, %0, c1, c0, 0	@ set CR"
+	  : : "r" (val) : "cc");
+	isb();
+}
+
+#endif /* __ASSEMBLY__ */
+
+#define arch_align_stack(x) (x)
+
+#endif /* __KERNEL__ */
+
+#endif