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@@ -88,6 +88,26 @@ static const struct dpll_params mpu_dpll_params_1100mhz[NUM_SYS_CLKS] = {
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{1375, 47, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
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};
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+static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = {
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+ {200, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
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+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
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+ {1000, 20, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
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+ {375, 8, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
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+ {400, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
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+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
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+ {375, 17, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
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+};
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+
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+static const struct dpll_params mpu_dpll_params_400mhz[NUM_SYS_CLKS] = {
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+ {200, 2, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
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+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
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+ {1000, 20, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
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+ {375, 8, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
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+ {400, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
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+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
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+ {375, 17, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
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+};
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+
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static const struct dpll_params mpu_dpll_params_550mhz[NUM_SYS_CLKS] = {
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{275, 2, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
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{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
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@@ -100,24 +120,24 @@ static const struct dpll_params mpu_dpll_params_550mhz[NUM_SYS_CLKS] = {
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static const struct dpll_params
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core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = {
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- {266, 2, 1, 5, 8, 4, 62, 5, 5, 7}, /* 12 MHz */
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+ {266, 2, 2, 5, 8, 4, 62, 5, 5, 7}, /* 12 MHz */
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{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
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- {570, 8, 1, 5, 8, 4, 62, 5, 5, 7}, /* 16.8 MHz */
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- {665, 11, 1, 5, 8, 4, 62, 5, 5, 7}, /* 19.2 MHz */
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- {532, 12, 1, 5, 8, 4, 62, 5, 5, 7}, /* 26 MHz */
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+ {570, 8, 2, 5, 8, 4, 62, 5, 5, 7}, /* 16.8 MHz */
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+ {665, 11, 2, 5, 8, 4, 62, 5, 5, 7}, /* 19.2 MHz */
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+ {532, 12, 2, 5, 8, 4, 62, 5, 5, 7}, /* 26 MHz */
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{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
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- {665, 23, 1, 5, 8, 4, 62, 5, 5, 7} /* 38.4 MHz */
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+ {665, 23, 2, 5, 8, 4, 62, 5, 5, 7} /* 38.4 MHz */
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};
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static const struct dpll_params
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core_dpll_params_2128mhz_ddr266[NUM_SYS_CLKS] = {
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- {266, 2, 2, 5, 8, 4, 62, 5, 5, 7}, /* 12 MHz */
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+ {266, 2, 4, 5, 8, 8, 62, 10, 10, 14}, /* 12 MHz */
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{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
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- {570, 8, 2, 5, 8, 4, 62, 5, 5, 7}, /* 16.8 MHz */
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- {665, 11, 2, 5, 8, 4, 62, 5, 5, 7}, /* 19.2 MHz */
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- {532, 12, 2, 5, 8, 4, 62, 5, 5, 7}, /* 26 MHz */
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+ {570, 8, 4, 5, 8, 8, 62, 10, 10, 14}, /* 16.8 MHz */
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+ {665, 11, 4, 5, 8, 8, 62, 10, 10, 14}, /* 19.2 MHz */
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+ {532, 12, 4, 8, 8, 8, 62, 10, 10, 14}, /* 26 MHz */
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{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
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- {665, 23, 2, 5, 8, 4, 62, 5, 5, 7} /* 38.4 MHz */
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+ {665, 23, 4, 8, 8, 8, 62, 10, 10, 14} /* 38.4 MHz */
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};
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static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = {
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@@ -131,40 +151,40 @@ static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = {
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};
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static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
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- {931, 11, -1, -1, 4, 7, -1, -1}, /* 12 MHz */
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- {931, 12, -1, -1, 4, 7, -1, -1}, /* 13 MHz */
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- {665, 11, -1, -1, 4, 7, -1, -1}, /* 16.8 MHz */
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- {727, 14, -1, -1, 4, 7, -1, -1}, /* 19.2 MHz */
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- {931, 25, -1, -1, 4, 7, -1, -1}, /* 26 MHz */
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- {931, 26, -1, -1, 4, 7, -1, -1}, /* 27 MHz */
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- {412, 16, -1, -1, 4, 7, -1, -1} /* 38.4 MHz */
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+ {1165, 11, -1, -1, 5, 6, -1, -1, -1, -1}, /* 12 MHz */
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+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
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+ {2011, 28, -1, -1, 5, 6, -1, -1, -1, -1}, /* 16.8 MHz */
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+ {1881, 30, -1, -1, 5, 6, -1, -1, -1, -1}, /* 19.2 MHz */
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+ {1165, 25, -1, -1, 5, 6, -1, -1, -1, -1}, /* 26 MHz */
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+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
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+ {1972, 64, -1, -1, 5, 6, -1, -1, -1, -1} /* 38.4 MHz */
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};
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/* ABE M & N values with sys_clk as source */
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static const struct dpll_params
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abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
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- {49, 5, 1, 1, -1, -1, -1, -1}, /* 12 MHz */
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- {68, 8, 1, 1, -1, -1, -1, -1}, /* 13 MHz */
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- {35, 5, 1, 1, -1, -1, -1, -1}, /* 16.8 MHz */
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- {46, 8, 1, 1, -1, -1, -1, -1}, /* 19.2 MHz */
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- {34, 8, 1, 1, -1, -1, -1, -1}, /* 26 MHz */
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- {29, 7, 1, 1, -1, -1, -1, -1}, /* 27 MHz */
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- {64, 24, 1, 1, -1, -1, -1, -1} /* 38.4 MHz */
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+ {49, 5, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
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+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
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+ {35, 5, 1, 1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
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+ {46, 8, 1, 1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
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+ {34, 8, 1, 1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
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+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
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+ {64, 24, 1, 1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
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};
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/* ABE M & N values with 32K clock as source */
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static const struct dpll_params abe_dpll_params_32k_196608khz = {
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- 750, 0, 1, 1, -1, -1, -1, -1
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+ 750, 0, 1, 1, -1, -1, -1, -1, -1, -1
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};
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static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
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- {80, 0, 2, -1, -1, -1, -1, -1}, /* 12 MHz */
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- {960, 12, 2, -1, -1, -1, -1, -1}, /* 13 MHz */
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- {400, 6, 2, -1, -1, -1, -1, -1}, /* 16.8 MHz */
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- {50, 0, 2, -1, -1, -1, -1, -1}, /* 19.2 MHz */
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- {480, 12, 2, -1, -1, -1, -1, -1}, /* 26 MHz */
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- {320, 8, 2, -1, -1, -1, -1, -1}, /* 27 MHz */
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- {25, 0, 2, -1, -1, -1, -1, -1} /* 38.4 MHz */
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+ {400, 4, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
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+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
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+ {400, 6, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
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+ {400, 7, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
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+ {480, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
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+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
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+ {400, 15, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
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};
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void setup_post_dividers(u32 *const base, const struct dpll_params *params)
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@@ -193,7 +213,7 @@ void setup_post_dividers(u32 *const base, const struct dpll_params *params)
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const struct dpll_params *get_mpu_dpll_params(void)
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{
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u32 sysclk_ind = get_sys_clk_index();
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- return &mpu_dpll_params_1100mhz[sysclk_ind];
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+ return &mpu_dpll_params_800mhz[sysclk_ind];
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}
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const struct dpll_params *get_core_dpll_params(void)
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@@ -201,8 +221,7 @@ const struct dpll_params *get_core_dpll_params(void)
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u32 sysclk_ind = get_sys_clk_index();
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/* Configuring the DDR to be at 532mhz */
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- return &core_dpll_params_2128mhz_ddr266[sysclk_ind];
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-
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+ return &core_dpll_params_2128mhz_ddr532[sysclk_ind];
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}
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const struct dpll_params *get_per_dpll_params(void)
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@@ -243,19 +262,33 @@ void scale_vcores(void)
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{
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u32 volt;
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- setup_sri2c();
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+ omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ);
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+
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+ /* Palmas settings */
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+ volt = VDD_CORE;
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+ do_scale_vcore(SMPS_REG_ADDR_8_CORE, volt);
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- /* Enable 1.22V from TPS for vdd_mpu */
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- volt = 1220;
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- do_scale_tps62361(TPS62361_REG_ADDR_SET1, volt);
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+ volt = VDD_MPU;
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+ do_scale_vcore(SMPS_REG_ADDR_12_MPU, volt);
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- /* VCORE 1 - for vdd_core */
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- volt = 1000;
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- do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt);
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+ volt = VDD_MM;
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+ do_scale_vcore(SMPS_REG_ADDR_45_IVA, volt);
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- /* VCORE 2 - for vdd_MM */
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- volt = 1125;
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- do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt);
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+}
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+
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+u32 get_offset_code(u32 volt_offset)
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+{
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+ u32 offset_code, step = 10000; /* 10 mV represented in uV */
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+
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+ volt_offset -= PALMAS_SMPS_BASE_VOLT_UV;
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+
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+ offset_code = (volt_offset + step - 1) / step;
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+
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+ /*
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+ * Offset codes 1-6 all give the base voltage in Palmas
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+ * Offset code 0 switches OFF the SMPS
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+ */
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+ return offset_code + 6;
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}
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/*
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@@ -306,6 +339,12 @@ void enable_basic_clocks(void)
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setbits_le32(&prcm->cm_l3init_hsmmc2_clkctrl,
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HSMMC_CLKCTRL_CLKSEL_MASK);
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+ /* Set the correct clock dividers for mmc */
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+ setbits_le32(&prcm->cm_l3init_hsmmc1_clkctrl,
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+ HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
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+ setbits_le32(&prcm->cm_l3init_hsmmc2_clkctrl,
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+ HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
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+
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/* Select 32KHz clock as the source of GPTIMER1 */
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setbits_le32(&prcm->cm_wkup_gptimer1_clkctrl,
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GPTIMER1_CLKCTRL_CLKSEL_MASK);
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@@ -314,6 +353,18 @@ void enable_basic_clocks(void)
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clk_modules_hw_auto_essential,
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clk_modules_explicit_en_essential,
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1);
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+
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+ /* Select 384Mhz for GPU as its the POR for ES1.0 */
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+ setbits_le32(&prcm->cm_sgx_sgx_clkctrl,
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+ CLKSEL_GPU_HYD_GCLK_MASK);
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+ setbits_le32(&prcm->cm_sgx_sgx_clkctrl,
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+ CLKSEL_GPU_CORE_GCLK_MASK);
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+
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+ /* Enable SCRM OPT clocks for PER and CORE dpll */
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+ setbits_le32(&prcm->cm_wkupaon_scrm_clkctrl,
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+ OPTFCLKEN_SCRM_PER_MASK);
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+ setbits_le32(&prcm->cm_wkupaon_scrm_clkctrl,
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+ OPTFCLKEN_SCRM_CORE_MASK);
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}
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void enable_basic_uboot_clocks(void)
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@@ -371,6 +422,7 @@ void enable_non_essential_clocks(void)
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&prcm->cm_l3instr_intrconn_wp1_clkctrl,
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&prcm->cm_l3init_hsi_clkctrl,
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&prcm->cm_l3init_hsusbtll_clkctrl,
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+ &prcm->cm_l4per_hdq1w_clkctrl,
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0
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};
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@@ -393,7 +445,6 @@ void enable_non_essential_clocks(void)
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&prcm->cm_l4per_gptimer11_clkctrl,
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&prcm->cm_l4per_gptimer3_clkctrl,
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&prcm->cm_l4per_gptimer4_clkctrl,
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- &prcm->cm_l4per_hdq1w_clkctrl,
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&prcm->cm_l4per_mcspi2_clkctrl,
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&prcm->cm_l4per_mcspi3_clkctrl,
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&prcm->cm_l4per_mcspi4_clkctrl,
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