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uboot-vybrid_pu...
/
arch
/
arm
/
include
/
asm
/
arch-exynos
/
power.h

power.h 7.6 KB
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  1. /*
    2. 

  2.  * Copyright (C) 2011 Samsung Electronics
    3. 

  3.  * Heungjun Kim <riverful.kim@samsung.com>
    4. 

  4.  *
    5. 

  5.  * See file CREDITS for list of people who contributed to this
    6. 

  6.  * project.
    7. 

  7.  *
    8. 

  8.  * This program is free software; you can redistribute it and/or
    9. 

  9.  * modify it under the terms of the GNU General Public License as
    10. 

  10.  * published by the Free Software Foundation; either version 2 of
    11. 

  11.  * the License, or (at your option) any later version.
    12. 

  12.  *
    13. 

  13.  * This program is distributed in the hope that it will be useful,
    14. 

  14.  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    15. 

  15.  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    16. 

  16.  * GNU General Public License for more details.
    17. 

  17.  *
    18. 

  18.  * You should have received a copy of the GNU General Public License
    19. 

  19.  * along with this program; if not, write to the Free Software
    20. 

  20.  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
    21. 

  21.  * MA 02111-1307 USA
    22. 

  22.  */
    23. 

  23. 

  24. #ifndef __ASM_ARM_ARCH_POWER_H_
    25. 

  25. #define __ASM_ARM_ARCH_POWER_H_
    26. 

  26. 

  27. #ifndef __ASSEMBLY__
    28. 

  28. struct exynos4_power {
    29. 

  29. 	unsigned int	om_stat;
    30. 

  30. 	unsigned char	res1[0x8];
    31. 

  31. 	unsigned int	rtc_clko_sel;
    32. 

  32. 	unsigned int	gnss_rtc_out_ctrl;
    33. 

  33. 	unsigned char	res2[0x1ec];
    34. 

  34. 	unsigned int	system_power_down_ctrl;
    35. 

  35. 	unsigned char	res3[0x1];
    36. 

  36. 	unsigned int	system_power_down_option;
    37. 

  37. 	unsigned char	res4[0x1f4];
    38. 

  38. 	unsigned int	swreset;
    39. 

  39. 	unsigned int	rst_stat;
    40. 

  40. 	unsigned char	res5[0x1f8];
    41. 

  41. 	unsigned int	wakeup_stat;
    42. 

  42. 	unsigned int	eint_wakeup_mask;
    43. 

  43. 	unsigned int	wakeup_mask;
    44. 

  44. 	unsigned char	res6[0xf4];
    45. 

  45. 	unsigned int	hdmi_phy_control;
    46. 

  46. 	unsigned int	usbdevice_phy_control;
    47. 

  47. 	unsigned int	usbhost_phy_control;
    48. 

  48. 	unsigned int	dac_phy_control;
    49. 

  49. 	unsigned int	mipi_phy0_control;
    50. 

  50. 	unsigned int	mipi_phy1_control;
    51. 

  51. 	unsigned int	adc_phy_control;
    52. 

  52. 	unsigned int	pcie_phy_control;
    53. 

  53. 	unsigned int	sata_phy_control;
    54. 

  54. 	unsigned char	res7[0xdc];
    55. 

  55. 	unsigned int	inform0;
    56. 

  56. 	unsigned int	inform1;
    57. 

  57. 	unsigned int	inform2;
    58. 

  58. 	unsigned int	inform3;
    59. 

  59. 	unsigned int	inform4;
    60. 

  60. 	unsigned int	inform5;
    61. 

  61. 	unsigned int	inform6;
    62. 

  62. 	unsigned int	inform7;
    63. 

  63. 	unsigned char	res8[0x1e0];
    64. 

  64. 	unsigned int	pmu_debug;
    65. 

  65. 	unsigned char	res9[0x5fc];
    66. 

  66. 	unsigned int	arm_core0_sys_pwr_reg;
    67. 

  67. 	unsigned char	res10[0xc];
    68. 

  68. 	unsigned int	arm_core1_sys_pwr_reg;
    69. 

  69. 	unsigned char	res11[0x6c];
    70. 

  70. 	unsigned int	arm_common_sys_pwr_reg;
    71. 

  71. 	unsigned char	res12[0x3c];
    72. 

  72. 	unsigned int	arm_cpu_l2_0_sys_pwr_reg;
    73. 

  73. 	unsigned int	arm_cpu_l2_1_sys_pwr_reg;
    74. 

  74. 	unsigned char	res13[0x38];
    75. 

  75. 	unsigned int	cmu_aclkstop_sys_pwr_reg;
    76. 

  76. 	unsigned int	cmu_sclkstop_sys_pwr_reg;
    77. 

  77. 	unsigned char	res14[0x4];
    78. 

  78. 	unsigned int	cmu_reset_sys_pwr_reg;
    79. 

  79. 	unsigned char	res15[0x10];
    80. 

  80. 	unsigned int	apll_sysclk_sys_pwr_reg;
    81. 

  81. 	unsigned int	mpll_sysclk_sys_pwr_reg;
    82. 

  82. 	unsigned int	vpll_sysclk_sys_pwr_reg;
    83. 

  83. 	unsigned int	epll_sysclk_sys_pwr_reg;
    84. 

  84. 	unsigned char	res16[0x8];
    85. 

  85. 	unsigned int	cmu_clkstop_gps_alive_sys_pwr_reg;
    86. 

  86. 	unsigned int	cmu_reset_gps_alive_sys_pwr_reg;
    87. 

  87. 	unsigned int	cmu_clkstop_cam_sys_pwr_reg;
    88. 

  88. 	unsigned int	cmu_clkstop_tv_sys_pwr_reg;
    89. 

  89. 	unsigned int	cmu_clkstop_mfc_sys_pwr_reg;
    90. 

  90. 	unsigned int	cmu_clkstop_g3d_sys_pwr_reg;
    91. 

  91. 	unsigned int	cmu_clkstop_lcd0_sys_pwr_reg;
    92. 

  92. 	unsigned int	cmu_clkstop_lcd1_sys_pwr_reg;
    93. 

  93. 	unsigned int	cmu_clkstop_maudio_sys_pwr_reg;
    94. 

  94. 	unsigned int	cmu_clkstop_gps_sys_pwr_reg;
    95. 

  95. 	unsigned int	cmu_reset_cam_sys_pwr_reg;
    96. 

  96. 	unsigned int	cmu_reset_tv_sys_pwr_reg;
    97. 

  97. 	unsigned int	cmu_reset_mfc_sys_pwr_reg;
    98. 

  98. 	unsigned int	cmu_reset_g3d_sys_pwr_reg;
    99. 

  99. 	unsigned int	cmu_reset_lcd0_sys_pwr_reg;
    100. 

  100. 	unsigned int	cmu_reset_lcd1_sys_pwr_reg;
    101. 

  101. 	unsigned int	cmu_reset_maudio_sys_pwr_reg;
    102. 

  102. 	unsigned int	cmu_reset_gps_sys_pwr_reg;
    103. 

  103. 	unsigned int	top_bus_sys_pwr_reg;
    104. 

  104. 	unsigned int	top_retention_sys_pwr_reg;
    105. 

  105. 	unsigned int	top_pwr_sys_pwr_reg;
    106. 

  106. 	unsigned char	res17[0x1c];
    107. 

  107. 	unsigned int	logic_reset_sys_pwr_reg;
    108. 

  108. 	unsigned char	res18[0x14];
    109. 

  109. 	unsigned int	onenandxl_mem_sys_pwr_reg;
    110. 

  110. 	unsigned int	modemif_mem_sys_pwr_reg;
    111. 

  111. 	unsigned char	res19[0x4];
    112. 

  112. 	unsigned int	usbdevice_mem_sys_pwr_reg;
    113. 

  113. 	unsigned int	sdmmc_mem_sys_pwr_reg;
    114. 

  114. 	unsigned int	cssys_mem_sys_pwr_reg;
    115. 

  115. 	unsigned int	secss_mem_sys_pwr_reg;
    116. 

  116. 	unsigned char	res20[0x4];
    117. 

  117. 	unsigned int	pcie_mem_sys_pwr_reg;
    118. 

  118. 	unsigned int	sata_mem_sys_pwr_reg;
    119. 

  119. 	unsigned char	res21[0x18];
    120. 

  120. 	unsigned int	pad_retention_dram_sys_pwr_reg;
    121. 

  121. 	unsigned int	pad_retention_maudio_sys_pwr_reg;
    122. 

  122. 	unsigned char	res22[0x18];
    123. 

  123. 	unsigned int	pad_retention_gpio_sys_pwr_reg;
    124. 

  124. 	unsigned int	pad_retention_uart_sys_pwr_reg;
    125. 

  125. 	unsigned int	pad_retention_mmca_sys_pwr_reg;
    126. 

  126. 	unsigned int	pad_retention_mmcb_sys_pwr_reg;
    127. 

  127. 	unsigned int	pad_retention_ebia_sys_pwr_reg;
    128. 

  128. 	unsigned int	pad_retention_ebib_sys_pwr_reg;
    129. 

  129. 	unsigned char	res23[0x8];
    130. 

  130. 	unsigned int	pad_isolation_sys_pwr_reg;
    131. 

  131. 	unsigned char	res24[0x1c];
    132. 

  132. 	unsigned int	pad_alv_sel_sys_pwr_reg;
    133. 

  133. 	unsigned char	res25[0x1c];
    134. 

  134. 	unsigned int	xusbxti_sys_pwr_reg;
    135. 

  135. 	unsigned int	xxti_sys_pwr_reg;
    136. 

  136. 	unsigned char	res26[0x38];
    137. 

  137. 	unsigned int	ext_regulator_sys_pwr_reg;
    138. 

  138. 	unsigned char	res27[0x3c];
    139. 

  139. 	unsigned int	gpio_mode_sys_pwr_reg;
    140. 

  140. 	unsigned char	res28[0x3c];
    141. 

  141. 	unsigned int	gpio_mode_maudio_sys_pwr_reg;
    142. 

  142. 	unsigned char	res29[0x3c];
    143. 

  143. 	unsigned int	cam_sys_pwr_reg;
    144. 

  144. 	unsigned int	tv_sys_pwr_reg;
    145. 

  145. 	unsigned int	mfc_sys_pwr_reg;
    146. 

  146. 	unsigned int	g3d_sys_pwr_reg;
    147. 

  147. 	unsigned int	lcd0_sys_pwr_reg;
    148. 

  148. 	unsigned int	lcd1_sys_pwr_reg;
    149. 

  149. 	unsigned int	maudio_sys_pwr_reg;
    150. 

  150. 	unsigned int	gps_sys_pwr_reg;
    151. 

  151. 	unsigned int	gps_alive_sys_pwr_reg;
    152. 

  152. 	unsigned char	res30[0xc5c];
    153. 

  153. 	unsigned int	arm_core0_configuration;
    154. 

  154. 	unsigned int	arm_core0_status;
    155. 

  155. 	unsigned int	arm_core0_option;
    156. 

  156. 	unsigned char	res31[0x74];
    157. 

  157. 	unsigned int	arm_core1_configuration;
    158. 

  158. 	unsigned int	arm_core1_status;
    159. 

  159. 	unsigned int	arm_core1_option;
    160. 

  160. 	unsigned char	res32[0x37c];
    161. 

  161. 	unsigned int	arm_common_option;
    162. 

  162. 	unsigned char	res33[0x1f4];
    163. 

  163. 	unsigned int	arm_cpu_l2_0_configuration;
    164. 

  164. 	unsigned int	arm_cpu_l2_0_status;
    165. 

  165. 	unsigned char	res34[0x18];
    166. 

  166. 	unsigned int	arm_cpu_l2_1_configuration;
    167. 

  167. 	unsigned int	arm_cpu_l2_1_status;
    168. 

  168. 	unsigned char	res35[0xa00];
    169. 

  169. 	unsigned int	pad_retention_maudio_option;
    170. 

  170. 	unsigned char	res36[0xdc];
    171. 

  171. 	unsigned int	pad_retention_gpio_option;
    172. 

  172. 	unsigned char	res37[0x1c];
    173. 

  173. 	unsigned int	pad_retention_uart_option;
    174. 

  174. 	unsigned char	res38[0x1c];
    175. 

  175. 	unsigned int	pad_retention_mmca_option;
    176. 

  176. 	unsigned char	res39[0x1c];
    177. 

  177. 	unsigned int	pad_retention_mmcb_option;
    178. 

  178. 	unsigned char	res40[0x1c];
    179. 

  179. 	unsigned int	pad_retention_ebia_option;
    180. 

  180. 	unsigned char	res41[0x1c];
    181. 

  181. 	unsigned int	pad_retention_ebib_option;
    182. 

  182. 	unsigned char	res42[0x160];
    183. 

  183. 	unsigned int	ps_hold_control;
    184. 

  184. 	unsigned char	res43[0xf0];
    185. 

  185. 	unsigned int	xusbxti_configuration;
    186. 

  186. 	unsigned int	xusbxti_status;
    187. 

  187. 	unsigned char	res44[0x14];
    188. 

  188. 	unsigned int	xusbxti_duration;
    189. 

  189. 	unsigned int	xxti_configuration;
    190. 

  190. 	unsigned int	xxti_status;
    191. 

  191. 	unsigned char	res45[0x14];
    192. 

  192. 	unsigned int	xxti_duration;
    193. 

  193. 	unsigned char	res46[0x1dc];
    194. 

  194. 	unsigned int	ext_regulator_duration;
    195. 

  195. 	unsigned char	res47[0x5e0];
    196. 

  196. 	unsigned int	cam_configuration;
    197. 

  197. 	unsigned int	cam_status;
    198. 

  198. 	unsigned int	cam_option;
    199. 

  199. 	unsigned char	res48[0x14];
    200. 

  200. 	unsigned int	tv_configuration;
    201. 

  201. 	unsigned int	tv_status;
    202. 

  202. 	unsigned int	tv_option;
    203. 

  203. 	unsigned char	res49[0x14];
    204. 

  204. 	unsigned int	mfc_configuration;
    205. 

  205. 	unsigned int	mfc_status;
    206. 

  206. 	unsigned int	mfc_option;
    207. 

  207. 	unsigned char	res50[0x14];
    208. 

  208. 	unsigned int	g3d_configuration;
    209. 

  209. 	unsigned int	g3d_status;
    210. 

  210. 	unsigned int	g3d_option;
    211. 

  211. 	unsigned char	res51[0x14];
    212. 

  212. 	unsigned int	lcd0_configuration;
    213. 

  213. 	unsigned int	lcd0_status;
    214. 

  214. 	unsigned int	lcd0_option;
    215. 

  215. 	unsigned char	res52[0x14];
    216. 

  216. 	unsigned int	lcd1_configuration;
    217. 

  217. 	unsigned int	lcd1_status;
    218. 

  218. 	unsigned int	lcd1_option;
    219. 

  219. 	unsigned char	res53[0x34];
    220. 

  220. 	unsigned int	gps_configuration;
    221. 

  221. 	unsigned int	gps_status;
    222. 

  222. 	unsigned int	gps_option;
    223. 

  223. 	unsigned char	res54[0x14];
    224. 

  224. 	unsigned int	gps_alive_configuration;
    225. 

  225. 	unsigned int	gps_alive_status;
    226. 

  226. 	unsigned int	gps_alive_option;
    227. 

  227. };
    228. 

  228. #endif	/* __ASSEMBLY__ */
    229. 

  229. 

  230. void set_mipi_phy_ctrl(unsigned int dev_index, unsigned int enable);
    231. 

  231. 

  232. #define EXYNOS_MIPI_PHY_ENABLE		(1 << 0)
    233. 

  233. #define EXYNOS_MIPI_PHY_SRESETN		(1 << 1)
    234. 

  234. #define EXYNOS_MIPI_PHY_MRESETN		(1 << 2)
    235. 

  235. 

  236. #endif
    237.