Add PCI support for Sorcery board.

Code cleanup (especially Sorcery / Alaska / Yukon serial driver).

CHANGELOG

@@ -2,6 +2,9 @@
 Changes for U-Boot 1.1.3:
 ======================================================================
 
+* Add PCI support for Sorcery board.
+  Code cleanup (especially Sorcery / Alaska / Yukon serial driver).
+
 * Fix compile problems caused by new burst mode SDRAM test;
   make port pins to trigger logic analyzer configurable
 

board/alaska/Makefile

@@ -24,7 +24,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= lib$(BOARD).a
 
-OBJS	:= $(BOARD).o flash.o extserial.o
+OBJS	:= $(BOARD).o flash.o
 
 $(LIB):	$(OBJS) $(SOBJS)
 	$(AR) crv $@ $(OBJS)

board/alaska/extserial.c

@@ -1,110 +0,0 @@
-/*
- * (C) Copyright 2004, Freescale, Inc
- * TsiChung Liew, Tsi-Chung.Liew@freescale.com.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-
-/*
- * Minimal serial functions needed to use one of the PSC ports
- * as serial console interface.
- */
-
-#include <common.h>
-#include <mpc8220.h>
-
-#if defined (CONFIG_EXTUART_CONSOLE)
-#   include <ns16550.h>
-
-#   define PADSERIAL_BAUD_115200   0x40
-#   define PADSERIAL_BAUD_57600    0x20
-#   define PADSERIAL_BAUD_9600     0
-#   define PADCARD_FREQ            18432000
-
-const NS16550_t com_port = (NS16550_t) CFG_NS16550_COM1;
-
-int ext_serial_init (void)
-{
-	DECLARE_GLOBAL_DATA_PTR;
-	volatile u8 *dipswitch = (volatile u8 *) (CFG_CPLD_BASE + 0x1002);
-	int baud_divisor;
-
-	/* Find out the baud rate speed on debug card dip switches */
-	if (*dipswitch & PADSERIAL_BAUD_115200)
-		gd->baudrate = 115200;
-	else if (*dipswitch & PADSERIAL_BAUD_57600)
-		gd->baudrate = 57600;
-	else
-		gd->baudrate = 9600;
-
-	/* Debug card frequency */
-	baud_divisor = PADCARD_FREQ / (16 * gd->baudrate);
-
-	NS16550_init (com_port, baud_divisor);
-
-	return (0);
-}
-
-void ext_serial_putc (const char c)
-{
-	if (c == '\n')
-		NS16550_putc (com_port, '\r');
-
-	NS16550_putc (com_port, c);
-}
-
-void ext_serial_puts (const char *s)
-{
-	while (*s) {
-		serial_putc (*s++);
-	}
-}
-
-int ext_serial_getc (void)
-{
-	return NS16550_getc (com_port);
-}
-
-int ext_serial_tstc (void)
-{
-	return NS16550_tstc (com_port);
-}
-
-void ext_serial_setbrg (void)
-{
-	DECLARE_GLOBAL_DATA_PTR;
-
-	volatile u8 *dipswitch = (volatile u8 *) (CFG_CPLD_BASE + 0x1002);
-	int baud_divisor;
-
-	/* Find out the baud rate speed on debug card dip switches */
-	if (*dipswitch & PADSERIAL_BAUD_115200)
-		gd->baudrate = 115200;
-	else if (*dipswitch & PADSERIAL_BAUD_57600)
-		gd->baudrate = 57600;
-	else
-		gd->baudrate = 9600;
-
-	/* Debug card frequency */
-	baud_divisor = PADCARD_FREQ / (16 * gd->baudrate);
-
-	NS16550_reinit (com_port, baud_divisor);
-}
-#endif /* CONFIG_EXTUART_CONSOLE */

board/sorcery/sorcery.c

@@ -25,6 +25,7 @@
 #include <mpc8220.h>
 #include <asm/processor.h>
 #include <asm/mmu.h>
+#include <pci.h>
 
 long int initdram (int board_type)
 {
@@ -41,3 +42,19 @@ int checkboard (void)
 
 	return 0;
 }
+
+#if defined(CONFIG_PCI)
+/*
+ * Initialize PCI devices, report devices found.
+ */
+static struct pci_controller hose;
+
+#endif /* CONFIG_PCI */
+
+void pci_init_board (void)
+{
+#ifdef CONFIG_PCI
+	extern void pci_mpc8220_init (struct pci_controller *hose);
+	pci_mpc8220_init (&hose);
+#endif /* CONFIG_PCI */
+}

cpu/mpc8220/Makefile

@@ -28,8 +28,8 @@ LIB	= lib$(CPU).a
 START	= start.o
 ASOBJS	= io.o fec_dma_tasks.o
 OBJS	= cpu.o cpu_init.o dramSetup.o fec.o i2c.o \
-	  interrupts.o loadtask.o serial.o speed.o \
-	  traps.o uart.o
+	  interrupts.o loadtask.o speed.o \
+	  traps.o uart.o pci.o
 
 all:	.depend $(START) $(ASOBJS) $(LIB)
 

cpu/mpc8220/cpu_init.c

@@ -49,6 +49,8 @@ void cpu_init_f (void)
 	portcfg->pcfg1 = 0;
 	portcfg->pcfg2 = 0;
 	portcfg->pcfg3 = 0;
+	portcfg->pcfg2 = CFG_GP1_PORT2_CONFIG;
+	portcfg->pcfg3 = CFG_PCI_PORT3_CONFIG | CFG_GP2_PORT3_CONFIG;
 
 	/*
 	 * Flexbus Controller: configure chip selects and enable them
@@ -109,7 +111,7 @@ void cpu_init_f (void)
 
 	/* Master Priority Enable */
 	xlbarb->mastPriority = 0;
-	xlbarb->mastPriEn = 0x1f;
+	xlbarb->mastPriEn = 0xff;
 }
 
 /*

cpu/mpc8220/dramSetup.c

@@ -543,12 +543,7 @@ u32 dramSetup (void)
 	}
 
 	/* Set up the Drive Strength register */
-	temp = ((DRIVE_STRENGTH_LOW << SDRAMDS_SBE_SHIFT)
-		| (DRIVE_STRENGTH_HIGH << SDRAMDS_SBC_SHIFT)
-		| (DRIVE_STRENGTH_LOW << SDRAMDS_SBA_SHIFT)
-		| (DRIVE_STRENGTH_OFF << SDRAMDS_SBS_SHIFT)
-		| (DRIVE_STRENGTH_LOW << SDRAMDS_SBD_SHIFT));
-	sysconf->sdramds = temp;
+	sysconf->sdramds = CFG_SDRAM_DRIVE_STRENGTH;
 
 	/* ********************** Cfg 1 ************************* */
 

cpu/mpc8220/fec.c

@@ -15,11 +15,10 @@
 #include "fec.h"
 
 #define DEBUG	0
-/*tbd - rtm */
-/*#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \
-    defined(CONFIG_MPC8220_FEC)*/
+#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \
+    defined(CONFIG_MPC8220_FEC)
 
-#if (CONFIG_COMMANDS & CFG_CMD_NET)
+/*#if (CONFIG_COMMANDS & CFG_CMD_NET)*/
 
 #if (DEBUG & 0x60)
 static void tfifo_print (mpc8220_fec_priv * fec);

cpu/mpc8220/pci.c

@@ -0,0 +1,191 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ * Copyright (C) 2003 Motorola Inc.
+ * Xianghua Xiao (x.xiao@motorola.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * PCI Configuration space access support for MPC8220 PCI Bridge
+ */
+#include <common.h>
+#include <mpc8220.h>
+#include <pci.h>
+#include <asm/io.h>
+
+#if defined(CONFIG_PCI)
+
+/* System RAM mapped over PCI */
+#define CONFIG_PCI_SYS_MEM_BUS	 CFG_SDRAM_BASE
+#define CONFIG_PCI_SYS_MEM_PHYS	 CFG_SDRAM_BASE
+#define CONFIG_PCI_SYS_MEM_SIZE	 (1024 * 1024 * 1024)
+
+#define cfg_read(val, addr, type, op)		*val = op((type)(addr));
+#define cfg_write(val, addr, type, op)		op((type *)(addr), (val));
+
+#define PCI_OP(rw, size, type, op, mask)				\
+int mpc8220_pci_##rw##_config_##size(struct pci_controller *hose,	\
+	pci_dev_t dev, int offset, type val)				\
+{									\
+	u32 addr = 0;							\
+	u16 cfg_type = 0;						\
+	addr = ((offset & 0xfc) | cfg_type | (dev)  | 0x80000000);	\
+	out_be32(hose->cfg_addr, addr);					\
+	__asm__ __volatile__("sync");					\
+	cfg_##rw(val, hose->cfg_data + (offset & mask), type, op);	\
+	out_be32(hose->cfg_addr, addr & 0x7fffffff);			\
+	__asm__ __volatile__("sync");					\
+	return 0;							\
+}
+
+PCI_OP(read, byte, u8 *, in_8, 3)
+PCI_OP(read, word, u16 *, in_le16, 2)
+PCI_OP(write, byte, u8, out_8, 3)
+PCI_OP(write, word, u16, out_le16, 2)
+PCI_OP(write, dword, u32, out_le32, 0)
+
+int mpc8220_pci_read_config_dword(struct pci_controller *hose, pci_dev_t dev,
+	int offset, u32 *val)
+{
+	u32 addr;
+	u32 tmpv;
+	u32 mask = 2;	 /* word access */
+	/* Read lower 16 bits */
+	addr = ((offset & 0xfc) | (dev) | 0x80000000);
+	out_be32(hose->cfg_addr, addr);
+	__asm__ __volatile__("sync");
+	*val = (u32) in_le16((u16 *) (hose->cfg_data + (offset & mask)));
+	out_be32(hose->cfg_addr, addr & 0x7fffffff);
+	__asm__ __volatile__("sync");
+
+	/* Read upper 16 bits */
+	offset += 2;
+	addr = ((offset & 0xfc) | 1 | (dev) | 0x80000000);
+	out_be32(hose->cfg_addr, addr);
+	__asm__ __volatile__("sync");
+	tmpv = (u32) in_le16((u16 *) (hose->cfg_data + (offset & mask)));
+	out_be32(hose->cfg_addr, addr & 0x7fffffff);
+	__asm__ __volatile__("sync");
+
+	/* combine results into dword value */
+	*val = (tmpv << 16) | *val;
+
+	return 0;
+}
+
+void
+pci_mpc8220_init(struct pci_controller *hose)
+{
+	u32 win0, win1, win2;
+	volatile mpc8220_xcpci_t *xcpci =
+		(volatile mpc8220_xcpci_t *) MMAP_XCPCI;
+
+	volatile pcfg8220_t *portcfg = (volatile pcfg8220_t *) MMAP_PCFG;
+
+	win0 = (u32) CONFIG_PCI_MEM_PHYS;
+	win1 = (u32) CONFIG_PCI_IO_PHYS;
+	win2 = (u32) CONFIG_PCI_CFG_PHYS;
+
+	/* Assert PCI reset */
+	out_be32 (&xcpci->glb_stat_ctl, PCI_GLB_STAT_CTRL_PR);
+
+	/* Disable prefetching but read-multiples will still prefetch */
+	out_be32 (&xcpci->target_ctrl, 0x00000000);
+
+	/* Initiator windows */
+	out_be32 (&xcpci->init_win0,  (win0 >> 16) | win0 | 0x003f0000);
+	out_be32 (&xcpci->init_win1, ((win1 >> 16) | win1 ));
+	out_be32 (&xcpci->init_win2, ((win2 >> 16) | win2 ));
+
+	out_be32 (&xcpci->init_win_cfg,
+		PCI_INIT_WIN_CFG_WIN0_CTRL_EN |
+		PCI_INIT_WIN_CFG_WIN1_CTRL_EN | PCI_INIT_WIN_CFG_WIN1_CTRL_IO |
+		PCI_INIT_WIN_CFG_WIN2_CTRL_EN | PCI_INIT_WIN_CFG_WIN2_CTRL_IO);
+
+	out_be32 (&xcpci->init_ctrl, 0x00000000);
+
+	/* Enable bus master and mem access */
+	out_be32 (&xcpci->stat_cmd_reg, PCI_STAT_CMD_B | PCI_STAT_CMD_M);
+
+	/* Cache line size and master latency */
+	out_be32 (&xcpci->bist_htyp_lat_cshl, (0xf8 << PCI_CFG1_LT_SHIFT));
+
+	out_be32 (&xcpci->base0, PCI_BASE_ADDR_REG0); /* 256MB - MBAR space */
+	out_be32 (&xcpci->base1, PCI_BASE_ADDR_REG1); /* 1GB - SDRAM space */
+
+	out_be32 (&xcpci->target_bar0,
+		PCI_TARGET_BASE_ADDR_REG0 | PCI_TARGET_BASE_ADDR_EN);
+	out_be32 (&xcpci->target_bar1,
+		PCI_TARGET_BASE_ADDR_REG1 | PCI_TARGET_BASE_ADDR_EN);
+
+	/* Deassert reset bit */
+	out_be32 (&xcpci->glb_stat_ctl, 0x00000000);
+
+	/* Enable PCI bus master support */
+	/* Set PCIGNT1, PCIREQ1, PCIREQ0/PCIGNTIN, PCIGNT0/PCIREQOUT,
+	       PCIREQ2, PCIGNT2 */
+	out_be32((volatile u32 *)&portcfg->pcfg3,
+		(in_be32((volatile u32 *)&portcfg->pcfg3) & 0xFC3FCE7F));
+	out_be32((volatile u32 *)&portcfg->pcfg3,
+		(in_be32((volatile u32 *)&portcfg->pcfg3) | 0x01400180));
+
+	hose->first_busno = 0;
+	hose->last_busno = 0xff;
+
+	pci_set_region(hose->regions + 0,
+		CONFIG_PCI_MEM_BUS,
+		CONFIG_PCI_MEM_PHYS,
+		CONFIG_PCI_MEM_SIZE,
+		PCI_REGION_MEM);
+
+	pci_set_region(hose->regions + 1,
+		CONFIG_PCI_IO_BUS,
+		CONFIG_PCI_IO_PHYS,
+		CONFIG_PCI_IO_SIZE,
+		PCI_REGION_IO);
+
+	pci_set_region(hose->regions + 2,
+		CONFIG_PCI_SYS_MEM_BUS,
+		CONFIG_PCI_SYS_MEM_PHYS,
+		CONFIG_PCI_SYS_MEM_SIZE,
+		PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+	hose->region_count = 3;
+
+	hose->cfg_addr = &(xcpci->cfg_adr);
+	hose->cfg_data = CONFIG_PCI_CFG_BUS;
+
+	pci_set_ops(hose,
+		mpc8220_pci_read_config_byte,
+		mpc8220_pci_read_config_word,
+		mpc8220_pci_read_config_dword,
+		mpc8220_pci_write_config_byte,
+		mpc8220_pci_write_config_word,
+		mpc8220_pci_write_config_dword);
+
+	/* Hose scan */
+	pci_register_hose(hose);
+	hose->last_busno = pci_hose_scan(hose);
+
+	out_be32 (&xcpci->base0, PCI_BASE_ADDR_REG0); /* 256MB - MBAR space */
+	out_be32 (&xcpci->base1, PCI_BASE_ADDR_REG1); /* 1GB - SDRAM space */
+}
+
+#endif /* CONFIG_PCI */

cpu/mpc8220/serial.c

@@ -1,131 +0,0 @@
-/*
- * (C) Copyright 2004, Freescale, Inc
- * TsiChung Liew, Tsi-Chung.Liew@freescale.com.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-
-/*
- * Minimal serial functions needed to use one of the PSC ports
- * as serial console interface.
- */
-
-#include <common.h>
-#include <mpc8220.h>
-
-int serial_init (void)
-{
-	DECLARE_GLOBAL_DATA_PTR;
-
-#if defined (CONFIG_EXTUART_CONSOLE)
-	volatile uchar *cpld = (volatile uchar *) CFG_CPLD_BASE;
-#endif
-
-	/* Check CPLD Switch 2 whether is external or internal */
-#if defined (CONFIG_EXTUART_CONSOLE)
-	if ((*cpld & 0x02) == 0x02) {
-		gd->bExtUart = 1;
-		return ext_serial_init ();
-	} else
-#endif
-	{
-#if defined(CONFIG_PSC_CONSOLE)
-		gd->bExtUart = 0;
-		return psc_serial_init ();
-#endif
-	}
-
-	return (0);
-}
-
-void serial_putc (const char c)
-{
-	DECLARE_GLOBAL_DATA_PTR;
-
-	if (gd->bExtUart) {
-#if defined (CONFIG_EXTUART_CONSOLE)
-		ext_serial_putc (c);
-#endif
-	} else {
-#if defined(CONFIG_PSC_CONSOLE)
-		psc_serial_putc (c);
-#endif
-	}
-}
-
-void serial_puts (const char *s)
-{
-	DECLARE_GLOBAL_DATA_PTR;
-
-	if (gd->bExtUart) {
-#if defined (CONFIG_EXTUART_CONSOLE)
-		ext_serial_puts (s);
-#endif
-	} else {
-#if defined(CONFIG_PSC_CONSOLE)
-		psc_serial_puts (s);
-#endif
-	}
-}
-
-int serial_getc (void)
-{
-	DECLARE_GLOBAL_DATA_PTR;
-
-	if (gd->bExtUart) {
-#if defined (CONFIG_EXTUART_CONSOLE)
-		return ext_serial_getc ();
-#endif
-	} else {
-#if defined(CONFIG_PSC_CONSOLE)
-		return psc_serial_getc ();
-#endif
-	}
-}
-
-int serial_tstc (void)
-{
-	DECLARE_GLOBAL_DATA_PTR;
-
-	if (gd->bExtUart) {
-#if defined (CONFIG_EXTUART_CONSOLE)
-		return ext_serial_tstc ();
-#endif
-	} else {
-#if defined(CONFIG_PSC_CONSOLE)
-		return psc_serial_tstc ();
-#endif
-	}
-}
-
-void serial_setbrg (void)
-{
-	DECLARE_GLOBAL_DATA_PTR;
-
-	if (gd->bExtUart) {
-#if defined (CONFIG_EXTUART_CONSOLE)
-		ext_serial_setbrg ();
-#endif
-	} else {
-#if defined(CONFIG_PSC_CONSOLE)
-		psc_serial_setbrg ();
-#endif
-	}
-}

cpu/mpc8220/uart.c

@@ -33,7 +33,7 @@
 #define PSC_BASE   MMAP_PSC1
 
 #if defined(CONFIG_PSC_CONSOLE)
-int psc_serial_init (void)
+int serial_init (void)
 {
 	DECLARE_GLOBAL_DATA_PTR;
 	volatile psc8220_t *psc = (psc8220_t *) PSC_BASE;
@@ -68,7 +68,7 @@ int psc_serial_init (void)
 	return (0);
 }
 
-void psc_serial_putc (const char c)
+void serial_putc (const char c)
 {
 	volatile psc8220_t *psc = (psc8220_t *) PSC_BASE;
 
@@ -81,14 +81,14 @@ void psc_serial_putc (const char c)
 	psc->xmitbuf[0] = c;
 }
 
-void psc_serial_puts (const char *s)
+void serial_puts (const char *s)
 {
 	while (*s) {
 		serial_putc (*s++);
 	}
 }
 
-int psc_serial_getc (void)
+int serial_getc (void)
 {
 	volatile psc8220_t *psc = (psc8220_t *) PSC_BASE;
 
@@ -97,14 +97,14 @@ int psc_serial_getc (void)
 	return psc->xmitbuf[2];
 }
 
-int psc_serial_tstc (void)
+int serial_tstc (void)
 {
 	volatile psc8220_t *psc = (psc8220_t *) PSC_BASE;
 
 	return (psc->sr_csr & PSC_SR_RXRDY);
 }
 
-void psc_serial_setbrg (void)
+void serial_setbrg (void)
 {
 	DECLARE_GLOBAL_DATA_PTR;
 

drivers/cfi_flash.c

@@ -189,6 +189,7 @@ static ulong flash_get_size (ulong base, int banknum);
 static int flash_write_cfiword (flash_info_t * info, ulong dest, cfiword_t cword);
 static int flash_full_status_check (flash_info_t * info, flash_sect_t sector,
 				    ulong tout, char *prompt);
+static flash_info_t *flash_get_info(ulong base);
 #ifdef CFG_FLASH_USE_BUFFER_WRITE
 static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp, int len);
 #endif
@@ -341,8 +342,8 @@ unsigned long flash_init (void)
 #if (CFG_MONITOR_BASE >= CFG_FLASH_BASE)
 	flash_protect (FLAG_PROTECT_SET,
 		       CFG_MONITOR_BASE,
-		       CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
-		       &flash_info[0]);
+		       CFG_MONITOR_BASE + monitor_flash_len  - 1,
+		       flash_get_info(CFG_MONITOR_BASE));
 #endif
 
 	/* Environment protection ON by default */
@@ -350,7 +351,7 @@ unsigned long flash_init (void)
 	flash_protect (FLAG_PROTECT_SET,
 		       CFG_ENV_ADDR,
 		       CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
-		       &flash_info[0]);
+		       flash_get_info(CFG_ENV_ADDR));
 #endif
 
 	/* Redundant environment protection ON by default */
@@ -358,11 +359,28 @@ unsigned long flash_init (void)
 	flash_protect (FLAG_PROTECT_SET,
 		       CFG_ENV_ADDR_REDUND,
 		       CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1,
-		       &flash_info[0]);
+		       flash_get_info(CFG_ENV_ADDR_REDUND));
 #endif
 	return (size);
 }
 
+/*-----------------------------------------------------------------------
+ */
+static flash_info_t *flash_get_info(ulong base)
+{
+	int i;
+	flash_info_t * info;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) {
+		info = & flash_info[i];
+		if (info->size && info->start[0] <= base &&
+		    base <= info->start[0] + info->size - 1)
+			break;
+	}
+
+	return i == CFG_MAX_FLASH_BANKS ? 0 : info;
+}
+
 /*-----------------------------------------------------------------------
  */
 int flash_erase (flash_info_t * info, int s_first, int s_last)

include/configs/Alaska8220.h

@@ -48,38 +48,45 @@
 /*
  * Serial console configuration
  */
-#define CONFIG_PSC_CONSOLE	1	/* console is on PSC */
+
+/* Define this for PSC console
+#define CONFIG_PSC_CONSOLE	1
+*/
+
 #define CONFIG_EXTUART_CONSOLE	1
 
 #ifdef CONFIG_EXTUART_CONSOLE
+#   define CONFIG_CONS_INDEX	1
+#   define CFG_NS16550_SERIAL
 #   define CFG_NS16550
 #   define CFG_NS16550_REG_SIZE 1
 #   define CFG_NS16550_COM1	(CFG_CPLD_BASE + 0x1008)
+#   define CFG_NS16550_CLK	18432000
 #endif
 
 #define CONFIG_BAUDRATE		115200	    /* ... at 115200 bps */
 
 #define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
-#define	CONFIG_TIMESTAMP			/* Print image info with timestamp */
+#define CONFIG_TIMESTAMP			/* Print image info with timestamp */
 
 /*
  * Supported commands
  */
-#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL  | \
-				CFG_CMD_BOOTD   | \
-				CFG_CMD_CACHE   | \
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_BOOTD	| \
+				CFG_CMD_CACHE	| \
 				CFG_CMD_DHCP	| \
-				CFG_CMD_DIAG    | \
-				CFG_CMD_EEPROM  | \
-				CFG_CMD_ELF     | \
-				CFG_CMD_I2C     | \
-				CFG_CMD_NET     | \
+				CFG_CMD_DIAG	| \
+				CFG_CMD_EEPROM	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_NET	| \
 				CFG_CMD_NFS	| \
-				CFG_CMD_PING    | \
 				CFG_CMD_PCI	| \
+				CFG_CMD_PING	| \
 				CFG_CMD_REGINFO | \
-				CFG_CMD_SDRAM   | \
+				CFG_CMD_SDRAM	| \
 				CFG_CMD_SNTP	)
 
 #define CONFIG_NET_MULTI
@@ -260,10 +267,17 @@
 #define CFG_BOOTMAPSZ		(8 << 20)   /* Initial Memory map for Linux */
 
 /* SDRAM configuration */
-#define CFG_SDRAM_TOTAL_BANKS           2
-#define CFG_SDRAM_SPD_I2C_ADDR          0x51            /* 7bit */
-#define CFG_SDRAM_SPD_SIZE              0x40
-#define CFG_SDRAM_CAS_LATENCY           4               /* (CL=2)x2 */
+#define CFG_SDRAM_TOTAL_BANKS		2
+#define CFG_SDRAM_SPD_I2C_ADDR		0x51		/* 7bit */
+#define CFG_SDRAM_SPD_SIZE		0x40
+#define CFG_SDRAM_CAS_LATENCY		4		/* (CL=2)x2 */
+
+/* SDRAM drive strength register */
+#define CFG_SDRAM_DRIVE_STRENGTH	((DRIVE_STRENGTH_LOW  << SDRAMDS_SBE_SHIFT) | \
+					 (DRIVE_STRENGTH_HIGH << SDRAMDS_SBC_SHIFT) | \
+					 (DRIVE_STRENGTH_LOW  << SDRAMDS_SBA_SHIFT) | \
+					 (DRIVE_STRENGTH_OFF  << SDRAMDS_SBS_SHIFT) | \
+					 (DRIVE_STRENGTH_LOW  << SDRAMDS_SBD_SHIFT))
 
 /*
  * Ethernet configuration

include/configs/sorcery.h

@@ -53,6 +53,22 @@
 #define CONFIG_BAUDRATE		115200	    /* ... at 115200 bps */
 #define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
+/* PCI */
+#define CONFIG_PCI              1
+#define CONFIG_PCI_PNP          1
+
+#define CONFIG_PCI_MEM_BUS      0x80000000
+#define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE     0x10000000
+
+#define CONFIG_PCI_IO_BUS	0x71000000
+#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE	0x01000000
+
+#define CONFIG_PCI_CFG_BUS	0x70000000
+#define CONFIG_PCI_CFG_PHYS	CONFIG_PCI_CFG_BUS
+#define CONFIG_PCI_CFG_SIZE	0x01000000
+
 /*
  * Supported commands
  */
@@ -65,6 +81,7 @@
 				CFG_CMD_I2C	| \
 				CFG_CMD_NET	| \
 				CFG_CMD_NFS	| \
+				CFG_CMD_PCI	| \
 				CFG_CMD_PING	| \
 				CFG_CMD_REGINFO	| \
 				CFG_CMD_SDRAM	| \
@@ -72,7 +89,6 @@
 				0)
 
 /*			CFG_CMD_MII	| \ */
-/*			       CFG_CMD_PCI	| \ */
 /*			       CFG_CMD_USB	| \ */
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
@@ -113,6 +129,7 @@
 #define CONFIG_TIMESTAMP		/* Print image info with timestamp */
 
 #define CONFIG_NET_MULTI
+#define CONFIG_EEPRO100
 
 /*
  * I2C configuration
@@ -138,49 +155,38 @@
 /* Flash */
 #define CFG_CS0_BASE		0xf800
 #define CFG_CS0_MASK		0x08000000 /* 128 MB (two chips) */
-
-/* Workaround of hang-up after setting ctrl register for flash
-   After reset this register has value 0x003ffd80, which differs
-   from suggested only by the number of wait states.
-#define CFG_CS0_CTRL		0x003f1580
-*/
+#define CFG_CS0_CTRL		0x001019c0
 
 /* NVM */
-#define CFG_CS1_BASE		0xf100
-#define CFG_CS1_MASK		0x00080000  /* 512K */
-#define CFG_CS1_CTRL		0x003ffd40  /* 8bit port size? */
+#define CFG_CS1_BASE		0xf7e8
+#define CFG_CS1_MASK		0x00040000 /* 256K */
+#define CFG_CS1_CTRL		0x00101940 /* 8bit port size */
 
 /* Atlas2 + Gemini */
-/* This CS# is mandatory? */
-#define CFG_CS2_BASE		0xf10A
-#define CFG_CS2_MASK		0x00020000 /* 2x64K*/
-#define CFG_CS2_CTRL		0x003ffd00 /* 32bit port size? */
+#define CFG_CS2_BASE		0xf7e7
+#define CFG_CS2_MASK		0x00010000 /* 64K*/
+#define CFG_CS2_CTRL		0x001011c0 /* 16bit port size */
 
 /* CAN Controller */
-/* This CS# is mandatory? */
-#define CFG_CS3_BASE		0xf10C
+#define CFG_CS3_BASE		0xf7e6
 #define CFG_CS3_MASK		0x00010000 /* 64K */
-#define CFG_CS3_CTRL		0x003ffd40 /* 8Bit port size */
+#define CFG_CS3_CTRL		0x00102140 /* 8Bit port size */
 
 /* Foreign interface */
-#define CFG_CS4_BASE		0xF10D
+#define CFG_CS4_BASE		0xf7e5
 #define CFG_CS4_MASK		0x00010000 /* 64K */
-#define CFG_CS4_CTRL		0x003ffd80 /* 16bit port size */
+#define CFG_CS4_CTRL		0x00101dc0 /* 16bit port size */
 
-/* CPLD? */
-/* This CS# is mandatory? */
-#define CFG_CS5_BASE		0xF108
-#define CFG_CS5_MASK		0x00010000
-#define CFG_CS5_CTRL		0x003ffd80 /* 16bit port size */
+/* CPLD */
+#define CFG_CS5_BASE		0xf7e4
+#define CFG_CS5_MASK		0x00010000 /* 64K */
+#define CFG_CS5_CTRL		0x001000c0 /* 16bit port size */
 
 #define CFG_FLASH0_BASE		(CFG_CS0_BASE << 16)
-#define CFG_FLASH_BASE		CFG_FLASH0_BASE
+#define CFG_FLASH_BASE		(CFG_FLASH0_BASE)
 
-#define CFG_MAX_FLASH_BANKS	2	/* max num of memory banks (actually 4? (at least 2)) */
-#define CFG_MAX_FLASH_SECT	512	/* max num of sects on one chip (actually 256) */
-
-
-#define PHYS_AMD_SECT_SIZE	0x00020000 /* 128 KB sectors (x2) */
+#define CFG_MAX_FLASH_BANKS	2	/* max num of flash banks */
+#define CFG_MAX_FLASH_SECT	512	/* max num of sects on one chip */
 
 #define CFG_FLASH_CFI_DRIVER
 #define CFG_FLASH_CFI
@@ -191,9 +197,11 @@
  * Environment settings
  */
 #define CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_ADDR		(CFG_FLASH0_BASE)
-#define CFG_ENV_SIZE		PHYS_AMD_SECT_SIZE
-#define CFG_ENV_SECT_SIZE	PHYS_AMD_SECT_SIZE
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x8000000 - 0x40000)
+#define CFG_ENV_SIZE		0x4000                       /* 16K */
+#define CFG_ENV_SECT_SIZE	0x20000
+#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR + 0x20000)
+#define CFG_ENV_SIZE_REDUND	CFG_ENV_SIZE
 
 #define CONFIG_ENV_OVERWRITE	1
 
@@ -240,6 +248,13 @@
 #define CFG_SDRAM_SPD_SIZE		0x100
 #define CFG_SDRAM_CAS_LATENCY		5 		/* (CL=2.5)x2 */
 
+/* SDRAM drive strength register (for SSTL_2 class II)*/
+#define CFG_SDRAM_DRIVE_STRENGTH 	((DRIVE_STRENGTH_HIGH << SDRAMDS_SBE_SHIFT) | \
+					 (DRIVE_STRENGTH_HIGH << SDRAMDS_SBC_SHIFT) | \
+					 (DRIVE_STRENGTH_HIGH << SDRAMDS_SBA_SHIFT) | \
+					 (DRIVE_STRENGTH_HIGH << SDRAMDS_SBS_SHIFT) | \
+					 (DRIVE_STRENGTH_HIGH << SDRAMDS_SBD_SHIFT))
+
 /*
  * Ethernet configuration
  */
@@ -274,4 +289,9 @@
 #define CFG_HID0_INIT		0
 #define CFG_HID0_FINAL		0
 
+/*
+#define CFG_HID0_INIT           HID0_ICE | HID0_ICFI
+#define CFG_HID0_FINAL          HID0_ICE
+*/
+
 #endif /* __CONFIG_H */

include/mpc8220.h

@@ -259,10 +259,12 @@
 #define PSC_TFLWFPTR(x)		(x&0x1ff)     /* last write frame pointer */
 
 /* PCI configuration (only for PLL determination)*/
-#define PCI_REG_PCIGSCR 	(MMAP_XCPCI + 0x60) /* Global status/control register */
+#define PCI_REG_PCIGSCR		(MMAP_XCPCI + 0x60) /* Global status/control register */
 #define PCI_REG_PCIGSCR_PCI2XLB_CLK_MASK	0x07000000
 #define PCI_REG_PCIGSCR_PCI2XLB_CLK_BIT		24
 
+#define PCI_REG_PCICAR		(MMAP_XCPCI + 0xF8) /* Configuration Address Register */
+
 /* ------------------------------------------------------------------------ */
 /*
  * Macro for General Purpose Timer
@@ -300,18 +302,21 @@
  */
 #define CFG_FEC1_PORT0_CONFIG	0x00000000
 #define CFG_FEC1_PORT1_CONFIG	0x00000000
-#define CFG_1284_PORT0_CONFIG	0x55555557
-#define CFG_1284_PORT1_CONFIG	0x80000000
+#define CFG_1284_PORT0_CONFIG  0x00000000
+#define CFG_1284_PORT1_CONFIG  0x00000000
 #define CFG_FEC2_PORT2_CONFIG	0x00000000
-#define CFG_PEV_PORT2_CONFIG	0x55555540
-#define CFG_GP0_PORT0_CONFIG	0xaaaaaaa0
-#define CFG_GP1_PORT2_CONFIG	0xaaaaa000
-#define CFG_PSC_PORT3_CONFIG	0x00000000
+#define CFG_PEV_PORT2_CONFIG   0x00000000
+#define CFG_GP0_PORT0_CONFIG   0x00000000
+#define CFG_GP1_PORT2_CONFIG   0xaaaaaac0
+#define CFG_PSC_PORT3_CONFIG   0x00020000
+#define CFG_CS1_PORT3_CONFIG   0x00000000
 #define CFG_CS2_PORT3_CONFIG	0x10000000
 #define CFG_CS3_PORT3_CONFIG	0x40000000
 #define CFG_CS4_PORT3_CONFIG	0x00000400
 #define CFG_CS5_PORT3_CONFIG	0x00000200
-#define CFG_I2C_PORT3_CONFIG	0x003c0000
+#define CFG_PCI_PORT3_CONFIG   0x01400180
+#define CFG_I2C_PORT3_CONFIG   0x00000000
+#define CFG_GP2_PORT3_CONFIG   0x000200a0
 
 /* ------------------------------------------------------------------------ */
 /*
@@ -527,6 +532,162 @@ struct mpc8220_dma {
     u32 EU37;		/* DMA + 0xfc */
 };
 
+/*
+ * PCI Header Registers
+ */
+typedef struct mpc8220_xcpci {
+	u32	dev_ven_id;		/* 0xb00 - device/vendor ID */
+	u32	stat_cmd_reg;		/* 0xb04 - status command register */
+	u32	class_code_rev_id;	/* 0xb08 - class code / revision ID */
+	u32	bist_htyp_lat_cshl;	/* 0xb0c - BIST/HeaderType/Latency/cache line */
+	u32	base0;			/* 0xb10 - base address 0 */
+	u32	base1;			/* 0xb14 - base address 1 */
+	u32	reserved1[4];		/* 0xb18->0xd27 - base address 2 - 5 */
+	u32	cis;			/* 0xb28 - cardBus CIS pointer */
+	u32	sub_sys_ven_id;		/* 0xb2c - sub system ID/ subsystem vendor ID */
+	u32	reserved2;		/* 0xb30 - expansion ROM base address */
+	u32	reserved3;		/* 0xb00 - reserved */
+	u32	reserved4;		/* 0xb00 - reserved */
+	u32	mlat_mgnt_ipl;		/* 0xb3c - MaxLat/MinGnt/ int pin/int line */
+	u32	reserved5[8];
+	/* MPC8220 specific - not accessible in PCI header space externally */
+	u32	glb_stat_ctl;		/* 0xb60 - Global Status Control */
+	u32	target_bar0;		/* 0xb64 - Target Base Address 0 */
+	u32	target_bar1;		/* 0xb68 - Target Base Address 1 */
+	u32	target_ctrl;		/* 0xb6c - Target Control */
+	u32	init_win0;		/* 0xb70 - Initiator Window 0 Base/Translation */
+	u32	init_win1;		/* 0xb74 - Initiator Window 1 Base/Translation */
+	u32	init_win2;		/* 0xb78 - Initiator Window 2 Base/Translation */
+	u32	reserved6;		/* 0xb7c - reserved  */
+	u32	init_win_cfg;		/* 0xb80 */
+	u32	init_ctrl;		/* 0xb84 */
+	u32	init_stat;		/* 0xb88 */
+	u32	reserved7[27];
+	u32	cfg_adr;		/* 0xbf8 */
+	u32	reserved8;
+} mpc8220_xcpci_t;
+
+/* PCI->XLB space translation (MPC8220 target), reg0 can address max 256MB,
+   reg1 - 1GB */
+#define PCI_BASE_ADDR_REG0			0x40000000
+#define PCI_BASE_ADDR_REG1			(CFG_SDRAM_BASE)
+#define PCI_TARGET_BASE_ADDR_REG0		(CFG_MBAR)
+#define PCI_TARGET_BASE_ADDR_REG1		(CFG_SDRAM_BASE)
+#define PCI_TARGET_BASE_ADDR_EN			1<<0
+
+
+/* PCI Global Status/Control Register (PCIGSCR) */
+#define PCI_GLB_STAT_CTRL_PE_SHIFT		29
+#define PCI_GLB_STAT_CTRL_SE_SHIFT		28
+#define PCI_GLB_STAT_CTRL_XLB_TO_PCI_CLK_SHIFT	24
+#define PCI_GLB_STAT_CTRL_XLB_TO_PCI_CLK_MASK	0x7
+#define PCI_GLB_STAT_CTRL_IPG_TO_PCI_CLK_SHIFT	16
+#define PCI_GLB_STAT_CTRL_IPG_TO_PCI_CLK_MASK	0x7
+#define PCI_GLB_STAT_CTRL_PEE_SHIFT		13
+#define PCI_GLB_STAT_CTRL_SEE_SHIFT		12
+#define PCI_GLB_STAT_CTRL_PR_SHIFT		0
+
+#define PCI_GLB_STAT_CTRL_PE			(1<<PCI_GLB_STAT_CTRL_PE_SHIFT)
+#define PCI_GLB_STAT_CTRL_SE			(1<<PCI_GLB_STAT_CTRL_SE_SHIFT)
+#define PCI_GLB_STAT_CTRL_PEE			(1<<PCI_GLB_STAT_CTRL_PEE_SHIFT)
+#define PCI_GLB_STAT_CTRL_SEE			(1<<PCI_GLB_STAT_CTRL_SEE_SHIFT)
+#define PCI_GLB_STAT_CTRL_PR			(1<<PCI_GLB_STAT_CTRL_PR_SHIFT)
+
+/* PCI Target Control Register (PCITCR) */
+#define PCI_TARGET_CTRL_LD_SHIFT		24
+#define PCI_TARGET_CTRL_P_SHIFT			16
+
+#define PCI_TARGET_CTRL_LD			(1<<PCI_TARGET_CTRL_LD_SHIFT)
+#define PCI_TARGET_CTRL_P			(1<<PCI_TARGET_CTRL_P_SHIFT)
+
+/* PCI Initiator Window Configuration Register (PCIIWCR) */
+#define PCI_INIT_WIN_CFG_WIN0_CTRL_IO_SHIFT	27
+#define PCI_INIT_WIN_CFG_WIN0_CTRL_PRC_SHIFT	25
+#define PCI_INIT_WIN_CFG_WIN0_CTRL_PRC_MASK	0x3
+#define PCI_INIT_WIN_CFG_WIN0_CTRL_EN_SHIFT	24
+#define PCI_INIT_WIN_CFG_WIN1_CTRL_IO_SHIFT	19
+#define PCI_INIT_WIN_CFG_WIN1_CTRL_PRC_SHIFT	17
+#define PCI_INIT_WIN_CFG_WIN1_CTRL_PRC_MASK	0x3
+#define PCI_INIT_WIN_CFG_WIN1_CTRL_EN_SHIFT	16
+#define PCI_INIT_WIN_CFG_WIN2_CTRL_IO_SHIFT	11
+#define PCI_INIT_WIN_CFG_WIN2_CTRL_PRC_SHIFT	9
+#define PCI_INIT_WIN_CFG_WIN2_CTRL_PRC_MASK	0x3
+#define PCI_INIT_WIN_CFG_WIN2_CTRL_EN_SHIFT	8
+
+#define PCI_INIT_WIN_CFG_WIN_MEM_READ		0x0
+#define PCI_INIT_WIN_CFG_WIN_MEM_READ_LINE	0x1
+#define PCI_INIT_WIN_CFG_WIN_MEM_READ_MULTIPLE	0x2
+
+#define PCI_INIT_WIN_CFG_WIN0_CTRL_IO		(1<<PCI_INIT_WIN_CFG_WIN0_CTRL_IO_SHIFT)
+#define PCI_INIT_WIN_CFG_WIN0_CTRL_EN		(1<<PCI_INIT_WIN_CFG_WIN0_CTRL_EN_SHIFT)
+#define PCI_INIT_WIN_CFG_WIN1_CTRL_IO		(1<<PCI_INIT_WIN_CFG_WIN1_CTRL_IO_SHIFT)
+#define PCI_INIT_WIN_CFG_WIN1_CTRL_EN		(1<<PCI_INIT_WIN_CFG_WIN1_CTRL_EN_SHIFT)
+#define PCI_INIT_WIN_CFG_WIN2_CTRL_IO		(1<<PCI_INIT_WIN_CFG_WIN2_CTRL_IO_SHIFT)
+#define PCI_INIT_WIN_CFG_WIN2_CTRL_EN		(1<<PCI_INIT_WIN_CFG_WIN2_CTRL_EN_SHIFT)
+
+/* PCI Initiator Control Register (PCIICR) */
+#define PCI_INIT_CTRL_REE_SHIFT			26
+#define PCI_INIT_CTRL_IAE_SHIFT			25
+#define PCI_INIT_CTRL_TAE_SHIFT			24
+#define PCI_INIT_CTRL_MAX_RETRIES_SHIFT		0
+#define PCI_INIT_CTRL_MAX_RETRIES_MASK		0xff
+
+#define PCI_INIT_CTRL_REE			(1<<PCI_INIT_CTRL_REE_SHIFT)
+#define PCI_INIT_CTRL_IAE			(1<<PCI_INIT_CTRL_IAE_SHIFT)
+#define PCI_INIT_CTRL_TAE			(1<<PCI_INIT_CTRL_TAE_SHIFT)
+
+/* PCI Status/Command Register (PCISCR) - PCI Dword 1 */
+#define PCI_STAT_CMD_PE_SHIFT			31
+#define PCI_STAT_CMD_SE_SHIFT			30
+#define PCI_STAT_CMD_MA_SHIFT			29
+#define PCI_STAT_CMD_TR_SHIFT			28
+#define PCI_STAT_CMD_TS_SHIFT			27
+#define PCI_STAT_CMD_DT_SHIFT			25
+#define PCI_STAT_CMD_DT_MASK			0x3
+#define PCI_STAT_CMD_DP_SHIFT			24
+#define PCI_STAT_CMD_FC_SHIFT			23
+#define PCI_STAT_CMD_R_SHIFT			22
+#define PCI_STAT_CMD_66M_SHIFT			21
+#define PCI_STAT_CMD_C_SHIFT			20
+#define PCI_STAT_CMD_F_SHIFT			9
+#define PCI_STAT_CMD_S_SHIFT			8
+#define PCI_STAT_CMD_ST_SHIFT			7
+#define PCI_STAT_CMD_PER_SHIFT			6
+#define PCI_STAT_CMD_V_SHIFT			5
+#define PCI_STAT_CMD_MW_SHIFT			4
+#define PCI_STAT_CMD_SP_SHIFT			3
+#define PCI_STAT_CMD_B_SHIFT			2
+#define PCI_STAT_CMD_M_SHIFT			1
+#define PCI_STAT_CMD_IO_SHIFT			0
+
+#define PCI_STAT_CMD_PE			(1<<PCI_STAT_CMD_PE_SHIFT)
+#define PCI_STAT_CMD_SE			(1<<PCI_STAT_CMD_SE_SHIFT)
+#define PCI_STAT_CMD_MA			(1<<PCI_STAT_CMD_MA_SHIFT)
+#define PCI_STAT_CMD_TR			(1<<PCI_STAT_CMD_TR_SHIFT)
+#define PCI_STAT_CMD_TS			(1<<PCI_STAT_CMD_TS_SHIFT)
+#define PCI_STAT_CMD_DP			(1<<PCI_STAT_CMD_DP_SHIFT)
+#define PCI_STAT_CMD_FC			(1<<PCI_STAT_CMD_FC_SHIFT)
+#define PCI_STAT_CMD_R				(1<<PCI_STAT_CMD_R_SHIFT)
+#define PCI_STAT_CMD_66M			(1<<PCI_STAT_CMD_66M_SHIFT)
+#define PCI_STAT_CMD_C				(1<<PCI_STAT_CMD_C_SHIFT)
+#define PCI_STAT_CMD_F				(1<<PCI_STAT_CMD_F_SHIFT)
+#define PCI_STAT_CMD_S				(1<<PCI_STAT_CMD_S_SHIFT)
+#define PCI_STAT_CMD_ST			(1<<PCI_STAT_CMD_ST_SHIFT)
+#define PCI_STAT_CMD_PER			(1<<PCI_STAT_CMD_PER_SHIFT)
+#define PCI_STAT_CMD_V				(1<<PCI_STAT_CMD_V_SHIFT)
+#define PCI_STAT_CMD_MW			(1<<PCI_STAT_CMD_MW_SHIFT)
+#define PCI_STAT_CMD_SP			(1<<PCI_STAT_CMD_SP_SHIFT)
+#define PCI_STAT_CMD_B				(1<<PCI_STAT_CMD_B_SHIFT)
+#define PCI_STAT_CMD_M				(1<<PCI_STAT_CMD_M_SHIFT)
+#define PCI_STAT_CMD_IO			(1<<PCI_STAT_CMD_IO_SHIFT)
+
+/* PCI Configuration 1 Register (PCICR1) - PCI Dword 3 */
+#define PCI_CFG1_HT_SHIFT			16
+#define PCI_CFG1_HT_MASK			0xff
+#define PCI_CFG1_LT_SHIFT			8
+#define PCI_CFG1_LT_MASK			0xff
+#define PCI_CFG1_CLS_SHIFT			0
+#define PCI_CFG1_CLS_MASK			0xf
 
 /* function prototypes */
 void loadtask(int basetask, int tasks);

net/eth.c

@@ -148,7 +148,7 @@ int eth_initialize(bd_t *bis)
 #if defined(CONFIG_MPC5xxx_FEC)
 	mpc5xxx_fec_initialize(bis);
 #endif
-#if defined(CONFIG_MPC8220)
+#if defined(CONFIG_MPC8220_FEC)
 	mpc8220_fec_initialize(bis);
 #endif
 #if defined(CONFIG_SK98)