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+/*
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+ * OMAP1 CPU identification code
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+ *
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+ * Copyright (C) 2004 Nokia Corporation
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+ * Written by Tony Lindgren <tony@atomide.com>
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ */
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+
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+#include <common.h>
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+#include <command.h>
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+#include <arm926ejs.h>
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+
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+#if defined(CONFIG_DISPLAY_CPUINFO) && defined(CONFIG_OMAP)
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+
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+#define omap_readw(x) *(volatile unsigned short *)(x)
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+#define omap_readl(x) *(volatile unsigned long *)(x)
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+
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+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
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+
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+#define OMAP_DIE_ID_0 0xfffe1800
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+#define OMAP_DIE_ID_1 0xfffe1804
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+#define OMAP_PRODUCTION_ID_0 0xfffe2000
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+#define OMAP_PRODUCTION_ID_1 0xfffe2004
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+#define OMAP32_ID_0 0xfffed400
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+#define OMAP32_ID_1 0xfffed404
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+
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+struct omap_id {
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+ u16 jtag_id; /* Used to determine OMAP type */
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+ u8 die_rev; /* Processor revision */
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+ u32 omap_id; /* OMAP revision */
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+ u32 type; /* Cpu id bits [31:08], cpu class bits [07:00] */
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+};
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+
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+/* Register values to detect the OMAP version */
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+static struct omap_id omap_ids[] = {
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+ { .jtag_id = 0xb574, .die_rev = 0x2, .omap_id = 0x03310315, .type = 0x03100000},
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+ { .jtag_id = 0x355f, .die_rev = 0x0, .omap_id = 0x03320000, .type = 0x07300100},
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+ { .jtag_id = 0xb55f, .die_rev = 0x0, .omap_id = 0x03320000, .type = 0x07300300},
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+ { .jtag_id = 0xb470, .die_rev = 0x0, .omap_id = 0x03310100, .type = 0x15100000},
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+ { .jtag_id = 0xb576, .die_rev = 0x0, .omap_id = 0x03320000, .type = 0x16100000},
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+ { .jtag_id = 0xb576, .die_rev = 0x2, .omap_id = 0x03320100, .type = 0x16110000},
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+ { .jtag_id = 0xb576, .die_rev = 0x3, .omap_id = 0x03320100, .type = 0x16100c00},
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+ { .jtag_id = 0xb576, .die_rev = 0x0, .omap_id = 0x03320200, .type = 0x16100d00},
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+ { .jtag_id = 0xb613, .die_rev = 0x0, .omap_id = 0x03320300, .type = 0x1610ef00},
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+ { .jtag_id = 0xb613, .die_rev = 0x0, .omap_id = 0x03320300, .type = 0x1610ef00},
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+ { .jtag_id = 0xb576, .die_rev = 0x1, .omap_id = 0x03320100, .type = 0x16110000},
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+ { .jtag_id = 0xb58c, .die_rev = 0x2, .omap_id = 0x03320200, .type = 0x16110b00},
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+ { .jtag_id = 0xb58c, .die_rev = 0x3, .omap_id = 0x03320200, .type = 0x16110c00},
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+ { .jtag_id = 0xb65f, .die_rev = 0x0, .omap_id = 0x03320400, .type = 0x16212300},
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+ { .jtag_id = 0xb65f, .die_rev = 0x1, .omap_id = 0x03320400, .type = 0x16212300},
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+ { .jtag_id = 0xb65f, .die_rev = 0x1, .omap_id = 0x03320500, .type = 0x16212300},
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+ { .jtag_id = 0xb5f7, .die_rev = 0x0, .omap_id = 0x03330000, .type = 0x17100000},
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+ { .jtag_id = 0xb5f7, .die_rev = 0x1, .omap_id = 0x03330100, .type = 0x17100000},
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+ { .jtag_id = 0xb5f7, .die_rev = 0x2, .omap_id = 0x03330100, .type = 0x17100000},
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+};
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+
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+/*
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+ * Get OMAP type from PROD_ID.
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+ * 1710 has the PROD_ID in bits 15:00, not in 16:01 as documented in TRM.
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+ * 1510 PROD_ID is empty, and 1610 PROD_ID does not make sense.
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+ * Undocumented register in TEST BLOCK is used as fallback; This seems to
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+ * work on 1510, 1610 & 1710. The official way hopefully will work in future
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+ * processors.
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+ */
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+static u16 omap_get_jtag_id(void)
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+{
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+ u32 prod_id, omap_id;
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+
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+ prod_id = omap_readl(OMAP_PRODUCTION_ID_1);
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+ omap_id = omap_readl(OMAP32_ID_1);
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+
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+ /* Check for unusable OMAP_PRODUCTION_ID_1 on 1611B/5912 and 730 */
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+ if (((prod_id >> 20) == 0) || (prod_id == omap_id))
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+ prod_id = 0;
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+ else
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+ prod_id &= 0xffff;
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+
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+ if (prod_id)
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+ return prod_id;
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+
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+ /* Use OMAP32_ID_1 as fallback */
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+ prod_id = ((omap_id >> 12) & 0xffff);
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+
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+ return prod_id;
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+}
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+
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+/*
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+ * Get OMAP revision from DIE_REV.
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+ * Early 1710 processors may have broken OMAP_DIE_ID, it contains PROD_ID.
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+ * Undocumented register in the TEST BLOCK is used as fallback.
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+ * REVISIT: This does not seem to work on 1510
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+ */
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+static u8 omap_get_die_rev(void)
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+{
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+ u32 die_rev;
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+
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+ die_rev = omap_readl(OMAP_DIE_ID_1);
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+
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+ /* Check for broken OMAP_DIE_ID on early 1710 */
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+ if (((die_rev >> 12) & 0xffff) == omap_get_jtag_id())
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+ die_rev = 0;
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+
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+ die_rev = (die_rev >> 17) & 0xf;
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+ if (die_rev)
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+ return die_rev;
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+
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+ die_rev = (omap_readl(OMAP32_ID_1) >> 28) & 0xf;
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+
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+ return die_rev;
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+}
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+
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+static unsigned long dpll1(void)
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+{
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+ unsigned short pll_ctl_val = omap_readw(DPLL_CTL_REG);
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+ unsigned long rate;
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+
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+ rate = CONFIG_SYS_CLK_FREQ; /* Base xtal rate */
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+ if (pll_ctl_val & 0x10) {
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+ /* PLL enabled, apply multiplier and divisor */
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+ if (pll_ctl_val & 0xf80)
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+ rate *= (pll_ctl_val & 0xf80) >> 7;
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+ rate /= ((pll_ctl_val & 0x60) >> 5) + 1;
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+ } else {
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+ /* PLL disabled, apply bypass divisor */
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+ switch (pll_ctl_val & 0xc) {
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+ case 0:
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+ break;
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+ case 0x4:
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+ rate /= 2;
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+ break;
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+ default:
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+ rate /= 4;
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+ break;
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+ }
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+ }
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+
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+ return rate;
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+}
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+
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+static unsigned long armcore(void)
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+{
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+ unsigned short arm_ckctl = omap_readw(ARM_CKCTL);
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+
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+ return (dpll1() >> ((arm_ckctl & 0x0030) >> 4));
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+}
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+
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+int print_cpuinfo (void)
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+{
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+ int i;
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+ u16 jtag_id;
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+ u8 die_rev;
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+ u32 omap_id;
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+ u8 cpu_type;
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+ u32 system_serial_high;
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+ u32 system_serial_low;
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+ u32 system_rev = 0;
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+
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+ jtag_id = omap_get_jtag_id();
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+ die_rev = omap_get_die_rev();
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+ omap_id = omap_readl(OMAP32_ID_0);
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+
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+#ifdef DEBUG
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+ printf("OMAP_DIE_ID_0: 0x%08x\n", omap_readl(OMAP_DIE_ID_0));
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+ printf("OMAP_DIE_ID_1: 0x%08x DIE_REV: %i\n",
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+ omap_readl(OMAP_DIE_ID_1),
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+ (omap_readl(OMAP_DIE_ID_1) >> 17) & 0xf);
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+ printf("OMAP_PRODUCTION_ID_0: 0x%08x\n", omap_readl(OMAP_PRODUCTION_ID_0));
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+ printf("OMAP_PRODUCTION_ID_1: 0x%08x JTAG_ID: 0x%04x\n",
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+ omap_readl(OMAP_PRODUCTION_ID_1),
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+ omap_readl(OMAP_PRODUCTION_ID_1) & 0xffff);
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+ printf("OMAP32_ID_0: 0x%08x\n", omap_readl(OMAP32_ID_0));
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+ printf("OMAP32_ID_1: 0x%08x\n", omap_readl(OMAP32_ID_1));
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+ printf("JTAG_ID: 0x%04x DIE_REV: %i\n", jtag_id, die_rev);
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+#endif
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+
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+ system_serial_high = omap_readl(OMAP_DIE_ID_0);
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+ system_serial_low = omap_readl(OMAP_DIE_ID_1);
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+
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+ /* First check only the major version in a safe way */
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+ for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
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+ if (jtag_id == (omap_ids[i].jtag_id)) {
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+ system_rev = omap_ids[i].type;
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+ break;
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+ }
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+ }
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+
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+ /* Check if we can find the die revision */
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+ for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
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+ if (jtag_id == omap_ids[i].jtag_id && die_rev == omap_ids[i].die_rev) {
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+ system_rev = omap_ids[i].type;
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+ break;
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+ }
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+ }
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+
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+ /* Finally check also the omap_id */
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+ for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
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+ if (jtag_id == omap_ids[i].jtag_id
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+ && die_rev == omap_ids[i].die_rev
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+ && omap_id == omap_ids[i].omap_id) {
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+ system_rev = omap_ids[i].type;
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+ break;
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+ }
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+ }
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+
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+ /* Add the cpu class info (7xx, 15xx, 16xx, 24xx) */
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+ cpu_type = system_rev >> 24;
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+
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+ switch (cpu_type) {
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+ case 0x07:
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+ system_rev |= 0x07;
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+ break;
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+ case 0x03:
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+ case 0x15:
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+ system_rev |= 0x15;
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+ break;
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+ case 0x16:
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+ case 0x17:
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+ system_rev |= 0x16;
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+ break;
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+ case 0x24:
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+ system_rev |= 0x24;
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+ break;
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+ default:
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+ printf("Unknown OMAP cpu type: 0x%02x\n", cpu_type);
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+ }
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+
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+ printf("CPU: OMAP%04x", system_rev >> 16);
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+ if ((system_rev >> 8) & 0xff)
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+ printf("%x", (system_rev >> 8) & 0xff);
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+#ifdef DEBUG
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+ printf(" revision %i handled as %02xxx id: %08x%08x",
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+ die_rev, system_rev & 0xff, system_serial_low, system_serial_high);
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+#endif
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+ printf(" at %ld.%01ld MHz (DPLL1=%ld.%01ld MHz)\n",
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+ armcore() / 1000000, (armcore() / 100000) % 10,
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+ dpll1() / 1000000, (dpll1() / 100000) % 10);
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+
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+ return 0;
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+}
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+
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+#endif /* #if defined(CONFIG_DISPLAY_CPUINFO) && defined(CONFIG_OMAP) */
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+
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Stefan Roese