* Patches by David M�ller, 12 Jun 2003:

  - rewrite of the S3C24X0 register definitions stuff
  - "driver" for the built-in S3C24X0 RTC

* Patches by Yuli Barcohen, 12 Jun 2003:
  - Add MII support and Ethernet PHY initialization for MPC8260ADS board
  - Fix incorrect SIUMCR initialisation caused by wrong Hard Reset
    configuration word supplied by FPGA on some MPC8260ADS boards

* Patch by Pantelis Antoniou, 10 Jun 2003:
  Unify status LED interface

CHANGELOG

@@ -2,6 +2,18 @@
 Changes since U-Boot 0.3.1:
 ======================================================================
 
+* Patches by David Müller, 12 Jun 2003:
+  - rewrite of the S3C24X0 register definitions stuff
+  - "driver" for the built-in S3C24X0 RTC
+
+* Patches by Yuli Barcohen, 12 Jun 2003:
+  - Add MII support and Ethernet PHY initialization for MPC8260ADS board
+  - Fix incorrect SIUMCR initialisation caused by wrong Hard Reset
+    configuration word supplied by FPGA on some MPC8260ADS boards
+
+* Patch by Pantelis Antoniou, 10 Jun 2003:
+  Unify status LED interface
+
 * Add support for DS12887 RTC; add RTC support for ATC board
 
 * Patch by Nicolas Lacressonniere, 11 Jun 2003:

board/mpc8260ads/mpc8260ads.c

@@ -9,6 +9,10 @@
  * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
  * Added support for the 16M dram simm on the 8260ads boards
  *
+ * (C) Copyright 2003 Arabella Software Ltd.
+ * Yuli Barcohen <yuli@arabellasw.com>
+ * Added support for SDRAM DIMMs SPD EEPROM, MII, Ethernet PHY init.
+ *
  * See file CREDITS for list of people who contributed to this
  * project.
  *

board/mpl/common/common_util.c

@@ -45,7 +45,11 @@ extern int  gunzip (void *, int, unsigned char *, int *);
 extern int mem_test(unsigned long start, unsigned long ramsize, int quiet);
 
 #define I2C_BACKUP_ADDR 0x7C00 /* 0x200 bytes for backup */
+#if defined(CONFIG_PIP405) || defined(CONFIG_MIP405)
 #define IMAGE_SIZE 0x80000
+#elif defined(CONFIG_VCMA9)
+#define IMAGE_SIZE 0x40000		/* ugly, but it works for now */
+#endif
 
 extern flash_info_t flash_info[];	/* info for FLASH chips */
 

board/mpl/vcma9/config.mk

@@ -15,10 +15,10 @@
 # Linux-Kernel is expected to be at 3000'8000, entry 3000'8000
 # optionally with a ramdisk at 3080'0000
 #
-# we load ourself to 33F0'0000
+# we load ourself to 33F8'0000
 #
 # download area is 3300'0000
 #
 
 
-TEXT_BASE = 0x33F00000
+TEXT_BASE = 0x33F80000

board/mpl/vcma9/memsetup.S

@@ -54,8 +54,10 @@
 
 /* BANK0CON */
 #define B0_Tacs		 	0x0	/*  0clk */
-#define B0_Tcos		 	0x0	/*  0clk */
-#define B0_Tacc		 	0x5	/*  8clk */
+#define B0_Tcos		 	0x1	/*  1clk */
+/*#define B0_Tcos		0x0	  0clk */
+#define B0_Tacc		 	0x7	/*  14clk */
+/*#define B0_Tacc		0x5	  8clk */
 #define B0_Tcoh		 	0x0	/*  0clk */
 #define B0_Tah		 	0x0	/*  0clk */
 #define B0_Tacp		 	0x0     /* page mode is not used */
@@ -63,8 +65,10 @@
 
 /* BANK1CON */
 #define B1_Tacs		 	0x0	/*  0clk */
-#define B1_Tcos		 	0x0	/*  0clk */
-#define B1_Tacc		 	0x5	/*  8clk */
+#define B1_Tcos		 	0x1	/*  1clk */
+/*#define B1_Tcos		0x0	  0clk */
+#define B1_Tacc			0x7	/*  14clk */
+/*#define B1_Tacc		0x5	  8clk */
 #define B1_Tcoh		 	0x0	/*  0clk */
 #define B1_Tah		 	0x0	/*  0clk */
 #define B1_Tacp		 	0x0     /* page mode is not used */

board/mpl/vcma9/vcma9.c

@@ -72,41 +72,46 @@ static inline void delay(unsigned long loops)
 int board_init(void)
 {
 	DECLARE_GLOBAL_DATA_PTR;
+	S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
+	S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
 
 	/* to reduce PLL lock time, adjust the LOCKTIME register */
-	rLOCKTIME = 0xFFFFFF;
+	clk_power->LOCKTIME = 0xFFFFFF;
 
 	/* configure MPLL */
-	rMPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
+	clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
 
 	/* some delay between MPLL and UPLL */
 	delay (4000);
 
 	/* configure UPLL */
-	rUPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
+	clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
 
 	/* some delay between MPLL and UPLL */
 	delay (8000);
 
 	/* set up the I/O ports */
-	rGPACON = 0x007FFFFF;
-	rGPBCON = 0x002AAAAA;
-	rGPBUP = 0x000002BF;
-	rGPCCON = 0xAAAAAAAA;
-	rGPCUP = 0x0000FFFF;
-	rGPDCON = 0xAAAAAAAA;
-	rGPDUP = 0x0000FFFF;
-	rGPECON = 0xAAAAAAAA;
-	rGPEUP = 0x000037F7;
-	rGPFCON = 0x00000000;
-	rGPFUP = 0x00000000;
-	rGPGCON = 0xFFEAFF5A;
-	rGPGUP = 0x0000F0DC;
-	rGPHCON = 0x0028AAAA;
-	rGPHUP = 0x00000656;
+	gpio->GPACON = 0x007FFFFF;
+	gpio->GPBCON = 0x002AAAAA;
+	gpio->GPBUP = 0x000002BF;
+	gpio->GPCCON = 0xAAAAAAAA;
+	gpio->GPCUP = 0x0000FFFF;
+	gpio->GPDCON = 0xAAAAAAAA;
+	gpio->GPDUP = 0x0000FFFF;
+	gpio->GPECON = 0xAAAAAAAA;
+	gpio->GPEUP = 0x000037F7;
+	gpio->GPFCON = 0x00000000;
+	gpio->GPFUP = 0x00000000;
+	gpio->GPGCON = 0xFFEAFF5A;
+	gpio->GPGUP = 0x0000F0DC;
+	gpio->GPHCON = 0x0028AAAA;
+	gpio->GPHUP = 0x00000656;
 
 	/* setup correct IRQ modes for NIC */
-	rEXTINT2 = (rEXTINT2 & ~(7<<8)) | (4<<8); /* rising edge mode */
+	gpio->EXTINT2 = (gpio->EXTINT2 & ~(7<<8)) | (4<<8); /* rising edge mode */
+
+	/* select USB port 2 to be host or device (fix to host for now) */
+	gpio->MISCCR |= 0x08;
 
 	/* init serial */
 	gd->baudrate = CONFIG_BAUDRATE;
@@ -135,6 +140,50 @@ int dram_init(void)
 	return 0;
 }
 
+/*
+ * NAND flash initialization.
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+extern void
+nand_probe(ulong physadr);
+
+
+static inline void NF_Reset(void)
+{
+    int i;
+
+    NF_SetCE(NFCE_LOW);
+    NF_Cmd(0xFF);		/* reset command */
+    for(i = 0; i < 10; i++);	/* tWB = 100ns. */
+    NF_WaitRB();		/* wait 200~500us; */
+    NF_SetCE(NFCE_HIGH);
+}
+
+
+static inline void NF_Init(void)
+{
+#define TACLS   0
+#define TWRPH0  3
+#define TWRPH1  0
+    NF_Conf((1<<15)|(0<<14)|(0<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0));
+    //nand->NFCONF = (1<<15)|(1<<14)|(1<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0);
+    // 1  1    1     1,   1      xxx,  r xxx,   r xxx
+    // En 512B 4step ECCR nFCE=H tACLS   tWRPH0   tWRPH1
+
+    NF_Reset();
+}
+
+void
+nand_init(void)
+{
+	S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
+
+	NF_Init();
+	printf("NAND flash probing at 0x%.8lX\n", (ulong)nand);
+	nand_probe((ulong)nand);
+}
+#endif
+
 /*
  * Get some Board/PLD Info
  */
@@ -195,12 +244,12 @@ int checkboard(void)
 			puts ("### No HW ID - assuming VCMA9");
 		} else {
 			b->serial_name[5] = 0;
-			printf ("%s-%d Rev %c SN: %s", b->serial_name, Get_Board_Config(),
+			printf ("%s-%d PCB Rev %c SN: %s", b->serial_name, Get_Board_Config(),
 					Get_Board_PCB(), &b->serial_name[6]);
 		}
 	} else {
 		s[5] = 0;
-		printf ("%s-%d Rev %c SN: %s", s, Get_Board_Config(), Get_Board_PCB(),
+		printf ("%s-%d PCB Rev %c SN: %s", s, Get_Board_Config(), Get_Board_PCB(),
 				&s[6]);
 	}
 	printf("\n");
@@ -211,7 +260,7 @@ int checkboard(void)
 
 void print_vcma9_rev(void)
 {
-	printf("Board: VCMA9-%d Rev: %c (PLD Ver: %d, Rev: %d)\n",
+	printf("Board: VCMA9-%d PCB Rev: %c (PLD Ver: %d, Rev: %d)\n",
 		Get_Board_Config(), Get_Board_PCB(),
 		Get_PLD_Version(), Get_PLD_Revision());
 }
@@ -245,5 +294,3 @@ void print_vcma9_info(void)
 {
     print_vcma9_rev();
 }
-
-

board/mpl/vcma9/vcma9.h

@@ -25,11 +25,97 @@
  * Global routines used for VCMA9
  *****************************************************************************/
 
+#include <s3c2410.h>
 
 extern int  mem_test(unsigned long start, unsigned long ramsize,int mode);
 
 void print_vcma9_info(void);
 
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+typedef enum {
+	NFCE_LOW,
+	NFCE_HIGH
+} NFCE_STATE;
+
+static inline void NF_Conf(u16 conf)
+{
+	S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
+
+	nand->NFCONF = conf;
+}
+
+static inline void NF_Cmd(u8 cmd)
+{
+	S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
+
+	nand->NFCMD = cmd;
+}
+
+static inline void NF_CmdW(u8 cmd)
+{
+	NF_Cmd(cmd);
+	udelay(1);
+}
+
+static inline void NF_Addr(u8 addr)
+{
+	S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
+
+	nand->NFADDR = addr;
+}
+
+static inline void NF_SetCE(NFCE_STATE s)
+{
+	S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
+
+	switch (s) {
+		case NFCE_LOW:
+			nand->NFCONF &= ~(1<<11);
+			break;
+
+		case NFCE_HIGH:
+			nand->NFCONF |= (1<<11);
+			break;
+	}
+}
+
+static inline void NF_WaitRB(void)
+{
+	S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
+
+	while (!(nand->NFSTAT & (1<<0)));
+}
+
+static inline void NF_Write(u8 data)
+{
+	S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
+
+	nand->NFDATA = data;
+}
+
+static inline u8 NF_Read(void)
+{
+	S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
+
+	return(nand->NFDATA);
+}
+
+static inline void NF_Init_ECC(void)
+{
+	S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
+
+	nand->NFCONF |= (1<<12);
+}
+
+static inline u32 NF_Read_ECC(void)
+{
+	S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
+
+	return(nand->NFECC);
+}
+
+#endif
+
 
 #define PLD_BASE_ADDRESS		0x2C000100
 #define PLD_ID_REG			(PLD_BASE_ADDRESS + 0)
@@ -39,5 +125,3 @@ void print_vcma9_info(void);
 #define PLD_GPCD_REG			(PLD_BASE_ADDRESS + 4)
 #define PLD_BOARD_REG			(PLD_BASE_ADDRESS + 5)
 
-
-

board/smdk2400/smdk2400.c

@@ -46,33 +46,35 @@ extern int do_mdm_init; /* defined in common/main.c */
 int board_init (void)
 {
 	DECLARE_GLOBAL_DATA_PTR;
+	S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
+	S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
 
 	/* memory and cpu-speed are setup before relocation */
 	/* change the clock to be 50 MHz 1:1:1 */
-	rMPLLCON = 0x5c042;
-	rCLKDIVN = 0;
+	clk_power->MPLLCON = 0x5c042;
+	clk_power->CLKDIVN = 0;
 	/* set up the I/O ports */
-	rPACON = 0x3ffff;
-	rPBCON = 0xaaaaaaaa;
-	rPBUP = 0xffff;
-	rPECON = 0x0;
-	rPEUP = 0x0;
+	gpio->PACON = 0x3ffff;
+	gpio->PBCON = 0xaaaaaaaa;
+	gpio->PBUP = 0xffff;
+	gpio->PECON = 0x0;
+	gpio->PEUP = 0x0;
 #ifdef CONFIG_HWFLOW
 	/*CTS[0] RTS[0] INPUT INPUT TXD[0] INPUT RXD[0] */
 	/*   10,   10,   00,   00,    10,   00,    10 */
-	rPFCON=0xa22;
+	gpio->PFCON=0xa22;
 	/* Disable pull-up on Rx, Tx, CTS and RTS pins */
-	rPFUP=0x35;
+	gpio->PFUP=0x35;
 #else
 	/*INPUT INPUT INPUT INPUT TXD[0] INPUT RXD[0] */
 	/*   00,   00,   00,   00,    10,   00,    10 */
-	rPFCON = 0x22;
+	gpio->PFCON = 0x22;
 	/* Disable pull-up on Rx and Tx pins */
-	rPFUP = 0x5;
+	gpio->PFUP = 0x5;
 #endif	/* CONFIG_HWFLOW */
-	rPGCON = 0x0;
-	rPGUP = 0x0;
-	rOPENCR = 0x0;
+	gpio->PGCON = 0x0;
+	gpio->PGUP = 0x0;
+	gpio->OPENCR = 0x0;
 
 	/* arch number of SAMSUNG-Board to MACH_TYPE_SMDK2400 */
 	gd->bd->bi_arch_number = 145;

board/smdk2410/config.mk

@@ -16,10 +16,10 @@
 # Linux-Kernel is expected to be at 3000'8000, entry 3000'8000
 # optionally with a ramdisk at 3080'0000
 #
-# we load ourself to 33F0'0000
+# we load ourself to 33F8'0000
 #
 # download area is 3300'0000
 #
 
 
-TEXT_BASE = 0x33F00000
+TEXT_BASE = 0x33F80000

board/smdk2410/smdk2410.c

@@ -68,38 +68,40 @@ static inline void delay (unsigned long loops)
 int board_init (void)
 {
 	DECLARE_GLOBAL_DATA_PTR;
+	S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
+	S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
 
 	/* to reduce PLL lock time, adjust the LOCKTIME register */
-	rLOCKTIME = 0xFFFFFF;
+	clk_power->LOCKTIME = 0xFFFFFF;
 
 	/* configure MPLL */
-	rMPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
+	clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
 
 	/* some delay between MPLL and UPLL */
 	delay (4000);
 
 	/* configure UPLL */
-	rUPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
+	clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
 
 	/* some delay between MPLL and UPLL */
 	delay (8000);
 
 	/* set up the I/O ports */
-	rGPACON = 0x007FFFFF;
-	rGPBCON = 0x00044555;
-	rGPBUP = 0x000007FF;
-	rGPCCON = 0xAAAAAAAA;
-	rGPCUP = 0x0000FFFF;
-	rGPDCON = 0xAAAAAAAA;
-	rGPDUP = 0x0000FFFF;
-	rGPECON = 0xAAAAAAAA;
-	rGPEUP = 0x0000FFFF;
-	rGPFCON = 0x000055AA;
-	rGPFUP = 0x000000FF;
-	rGPGCON = 0xFF95FFBA;
-	rGPGUP = 0x0000FFFF;
-	rGPHCON = 0x002AFAAA;
-	rGPHUP = 0x000007FF;
+	gpio->GPACON = 0x007FFFFF;
+	gpio->GPBCON = 0x00044555;
+	gpio->GPBUP = 0x000007FF;
+	gpio->GPCCON = 0xAAAAAAAA;
+	gpio->GPCUP = 0x0000FFFF;
+	gpio->GPDCON = 0xAAAAAAAA;
+	gpio->GPDUP = 0x0000FFFF;
+	gpio->GPECON = 0xAAAAAAAA;
+	gpio->GPEUP = 0x0000FFFF;
+	gpio->GPFCON = 0x000055AA;
+	gpio->GPFUP = 0x000000FF;
+	gpio->GPGCON = 0xFF95FFBA;
+	gpio->GPGUP = 0x0000FFFF;
+	gpio->GPHCON = 0x002AFAAA;
+	gpio->GPHUP = 0x000007FF;
 
 	/* arch number of SMDK2410-Board */
 	gd->bd->bi_arch_number = 193;

board/trab/trab.c

@@ -71,37 +71,39 @@ int board_init ()
 	extern int vfd_init_clocks(void);
 #endif
 	DECLARE_GLOBAL_DATA_PTR;
+	S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
+	S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
 
 	/* memory and cpu-speed are setup before relocation */
 #ifdef CONFIG_TRAB_50MHZ
 	/* change the clock to be 50 MHz 1:1:1 */
 	/* MDIV:0x5c PDIV:4 SDIV:2 */
-	rMPLLCON = 0x5c042;
-	rCLKDIVN = 0;
+	clk_power->MPLLCON = 0x5c042;
+	clk_power->CLKDIVN = 0;
 #else
 	/* change the clock to be 133 MHz 1:2:4 */
 	/* MDIV:0x7d PDIV:4 SDIV:1 */
-	rMPLLCON = 0x7d041;
-	rCLKDIVN = 3;
+	clk_power->MPLLCON = 0x7d041;
+	clk_power->CLKDIVN = 3;
 #endif
 
 	/* set up the I/O ports */
-	rPACON = 0x3ffff;
-	rPBCON = 0xaaaaaaaa;
-	rPBUP  = 0xffff;
+	gpio->PACON = 0x3ffff;
+	gpio->PBCON = 0xaaaaaaaa;
+	gpio->PBUP  = 0xffff;
 	/* INPUT nCTS0 nRTS0 TXD[1] TXD[0] RXD[1] RXD[0]	*/
 	/*  00,    10,      10,      10,      10,      10,      10 	*/
-	rPFCON = (2<<0) | (2<<2) | (2<<4) | (2<<6) | (2<<8) | (2<<10);
+	gpio->PFCON = (2<<0) | (2<<2) | (2<<4) | (2<<6) | (2<<8) | (2<<10);
 #ifdef CONFIG_HWFLOW
 	/* do not pull up RXD0, RXD1, TXD0, TXD1, CTS0, RTS0 */
-	rPFUP  = (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5);
+	gpio->PFUP  = (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5);
 #else
 	/* do not pull up RXD0, RXD1, TXD0, TXD1 */
-	rPFUP  = (1<<0) | (1<<1) | (1<<2) | (1<<3);
+	gpio->PFUP  = (1<<0) | (1<<1) | (1<<2) | (1<<3);
 #endif
-	rPGCON = 0x0;
-	rPGUP  = 0x0;
-	rOPENCR= 0x0;
+	gpio->PGCON = 0x0;
+	gpio->PGUP  = 0x0;
+	gpio->OPENCR= 0x0;
 
 	/* arch number of SAMSUNG-Board */
 	/* MACH_TYPE_SMDK2400 */
@@ -112,8 +114,8 @@ int board_init ()
 	gd->bd->bi_boot_params = 0x0c000100;
 
 	/* Make sure both buzzers are turned off */
-	rPDCON |= 0x5400;
-	rPDDAT &= ~0xE0;
+	gpio->PDCON |= 0x5400;
+	gpio->PDDAT &= ~0xE0;
 
 #ifdef CONFIG_VFD
 	vfd_init_clocks();
@@ -305,57 +307,73 @@ static int key_pressed(void)
 
 #ifdef CFG_BRIGHTNESS
 
-#define SET_CS_TOUCH        (rPDDAT &= 0x5FF)
-#define CLR_CS_TOUCH        (rPDDAT |= 0x200)
+static inline void SET_CS_TOUCH(void)
+{
+	S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+
+	gpio->PDDAT &= 0x5FF;
+}
+
+static inline void CLR_CS_TOUCH(void)
+{
+	S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+
+	gpio->PDDAT |= 0x200;
+}
 
 static void spi_init(void)
 {
+	S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+	S3C24X0_SPI * const spi = S3C24X0_GetBase_SPI();
 	int i;
 
 	/* Configure I/O ports. */
- 	rPDCON = (rPDCON & 0xF3FFFF) | 0x040000;
-	rPGCON = (rPGCON & 0x0F3FFF) | 0x008000;
-	rPGCON = (rPGCON & 0x0CFFFF) | 0x020000;
-	rPGCON = (rPGCON & 0x03FFFF) | 0x080000;
+ 	gpio->PDCON = (gpio->PDCON & 0xF3FFFF) | 0x040000;
+	gpio->PGCON = (gpio->PGCON & 0x0F3FFF) | 0x008000;
+	gpio->PGCON = (gpio->PGCON & 0x0CFFFF) | 0x020000;
+	gpio->PGCON = (gpio->PGCON & 0x03FFFF) | 0x080000;
 
-	CLR_CS_TOUCH;
+	CLR_CS_TOUCH();
 
-	rSPPRE = 0x1F; /* Baudrate ca. 514kHz */
-	rSPPIN = 0x01;  /* SPI-MOSI holds Level after last bit */
-	rSPCON = 0x1A;  /* Polling, Prescaler, Master, CPOL=0, CPHA=1 */
+	spi->ch[0].SPPRE = 0x1F; /* Baudrate ca. 514kHz */
+	spi->ch[0].SPPIN = 0x01;  /* SPI-MOSI holds Level after last bit */
+	spi->ch[0].SPCON = 0x1A;  /* Polling, Prescaler, Master, CPOL=0, CPHA=1 */
 
 	/* Dummy byte ensures clock to be low. */
 	for (i = 0; i < 10; i++) {
-		rSPTDAT = 0xFF;
+		spi->ch[0].SPTDAT = 0xFF;
 	}
 	wait_transmit_done();
 }
 
 static void wait_transmit_done(void)
 {
-	while (!(rSPSTA & 0x01)); /* wait until transfer is done */
+	S3C24X0_SPI * const spi = S3C24X0_GetBase_SPI();
+
+	while (!(spi->ch[0].SPSTA & 0x01)); /* wait until transfer is done */
 }
 
 static void tsc2000_write(unsigned int page, unsigned int reg,
 						  unsigned int data)
 {
+	S3C24X0_SPI * const spi = S3C24X0_GetBase_SPI();
 	unsigned int command;
 
-	SET_CS_TOUCH;
+	SET_CS_TOUCH();
 	command = 0x0000;
 	command |= (page << 11);
 	command |= (reg << 5);
 
-	rSPTDAT = (command & 0xFF00) >> 8;
+	spi->ch[0].SPTDAT = (command & 0xFF00) >> 8;
 	wait_transmit_done();
-	rSPTDAT = (command & 0x00FF);
+	spi->ch[0].SPTDAT = (command & 0x00FF);
 	wait_transmit_done();
-	rSPTDAT = (data & 0xFF00) >> 8;
+	spi->ch[0].SPTDAT = (data & 0xFF00) >> 8;
 	wait_transmit_done();
-	rSPTDAT = (data & 0x00FF);
+	spi->ch[0].SPTDAT = (data & 0x00FF);
 	wait_transmit_done();
 
-	CLR_CS_TOUCH;
+	CLR_CS_TOUCH();
 }
 
 static void tsc2000_set_brightness(void)

board/trab/vfd.c

@@ -359,14 +359,17 @@ void transfer_pic(int display, unsigned char *adr, int height, int width)
  */
 int vfd_init_clocks (void)
 {
+	S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+	S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS();
+	S3C24X0_LCD * const lcd = S3C24X0_GetBase_LCD();
 
 	/* try to determine display type from the value
 	 * defined by pull-ups
 	 */
-	rPCUP = (rPCUP & 0xFFF0);	/* activate  GPC0...GPC3 pullups */
-	rPCCON = (rPCCON & 0xFFFFFF00);	/* configure GPC0...GPC3 as inputs */
+	gpio->PCUP = (gpio->PCUP & 0xFFF0);	/* activate  GPC0...GPC3 pullups */
+	gpio->PCCON = (gpio->PCCON & 0xFFFFFF00);	/* configure GPC0...GPC3 as inputs */
 	udelay (10);				/* allow signals to settle */
-	vfd_board_id = (~rPCDAT) & 0x000F;	/* read GPC0...GPC3 port pins */
+	vfd_board_id = (~gpio->PCDAT) & 0x000F;	/* read GPC0...GPC3 port pins */
 
 	VFD_DISABLE;				/* activate blank for the vfd */
 
@@ -377,39 +380,39 @@ int vfd_init_clocks (void)
 		/* If new board revision, then use PWM 3 as cpld-clock */
 		/* Enable 500 Hz timer for fill level sensor to operate properly */
 		/* Configure TOUT3 as functional pin, disable pull-up */
-		rPDCON &= ~0x30000;
-		rPDCON |= 0x20000;
-		rPDUP |= (1 << 8);
+		gpio->PDCON &= ~0x30000;
+		gpio->PDCON |= 0x20000;
+		gpio->PDUP |= (1 << 8);
 
 		/* Configure the prescaler */
-		rTCFG0 &= ~0xff00;
-		rTCFG0 |= 0x0f00;
+		timers->TCFG0 &= ~0xff00;
+		timers->TCFG0 |= 0x0f00;
 
 		/* Select MUX input (divider) for timer3 (1/16) */
-		rTCFG1 &= ~0xf000;
-		rTCFG1 |= 0x3000;
+		timers->TCFG1 &= ~0xf000;
+		timers->TCFG1 |= 0x3000;
 
 		/* Enable autoreload and set the counter and compare
 		 * registers to values for the 500 Hz clock
 		 * (for a given  prescaler (15) and divider (16)):
 		 * counter = (66000000 / 500) >> 9;
 		 */
-		rTCNTB3 = 0x101;
-		rTCMPB3 = 0x101 / 2;
+		timers->ch[3].TCNTB = 0x101;
+		timers->ch[3].TCMPB = 0x101 / 2;
 
 		/* Start timer */
-		rTCON = (rTCON | UPDATE3 | RELOAD3) & ~INVERT3;
-		rTCON = (rTCON | START3) & ~UPDATE3;
+		timers->TCON = (timers->TCON | UPDATE3 | RELOAD3) & ~INVERT3;
+		timers->TCON = (timers->TCON | START3) & ~UPDATE3;
 	}
 #endif
 	/* If old board revision, then use vm-signal as cpld-clock */
-	rLCDCON2 = 0x00FFC000;
-	rLCDCON3 = 0x0007FF00;
-	rLCDCON4 = 0x00000000;
-	rLCDCON5 = 0x00000400;
-	rLCDCON1 = 0x00000B75;
+	lcd->LCDCON2 = 0x00FFC000;
+	lcd->LCDCON3 = 0x0007FF00;
+	lcd->LCDCON4 = 0x00000000;
+	lcd->LCDCON5 = 0x00000400;
+	lcd->LCDCON1 = 0x00000B75;
 	/* VM (GPD1) is used as clock for the CPLD */
-	rPDCON = (rPDCON & 0xFFFFFFF3) | 0x00000008;
+	gpio->PDCON = (gpio->PDCON & 0xFFFFFFF3) | 0x00000008;
 
 	return 0;
 }
@@ -425,6 +428,8 @@ int vfd_init_clocks (void)
  */
 int drv_vfd_init(void)
 {
+	S3C24X0_LCD * const lcd = S3C24X0_GetBase_LCD();
+	S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
 	char *tmp;
 	ulong palette;
 	static int vfd_init_done = 0;
@@ -481,40 +486,40 @@ int drv_vfd_init(void)
 	 * see manual S3C2400
 	 */
 	/* Stopp LCD-Controller */
-	rLCDCON1 = 0x00000000;
+	lcd->LCDCON1 = 0x00000000;
 	/* frame buffer startadr */
-	rLCDSADDR1 = gd->fb_base >> 1;
+	lcd->LCDSADDR1 = gd->fb_base >> 1;
  	/* frame buffer endadr */
-	rLCDSADDR2 = (gd->fb_base + FRAME_BUF_SIZE) >> 1;
-	rLCDSADDR3 = ((256/4));
-rLCDCON2 = 0x000DC000;
+	lcd->LCDSADDR2 = (gd->fb_base + FRAME_BUF_SIZE) >> 1;
+	lcd->LCDSADDR3 = ((256/4));
+	lcd->LCDCON2 = 0x000DC000;
 	if(gd->vfd_type == VFD_TYPE_MN11236)
-		rLCDCON2 = 37 << 14;	/* MN11236: 38 lines */
+		lcd->LCDCON2 = 37 << 14;	/* MN11236: 38 lines */
 	else
-		rLCDCON2 = 55 << 14;	/* T119C:   56 lines */
-	rLCDCON3 = 0x0051000A;
-	rLCDCON4 = 0x00000001;
+		lcd->LCDCON2 = 55 << 14;	/* T119C:   56 lines */
+	lcd->LCDCON3 = 0x0051000A;
+	lcd->LCDCON4 = 0x00000001;
 	if (gd->vfd_type && vfd_inv_data)
-		rLCDCON5 = 0x000004C0;
+		lcd->LCDCON5 = 0x000004C0;
 	else
-		rLCDCON5 = 0x00000440;
+		lcd->LCDCON5 = 0x00000440;
 
 	/* Port pins as LCD output */
-	rPCCON =   (rPCCON & 0xFFFFFF00)| 0x000000AA;
-	rPDCON =   (rPDCON & 0xFFFFFF03)| 0x000000A8;
+	gpio->PCCON =   (gpio->PCCON & 0xFFFFFF00)| 0x000000AA;
+	gpio->PDCON =   (gpio->PDCON & 0xFFFFFF03)| 0x000000A8;
 
 	/* Synchronize VFD enable with LCD controller to avoid flicker	*/
-	rLCDCON1 = 0x00000B75;			/* Start LCD-Controller	*/
-	while((rLCDCON5 & 0x180000)!=0x100000);	/* Wait for end of VSYNC */
-	while((rLCDCON5 & 0x060000)!=0x040000);	/* Wait for next HSYNC	*/
-	while((rLCDCON5 & 0x060000)==0x040000);
-	while((rLCDCON5 & 0x060000)!=0x000000);
+	lcd->LCDCON1 = 0x00000B75;			/* Start LCD-Controller	*/
+	while((lcd->LCDCON5 & 0x180000)!=0x100000);	/* Wait for end of VSYNC */
+	while((lcd->LCDCON5 & 0x060000)!=0x040000);	/* Wait for next HSYNC	*/
+	while((lcd->LCDCON5 & 0x060000)==0x040000);
+	while((lcd->LCDCON5 & 0x060000)!=0x000000);
 	if(gd->vfd_type)
 		VFD_ENABLE;
 
-	debug ("LCDSADDR1: %lX\n", rLCDSADDR1);
-	debug ("LCDSADDR2: %lX\n", rLCDSADDR2);
-	debug ("LCDSADDR3: %lX\n", rLCDSADDR3);
+	debug ("LCDSADDR1: %lX\n", lcd->LCDSADDR1);
+	debug ("LCDSADDR2: %lX\n", lcd->LCDSADDR2);
+	debug ("LCDSADDR3: %lX\n", lcd->LCDSADDR3);
 
 	return 0;
 }
@@ -525,9 +530,11 @@ rLCDCON2 = 0x000DC000;
  */
 void disable_vfd (void)
 {
+	S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+
 	VFD_DISABLE;
-	rPDCON &= ~0xC;
-	rPDUP  &= ~0x2;
+	gpio->PDCON &= ~0xC;
+	gpio->PDUP  &= ~0x2;
 }
 
 /************************************************************************/

cpu/arm920t/interrupts.c

@@ -43,7 +43,12 @@ extern void reset_cpu(ulong addr);
 int timer_load_val = 0;
 
 /* macro to read the 16 bit timer */
-#define READ_TIMER (rTCNTO4 & 0xffff)
+static inline ulong READ_TIMER(void)
+{
+	S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS();
+
+	return (timers->TCNTO4 & 0xffff);
+}
 
 #ifdef CONFIG_USE_IRQ
 /* enable IRQ interrupts */
@@ -184,9 +189,11 @@ static ulong lastdec;
 
 int interrupt_init (void)
 {
+	S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS();
+
 	/* use PWM Timer 4 because it has no output */
 	/* prescaler for Timer 4 is 16 */
-	rTCFG0 = 0x0f00;
+	timers->TCFG0 = 0x0f00;
 	if (timer_load_val == 0)
 	{
 		/*
@@ -197,11 +204,11 @@ int interrupt_init (void)
 		timer_load_val = get_PCLK()/(2 * 16 * 100);
 	}
 	/* load value for 10 ms timeout */
-	lastdec = rTCNTB4 = timer_load_val;
+	lastdec = timers->TCNTB4 = timer_load_val;
 	/* auto load, manual update of Timer 4 */
-	rTCON = (rTCON & ~0x0700000) | 0x600000;
+	timers->TCON = (timers->TCON & ~0x0700000) | 0x600000;
 	/* auto load, start Timer 4 */
-	rTCON = (rTCON & ~0x0700000) | 0x500000;
+	timers->TCON = (timers->TCON & ~0x0700000) | 0x500000;
 	timestamp = 0;
 
 	return (0);
@@ -243,13 +250,13 @@ void udelay (unsigned long usec)
 void reset_timer_masked (void)
 {
 	/* reset time */
-	lastdec = READ_TIMER;
+	lastdec = READ_TIMER();
 	timestamp = 0;
 }
 
 ulong get_timer_masked (void)
 {
-	ulong now = READ_TIMER;
+	ulong now = READ_TIMER();
 
 	if (lastdec >= now) {
 		/* normal mode */

cpu/arm920t/serial.c

@@ -25,57 +25,51 @@
 #include <s3c2410.h>
 #endif
 
+#ifdef CONFIG_SERIAL1
+#define UART_NR	S3C24X0_UART0
+
+#elif CONFIG_SERIAL2
+# if defined(CONFIG_TRAB)
+#  #error "TRAB supports only CONFIG_SERIAL1"
+# endif
+#define UART_NR	S3C24X0_UART1
+
+#elif CONFIG_SERIAL3
+# if defined(CONFIG_TRAB)
+#  #error "TRAB supports only CONFIG_SERIAL1"
+# endif
+#define UART_NR	S3C24X0_UART2
+
+#else
+#error "Bad: you didn't configure serial ..."
+#endif
 
 void serial_setbrg (void)
 {
 	DECLARE_GLOBAL_DATA_PTR;
-
+	S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR);
 	int i;
 	unsigned int reg = 0;
 
 	/* value is calculated so : (int)(PCLK/16./baudrate) -1 */
 	reg = get_PCLK() / (16 * gd->baudrate) - 1;
 
-#ifdef CONFIG_SERIAL1
 	/* FIFO enable, Tx/Rx FIFO clear */
-	rUFCON0 = 0x07;
-	rUMCON0 = 0x0;
+	uart->UFCON = 0x07;
+	uart->UMCON = 0x0;
 	/* Normal,No parity,1 stop,8 bit */
-	rULCON0 = 0x3;
+	uart->ULCON = 0x3;
 	/*
 	 * tx=level,rx=edge,disable timeout int.,enable rx error int.,
 	 * normal,interrupt or polling
 	 */
-	rUCON0 = 0x245;
-	rUBRDIV0 = reg;
+	uart->UCON = 0x245;
+	uart->UBRDIV = reg;
 
 #ifdef CONFIG_HWFLOW
-	rUMCON0 = 0x1; /* RTS up */
+	uart->UMCON = 0x1; /* RTS up */
 #endif
 	for (i = 0; i < 100; i++);
-#elif CONFIG_SERIAL2
-# if defined(CONFIG_TRAB)
-#  #error "TRAB supports only CONFIG_SERIAL1"
-# endif
-	/* FIFO enable, Tx/Rx FIFO clear */
-	rUFCON1 = 0x06;
-	rUMCON1 = 0x0;
-	/* Normal,No parity,1 stop,8 bit */
-	rULCON1 = 0x3;
-	/*
-	 * tx=level,rx=edge,disable timeout int.,enable rx error int.,
-	 * normal,interrupt or polling
-	 */
-	rUCON1 = 0x245;
-	rUBRDIV1 = reg;
-
-#ifdef CONFIG_HWFLOW
-	rUMCON1 = 0x1; /* RTS up */
-#endif
-	for (i = 0; i < 100; i++);
-#else
-#error "Bad: you didn't configure serial ..."
-#endif
 }
 
 /*
@@ -97,15 +91,12 @@ int serial_init (void)
  */
 int serial_getc (void)
 {
-#ifdef CONFIG_SERIAL1
-	while (!(rUTRSTAT0 & 0x1));
+	S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR);
+	
+	/* wait for character to arrive */
+	while (!(uart->UTRSTAT & 0x1));
 
-	return rURXH0 & 0xff;
-#elif CONFIG_SERIAL2
-	while (!(rUTRSTAT1 & 0x1));
-
-	return rURXH1 & 0xff;
-#endif
+	return uart->URXH & 0xff;
 }
 
 #ifdef CONFIG_HWFLOW
@@ -146,33 +137,22 @@ void enable_putc(void)
  */
 void serial_putc (const char c)
 {
+	S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR);
 #ifdef CONFIG_MODEM_SUPPORT
 	if (be_quiet)
 		return;
 #endif
 
-#ifdef CONFIG_SERIAL1
-	/* wait for room in the tx FIFO on SERIAL1 */
-	while (!(rUTRSTAT0 & 0x2));
+	/* wait for room in the tx FIFO */
+	while (!(uart->UTRSTAT & 0x2));
 
 #ifdef CONFIG_HWFLOW
 	/* Wait for CTS up */
-	while(hwflow && !(rUMSTAT0 & 0x1))
+	while(hwflow && !(uart->UMSTAT & 0x1))
 		;
 #endif
 
-	rUTXH0 = c;
-#elif CONFIG_SERIAL2
-	/* wait for room in the tx FIFO on SERIAL2 */
-	while (!(rUTRSTAT1 & 0x2));
-
-#ifdef CONFIG_HWFLOW
-	/* Wait for CTS up */
-	while(hwflow && !(rUMSTAT1 & 0x1))
-		;
-#endif
-	rUTXH1 = c;
-#endif
+	uart->UTXH = c;
 
 	/* If \n, also do \r */
 	if (c == '\n')
@@ -184,11 +164,9 @@ void serial_putc (const char c)
  */
 int serial_tstc (void)
 {
-#ifdef CONFIG_SERIAL1
-	return rUTRSTAT0 & 0x1;
-#elif CONFIG_SERIAL2
-	return rUTRSTAT1 & 0x1;
-#endif
+	S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR);
+
+	return uart->UTRSTAT & 0x1;
 }
 
 void

cpu/arm920t/speed.c

@@ -51,12 +51,13 @@
 
 static ulong get_PLLCLK(int pllreg)
 {
+    S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
     ulong r, m, p, s;
 
     if (pllreg == MPLL)
-	r = rMPLLCON;
+	r = clk_power->MPLLCON;
     else if (pllreg == UPLL)
-	r = rUPLLCON;
+	r = clk_power->UPLLCON;
     else
 	hang();
 
@@ -76,17 +77,17 @@ ulong get_FCLK(void)
 /* return HCLK frequency */
 ulong get_HCLK(void)
 {
-    ulong clkdiv = rCLKDIVN;
+    S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
 
-    return((clkdiv & 0x2) ? get_FCLK()/2 : get_FCLK());
+    return((clk_power->CLKDIVN & 0x2) ? get_FCLK()/2 : get_FCLK());
 }
 
 /* return PCLK frequency */
 ulong get_PCLK(void)
 {
-    ulong clkdiv = rCLKDIVN;
+    S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
 
-    return((clkdiv & 0x1) ? get_HCLK()/2 : get_HCLK());
+    return((clk_power->CLKDIVN & 0x1) ? get_HCLK()/2 : get_HCLK());
 }
 
 /* return UCLK frequency */

cpu/mpc5xx/Makefile

@@ -35,7 +35,7 @@ include $(TOPDIR)/config.mk
 LIB	= lib$(CPU).a
 
 START	= start.S 
-OBJS	= serial.o cpu.o cpu_init.o interrupts.o traps.o speed.o status_led.o
+OBJS	= serial.o cpu.o cpu_init.o interrupts.o traps.o speed.o
 
 all:	.depend $(START) $(LIB)
 

cpu/mpc5xx/status_led.c

@@ -1,161 +0,0 @@
-/*
- * (C) Copyright 2000-2002	Wolfgang Denk, DENX Software Engineering, wd@denx.de
- * (C) Copyright 2003		Martin Winistoerfer, martinwinistoerfer@gmx.ch.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * File:		status_led.c
- * 
- * Discription:		Blink a board led to show boot progress. Led's
- *			are connected via the MIOS module.
- */
-
-#include <common.h>
-#include <mpc5xx.h>
-#include <status_led.h>
-
-#ifdef CONFIG_STATUS_LED
-
-typedef struct {
-	ulong	mask;
-	int	state;
-	int	period;
-	int	cnt;
-} led_dev_t;
-
-led_dev_t led_dev[] = {
-    {	STATUS_LED_BIT,
-	STATUS_LED_STATE,
-	STATUS_LED_PERIOD,
-	0,
-    },
-#if defined(STATUS_LED_BIT1)
-    {	STATUS_LED_BIT1,
-	STATUS_LED_STATE1,
-	STATUS_LED_PERIOD1,
-	0,
-    },
-#endif
-#if defined(STATUS_LED_BIT2)
-    {	STATUS_LED_BIT2,
-	STATUS_LED_STATE2,
-	STATUS_LED_PERIOD2,
-	0,
-    },
-#endif
-#if defined(STATUS_LED_BIT3)
-    {	STATUS_LED_BIT3,
-	STATUS_LED_STATE3,
-	STATUS_LED_PERIOD3,
-	0,
-    },
-#endif
-};
-
-#define MAX_LED_DEV	(sizeof(led_dev)/sizeof(led_dev_t))
-
-static int status_led_init_done = 0;
-
-static void status_led_init (void)
-{
-    volatile immap_t *immr = (immap_t *)CFG_IMMR;
-    int i;
-
-    for (i=0; i<MAX_LED_DEV; ++i) {
-	led_dev_t *ld = &led_dev[i];
-	
-	immr->STATUS_LED_DIR = STATUS_LED_BIT;
-
-#if (STATUS_LED_ACTIVE == 0)
-	if (ld->state == STATUS_LED_ON)
-		immr->STATUS_LED_DAT &= ~(ld->mask);
-	else
-		immr->STATUS_LED_DAT |=   ld->mask ;
-#else
-	if (ld->state == STATUS_LED_ON)
-		immr->STATUS_LED_DAT |=   ld->mask ;
-	else
-		immr->STATUS_LED_DAT &= ~(ld->mask);
-#endif
-    }
-
-    status_led_init_done  = 1;
-}
-
-void status_led_tick (ulong timestamp)
-{
-    volatile immap_t *immr = (immap_t *)CFG_IMMR;
-    int i;
-
-    if (!status_led_init_done)
-	status_led_init();
-
-    for (i=0; i<MAX_LED_DEV; ++i) {
-	led_dev_t *ld = &led_dev[i];
-
-	if (ld->state != STATUS_LED_BLINKING)
-		continue;
-
-	if (++(ld->cnt) >= ld->period) {
-		immr->STATUS_LED_DAT ^= ld->mask;
-		ld->cnt -= ld->period;
-	}
-    }
-}
-
-void status_led_set (int led, int state)
-{
-    volatile immap_t *immr = (immap_t *)CFG_IMMR;
-    led_dev_t *ld;
-
-    if (led < 0 || led >= MAX_LED_DEV)
-	return;
-
-    if (!status_led_init_done)
-	status_led_init();
-
-    ld = &led_dev[led];
-
-    switch (state) {
-    default:
-	return;
-    case STATUS_LED_BLINKING:
-	ld->cnt = 0;		/* always start with full period	*/
-	/* fall through */	/* always start with LED _ON_		*/
-    case STATUS_LED_ON:
-#if (STATUS_LED_ACTIVE == 0)
-	immr->STATUS_LED_DAT &= ~(ld->mask);
-#else
-	immr->STATUS_LED_DAT |=   ld->mask ;
-#endif
-	break;
-    case STATUS_LED_OFF:
-#if (STATUS_LED_ACTIVE == 0)
-	immr->STATUS_LED_DAT |=   ld->mask ;
-#else
-	immr->STATUS_LED_DAT &= ~(ld->mask);
-#endif
-	break;
-    }
-    ld->state = state;
-}
-
-#endif	/* CONFIG_STATUS_LED */

cpu/mpc8260/Makefile

@@ -28,7 +28,7 @@ LIB	= lib$(CPU).a
 START	= start.o kgdb.o
 OBJS	= traps.o serial_smc.o serial_scc.o cpu.o cpu_init.o speed.o \
 	  interrupts.o ether_scc.o ether_fcc.o i2c.o commproc.o \
-	  bedbug_603e.o status_led.o pci.o spi.o
+	  bedbug_603e.o pci.o spi.o
 
 all:	.depend $(START) $(LIB)
 

cpu/mpc8260/ether_scc.c

@@ -333,7 +333,7 @@ int eth_init(bd_t *bis)
     immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl |= (SCC_GSMRL_ENR |
                                                      SCC_GSMRL_ENT);
 
-    return 1;
+    return 0;
 }
 
 

cpu/mpc8260/start.S

@@ -161,6 +161,7 @@ _hrcw_table:
 	.globl	_start
 _start:
 	li	r21, BOOTFLAG_COLD	/* Normal Power-On: Boot from FLASH*/
+	nop
 	b	boot_cold
 
 	. = EXC_OFF_SYS_RESET + 0x10
@@ -171,6 +172,18 @@ _start_warm:
 	b	boot_warm
 
 boot_cold:
+#if defined(CONFIG_MPC8260ADS)
+	lis	r3, CFG_DEFAULT_IMMR@h
+	nop
+	lwz	r4, 0(r3)
+	nop
+	rlwinm	r4, r4, 0, 8, 5
+	nop
+	oris	r4, r4, 0x0200
+	nop
+	stw	r4, 0(r3)
+	nop
+#endif /* CONFIG_MPC8260ADS */
 boot_warm:
 	mfmsr	r5			/* save msr contents		*/
 

cpu/mpc8260/status_led.c

@@ -1,160 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <status_led.h>
-
-/*
- * The purpose of this code is to signal the operational status of a
- * target which usually boots over the network; while running in
- * PCBoot, a status LED is blinking. As soon as a valid BOOTP reply
- * message has been received, the LED is turned off. The Linux
- * kernel, once it is running, will start blinking the LED again,
- * with another frequency.
- */
-
-/* ------------------------------------------------------------------------- */
-
-#ifdef CONFIG_STATUS_LED
-
-typedef struct {
-	ulong	mask;
-	int	state;
-	int	period;
-	int	cnt;
-} led_dev_t;
-
-led_dev_t led_dev[] = {
-    {	STATUS_LED_BIT,
-	STATUS_LED_STATE,
-	STATUS_LED_PERIOD,
-	0,
-    },
-#if defined(STATUS_LED_BIT1)
-    {	STATUS_LED_BIT1,
-	STATUS_LED_STATE1,
-	STATUS_LED_PERIOD1,
-	0,
-    },
-#endif
-#if defined(STATUS_LED_BIT2)
-    {	STATUS_LED_BIT2,
-	STATUS_LED_STATE2,
-	STATUS_LED_PERIOD2,
-	0,
-    },
-#endif
-};
-
-#define MAX_LED_DEV	(sizeof(led_dev)/sizeof(led_dev_t))
-
-static int status_led_init_done = 0;
-
-static void status_led_init (void)
-{
-    volatile immap_t *immr = (immap_t *)CFG_IMMR;
-    int i;
-
-    for (i=0; i<MAX_LED_DEV; ++i) {
-	led_dev_t *ld = &led_dev[i];
-
-	immr->STATUS_LED_PAR &= ~(ld->mask);
-#ifdef STATUS_LED_ODR
-	immr->STATUS_LED_ODR &= ~(ld->mask);
-#endif
-#if (STATUS_LED_ACTIVE == 0)
-	if (ld->state == STATUS_LED_ON)
-		immr->STATUS_LED_DAT &= ~(ld->mask);
-	else
-		immr->STATUS_LED_DAT |=   ld->mask ;
-#else
-	if (ld->state == STATUS_LED_ON)
-		immr->STATUS_LED_DAT |=   ld->mask ;
-	else
-		immr->STATUS_LED_DAT &= ~(ld->mask);
-#endif
-	immr->STATUS_LED_DIR |=   ld->mask ;
-    }
-
-    status_led_init_done  = 1;
-}
-
-void status_led_tick (ulong timestamp)
-{
-    volatile immap_t *immr = (immap_t *)CFG_IMMR;
-    int i;
-
-    if (!status_led_init_done)
-	status_led_init();
-
-    for (i=0; i<MAX_LED_DEV; ++i) {
-	led_dev_t *ld = &led_dev[i];
-
-	if (ld->state != STATUS_LED_BLINKING)
-		continue;
-
-	if (++(ld->cnt) >= ld->period) {
-		immr->STATUS_LED_DAT ^= ld->mask;
-		ld->cnt -= ld->period;
-	}
-    }
-}
-
-void status_led_set (int led, int state)
-{
-    volatile immap_t *immr = (immap_t *)CFG_IMMR;
-    led_dev_t *ld;
-
-    if (led < 0 || led >= MAX_LED_DEV)
-	return;
-
-    if (!status_led_init_done)
-	status_led_init();
-
-    ld = &led_dev[led];
-
-    switch (state) {
-    default:
-	return;
-    case STATUS_LED_BLINKING:
-	ld->cnt = 0;		/* always start with full period	*/
-	/* fall through */	/* always start with LED _ON_		*/
-    case STATUS_LED_ON:
-#if (STATUS_LED_ACTIVE == 0)
-	immr->STATUS_LED_DAT &= ~(ld->mask);
-#else
-	immr->STATUS_LED_DAT |=   ld->mask ;
-#endif
-	break;
-    case STATUS_LED_OFF:
-#if (STATUS_LED_ACTIVE == 0)
-	immr->STATUS_LED_DAT |=   ld->mask ;
-#else
-	immr->STATUS_LED_DAT &= ~(ld->mask);
-#endif
-	break;
-    }
-    ld->state = state;
-}
-
-#endif	/* CONFIG_STATUS_LED */

cpu/mpc8xx/Makefile

@@ -30,7 +30,7 @@ LIB	= lib$(CPU).a
 START	= start.o kgdb.o
 OBJS	= bedbug_860.o commproc.o cpu.o cpu_init.o	\
 	  fec.o i2c.o interrupts.o lcd.o scc.o		\
-	  serial.o speed.o spi.o status_led.o\
+	  serial.o speed.o spi.o \
 	  traps.o upatch.o video.o
 
 all:	.depend $(START) $(LIB)

drivers/Makefile

@@ -38,7 +38,8 @@ OBJS	= 3c589.o 5701rls.o ali512x.o \
 	  pcnet.o plb2800_eth.o \
 	  s3c24x0_i2c.o sed13806.o serial.o \
 	  smc91111.o smiLynxEM.o              sym53c8xx.o \
-	  ti_pci1410a.o tigon3.o w83c553f.o
+	  ti_pci1410a.o tigon3.o w83c553f.o \
+	  status_led.o
 
 ## Disabled for now:
 ##	  cs8900.o ct69000.o dataflash.o dc2114x.o ds1722.o \

drivers/s3c24x0_i2c.c

@@ -39,103 +39,114 @@
 
 #ifdef CONFIG_HARD_I2C
 
-#define	IIC_WRITE	0
-#define IIC_READ	1
+#define	I2C_WRITE	0
+#define I2C_READ	1
 
-#define IIC_OK		0
-#define IIC_NOK		1
-#define IIC_NACK	2
-#define IIC_NOK_LA	3		/* Lost arbitration */
-#define IIC_NOK_TOUT	4		/* time out */
+#define I2C_OK		0
+#define I2C_NOK		1
+#define I2C_NACK	2
+#define I2C_NOK_LA	3		/* Lost arbitration */
+#define I2C_NOK_TOUT	4		/* time out */
 
-#define IICSTAT_BSY	0x20		/* Busy bit */
-#define IICSTAT_NACK	0x01		/* Nack bit */
-#define IICCON_IRPND	0x10		/* Interrupt pending bit */
-#define IIC_MODE_MT	0xC0		/* Master Transmit Mode */
-#define IIC_MODE_MR	0x80		/* Master Receive Mode */
-#define IIC_START_STOP	0x20		/* START / STOP */
-#define IIC_TXRX_ENA	0x10		/* I2C Tx/Rx enable */
+#define I2CSTAT_BSY	0x20		/* Busy bit */
+#define I2CSTAT_NACK	0x01		/* Nack bit */
+#define I2CCON_IRPND	0x10		/* Interrupt pending bit */
+#define I2C_MODE_MT	0xC0		/* Master Transmit Mode */
+#define I2C_MODE_MR	0x80		/* Master Receive Mode */
+#define I2C_START_STOP	0x20		/* START / STOP */
+#define I2C_TXRX_ENA	0x10		/* I2C Tx/Rx enable */
 
-#define IIC_TIMEOUT 1			/* 1 seconde */
+#define I2C_TIMEOUT 1			/* 1 seconde */
 
 
-static int GetIICSDA(void)
+static int GetI2CSDA(void)
 {
-	return (rGPEDAT & 0x8000) >> 15;
+	S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+
+	return (gpio->GPEDAT & 0x8000) >> 15;
 }
 
 #if 0
-static void SetIICSDA(int x)
+static void SetI2CSDA(int x)
 {
 	rGPEDAT = (rGPEDAT & ~0x8000) | (x&1) << 15;
 }
 #endif
 
-static void SetIICSCL(int x)
+static void SetI2CSCL(int x)
 {
-	rGPEDAT = (rGPEDAT & ~0x4000) | (x&1) << 14;
+	S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+
+	gpio->GPEDAT = (gpio->GPEDAT & ~0x4000) | (x&1) << 14;
 }
 
 
 static int WaitForXfer(void)
 {
+    S3C24X0_I2C * const i2c = S3C24X0_GetBase_I2C();
     int i, status;
 
-    i = IIC_TIMEOUT * 1000;
-    status = rIICCON;
-    while ((i > 0) && !(status & IICCON_IRPND)) {
+    i = I2C_TIMEOUT * 1000;
+    status = i2c->IICCON;
+    while ((i > 0) && !(status & I2CCON_IRPND)) {
     	udelay(1000);
-	status = rIICCON;
+	status = i2c->IICCON;
 	i--;
     }
 
-    return(status & IICCON_IRPND) ? IIC_OK : IIC_NOK_TOUT;
+    return(status & I2CCON_IRPND) ? I2C_OK : I2C_NOK_TOUT;
 }
 
 static int IsACK(void)
 {
-    return(!(rIICSTAT & IICSTAT_NACK));
+    S3C24X0_I2C * const i2c = S3C24X0_GetBase_I2C();
+
+    return(!(i2c->IICSTAT & I2CSTAT_NACK));
 }
 
 static void ReadWriteByte(void)
 {
-    rIICCON &= ~IICCON_IRPND;
+    S3C24X0_I2C * const i2c = S3C24X0_GetBase_I2C();
+
+    i2c->IICCON &= ~I2CCON_IRPND;
 }
 
 void i2c_init (int speed, int slaveadd)
 {
+    S3C24X0_I2C * const i2c = S3C24X0_GetBase_I2C();
+    S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
     ulong freq, pres = 16, div;
     int i, status;
 
     /* wait for some time to give previous transfer a chance to finish */
 
-    i = IIC_TIMEOUT * 1000;
-    status = rIICSTAT;
-    while ((i > 0) && (status & IICSTAT_BSY)) {
+    i = I2C_TIMEOUT * 1000;
+    status = i2c->IICSTAT;
+    while ((i > 0) && (status & I2CSTAT_BSY)) {
 	udelay(1000);
-	status = rIICSTAT;
+	status = i2c->IICSTAT;
 	i--;
     }
 
-    if ((status & IICSTAT_BSY) || GetIICSDA() == 0) {
-	ulong old_gpecon = rGPECON;
+    if ((status & I2CSTAT_BSY) || GetI2CSDA() == 0) {
+	ulong old_gpecon = gpio->GPECON;
 	/* bus still busy probably by (most) previously interrupted transfer */
 
-	/* set IICSDA and IICSCL (GPE15, GPE14) to GPIO */
-	rGPECON = (rGPECON & ~0xF0000000) | 0x10000000;
+	/* set I2CSDA and I2CSCL (GPE15, GPE14) to GPIO */
+	gpio->GPECON = (gpio->GPECON & ~0xF0000000) | 0x10000000;
 
-	/* toggle IICSCL until bus idle */
-	SetIICSCL(0); udelay(1000);
+	/* toggle I2CSCL until bus idle */
+	SetI2CSCL(0); udelay(1000);
 	i = 10;
-	while ((i > 0) && (GetIICSDA() != 1)) {
-		SetIICSCL(1); udelay(1000);
-		SetIICSCL(0); udelay(1000);
+	while ((i > 0) && (GetI2CSDA() != 1)) {
+		SetI2CSCL(1); udelay(1000);
+		SetI2CSCL(0); udelay(1000);
 		i--;
 	}
-	SetIICSCL(1); udelay(1000);
+	SetI2CSCL(1); udelay(1000);
 
 	/* restore pin functions */
-	rGPECON = old_gpecon;
+	gpio->GPECON = old_gpecon;
     }
 
     /* calculate prescaler and divisor values */
@@ -150,13 +161,13 @@ void i2c_init (int speed, int slaveadd)
 
     /* set prescaler, divisor according to freq, also set
        ACKGEN, IRQ */
-    rIICCON = (div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0);
+    i2c->IICCON = (div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0);
 
     /* init to SLAVE REVEIVE and set slaveaddr */
-    rIICSTAT = 0;
-    rIICADD = slaveadd;
+    i2c->IICSTAT = 0;
+    i2c->IICADD = slaveadd;
     /* program Master Transmit (and implicit STOP) */
-    rIICSTAT = IIC_MODE_MT | IIC_TXRX_ENA;
+    i2c->IICSTAT = I2C_MODE_MT | I2C_TXRX_ENA;
 
 }
 
@@ -176,142 +187,143 @@ int i2c_transfer(unsigned char cmd_type,
                  unsigned char data[],
 		 unsigned short data_len)
 {
+    S3C24X0_I2C * const i2c = S3C24X0_GetBase_I2C();
     int i, status, result;
 
     if (data == 0 || data_len == 0) {
 	/*Don't support data transfer of no length or to address 0*/
 	printf( "i2c_transfer: bad call\n" );
-	return IIC_NOK;
+	return I2C_NOK;
     }
 
     //CheckDelay();
 
     /* Check I2C bus idle */
-    i = IIC_TIMEOUT * 1000;
-    status = rIICSTAT;
-    while ((i > 0) && (status & IICSTAT_BSY)) {
+    i = I2C_TIMEOUT * 1000;
+    status = i2c->IICSTAT;
+    while ((i > 0) && (status & I2CSTAT_BSY)) {
 	udelay(1000);
-	status = rIICSTAT;
+	status = i2c->IICSTAT;
 	i--;
     }
 
 
-    if (status & IICSTAT_BSY) {
-	result = IIC_NOK_TOUT;
+    if (status & I2CSTAT_BSY) {
+	result = I2C_NOK_TOUT;
         return(result);
     }
 
-    rIICCON |= 0x80;
+    i2c->IICCON |= 0x80;
 
-    result = IIC_OK;
+    result = I2C_OK;
 
     switch (cmd_type) {
-	case IIC_WRITE:
+	case I2C_WRITE:
 	    if (addr && addr_len) {
-		rIICDS = chip;
+		i2c->IICDS = chip;
 		/* send START */
-		rIICSTAT = IIC_MODE_MT | IIC_TXRX_ENA | IIC_START_STOP;
+		i2c->IICSTAT = I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP;
 		i = 0;
-		while ((i < addr_len) && (result == IIC_OK)) {
+		while ((i < addr_len) && (result == I2C_OK)) {
 		    result = WaitForXfer();
-		    rIICDS = addr[i];
+		    i2c->IICDS = addr[i];
 		    ReadWriteByte();
 		    i++;
 		}
 		i = 0;
-		while ((i < data_len) && (result == IIC_OK)) {
+		while ((i < data_len) && (result == I2C_OK)) {
 		    result = WaitForXfer();
-		    rIICDS = data[i];
+		    i2c->IICDS = data[i];
 		    ReadWriteByte();
 		    i++;
 		}
 	    } else {
-		rIICDS = chip;
+		i2c->IICDS = chip;
 		/* send START */
-		rIICSTAT = IIC_MODE_MT | IIC_TXRX_ENA | IIC_START_STOP;
+		i2c->IICSTAT = I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP;
 		i = 0;
-		while ((i < data_len) && (result = IIC_OK)) {
+		while ((i < data_len) && (result = I2C_OK)) {
 		    result = WaitForXfer();
-		    rIICDS = data[i];
+		    i2c->IICDS = data[i];
 		    ReadWriteByte();
 		    i++;
 		}
 	    }
 
-	    if (result == IIC_OK)
+	    if (result == I2C_OK)
 	        result = WaitForXfer();
 
 	    /* send STOP */
-	    rIICSTAT = IIC_MODE_MR | IIC_TXRX_ENA;
+	    i2c->IICSTAT = I2C_MODE_MR | I2C_TXRX_ENA;
 	    ReadWriteByte();
 	    break;
 
-	case IIC_READ:
+	case I2C_READ:
 	    if (addr && addr_len) {
-		rIICSTAT = IIC_MODE_MT | IIC_TXRX_ENA;
-		rIICDS = chip;
+		i2c->IICSTAT = I2C_MODE_MT | I2C_TXRX_ENA;
+		i2c->IICDS = chip;
 		/* send START */
-		rIICSTAT |= IIC_START_STOP;
+		i2c->IICSTAT |= I2C_START_STOP;
 		result = WaitForXfer();
 		if (IsACK()) {
 		    i = 0;
-		    while ((i < addr_len) && (result == IIC_OK)) {
-			rIICDS = addr[i];
+		    while ((i < addr_len) && (result == I2C_OK)) {
+			i2c->IICDS = addr[i];
 			ReadWriteByte();
 			result = WaitForXfer();
 			i++;
 		    }
 
-		    rIICDS = chip;
+		    i2c->IICDS = chip;
 		    /* resend START */
-		    rIICSTAT = IIC_MODE_MR | IIC_TXRX_ENA | IIC_START_STOP;
+		    i2c->IICSTAT = I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP;
 		    ReadWriteByte();
 		    result = WaitForXfer();
 		    i = 0;
-		    while ((i < data_len) && (result == IIC_OK)) {
+		    while ((i < data_len) && (result == I2C_OK)) {
 			/* disable ACK for final READ */
 			if (i == data_len - 1)
-			    rIICCON &= ~0x80;
+			    i2c->IICCON &= ~0x80;
 			ReadWriteByte();
 			result = WaitForXfer();
-			data[i] = rIICDS;
+			data[i] = i2c->IICDS;
 			i++;
 		    }
 		} else {
-		    result = IIC_NACK;
+		    result = I2C_NACK;
 		}
 
 	    } else {
-		rIICSTAT = IIC_MODE_MR | IIC_TXRX_ENA;
-		rIICDS = chip;
+		i2c->IICSTAT = I2C_MODE_MR | I2C_TXRX_ENA;
+		i2c->IICDS = chip;
 		/* send START */
-		rIICSTAT |= IIC_START_STOP;
+		i2c->IICSTAT |= I2C_START_STOP;
 		result = WaitForXfer();
 
 		if (IsACK()) {
 		    i = 0;
-		    while ((i < data_len) && (result == IIC_OK)) {
+		    while ((i < data_len) && (result == I2C_OK)) {
 			/* disable ACK for final READ */
 			if (i == data_len - 1)
-			    rIICCON &= ~0x80;
+			    i2c->IICCON &= ~0x80;
 		        ReadWriteByte();
 			result = WaitForXfer();
-			data[i] = rIICDS;
+			data[i] = i2c->IICDS;
 			i++;
 		    }
 		} else {
-		    result = IIC_NACK;
+		    result = I2C_NACK;
 		}
 	    }
 
 	    /* send STOP */
-	    rIICSTAT = IIC_MODE_MR | IIC_TXRX_ENA;
+	    i2c->IICSTAT = I2C_MODE_MR | I2C_TXRX_ENA;
 	    ReadWriteByte();
 	    break;
 
 	default:
 	    printf( "i2c_transfer: bad call\n" );
-    	    result = IIC_NOK;
+    	    result = I2C_NOK;
 	    break;
     }
 
@@ -329,7 +341,7 @@ int i2c_probe (uchar chip)
      * address was <ACK>ed (i.e. there was a chip at that address which
      * drove the data line low).
      */
-    return(i2c_transfer (IIC_READ, chip << 1, 0, 0, buf, 1) != IIC_OK);
+    return(i2c_transfer (I2C_READ, chip << 1, 0, 0, buf, 1) != I2C_OK);
 }
 
 int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len)
@@ -365,7 +377,7 @@ int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len)
     if( alen > 0 )
 	chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
 #endif
-    if( (ret = i2c_transfer(IIC_READ, chip<<1, &xaddr[4-alen], alen, buffer, len )) != 0) {
+    if( (ret = i2c_transfer(I2C_READ, chip<<1, &xaddr[4-alen], alen, buffer, len )) != 0) {
         printf( "I2c read: failed %d\n", ret);
         return 1;
     }
@@ -403,7 +415,7 @@ int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len)
     if( alen > 0 )
         chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
 #endif
-    return (i2c_transfer(IIC_WRITE, chip<<1, &xaddr[4-alen], alen, buffer, len ) != 0);
+    return (i2c_transfer(I2C_WRITE, chip<<1, &xaddr[4-alen], alen, buffer, len ) != 0);
 }
 
 #endif	/* CONFIG_HARD_I2C */

cpu/mpc8xx/status_led.c → drivers/status_led.c

@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000
+ * (C) Copyright 2000-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -22,13 +22,12 @@
  */
 
 #include <common.h>
-#include <mpc8xx.h>
 #include <status_led.h>
 
 /*
  * The purpose of this code is to signal the operational status of a
  * target which usually boots over the network; while running in
- * PCBoot, a status LED is blinking. As soon as a valid BOOTP reply
+ * U-Boot, a status LED is blinking. As soon as a valid BOOTP reply
  * message has been received, the LED is turned off. The Linux
  * kernel, once it is running, will start blinking the LED again,
  * with another frequency.
@@ -39,10 +38,10 @@
 #ifdef CONFIG_STATUS_LED
 
 typedef struct {
-	ulong	mask;
-	int	state;
-	int	period;
-	int	cnt;
+	led_id_t mask;
+	int state;
+	int period;
+	int cnt;
 } led_dev_t;
 
 led_dev_t led_dev[] = {
@@ -80,89 +79,53 @@ static int status_led_init_done = 0;
 
 static void status_led_init (void)
 {
-    volatile immap_t *immr = (immap_t *)CFG_IMMR;
-    int i;
+	led_dev_t *ld;
+	int i;
 
-    for (i=0; i<MAX_LED_DEV; ++i) {
-	led_dev_t *ld = &led_dev[i];
-
-	immr->STATUS_LED_PAR &= ~(ld->mask);
-#ifdef STATUS_LED_ODR
-	immr->STATUS_LED_ODR &= ~(ld->mask);
-#endif
-#if (STATUS_LED_ACTIVE == 0)
-	if (ld->state == STATUS_LED_ON)
-		immr->STATUS_LED_DAT &= ~(ld->mask);
-	else
-		immr->STATUS_LED_DAT |=   ld->mask ;
-#else
-	if (ld->state == STATUS_LED_ON)
-		immr->STATUS_LED_DAT |=   ld->mask ;
-	else
-		immr->STATUS_LED_DAT &= ~(ld->mask);
-#endif
-	immr->STATUS_LED_DIR |=   ld->mask ;
-    }
-
-    status_led_init_done  = 1;
+	for (i = 0, ld = led_dev; i < MAX_LED_DEV; i++, ld++)
+		__led_init (ld->mask, ld->state);
+	status_led_init_done = 1;
 }
 
 void status_led_tick (ulong timestamp)
 {
-    volatile immap_t *immr = (immap_t *)CFG_IMMR;
-    int i;
+	led_dev_t *ld;
+	int i;
+
+	if (!status_led_init_done)
+		status_led_init ();
 
-    if (!status_led_init_done)
-	status_led_init();
+	for (i = 0, ld = led_dev; i < MAX_LED_DEV; i++, ld++) {
 
-    for (i=0; i<MAX_LED_DEV; ++i) {
-	led_dev_t *ld = &led_dev[i];
+		if (ld->state != STATUS_LED_BLINKING)
+			continue;
 
-	if (ld->state != STATUS_LED_BLINKING)
-		continue;
+		if (++ld->cnt >= ld->period) {
+			__led_toggle (ld->mask);
+			ld->cnt -= ld->period;
+		}
 
-	if (++(ld->cnt) >= ld->period) {
-		immr->STATUS_LED_DAT ^= ld->mask;
-		ld->cnt -= ld->period;
 	}
-    }
 }
 
 void status_led_set (int led, int state)
 {
-    volatile immap_t *immr = (immap_t *)CFG_IMMR;
-    led_dev_t *ld;
-
-    if (led < 0 || led >= MAX_LED_DEV)
-	return;
-
-    if (!status_led_init_done)
-	status_led_init();
-
-    ld = &led_dev[led];
-
-    switch (state) {
-    default:
-	return;
-    case STATUS_LED_BLINKING:
-	ld->cnt = 0;		/* always start with full period	*/
-	/* fall through */	/* always start with LED _ON_		*/
-    case STATUS_LED_ON:
-#if (STATUS_LED_ACTIVE == 0)
-	immr->STATUS_LED_DAT &= ~(ld->mask);
-#else
-	immr->STATUS_LED_DAT |=   ld->mask ;
-#endif
-	break;
-    case STATUS_LED_OFF:
-#if (STATUS_LED_ACTIVE == 0)
-	immr->STATUS_LED_DAT |=   ld->mask ;
-#else
-	immr->STATUS_LED_DAT &= ~(ld->mask);
-#endif
-	break;
-    }
-    ld->state = state;
+	led_dev_t *ld;
+
+	if (led < 0 || led >= MAX_LED_DEV)
+		return;
+
+	if (!status_led_init_done)
+		status_led_init ();
+
+	ld = &led_dev[led];
+
+	ld->state = state;
+	if (state == STATUS_LED_BLINKING) {
+		ld->cnt = 0;		/* always start with full period    */
+		state = STATUS_LED_ON;	/* always start with LED _ON_       */
+	}
+	__led_set (ld->mask, state);
 }
 
 #endif	/* CONFIG_STATUS_LED */

include/asm-ppc/status_led.h

@@ -0,0 +1,77 @@
+/*
+ * asm/status_led.h
+ *
+ * MPC8xx/MPC8260/MPC5xx based status led support functions
+ */
+
+#ifndef __ASM_STATUS_LED_H__
+#define __ASM_STATUS_LED_H__
+
+/* if not overriden */
+#ifndef CONFIG_BOARD_SPECIFIC_LED
+# if defined(CONFIG_8xx)
+#  include <mpc8xx.h>
+# elif defined(CONFIG_8260)
+#  include <mpc8260.h>
+# elif defined(CONFIG_5xx)
+#  include <mpc5xx.h>
+# else
+#  error CPU specific Status LED header file missing.
+#endif
+
+/* led_id_t is unsigned long mask */
+typedef unsigned long led_id_t;
+
+static inline void __led_init (led_id_t mask, int state)
+{
+	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+
+#ifdef STATUS_LED_PAR
+	immr->STATUS_LED_PAR &= ~mask;
+#endif
+#ifdef STATUS_LED_ODR
+	immr->STATUS_LED_ODR &= ~mask;
+#endif
+
+#if (STATUS_LED_ACTIVE == 0)
+	if (state == STATUS_LED_ON)
+		immr->STATUS_LED_DAT &= ~mask;
+	else
+		immr->STATUS_LED_DAT |= mask;
+#else
+	if (state == STATUS_LED_ON)
+		immr->STATUS_LED_DAT |= mask;
+	else
+		immr->STATUS_LED_DAT &= ~mask;
+#endif
+#ifdef STATUS_LED_DIR
+	immr->STATUS_LED_DIR |= mask;
+#endif
+}
+
+static inline void __led_toggle (led_id_t mask)
+{
+	((immap_t *) CFG_IMMR)->STATUS_LED_DAT ^= mask;
+}
+
+static inline void __led_set (led_id_t mask, int state)
+{
+	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+
+#if (STATUS_LED_ACTIVE == 0)
+	if (state == STATUS_LED_ON)
+		immr->STATUS_LED_DAT &= ~mask;
+	else
+		immr->STATUS_LED_DAT |= mask;
+#else
+	if (state == STATUS_LED_ON)
+		immr->STATUS_LED_DAT |= mask;
+	else
+		immr->STATUS_LED_DAT &= ~mask;
+#endif
+
+}
+
+#endif
+
+#endif	/* __ASM_STATUS_LED_H__ */

include/configs/MPC8260ADS.h

@@ -26,10 +26,6 @@
  * MA 02111-1307 USA
  */
 
-/*
- * Config header file for a MPC8260ADS Pilot 16M Ram Simm, 8Mbytes Flash Simm
- */
-
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
@@ -77,23 +73,45 @@
 #undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC   */
 #define CONFIG_ETHER_ON_FCC		/* define if ether on FCC   */
 #undef	CONFIG_ETHER_NONE		/* define if ether on something else */
-#define CONFIG_ETHER_INDEX	2	/* which channel for ether  */
 
-#if (CONFIG_ETHER_INDEX == 2)
+#ifdef CONFIG_ETHER_ON_FCC
 
+#define CONFIG_ETHER_INDEX	2	/* which SCC/FCC channel for ethernet */
+
+#if (CONFIG_ETHER_INDEX == 2)
 /*
  * - Rx-CLK is CLK13
  * - Tx-CLK is CLK14
  * - Select bus for bd/buffers (see 28-13)
- * - Half duplex
+ * - Full duplex
  */
 # define CFG_CMXFCR_MASK	(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
 # define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
 # define CFG_CPMFCR_RAMTYPE	0
-# define CFG_FCC_PSMR		0
+# define CFG_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
 
 #endif	/* CONFIG_ETHER_INDEX */
 
+#define CONFIG_MII			/* MII PHY management		*/
+#define CONFIG_BITBANGMII		/* bit-bang MII PHY management	*/
+/*
+ * GPIO pins used for bit-banged MII communications
+ */
+#define MDIO_PORT	2		/* Port C */
+#define MDIO_ACTIVE	(iop->pdir |=  0x00400000)
+#define MDIO_TRISTATE	(iop->pdir &= ~0x00400000)
+#define MDIO_READ	((iop->pdat &  0x00400000) != 0)
+
+#define MDIO(bit)	if(bit) iop->pdat |=  0x00400000; \
+			else	iop->pdat &= ~0x00400000
+
+#define MDC(bit)	if(bit) iop->pdat |=  0x00200000; \
+			else	iop->pdat &= ~0x00200000
+
+#define MIIDELAY	udelay(1)
+
+#endif /* CONFIG_ETHER_ON_FCC */
+
 /* other options */
 #define CONFIG_HARD_I2C		1	/* To enable I2C support	*/
 #define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
@@ -172,9 +190,6 @@
 #define CFG_MEMTEST_START	0x00100000	/* memtest works on */
 #define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
 
-#define CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
-					/* for versions < 2.4.5-pre5	*/
-
 #define CFG_LOAD_ADDR		0x100000	/* default load address */
 
 #define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
@@ -239,8 +254,8 @@
 
 #ifndef CFG_RAMBOOT
 #  define CFG_ENV_IS_IN_FLASH	1
-#    define CFG_ENV_ADDR	(CFG_MONITOR_BASE + 0x40000)
-#    define CFG_ENV_SECT_SIZE	0x40000
+#  define CFG_ENV_SECT_SIZE	0x40000
+#  define CFG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_ENV_SECT_SIZE)
 #else
 #  define CFG_ENV_IS_IN_NVRAM	1
 #  define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)

include/configs/VCMA9.h

@@ -59,9 +59,13 @@
 #define CONFIG_COMMANDS \
 			(CONFIG_CMD_DFL	 | \
 			CFG_CMD_CACHE	 | \
+			/*CFG_CMD_JFFS2	 |*/ \
+			/*CFG_CMD_NAND	 |*/ \
 			CFG_CMD_EEPROM	 | \
 			CFG_CMD_I2C	 | \
+			/*CFG_CMD_USB	 |*/ \
 			CFG_CMD_REGINFO  | \
+			CFG_CMD_DATE	 | \
 			CFG_CMD_ELF	 | \
 			CFG_CMD_BSP)
 
@@ -111,6 +115,24 @@
  */
 #define CONFIG_SERIAL1          1	/* we use SERIAL 1 on VCMA9 */
 
+/************************************************************
+ * USB support
+ ************************************************************/
+#if 0
+#define CONFIG_USB_OHCI
+#define CONFIG_USB_KEYBOARD
+#define CONFIG_USB_STORAGE
+
+/* Enable needed helper functions */
+#define CFG_DEVICE_DEREGISTER		/* needs device_deregister */
+#endif
+
+/************************************************************
+ * RTC
+ ************************************************************/
+#define	CONFIG_RTC_S3C24X0	1
+
+
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
 
@@ -138,7 +160,7 @@
 #define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
 
 #define CFG_MEMTEST_START	0x30000000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x33F00000	/* 63 MB in DRAM	*/
+#define CFG_MEMTEST_END		0x33F80000	/* 63.5 MB in DRAM	*/
 #define CFG_ALT_MEMTEST
 #define	CFG_LOAD_ADDR		0x33000000	/* default load address	*/
 
@@ -152,6 +174,13 @@
 /* valid baudrates */
 #define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
+/************************************************************
+ * Ident
+ ************************************************************/
+/*#define VERSION_TAG "released"*/
+#define VERSION_TAG "unstable"
+#define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, MEV-10080-001 " VERSION_TAG
+
 /*-----------------------------------------------------------------------
  * Stack sizes
  *
@@ -204,6 +233,48 @@
 #define CFG_ENV_SIZE		0x10000	/* Total Size of Environment Sector */
 #endif
 
-#define MULTI_PURPOSE_SOCKET_ADDR 0
+
+#define CFG_JFFS2_FIRST_BANK	0
+#define CFG_JFFS2_NUM_BANKS	1
+
+#define MULTI_PURPOSE_SOCKET_ADDR 0x08000000
+
+/*-----------------------------------------------------------------------
+ * NAND flash settings
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+
+#define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
+#define SECTORSIZE 512
+
+#define ADDR_COLUMN 1
+#define ADDR_PAGE 2
+#define ADDR_COLUMN_PAGE 3
+
+#define NAND_ChipID_UNKNOWN 	0x00
+#define NAND_MAX_FLOORS 1
+#define NAND_MAX_CHIPS 1
+
+#define NAND_WAIT_READY(nand)	NF_WaitRB()
+
+#define NAND_DISABLE_CE(nand)	NF_SetCE(NFCE_HIGH)
+#define NAND_ENABLE_CE(nand)	NF_SetCE(NFCE_LOW)
+
+
+#define WRITE_NAND_COMMAND(d, adr)	NF_Cmd(d)
+#define WRITE_NAND_COMMANDW(d, adr)	NF_CmdW(d)
+#define WRITE_NAND_ADDRESS(d, adr)	NF_Addr(d)
+#define WRITE_NAND(d, adr)		NF_Write(d)
+#define READ_NAND(adr)			NF_Read()
+/* the following functions are NOP's because S3C24X0 handles this in hardware */
+#define NAND_CTL_CLRALE(nandptr)
+#define NAND_CTL_SETALE(nandptr)
+#define NAND_CTL_CLRCLE(nandptr)
+#define NAND_CTL_SETCLE(nandptr)
+
+#define CONFIG_MTD_NAND_VERIFY_WRITE	1
+#define CONFIG_MTD_NAND_ECC_JFFS2	1
+
+#endif	/* CONFIG_COMMANDS & CFG_CMD_NAND */
 
 #endif	/* __CONFIG_H */

include/configs/smdk2400.h

@@ -86,10 +86,14 @@
 
 #define	CONFIG_TIMESTAMP	1	/* Print timestamp info for images */
 
+/* Use s3c2400's RTC */
+#define CONFIG_RTC_S3C24X0	1
+
 #ifndef USE_920T_MMU
-#define CONFIG_COMMANDS_tmp	(CONFIG_CMD_DFL & ~CFG_CMD_CACHE)
+#define CONFIG_COMMANDS_tmp	((CONFIG_CMD_DFL & ~CFG_CMD_CACHE) | \
+				 CFG_CMD_DATE)
 #else
-#define CONFIG_COMMANDS_tmp	(CONFIG_CMD_DFL)
+#define CONFIG_COMMANDS_tmp	(CONFIG_CMD_DFL | CFG_CMD_DATE)
 #endif
 
 #ifdef CONFIG_HWFLOW

include/configs/smdk2410.h

@@ -67,16 +67,29 @@
  */
 #define CONFIG_SERIAL1          1	/* we use SERIAL 1 on SMDK2410 */
 
+/************************************************************
+ * RTC
+ ************************************************************/
+#define	CONFIG_RTC_S3C24X0	1
+
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
 
 #define CONFIG_BAUDRATE		115200
 
-#ifndef USE_920T_MMU
-#define CONFIG_COMMANDS		(CONFIG_CMD_DFL & ~CFG_CMD_CACHE)
-#else
-#define CONFIG_COMMANDS		(CONFIG_CMD_DFL)
-#endif
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+#define CONFIG_COMMANDS \
+			(CONFIG_CMD_DFL	 | \
+			CFG_CMD_CACHE	 | \
+			/*CFG_CMD_NAND	 |*/ \
+			/*CFG_CMD_EEPROM |*/ \
+			/*CFG_CMD_I2C	 |*/ \
+			/*CFG_CMD_USB	 |*/ \
+			CFG_CMD_REGINFO  | \
+			CFG_CMD_DATE	 | \
+			CFG_CMD_ELF)
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>

include/configs/trab.h

@@ -90,6 +90,9 @@
 
 #define	CONFIG_TIMESTAMP	1	/* Print timestamp info for images */
 
+/* Use s3c2400's RTC */
+#define CONFIG_RTC_S3C24X0	1
+
 #ifdef CONFIG_HWFLOW
 #define CONFIG_COMMANDS_ADD_HWFLOW	CFG_CMD_HWFLOW
 #else
@@ -105,11 +108,13 @@
 #ifndef USE_920T_MMU
 #define CONFIG_COMMANDS		((CONFIG_CMD_DFL & ~CFG_CMD_CACHE) | \
 				 CFG_CMD_BSP			| \
+				 CFG_CMD_DATE			| \
 				 CONFIG_COMMANDS_ADD_HWFLOW	| \
 				 CONFIG_COMMANDS_ADD_VFD	)
 #else
 #define CONFIG_COMMANDS		(CONFIG_CMD_DFL			| \
 				 CFG_CMD_BSP			| \
+				 CFG_CMD_DATE			| \
 				 CONFIG_COMMANDS_ADD_HWFLOW	| \
 				 CONFIG_COMMANDS_ADD_VFD	)
 #endif

include/s3c2400.h

@@ -1,13 +1,138 @@
+/*
+ * (C) Copyright 2003
+ * David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
 /************************************************
  * NAME	    : s3c2400.h
- * Version  : 3.7.2002
+ * Version  : 31.3.2003
  *
- * Based on 24x.h for the Samsung Development Board
+ * Based on S3C2400X User's manual Rev 1.1
  ************************************************/
 
 #ifndef __S3C2400_H__
 #define __S3C2400_H__
 
+#define S3C24X0_UART_CHANNELS	2
+#define S3C24X0_SPI_CHANNELS	1
+#define PALETTE			(0x14A00400)	/* SJS */
+
+typedef enum {
+	S3C24X0_UART0,
+	S3C24X0_UART1,
+} S3C24X0_UARTS_NR;
+
+/* S3C2400 device base addresses */
+#define S3C24X0_MEMCTL_BASE		0x14000000
+#define S3C24X0_USB_HOST_BASE		0x14200000
+#define S3C24X0_INTERRUPT_BASE		0x14400000
+#define S3C24X0_DMA_BASE		0x14600000
+#define S3C24X0_CLOCK_POWER_BASE	0x14800000
+#define S3C24X0_LCD_BASE		0x14A00000
+#define S3C24X0_UART_BASE		0x15000000
+#define S3C24X0_TIMER_BASE		0x15100000
+#define S3C24X0_USB_DEVICE_BASE		0x15200140
+#define S3C24X0_WATCHDOG_BASE		0x15300000
+#define S3C24X0_I2C_BASE		0x15400000
+#define S3C24X0_I2S_BASE		0x15508000
+#define S3C24X0_GPIO_BASE		0x15600000
+#define S3C24X0_RTC_BASE		0x15700000
+#define S3C24X0_ADC_BASE		0x15800000
+#define S3C24X0_SPI_BASE		0x15900000
+#define S3C2400_MMC_BASE		0x15A00000
+
+/* include common stuff */
+#include <s3c24x0.h>
+
+
+static inline S3C24X0_MEMCTL * const S3C24X0_GetBase_MEMCTL(void)
+{
+	return (S3C24X0_MEMCTL * const)S3C24X0_MEMCTL_BASE;
+}
+static inline S3C24X0_USB_HOST * const S3C24X0_GetBase_USB_HOST(void)
+{
+	return (S3C24X0_USB_HOST * const)S3C24X0_USB_HOST_BASE;
+}
+static inline S3C24X0_INTERRUPT * const S3C24X0_GetBase_INTERRUPT(void)
+{
+	return (S3C24X0_INTERRUPT * const)S3C24X0_INTERRUPT_BASE;
+}
+static inline S3C24X0_DMAS * const S3C24X0_GetBase_DMAS(void)
+{
+	return (S3C24X0_DMAS * const)S3C24X0_DMA_BASE;
+}
+static inline S3C24X0_CLOCK_POWER * const S3C24X0_GetBase_CLOCK_POWER(void)
+{
+	return (S3C24X0_CLOCK_POWER * const)S3C24X0_CLOCK_POWER_BASE;
+}
+static inline S3C24X0_LCD * const S3C24X0_GetBase_LCD(void)
+{
+	return (S3C24X0_LCD * const)S3C24X0_LCD_BASE;
+}
+static inline S3C24X0_UART * const S3C24X0_GetBase_UART(S3C24X0_UARTS_NR nr)
+{
+	return (S3C24X0_UART * const)(S3C24X0_UART_BASE + (nr * 0x4000));
+}
+static inline S3C24X0_TIMERS * const S3C24X0_GetBase_TIMERS(void)
+{
+	return (S3C24X0_TIMERS * const)S3C24X0_TIMER_BASE;
+}
+static inline S3C24X0_USB_DEVICE * const S3C24X0_GetBase_USB_DEVICE(void)
+{
+	return (S3C24X0_USB_DEVICE * const)S3C24X0_USB_DEVICE_BASE;
+}
+static inline S3C24X0_WATCHDOG * const S3C24X0_GetBase_WATCHDOG(void)
+{
+	return (S3C24X0_WATCHDOG * const)S3C24X0_WATCHDOG_BASE;
+}
+static inline S3C24X0_I2C * const S3C24X0_GetBase_I2C(void)
+{
+	return (S3C24X0_I2C * const)S3C24X0_I2C_BASE;
+}
+static inline S3C24X0_I2S * const S3C24X0_GetBase_I2S(void)
+{
+	return (S3C24X0_I2S * const)S3C24X0_I2S_BASE;
+}
+static inline S3C24X0_GPIO * const S3C24X0_GetBase_GPIO(void)
+{
+	return (S3C24X0_GPIO * const)S3C24X0_GPIO_BASE;
+}
+static inline S3C24X0_RTC * const S3C24X0_GetBase_RTC(void)
+{
+	return (S3C24X0_RTC * const)S3C24X0_RTC_BASE;
+}
+static inline S3C2400_ADC * const S3C2400_GetBase_ADC(void)
+{
+	return (S3C2400_ADC * const)S3C24X0_ADC_BASE;
+}
+static inline S3C24X0_SPI * const S3C24X0_GetBase_SPI(void)
+{
+	return (S3C24X0_SPI * const)S3C24X0_SPI_BASE;
+}
+static inline S3C2400_MMC * const S3C2400_GetBase_MMC(void)
+{
+	return (S3C2400_MMC * const)S3C2400_MMC_BASE;
+}
+
+#if 0
 /* Memory control */
 #define rBWSCON		(*(volatile unsigned *)0x14000000)
 #define rBANKCON0	(*(volatile unsigned *)0x14000004)
@@ -426,4 +551,5 @@
 		 rINTPND;\
 		 }
 /* Wait until rINTPND is changed for the case that the ISR is very short. */
+#endif
 #endif /*__S3C2400_H__*/

include/s3c2410.h

@@ -1,493 +1,147 @@
+/*
+ * (C) Copyright 2003
+ * David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
 /************************************************
  * NAME	    : s3c2410.h
- * Version  : 3.7.2002
+ * Version  : 31.3.2003
  *
- * Based on S3C2410X User's manual Rev 0.1
+ * Based on S3C2410X User's manual Rev 1.1
  ************************************************/
 
 #ifndef __S3C2410_H__
 #define __S3C2410_H__
 
+#define S3C24X0_UART_CHANNELS	3
+#define S3C24X0_SPI_CHANNELS	2
+
+/* S3C2410 only supports 512 Byte HW ECC */
+#define S3C2410_ECCSIZE		512
+#define S3C2410_ECCBYTES	3
+
+typedef enum {
+	S3C24X0_UART0,
+	S3C24X0_UART1,
+	S3C24X0_UART2
+} S3C24X0_UARTS_NR;
+
+/* S3C2410 device base addresses */
+#define S3C24X0_MEMCTL_BASE		0x48000000
+#define S3C24X0_USB_HOST_BASE		0x49000000
+#define S3C24X0_INTERRUPT_BASE		0x4A000000
+#define S3C24X0_DMA_BASE		0x4B000000
+#define S3C24X0_CLOCK_POWER_BASE	0x4C000000
+#define S3C24X0_LCD_BASE		0x4D000000
+#define S3C2410_NAND_BASE		0x4E000000
+#define S3C24X0_UART_BASE		0x50000000
+#define S3C24X0_TIMER_BASE		0x51000000
+#define S3C24X0_USB_DEVICE_BASE		0x52000140
+#define S3C24X0_WATCHDOG_BASE		0x53000000
+#define S3C24X0_I2C_BASE		0x54000000
+#define S3C24X0_I2S_BASE		0x55000000
+#define S3C24X0_GPIO_BASE		0x56000000
+#define S3C24X0_RTC_BASE		0x57000000
+#define S3C2410_ADC_BASE		0x58000000
+#define S3C24X0_SPI_BASE		0x59000000
+#define S3C2410_SDI_BASE		0x5A000000
+
+
+/* include common stuff */
+#include <s3c24x0.h>
+
+
+static inline S3C24X0_MEMCTL * const S3C24X0_GetBase_MEMCTL(void)
+{
+	return (S3C24X0_MEMCTL * const)S3C24X0_MEMCTL_BASE;
+}
+static inline S3C24X0_USB_HOST * const S3C24X0_GetBase_USB_HOST(void)
+{
+	return (S3C24X0_USB_HOST * const)S3C24X0_USB_HOST_BASE;
+}
+static inline S3C24X0_INTERRUPT * const S3C24X0_GetBase_INTERRUPT(void)
+{
+	return (S3C24X0_INTERRUPT * const)S3C24X0_INTERRUPT_BASE;
+}
+static inline S3C24X0_DMAS * const S3C24X0_GetBase_DMAS(void)
+{
+	return (S3C24X0_DMAS * const)S3C24X0_DMA_BASE;
+}
+static inline S3C24X0_CLOCK_POWER * const S3C24X0_GetBase_CLOCK_POWER(void)
+{
+	return (S3C24X0_CLOCK_POWER * const)S3C24X0_CLOCK_POWER_BASE;
+}
+static inline S3C24X0_LCD * const S3C24X0_GetBase_LCD(void)
+{
+	return (S3C24X0_LCD * const)S3C24X0_LCD_BASE;
+}
+static inline S3C2410_NAND * const S3C2410_GetBase_NAND(void)
+{
+	return (S3C2410_NAND * const)S3C2410_NAND_BASE;
+}
+static inline S3C24X0_UART * const S3C24X0_GetBase_UART(S3C24X0_UARTS_NR nr)
+{
+	return (S3C24X0_UART * const)(S3C24X0_UART_BASE + (nr * 0x4000));
+}
+static inline S3C24X0_TIMERS * const S3C24X0_GetBase_TIMERS(void)
+{
+	return (S3C24X0_TIMERS * const)S3C24X0_TIMER_BASE;
+}
+static inline S3C24X0_USB_DEVICE * const S3C24X0_GetBase_USB_DEVICE(void)
+{
+	return (S3C24X0_USB_DEVICE * const)S3C24X0_USB_DEVICE_BASE;
+}
+static inline S3C24X0_WATCHDOG * const S3C24X0_GetBase_WATCHDOG(void)
+{
+	return (S3C24X0_WATCHDOG * const)S3C24X0_WATCHDOG_BASE;
+}
+static inline S3C24X0_I2C * const S3C24X0_GetBase_I2C(void)
+{
+	return (S3C24X0_I2C * const)S3C24X0_I2C_BASE;
+}
+static inline S3C24X0_I2S * const S3C24X0_GetBase_I2S(void)
+{
+	return (S3C24X0_I2S * const)S3C24X0_I2S_BASE;
+}
+static inline S3C24X0_GPIO * const S3C24X0_GetBase_GPIO(void)
+{
+	return (S3C24X0_GPIO * const)S3C24X0_GPIO_BASE;
+}
+static inline S3C24X0_RTC * const S3C24X0_GetBase_RTC(void)
+{
+	return (S3C24X0_RTC * const)S3C24X0_RTC_BASE;
+}
+static inline S3C2410_ADC * const S3C2410_GetBase_ADC(void)
+{
+	return (S3C2410_ADC * const)S3C2410_ADC_BASE;
+}
+static inline S3C24X0_SPI * const S3C24X0_GetBase_SPI(void)
+{
+	return (S3C24X0_SPI * const)S3C24X0_SPI_BASE;
+}
+static inline S3C2410_SDI * const S3C2410_GetBase_SDI(void)
+{
+	return (S3C2410_SDI * const)S3C2410_SDI_BASE;
+}
 
-/* Memory control */
-#define rBWSCON			(*(volatile unsigned *)0x48000000)
-#define rBANKCON0		(*(volatile unsigned *)0x48000004)
-#define rBANKCON1		(*(volatile unsigned *)0x48000008)
-#define rBANKCON2		(*(volatile unsigned *)0x4800000C)
-#define rBANKCON3		(*(volatile unsigned *)0x48000010)
-#define rBANKCON4		(*(volatile unsigned *)0x48000014)
-#define rBANKCON5		(*(volatile unsigned *)0x48000018)
-#define rBANKCON6		(*(volatile unsigned *)0x4800001C)
-#define rBANKCON7		(*(volatile unsigned *)0x48000020)
-#define rREFRESH		(*(volatile unsigned *)0x48000024)
-#define rBANKSIZE		(*(volatile unsigned *)0x48000028)
-#define rMRSRB6			(*(volatile unsigned *)0x4800002C)
-#define rMRSRB7			(*(volatile unsigned *)0x48000030)
-
-
-/* USB HOST */
-#define rHcRevision		(*(volatile unsigned *)0x49000000)
-#define rHcControl		(*(volatile unsigned *)0x49000004)
-#define rHcCommonStatus		(*(volatile unsigned *)0x49000008)
-#define rHcInterruptStatus	(*(volatile unsigned *)0x4900000C)
-#define rHcInterruptEnable	(*(volatile unsigned *)0x49000010)
-#define rHcInterruptDisable	(*(volatile unsigned *)0x49000014)
-#define rHcHCCA			(*(volatile unsigned *)0x49000018)
-#define rHcPeriodCuttendED	(*(volatile unsigned *)0x4900001C)
-#define rHcControlHeadED	(*(volatile unsigned *)0x49000020)
-#define rHcControlCurrentED	(*(volatile unsigned *)0x49000024)
-#define rHcBulkHeadED		(*(volatile unsigned *)0x49000028)
-#define rHcBuldCurrentED	(*(volatile unsigned *)0x4900002C)
-#define rHcDoneHead		(*(volatile unsigned *)0x49000030)
-#define rHcRmInterval		(*(volatile unsigned *)0x49000034)
-#define rHcFmRemaining		(*(volatile unsigned *)0x49000038)
-#define rHcFmNumber		(*(volatile unsigned *)0x4900003C)
-#define rHcPeriodicStart	(*(volatile unsigned *)0x49000040)
-#define rHcLSThreshold		(*(volatile unsigned *)0x49000044)
-#define rHcRhDescriptorA	(*(volatile unsigned *)0x49000048)
-#define rHcRhDescriptorB	(*(volatile unsigned *)0x4900004C)
-#define rHcRhStatus		(*(volatile unsigned *)0x49000050)
-#define rHcRhPortStatus1	(*(volatile unsigned *)0x49000054)
-#define rHcRhPortStatus2	(*(volatile unsigned *)0x49000058)
-
-
-/* INTERRUPT */
-#define rSRCPND			(*(volatile unsigned *)0x4A000000)
-#define rINTMOD			(*(volatile unsigned *)0x4A000004)
-#define rINTMSK			(*(volatile unsigned *)0x4A000008)
-#define rPRIORITY		(*(volatile unsigned *)0x4A00000C)
-#define rINTPND			(*(volatile unsigned *)0x4A000010)
-#define rINTOFFSET		(*(volatile unsigned *)0x4A000014)
-#define rSUBSRCPND		(*(volatile unsigned *)0x4A000018)
-#define rINTSUBMSK		(*(volatile unsigned *)0x4A00001C)
-
-
-/* DMA */
-#define rDISRC0			(*(volatile unsigned *)0x4B000000)
-#define rDISRCC0		(*(volatile unsigned *)0x4B000004)
-#define rDIDST0			(*(volatile unsigned *)0x4B000008)
-#define rDIDSTC0		(*(volatile unsigned *)0x4B00000C)
-#define rDCON0			(*(volatile unsigned *)0x4B000010)
-#define rDSTAT0			(*(volatile unsigned *)0x4B000014)
-#define rDCSRC0			(*(volatile unsigned *)0x4B000018)
-#define rDCDST0			(*(volatile unsigned *)0x4B00001C)
-#define rDMASKTRIG0		(*(volatile unsigned *)0x4B000020)
-#define rDISRC1			(*(volatile unsigned *)0x4B000040)
-#define rDISRCC1		(*(volatile unsigned *)0x4B000044)
-#define rDIDST1			(*(volatile unsigned *)0x4B000048)
-#define rDIDSTC1		(*(volatile unsigned *)0x4B00004C)
-#define rDCON1			(*(volatile unsigned *)0x4B000050)
-#define rDSTAT1			(*(volatile unsigned *)0x4B000054)
-#define rDCSRC1			(*(volatile unsigned *)0x4B000058)
-#define rDCDST1			(*(volatile unsigned *)0x4B00005C)
-#define rDMASKTRIG1		(*(volatile unsigned *)0x4B000060)
-#define rDISRC2			(*(volatile unsigned *)0x4B000080)
-#define rDISRCC2		(*(volatile unsigned *)0x4B000084)
-#define rDIDST2			(*(volatile unsigned *)0x4B000088)
-#define rDIDSTC2		(*(volatile unsigned *)0x4B00008C)
-#define rDCON2			(*(volatile unsigned *)0x4B000090)
-#define rDSTAT2			(*(volatile unsigned *)0x4B000094)
-#define rDCSRC2			(*(volatile unsigned *)0x4B000098)
-#define rDCDST2			(*(volatile unsigned *)0x4B00009C)
-#define rDMASKTRIG2		(*(volatile unsigned *)0x4B0000A0)
-#define rDISRC3			(*(volatile unsigned *)0x4B0000C0)
-#define rDISRCC3		(*(volatile unsigned *)0x4B0000C4)
-#define rDIDST3			(*(volatile unsigned *)0x4B0000C8)
-#define rDIDSTC3		(*(volatile unsigned *)0x4B0000CC)
-#define rDCON3			(*(volatile unsigned *)0x4B0000D0)
-#define rDSTAT3			(*(volatile unsigned *)0x4B0000D4)
-#define rDCSRC3			(*(volatile unsigned *)0x4B0000D8)
-#define rDCDST3			(*(volatile unsigned *)0x4B0000DC)
-#define rDMASKTRIG3		(*(volatile unsigned *)0x4B0000E0)
-
-
-/* CLOCK & POWER MANAGEMENT */
-#define rLOCKTIME		(*(volatile unsigned *)0x4C000000)
-#define rMPLLCON		(*(volatile unsigned *)0x4C000004)
-#define rUPLLCON		(*(volatile unsigned *)0x4C000008)
-#define rCLKCON			(*(volatile unsigned *)0x4C00000C)
-#define rCLKSLOW		(*(volatile unsigned *)0x4C000010)
-#define rCLKDIVN		(*(volatile unsigned *)0x4C000014)
-
-
-/* LCD CONTROLLER */
-#define rLCDCON1		(*(volatile unsigned *)0x4D000000)
-#define rLCDCON2		(*(volatile unsigned *)0x4D000004)
-#define rLCDCON3		(*(volatile unsigned *)0x4D000008)
-#define rLCDCON4		(*(volatile unsigned *)0x4D00000C)
-#define rLCDCON5		(*(volatile unsigned *)0x4D000010)
-#define rLCDSADDR1		(*(volatile unsigned *)0x4D000014)
-#define rLCDSADDR2		(*(volatile unsigned *)0x4D000018)
-#define rLCDSADDR3		(*(volatile unsigned *)0x4D00001C)
-#define rREDLUT			(*(volatile unsigned *)0x4D000020)
-#define rGREENLUT		(*(volatile unsigned *)0x4D000024)
-#define rBLUELUT		(*(volatile unsigned *)0x4D000028)
-#define rDITHMODE		(*(volatile unsigned *)0x4D00004C)
-#define rTPAL			(*(volatile unsigned *)0x4D000050)
-#define rLCDINTPND		(*(volatile unsigned *)0x4D000054)
-#define rLCDSRCPND		(*(volatile unsigned *)0x4D000058)
-#define rLCDINTMSK		(*(volatile unsigned *)0x4D00005C)
-
-
-/* NAND FLASH */
-#define rNFCONF			(*(volatile unsigned *)0x4E000000)
-#define rNFCMD			(*(volatile unsigned *)0x4E000004)
-#define rNFADDR			(*(volatile unsigned *)0x4E000008)
-#define rNFDATA			(*(volatile unsigned *)0x4E00000C)
-#define rNFSTAT			(*(volatile unsigned *)0x4E000010)
-#define rNFECC			(*(volatile unsigned *)0x4E000014)
-
-
-/* UART */
-#define rULCON0			(*(volatile unsigned *)0x50000000)
-#define rUCON0			(*(volatile unsigned *)0x50000004)
-#define rUFCON0			(*(volatile unsigned *)0x50000008)
-#define rUMCON0			(*(volatile unsigned *)0x5000000C)
-#define rUTRSTAT0		(*(volatile unsigned *)0x50000010)
-#define rUERSTAT0		(*(volatile unsigned *)0x50000014)
-#define rUFSTAT0		(*(volatile unsigned *)0x50000018)
-#define rUMSTAT0		(*(volatile unsigned *)0x5000001C)
-#define rUBRDIV0		(*(volatile unsigned *)0x50000028)
-
-#define rULCON1			(*(volatile unsigned *)0x50004000)
-#define rUCON1			(*(volatile unsigned *)0x50004004)
-#define rUFCON1			(*(volatile unsigned *)0x50004008)
-#define rUMCON1			(*(volatile unsigned *)0x5000400C)
-#define rUTRSTAT1		(*(volatile unsigned *)0x50004010)
-#define rUERSTAT1		(*(volatile unsigned *)0x50004014)
-#define rUFSTAT1		(*(volatile unsigned *)0x50004018)
-#define rUMSTAT1		(*(volatile unsigned *)0x5000401C)
-#define rUBRDIV1		(*(volatile unsigned *)0x50004028)
-
-#define rULCON2			(*(volatile unsigned *)0x50008000)
-#define rUCON2			(*(volatile unsigned *)0x50008004)
-#define rUFCON2			(*(volatile unsigned *)0x50008008)
-#define rUTRSTAT2		(*(volatile unsigned *)0x50008010)
-#define rUERSTAT2		(*(volatile unsigned *)0x50008014)
-#define rUFSTAT2		(*(volatile unsigned *)0x50008018)
-#define rUBRDIV2		(*(volatile unsigned *)0x50008028)
-
-#ifdef __BIG_ENDIAN
-#define rUTXH0			(*(volatile unsigned char *)0x50000023)
-#define rURXH0			(*(volatile unsigned char *)0x50000027)
-#define rUTXH1			(*(volatile unsigned char *)0x50004023)
-#define rURXH1			(*(volatile unsigned char *)0x50004027)
-#define rUTXH2			(*(volatile unsigned char *)0x50008023)
-#define rURXH2			(*(volatile unsigned char *)0x50008027)
-
-#define WrUTXH0(ch)		(*(volatile unsigned char *)0x50000023)=(unsigned char)(ch)
-#define RdURXH0()		(*(volatile unsigned char *)0x50000027)
-#define WrUTXH1(ch)		(*(volatile unsigned char *)0x50004023)=(unsigned char)(ch)
-#define RdURXH1()		(*(volatile unsigned char *)0x50004027)
-#define WrUTXH2(ch)		(*(volatile unsigned char *)0x50008023)=(unsigned char)(ch)
-#define RdURXH2()		(*(volatile unsigned char *)0x50008027)
-
-#define UTXH0			(0x50000020+3)  /* byte_access address by DMA */
-#define URXH0			(0x50000024+3)
-#define UTXH1			(0x50004020+3)
-#define URXH1			(0x50004024+3)
-#define UTXH2			(0x50008020+3)
-#define URXH2			(0x50008024+3)
-
-#else /* Little Endian */
-#define rUTXH0			(*(volatile unsigned char *)0x50000020)
-#define rURXH0			(*(volatile unsigned char *)0x50000024)
-#define rUTXH1			(*(volatile unsigned char *)0x50004020)
-#define rURXH1			(*(volatile unsigned char *)0x50004024)
-#define rUTXH2			(*(volatile unsigned char *)0x50008020)
-#define rURXH2			(*(volatile unsigned char *)0x50008024)
-
-#define WrUTXH0(ch)		(*(volatile unsigned char *)0x50000020)=(unsigned char)(ch)
-#define RdURXH0()		(*(volatile unsigned char *)0x50000024)
-#define WrUTXH1(ch)		(*(volatile unsigned char *)0x50004020)=(unsigned char)(ch)
-#define RdURXH1()		(*(volatile unsigned char *)0x50004024)
-#define WrUTXH2(ch)		(*(volatile unsigned char *)0x50008020)=(unsigned char)(ch)
-#define RdURXH2()		(*(volatile unsigned char *)0x50008024)
-
-#define UTXH0			(0x50000020)    /* byte_access address by DMA */
-#define URXH0			(0x50000024)
-#define UTXH1			(0x50004020)
-#define URXH1			(0x50004024)
-#define UTXH2			(0x50008020)
-#define URXH2			(0x50008024)
-#endif
-
-
-/* PWM TIMER */
-#define rTCFG0			(*(volatile unsigned *)0x51000000)
-#define rTCFG1			(*(volatile unsigned *)0x51000004)
-#define rTCON			(*(volatile unsigned *)0x51000008)
-#define rTCNTB0			(*(volatile unsigned *)0x5100000C)
-#define rTCMPB0			(*(volatile unsigned *)0x51000010)
-#define rTCNTO0			(*(volatile unsigned *)0x51000014)
-#define rTCNTB1			(*(volatile unsigned *)0x51000018)
-#define rTCMPB1			(*(volatile unsigned *)0x5100001C)
-#define rTCNTO1			(*(volatile unsigned *)0x51000020)
-#define rTCNTB2			(*(volatile unsigned *)0x51000024)
-#define rTCMPB2			(*(volatile unsigned *)0x51000028)
-#define rTCNTO2			(*(volatile unsigned *)0x5100002C)
-#define rTCNTB3			(*(volatile unsigned *)0x51000030)
-#define rTCMPB3			(*(volatile unsigned *)0x51000034)
-#define rTCNTO3			(*(volatile unsigned *)0x51000038)
-#define rTCNTB4			(*(volatile unsigned *)0x5100003C)
-#define rTCNTO4			(*(volatile unsigned *)0x51000040)
-
-
-/* USB DEVICE */
-#ifdef __BIG_ENDIAN
-#define rFUNC_ADDR_REG		(*(volatile unsigned char *)0x52000143)
-#define rPWR_REG		(*(volatile unsigned char *)0x52000147)
-#define rEP_INT_REG		(*(volatile unsigned char *)0x5200014B)
-#define rUSB_INT_REG		(*(volatile unsigned char *)0x5200015B)
-#define rEP_INT_EN_REG		(*(volatile unsigned char *)0x5200015F)
-#define rUSB_INT_EN_REG		(*(volatile unsigned char *)0x5200016F)
-#define rFRAME_NUM1_REG		(*(volatile unsigned char *)0x52000173)
-#define rFRAME_NUM2_REG		(*(volatile unsigned char *)0x52000177)
-#define rINDEX_REG		(*(volatile unsigned char *)0x5200017B)
-#define rMAXP_REG		(*(volatile unsigned char *)0x52000183)
-#define rEP0_CSR		(*(volatile unsigned char *)0x52000187)
-#define rIN_CSR1_REG		(*(volatile unsigned char *)0x52000187)
-#define rIN_CSR2_REG		(*(volatile unsigned char *)0x5200018B)
-#define rOUT_CSR1_REG		(*(volatile unsigned char *)0x52000193)
-#define rOUT_CSR2_REG		(*(volatile unsigned char *)0x52000197)
-#define rOUT_FIFO_CNT1_REG	(*(volatile unsigned char *)0x5200019B)
-#define rOUT_FIFO_CNT2_REG	(*(volatile unsigned char *)0x5200019F)
-#define rEP0_FIFO		(*(volatile unsigned char *)0x520001C3)
-#define rEP1_FIFO		(*(volatile unsigned char *)0x520001C7)
-#define rEP2_FIFO		(*(volatile unsigned char *)0x520001CB)
-#define rEP3_FIFO		(*(volatile unsigned char *)0x520001CF)
-#define rEP4_FIFO		(*(volatile unsigned char *)0x520001D3)
-#define rEP1_DMA_CON		(*(volatile unsigned char *)0x52000203)
-#define rEP1_DMA_UNIT		(*(volatile unsigned char *)0x52000207)
-#define rEP1_DMA_FIFO		(*(volatile unsigned char *)0x5200020B)
-#define rEP1_DMA_TX_LO		(*(volatile unsigned char *)0x5200020F)
-#define rEP1_DMA_TX_MD		(*(volatile unsigned char *)0x52000213)
-#define rEP1_DMA_TX_HI		(*(volatile unsigned char *)0x52000217)
-#define rEP2_DMA_CON		(*(volatile unsigned char *)0x5200021B)
-#define rEP2_DMA_UNIT		(*(volatile unsigned char *)0x5200021F)
-#define rEP2_DMA_FIFO		(*(volatile unsigned char *)0x52000223)
-#define rEP2_DMA_TX_LO		(*(volatile unsigned char *)0x52000227)
-#define rEP2_DMA_TX_MD		(*(volatile unsigned char *)0x5200022B)
-#define rEP2_DMA_TX_HI		(*(volatile unsigned char *)0x5200022F)
-#define rEP3_DMA_CON		(*(volatile unsigned char *)0x52000243)
-#define rEP3_DMA_UNIT		(*(volatile unsigned char *)0x52000247)
-#define rEP3_DMA_FIFO		(*(volatile unsigned char *)0x5200024B)
-#define rEP3_DMA_TX_LO		(*(volatile unsigned char *)0x5200024F)
-#define rEP3_DMA_TX_MD		(*(volatile unsigned char *)0x52000253)
-#define rEP3_DMA_TX_HI		(*(volatile unsigned char *)0x52000257)
-#define rEP4_DMA_CON		(*(volatile unsigned char *)0x5200025B)
-#define rEP4_DMA_UNIT		(*(volatile unsigned char *)0x5200025F)
-#define rEP4_DMA_FIFO		(*(volatile unsigned char *)0x52000263)
-#define rEP4_DMA_TX_LO		(*(volatile unsigned char *)0x52000267)
-#define rEP4_DMA_TX_MD		(*(volatile unsigned char *)0x5200026B)
-#define rEP4_DMA_TX_HI		(*(volatile unsigned char *)0x5200026F)
-#else /*  little endian */
-#define rFUNC_ADDR_REG		(*(volatile unsigned char *)0x52000140)
-#define rPWR_REG		(*(volatile unsigned char *)0x52000144)
-#define rEP_INT_REG		(*(volatile unsigned char *)0x52000148)
-#define rUSB_INT_REG		(*(volatile unsigned char *)0x52000158)
-#define rEP_INT_EN_REG		(*(volatile unsigned char *)0x5200015C)
-#define rUSB_INT_EN_REG		(*(volatile unsigned char *)0x5200016C)
-#define rFRAME_NUM1_REG		(*(volatile unsigned char *)0x52000170)
-#define rFRAME_NUM2_REG		(*(volatile unsigned char *)0x52000174)
-#define rINDEX_REG		(*(volatile unsigned char *)0x52000178)
-#define rMAXP_REG		(*(volatile unsigned char *)0x52000180)
-#define rEP0_CSR		(*(volatile unsigned char *)0x52000184)
-#define rIN_CSR1_REG		(*(volatile unsigned char *)0x52000184)
-#define rIN_CSR2_REG		(*(volatile unsigned char *)0x52000188)
-#define rOUT_CSR1_REG		(*(volatile unsigned char *)0x52000190)
-#define rOUT_CSR2_REG		(*(volatile unsigned char *)0x52000194)
-#define rOUT_FIFO_CNT1_REG	(*(volatile unsigned char *)0x52000198)
-#define rOUT_FIFO_CNT2_REG	(*(volatile unsigned char *)0x5200019C)
-#define rEP0_FIFO		(*(volatile unsigned char *)0x520001C0)
-#define rEP1_FIFO		(*(volatile unsigned char *)0x520001C4)
-#define rEP2_FIFO		(*(volatile unsigned char *)0x520001C8)
-#define rEP3_FIFO		(*(volatile unsigned char *)0x520001CC)
-#define rEP4_FIFO		(*(volatile unsigned char *)0x520001D0)
-#define rEP1_DMA_CON		(*(volatile unsigned char *)0x52000200)
-#define rEP1_DMA_UNIT		(*(volatile unsigned char *)0x52000204)
-#define rEP1_DMA_FIFO		(*(volatile unsigned char *)0x52000208)
-#define rEP1_DMA_TX_LO		(*(volatile unsigned char *)0x5200020C)
-#define rEP1_DMA_TX_MD		(*(volatile unsigned char *)0x52000210)
-#define rEP1_DMA_TX_HI		(*(volatile unsigned char *)0x52000214)
-#define rEP2_DMA_CON		(*(volatile unsigned char *)0x52000218)
-#define rEP2_DMA_UNIT		(*(volatile unsigned char *)0x5200021C)
-#define rEP2_DMA_FIFO		(*(volatile unsigned char *)0x52000220)
-#define rEP2_DMA_TX_LO		(*(volatile unsigned char *)0x52000224)
-#define rEP2_DMA_TX_MD		(*(volatile unsigned char *)0x52000228)
-#define rEP2_DMA_TX_HI		(*(volatile unsigned char *)0x5200022C)
-#define rEP3_DMA_CON		(*(volatile unsigned char *)0x52000240)
-#define rEP3_DMA_UNIT		(*(volatile unsigned char *)0x52000244)
-#define rEP3_DMA_FIFO		(*(volatile unsigned char *)0x52000248)
-#define rEP3_DMA_TX_LO		(*(volatile unsigned char *)0x5200024C)
-#define rEP3_DMA_TX_MD		(*(volatile unsigned char *)0x52000250)
-#define rEP3_DMA_TX_HI		(*(volatile unsigned char *)0x52000254)
-#define rEP4_DMA_CON		(*(volatile unsigned char *)0x52000258)
-#define rEP4_DMA_UNIT		(*(volatile unsigned char *)0x5200025C)
-#define rEP4_DMA_FIFO		(*(volatile unsigned char *)0x52000260)
-#define rEP4_DMA_TX_LO		(*(volatile unsigned char *)0x52000264)
-#define rEP4_DMA_TX_MD		(*(volatile unsigned char *)0x52000268)
-#define rEP4_DMA_TX_HI		(*(volatile unsigned char *)0x5200026C)
-#endif /*  __BIG_ENDIAN */
-
-/* WATCH DOG TIMER */
-#define rWTCON			(*(volatile unsigned *)0x53000000)
-#define rWTDAT			(*(volatile unsigned *)0x53000004)
-#define rWTCNT			(*(volatile unsigned *)0x53000008)
-
-
-/* IIC */
-#define rIICCON			(*(volatile unsigned *)0x54000000)
-#define rIICSTAT		(*(volatile unsigned *)0x54000004)
-#define rIICADD			(*(volatile unsigned *)0x54000008)
-#define rIICDS			(*(volatile unsigned *)0x5400000C)
-
-
-/* IIS */
-#define rIISCON			(*(volatile unsigned *)0x55000000)
-#define rIISMOD			(*(volatile unsigned *)0x55000004)
-#define rIISPSR			(*(volatile unsigned *)0x55000008)
-#define rIISFCON		(*(volatile unsigned *)0x5500000C)
-
-#ifdef __BIG_ENDIAN
-#define IISFIF			((volatile unsigned short *)0x55000012)
-#else /*  little endian */
-#define IISFIF			((volatile unsigned short *)0x55000010)
-#endif
-
-
-/* I/O PORT */
-#define rGPACON			(*(volatile unsigned *)0x56000000)
-#define rGPADAT			(*(volatile unsigned *)0x56000004)
-
-#define rGPBCON			(*(volatile unsigned *)0x56000010)
-#define rGPBDAT			(*(volatile unsigned *)0x56000014)
-#define rGPBUP			(*(volatile unsigned *)0x56000018)
-
-#define rGPCCON			(*(volatile unsigned *)0x56000020)
-#define rGPCDAT			(*(volatile unsigned *)0x56000024)
-#define rGPCUP			(*(volatile unsigned *)0x56000028)
-
-#define rGPDCON			(*(volatile unsigned *)0x56000030)
-#define rGPDDAT			(*(volatile unsigned *)0x56000034)
-#define rGPDUP			(*(volatile unsigned *)0x56000038)
-
-#define rGPECON			(*(volatile unsigned *)0x56000040)
-#define rGPEDAT			(*(volatile unsigned *)0x56000044)
-#define rGPEUP			(*(volatile unsigned *)0x56000048)
-
-#define rGPFCON			(*(volatile unsigned *)0x56000050)
-#define rGPFDAT			(*(volatile unsigned *)0x56000054)
-#define rGPFUP			(*(volatile unsigned *)0x56000058)
-
-#define rGPGCON			(*(volatile unsigned *)0x56000060)
-#define rGPGDAT			(*(volatile unsigned *)0x56000064)
-#define rGPGUP			(*(volatile unsigned *)0x56000068)
-
-#define rGPHCON			(*(volatile unsigned *)0x56000070)
-#define rGPHDAT			(*(volatile unsigned *)0x56000074)
-#define rGPHUP			(*(volatile unsigned *)0x56000078)
-
-#define rMISCCR			(*(volatile unsigned *)0x56000080)
-#define rDCLKCON		(*(volatile unsigned *)0x56000084)
-#define rEXTINT0		(*(volatile unsigned *)0x56000088)
-#define rEXTINT1		(*(volatile unsigned *)0x5600008C)
-#define rEXTINT2		(*(volatile unsigned *)0x56000090)
-#define rEINTFLT0		(*(volatile unsigned *)0x56000094)
-#define rEINTFLT1		(*(volatile unsigned *)0x56000098)
-#define rEINTFLT2		(*(volatile unsigned *)0x5600009C)
-#define rEINTFLT3		(*(volatile unsigned *)0x560000A0)
-#define rEINTMASK		(*(volatile unsigned *)0x560000A4)
-#define rEINTPEND		(*(volatile unsigned *)0x560000A8)
-#define rGSTATUS0		(*(volatile unsigned *)0x560000AC)
-#define rGSTATUS1		(*(volatile unsigned *)0x560000B0)
-
-
-/* RTC */
-#ifdef __BIG_ENDIAN
-#define rRTCCON			(*(volatile unsigned char *)0x57000043)
-#define rTICNT			(*(volatile unsigned char *)0x57000047)
-#define rRTCALM			(*(volatile unsigned char *)0x57000053)
-#define rALMSEC			(*(volatile unsigned char *)0x57000057)
-#define rALMMIN			(*(volatile unsigned char *)0x5700005B)
-#define rALMHOUR		(*(volatile unsigned char *)0x5700005F)
-#define rALMDATE		(*(volatile unsigned char *)0x57000063)
-#define rALMMON			(*(volatile unsigned char *)0x57000067)
-#define rALMYEAR		(*(volatile unsigned char *)0x5700006B)
-#define rRTCRST			(*(volatile unsigned char *)0x5700006F)
-#define rBCDSEC			(*(volatile unsigned char *)0x57000073)
-#define rBCDMIN			(*(volatile unsigned char *)0x57000077)
-#define rBCDHOUR		(*(volatile unsigned char *)0x5700007B)
-#define rBCDDATE		(*(volatile unsigned char *)0x5700007F)
-#define rBCDDAY			(*(volatile unsigned char *)0x57000083)
-#define rBCDMON			(*(volatile unsigned char *)0x57000087)
-#define rBCDYEAR		(*(volatile unsigned char *)0x5700008B)
-#else /*  little endian */
-#define rRTCCON			(*(volatile unsigned char *)0x57000040)
-#define rTICNT			(*(volatile unsigned char *)0x57000044)
-#define rRTCALM			(*(volatile unsigned char *)0x57000050)
-#define rALMSEC			(*(volatile unsigned char *)0x57000054)
-#define rALMMIN			(*(volatile unsigned char *)0x57000058)
-#define rALMHOUR		(*(volatile unsigned char *)0x5700005C)
-#define rALMDATE		(*(volatile unsigned char *)0x57000060)
-#define rALMMON			(*(volatile unsigned char *)0x57000064)
-#define rALMYEAR		(*(volatile unsigned char *)0x57000068)
-#define rRTCRST			(*(volatile unsigned char *)0x5700006C)
-#define rBCDSEC			(*(volatile unsigned char *)0x57000070)
-#define rBCDMIN			(*(volatile unsigned char *)0x57000074)
-#define rBCDHOUR		(*(volatile unsigned char *)0x57000078)
-#define rBCDDATE		(*(volatile unsigned char *)0x5700007C)
-#define rBCDDAY			(*(volatile unsigned char *)0x57000080)
-#define rBCDMON			(*(volatile unsigned char *)0x57000084)
-#define rBCDYEAR		(*(volatile unsigned char *)0x57000088)
-#endif
-
-
-/* ADC */
-#define rADCCON			(*(volatile unsigned *)0x58000000)
-#define rADCTSC			(*(volatile unsigned *)0x58000004)
-#define rADCDLY			(*(volatile unsigned *)0x58000008)
-#define rADCDAT0		(*(volatile unsigned *)0x5800000C)
-#define rADCDAT1		(*(volatile unsigned *)0x58000010)
-
-
-/* SPI */
-#define rSPCON0			(*(volatile unsigned *)0x59000000)
-#define rSPSTA0			(*(volatile unsigned *)0x59000004)
-#define rSPPIN0			(*(volatile unsigned *)0x59000008)
-#define rSPPRE0			(*(volatile unsigned *)0x5900000C)
-#define rSPTDAT0		(*(volatile unsigned *)0x59000010)
-#define rSPRDAT0		(*(volatile unsigned *)0x59000014)
-#define rSPCON1			(*(volatile unsigned *)0x59000020)
-#define rSPSTA1			(*(volatile unsigned *)0x59000024)
-#define rSPPIN1			(*(volatile unsigned *)0x59000028)
-#define rSPPRE1			(*(volatile unsigned *)0x5900002C)
-#define rSPTDAT1		(*(volatile unsigned *)0x59000030)
-#define rSPRDAT1		(*(volatile unsigned *)0x59000034)
-
-
-/* SD INTERFACE */
-#define rSDICON			(*(volatile unsigned *)0x5A000000)
-#define rSDIPRE			(*(volatile unsigned *)0x5A000004)
-#define rSDICmdArg		(*(volatile unsigned *)0x5A000008)
-#define rSDICmdCon		(*(volatile unsigned *)0x5A00000C)
-#define rSDICmdSta		(*(volatile unsigned *)0x5A000010)
-#define rSDIRSP0		(*(volatile unsigned *)0x5A000014)
-#define rSDIRSP1		(*(volatile unsigned *)0x5A000018)
-#define rSDIRSP2		(*(volatile unsigned *)0x5A00001C)
-#define rSDIRSP3		(*(volatile unsigned *)0x5A000020)
-#define rSDIDTimer		(*(volatile unsigned *)0x5A000024)
-#define rSDIBSize		(*(volatile unsigned *)0x5A000028)
-#define rSDIDatCon		(*(volatile unsigned *)0x5A00002C)
-#define rSDIDatCnt		(*(volatile unsigned *)0x5A000030)
-#define rSDIDatSta		(*(volatile unsigned *)0x5A000034)
-#define rSDIFSTA		(*(volatile unsigned *)0x5A000038)
-#ifdef __BIG_ENDIAN
-#define rSDIDAT			(*(volatile unsigned char *)0x5A00003F)
-#else
-#define rSDIDAT			(*(volatile unsigned char *)0x5A00003C)
-#endif
-#define rSDIIntMsk		(*(volatile unsigned *)0x5A000040)
 
 /* ISR */
 #define pISR_RESET		(*(unsigned *)(_ISR_STARTADDRESS+0x0))

include/s3c24x0.h

@@ -0,0 +1,1135 @@
+/*
+ * (C) Copyright 2003
+ * David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************
+ * NAME	    : s3c24x0.h
+ * Version  : 31.3.2003
+ *
+ * common stuff for SAMSUNG S3C24X0 SoC
+ ************************************************/
+
+#ifndef __S3C24X0_H__
+#define __S3C24X0_H__
+
+typedef volatile u8	S3C24X0_REG8;
+typedef volatile u16	S3C24X0_REG16;
+typedef volatile u32	S3C24X0_REG32;
+
+/* Memory controller (see manual chapter 5) */
+typedef struct {
+	S3C24X0_REG32	BWSCON;
+	S3C24X0_REG32	BANKCON[8];
+	S3C24X0_REG32	REFRESH;
+	S3C24X0_REG32	BANKSIZE;
+	S3C24X0_REG32	MRSRB6;
+	S3C24X0_REG32	MRSRB7;
+} /*__attribute__((__packed__))*/ S3C24X0_MEMCTL;
+
+
+/* USB HOST (see manual chapter 12) */
+typedef struct {
+	S3C24X0_REG32	HcRevision;
+	S3C24X0_REG32	HcControl;
+	S3C24X0_REG32	HcCommonStatus;
+	S3C24X0_REG32	HcInterruptStatus;
+	S3C24X0_REG32	HcInterruptEnable;
+	S3C24X0_REG32	HcInterruptDisable;
+	S3C24X0_REG32	HcHCCA;
+	S3C24X0_REG32	HcPeriodCuttendED;
+	S3C24X0_REG32	HcControlHeadED;
+	S3C24X0_REG32	HcControlCurrentED;
+	S3C24X0_REG32	HcBulkHeadED;
+	S3C24X0_REG32	HcBuldCurrentED;
+	S3C24X0_REG32	HcDoneHead;
+	S3C24X0_REG32	HcRmInterval;
+	S3C24X0_REG32	HcFmRemaining;
+	S3C24X0_REG32	HcFmNumber;
+	S3C24X0_REG32	HcPeriodicStart;
+	S3C24X0_REG32	HcLSThreshold;
+	S3C24X0_REG32	HcRhDescriptorA;
+	S3C24X0_REG32	HcRhDescriptorB;
+	S3C24X0_REG32	HcRhStatus;
+	S3C24X0_REG32	HcRhPortStatus1;
+	S3C24X0_REG32	HcRhPortStatus2;
+} /*__attribute__((__packed__))*/ S3C24X0_USB_HOST;
+
+
+/* INTERRUPT (see manual chapter 14) */
+typedef struct {
+	S3C24X0_REG32	SRCPND;
+	S3C24X0_REG32	INTMOD;
+	S3C24X0_REG32	INTMSK;
+	S3C24X0_REG32	PRIORITY;
+	S3C24X0_REG32	INTPND;
+	S3C24X0_REG32	INTOFFSET;
+#ifdef CONFIG_S3C2410
+	S3C24X0_REG32	SUBSRCPND;
+	S3C24X0_REG32	INTSUBMSK;
+#endif
+} /*__attribute__((__packed__))*/ S3C24X0_INTERRUPT;
+
+
+/* DMAS (see manual chapter 8) */
+typedef struct {
+	S3C24X0_REG32	DISRC;
+#ifdef CONFIG_S3C2410
+	S3C24X0_REG32	DISRCC;
+#endif
+	S3C24X0_REG32	DIDST;
+#ifdef CONFIG_S3C2410
+	S3C24X0_REG32	DIDSTC;
+#endif
+	S3C24X0_REG32	DCON;
+	S3C24X0_REG32	DSTAT;
+	S3C24X0_REG32	DCSRC;
+	S3C24X0_REG32	DCDST;
+	S3C24X0_REG32	DMASKTRIG;
+#ifdef CONFIG_S3C2400
+	S3C24X0_REG32	res[1];
+#endif
+#ifdef CONFIG_S3C2410
+	S3C24X0_REG32	res[7];
+#endif
+} /*__attribute__((__packed__))*/ S3C24X0_DMA;
+
+typedef struct {
+	S3C24X0_DMA	dma[4];
+} /*__attribute__((__packed__))*/ S3C24X0_DMAS;
+
+
+/* CLOCK & POWER MANAGEMENT (see S3C2400 manual chapter 6) */
+/*                          (see S3C2410 manual chapter 7) */
+typedef struct {
+	S3C24X0_REG32	LOCKTIME;
+	S3C24X0_REG32	MPLLCON;
+	S3C24X0_REG32	UPLLCON;
+	S3C24X0_REG32	CLKCON;
+	S3C24X0_REG32	CLKSLOW;
+	S3C24X0_REG32	CLKDIVN;
+} /*__attribute__((__packed__))*/ S3C24X0_CLOCK_POWER;
+
+
+/* LCD CONTROLLER (see manual chapter 15) */
+typedef struct {
+	S3C24X0_REG32	LCDCON1;
+	S3C24X0_REG32	LCDCON2;
+	S3C24X0_REG32	LCDCON3;
+	S3C24X0_REG32	LCDCON4;
+	S3C24X0_REG32	LCDCON5;
+	S3C24X0_REG32	LCDSADDR1;
+	S3C24X0_REG32	LCDSADDR2;
+	S3C24X0_REG32	LCDSADDR3;
+	S3C24X0_REG32	REDLUT;
+	S3C24X0_REG32	GREENLUT;
+	S3C24X0_REG32	BLUELUT;
+	S3C24X0_REG32	res[8];
+	S3C24X0_REG32	DITHMODE;
+	S3C24X0_REG32	TPAL;
+#ifdef CONFIG_S3C2410
+	S3C24X0_REG32	LCDINTPND;
+	S3C24X0_REG32	LCDSRCPND;
+	S3C24X0_REG32	LCDINTMSK;
+	S3C24X0_REG32	LPCSEL;
+#endif
+} /*__attribute__((__packed__))*/ S3C24X0_LCD;
+
+
+/* NAND FLASH (see S3C2410 manual chapter 6) */
+typedef struct {
+	S3C24X0_REG32	NFCONF;
+	S3C24X0_REG32	NFCMD;
+	S3C24X0_REG32	NFADDR;
+	S3C24X0_REG32	NFDATA;
+	S3C24X0_REG32	NFSTAT;
+	S3C24X0_REG32	NFECC;
+} /*__attribute__((__packed__))*/ S3C2410_NAND;
+
+
+/* UART (see manual chapter 11) */
+typedef struct {
+	S3C24X0_REG32	ULCON;
+	S3C24X0_REG32	UCON;
+	S3C24X0_REG32	UFCON;
+	S3C24X0_REG32	UMCON;
+	S3C24X0_REG32	UTRSTAT;
+	S3C24X0_REG32	UERSTAT;
+	S3C24X0_REG32	UFSTAT;
+	S3C24X0_REG32	UMSTAT;
+#ifdef __BIG_ENDIAN
+	S3C24X0_REG8	res1[3];
+	S3C24X0_REG8	UTXH;
+	S3C24X0_REG8	res2[3];
+	S3C24X0_REG8	URXH;
+#else /* Little Endian */
+	S3C24X0_REG8	UTXH;
+	S3C24X0_REG8	res1[3];
+	S3C24X0_REG8	URXH;
+	S3C24X0_REG8	res2[3];
+#endif
+	S3C24X0_REG32	UBRDIV;
+} /*__attribute__((__packed__))*/ S3C24X0_UART;
+
+
+/* PWM TIMER (see manual chapter 10) */
+typedef struct {
+	S3C24X0_REG32	TCNTB;
+	S3C24X0_REG32	TCMPB;
+	S3C24X0_REG32	TCNTO;
+} /*__attribute__((__packed__))*/ S3C24X0_TIMER;
+
+typedef struct {
+	S3C24X0_REG32	TCFG0;
+	S3C24X0_REG32	TCFG1;
+	S3C24X0_REG32	TCON;
+	S3C24X0_TIMER	ch[4];
+	S3C24X0_REG32	TCNTB4;
+	S3C24X0_REG32	TCNTO4;
+} /*__attribute__((__packed__))*/ S3C24X0_TIMERS;
+
+
+/* USB DEVICE (see manual chapter 13) */
+typedef struct {
+#ifdef __BIG_ENDIAN
+	S3C24X0_REG8	res[3];
+	S3C24X0_REG8	EP_FIFO_REG;
+#else /*  little endian */
+	S3C24X0_REG8	EP_FIFO_REG;
+	S3C24X0_REG8	res[3];
+#endif
+} /*__attribute__((__packed__))*/ S3C24X0_USB_DEV_FIFOS;
+
+typedef struct {
+#ifdef __BIG_ENDIAN
+	S3C24X0_REG8	res1[3];
+	S3C24X0_REG8	EP_DMA_CON;
+	S3C24X0_REG8	res2[3];
+	S3C24X0_REG8	EP_DMA_UNIT;
+	S3C24X0_REG8	res3[3];
+	S3C24X0_REG8	EP_DMA_FIFO;
+	S3C24X0_REG8	res4[3];
+	S3C24X0_REG8	EP_DMA_TTC_L;
+	S3C24X0_REG8	res5[3];
+	S3C24X0_REG8	EP_DMA_TTC_M;
+	S3C24X0_REG8	res6[3];
+	S3C24X0_REG8	EP_DMA_TTC_H;
+#else /*  little endian */
+	S3C24X0_REG8	EP_DMA_CON;
+	S3C24X0_REG8	res1[3];
+	S3C24X0_REG8	EP_DMA_UNIT;
+	S3C24X0_REG8	res2[3];
+	S3C24X0_REG8	EP_DMA_FIFO;
+	S3C24X0_REG8	res3[3];
+	S3C24X0_REG8	EP_DMA_TTC_L;
+	S3C24X0_REG8	res4[3];
+	S3C24X0_REG8	EP_DMA_TTC_M;
+	S3C24X0_REG8	res5[3];
+	S3C24X0_REG8	EP_DMA_TTC_H;
+	S3C24X0_REG8	res6[3];
+#endif
+} /*__attribute__((__packed__))*/ S3C24X0_USB_DEV_DMAS;
+
+typedef struct {
+#ifdef __BIG_ENDIAN
+	S3C24X0_REG8	res1[3];
+	S3C24X0_REG8	FUNC_ADDR_REG;
+	S3C24X0_REG8	res2[3];
+	S3C24X0_REG8	PWR_REG;
+	S3C24X0_REG8	res3[3];
+	S3C24X0_REG8	EP_INT_REG;
+	S3C24X0_REG8	res4[15];
+	S3C24X0_REG8	USB_INT_REG;
+	S3C24X0_REG8	res5[3];
+	S3C24X0_REG8	EP_INT_EN_REG;
+	S3C24X0_REG8	res6[15];
+	S3C24X0_REG8	USB_INT_EN_REG;
+	S3C24X0_REG8	res7[3];
+	S3C24X0_REG8	FRAME_NUM1_REG;
+	S3C24X0_REG8	res8[3];
+	S3C24X0_REG8	FRAME_NUM2_REG;
+	S3C24X0_REG8	res9[3];
+	S3C24X0_REG8	INDEX_REG;
+	S3C24X0_REG8	res10[7];
+	S3C24X0_REG8	MAXP_REG;
+	S3C24X0_REG8	res11[3];
+	S3C24X0_REG8	EP0_CSR_IN_CSR1_REG;
+	S3C24X0_REG8	res12[3];
+	S3C24X0_REG8	IN_CSR2_REG;
+	S3C24X0_REG8	res13[7];
+	S3C24X0_REG8	OUT_CSR1_REG;
+	S3C24X0_REG8	res14[3];
+	S3C24X0_REG8	OUT_CSR2_REG;
+	S3C24X0_REG8	res15[3];
+	S3C24X0_REG8	OUT_FIFO_CNT1_REG;
+	S3C24X0_REG8	res16[3];
+	S3C24X0_REG8	OUT_FIFO_CNT2_REG;
+#else /*  little endian */
+	S3C24X0_REG8	FUNC_ADDR_REG;
+	S3C24X0_REG8	res1[3];
+	S3C24X0_REG8	PWR_REG;
+	S3C24X0_REG8	res2[3];
+	S3C24X0_REG8	EP_INT_REG;
+	S3C24X0_REG8	res3[15];
+	S3C24X0_REG8	USB_INT_REG;
+	S3C24X0_REG8	res4[3];
+	S3C24X0_REG8	EP_INT_EN_REG;
+	S3C24X0_REG8	res5[15];
+	S3C24X0_REG8	USB_INT_EN_REG;
+	S3C24X0_REG8	res6[3];
+	S3C24X0_REG8	FRAME_NUM1_REG;
+	S3C24X0_REG8	res7[3];
+	S3C24X0_REG8	FRAME_NUM2_REG;
+	S3C24X0_REG8	res8[3];
+	S3C24X0_REG8	INDEX_REG;
+	S3C24X0_REG8	res9[7];
+	S3C24X0_REG8	MAXP_REG;
+	S3C24X0_REG8	res10[7];
+	S3C24X0_REG8	EP0_CSR_IN_CSR1_REG;
+	S3C24X0_REG8	res11[3];
+	S3C24X0_REG8	IN_CSR2_REG;
+	S3C24X0_REG8	res12[3];
+	S3C24X0_REG8	OUT_CSR1_REG;
+	S3C24X0_REG8	res13[7];
+	S3C24X0_REG8	OUT_CSR2_REG;
+	S3C24X0_REG8	res14[3];
+	S3C24X0_REG8	OUT_FIFO_CNT1_REG;
+	S3C24X0_REG8	res15[3];
+	S3C24X0_REG8	OUT_FIFO_CNT2_REG;
+	S3C24X0_REG8	res16[3];
+#endif /*  __BIG_ENDIAN */
+	S3C24X0_USB_DEV_FIFOS	fifo[5];
+	S3C24X0_USB_DEV_DMAS	dma[5];
+} /*__attribute__((__packed__))*/ S3C24X0_USB_DEVICE;
+
+
+/* WATCH DOG TIMER (see manual chapter 18) */
+typedef struct {
+	S3C24X0_REG32	WTCON;
+	S3C24X0_REG32	WTDAT;
+	S3C24X0_REG32	WTCNT;
+} /*__attribute__((__packed__))*/ S3C24X0_WATCHDOG;
+
+
+/* IIC (see manual chapter 20) */
+typedef struct {
+	S3C24X0_REG32	IICCON;
+	S3C24X0_REG32	IICSTAT;
+	S3C24X0_REG32	IICADD;
+	S3C24X0_REG32	IICDS;
+} /*__attribute__((__packed__))*/ S3C24X0_I2C;
+
+
+/* IIS (see manual chapter 21) */
+typedef struct {
+#ifdef __BIG_ENDIAN
+	S3C24X0_REG16	res1;
+	S3C24X0_REG16	IISCON;
+	S3C24X0_REG16	res2;
+	S3C24X0_REG16	IISMOD;
+	S3C24X0_REG16	res3;
+	S3C24X0_REG16	IISPSR;
+	S3C24X0_REG16	res4;
+	S3C24X0_REG16	IISFCON;
+	S3C24X0_REG16	res5;
+	S3C24X0_REG16	IISFIFO;
+#else /*  little endian */
+	S3C24X0_REG16	IISCON;
+	S3C24X0_REG16	res1;
+	S3C24X0_REG16	IISMOD;
+	S3C24X0_REG16	res2;
+	S3C24X0_REG16	IISPSR;
+	S3C24X0_REG16	res3;
+	S3C24X0_REG16	IISFCON;
+	S3C24X0_REG16	res4;
+	S3C24X0_REG16	IISFIFO;
+	S3C24X0_REG16	res5;
+#endif
+} /*__attribute__((__packed__))*/ S3C24X0_I2S;
+
+
+/* I/O PORT (see manual chapter 9) */
+typedef struct {
+#ifdef CONFIG_S3C2400
+	S3C24X0_REG32	PACON;
+	S3C24X0_REG32	PADAT;
+	
+	S3C24X0_REG32	PBCON;
+	S3C24X0_REG32	PBDAT;
+	S3C24X0_REG32	PBUP;
+
+	S3C24X0_REG32	PCCON;
+	S3C24X0_REG32	PCDAT;
+	S3C24X0_REG32	PCUP;
+
+	S3C24X0_REG32	PDCON;
+	S3C24X0_REG32	PDDAT;
+	S3C24X0_REG32	PDUP;
+
+	S3C24X0_REG32	PECON;
+	S3C24X0_REG32	PEDAT;
+	S3C24X0_REG32	PEUP;
+
+	S3C24X0_REG32	PFCON;
+	S3C24X0_REG32	PFDAT;
+	S3C24X0_REG32	PFUP;
+
+	S3C24X0_REG32	PGCON;
+	S3C24X0_REG32	PGDAT;
+	S3C24X0_REG32	PGUP;
+
+	S3C24X0_REG32	OPENCR;
+
+	S3C24X0_REG32	MISCCR;
+	S3C24X0_REG32	EXTINT;
+#endif
+#ifdef CONFIG_S3C2410
+	S3C24X0_REG32	GPACON;
+	S3C24X0_REG32	GPADAT;
+	S3C24X0_REG32	res1[2];
+	S3C24X0_REG32	GPBCON;
+	S3C24X0_REG32	GPBDAT;
+	S3C24X0_REG32	GPBUP;
+	S3C24X0_REG32	res2;
+	S3C24X0_REG32	GPCCON;
+	S3C24X0_REG32	GPCDAT;
+	S3C24X0_REG32	GPCUP;
+	S3C24X0_REG32	res3;
+	S3C24X0_REG32	GPDCON;
+	S3C24X0_REG32	GPDDAT;
+	S3C24X0_REG32	GPDUP;
+	S3C24X0_REG32	res4;
+	S3C24X0_REG32	GPECON;
+	S3C24X0_REG32	GPEDAT;
+	S3C24X0_REG32	GPEUP;
+	S3C24X0_REG32	res5;
+	S3C24X0_REG32	GPFCON;
+	S3C24X0_REG32	GPFDAT;
+	S3C24X0_REG32	GPFUP;
+	S3C24X0_REG32	res6;
+	S3C24X0_REG32	GPGCON;
+	S3C24X0_REG32	GPGDAT;
+	S3C24X0_REG32	GPGUP;
+	S3C24X0_REG32	res7;
+	S3C24X0_REG32	GPHCON;
+	S3C24X0_REG32	GPHDAT;
+	S3C24X0_REG32	GPHUP;
+	S3C24X0_REG32	res8;
+
+	S3C24X0_REG32	MISCCR;
+	S3C24X0_REG32	DCLKCON;
+	S3C24X0_REG32	EXTINT0;
+	S3C24X0_REG32	EXTINT1;
+	S3C24X0_REG32	EXTINT2;
+	S3C24X0_REG32	EINTFLT0;
+	S3C24X0_REG32	EINTFLT1;
+	S3C24X0_REG32	EINTFLT2;
+	S3C24X0_REG32	EINTFLT3;
+	S3C24X0_REG32	EINTMASK;
+	S3C24X0_REG32	EINTPEND;
+	S3C24X0_REG32	GSTATUS0;
+	S3C24X0_REG32	GSTATUS1;
+	S3C24X0_REG32	GSTATUS2;
+	S3C24X0_REG32	GSTATUS3;
+	S3C24X0_REG32	GSTATUS4;
+#endif
+} /*__attribute__((__packed__))*/ S3C24X0_GPIO;
+
+
+/* RTC (see manual chapter 17) */
+typedef struct {
+#ifdef __BIG_ENDIAN
+	S3C24X0_REG8	res1[67];
+	S3C24X0_REG8	RTCCON;
+	S3C24X0_REG8	res2[3];
+	S3C24X0_REG8	TICNT;
+	S3C24X0_REG8	res3[11];
+	S3C24X0_REG8	RTCALM;
+	S3C24X0_REG8	res4[3];
+	S3C24X0_REG8	ALMSEC;
+	S3C24X0_REG8	res5[3];
+	S3C24X0_REG8	ALMMIN;
+	S3C24X0_REG8	res6[3];
+	S3C24X0_REG8	ALMHOUR;
+	S3C24X0_REG8	res7[3];
+	S3C24X0_REG8	ALMDATE;
+	S3C24X0_REG8	res8[3];
+	S3C24X0_REG8	ALMMON;
+	S3C24X0_REG8	res9[3];
+	S3C24X0_REG8	ALMYEAR;
+	S3C24X0_REG8	res10[3];
+	S3C24X0_REG8	RTCRST;
+	S3C24X0_REG8	res11[3];
+	S3C24X0_REG8	BCDSEC;
+	S3C24X0_REG8	res12[3];
+	S3C24X0_REG8	BCDMIN;
+	S3C24X0_REG8	res13[3];
+	S3C24X0_REG8	BCDHOUR;
+	S3C24X0_REG8	res14[3];
+	S3C24X0_REG8	BCDDATE;
+	S3C24X0_REG8	res15[3];
+	S3C24X0_REG8	BCDDAY;
+	S3C24X0_REG8	res16[3];
+	S3C24X0_REG8	BCDMON;
+	S3C24X0_REG8	res17[3];
+	S3C24X0_REG8	BCDYEAR;
+#else /*  little endian */
+	S3C24X0_REG8	res0[64];
+	S3C24X0_REG8	RTCCON;
+	S3C24X0_REG8	res1[3];
+	S3C24X0_REG8	TICNT;
+	S3C24X0_REG8	res2[11];
+	S3C24X0_REG8	RTCALM;
+	S3C24X0_REG8	res3[3];
+	S3C24X0_REG8	ALMSEC;
+	S3C24X0_REG8	res4[3];
+	S3C24X0_REG8	ALMMIN;
+	S3C24X0_REG8	res5[3];
+	S3C24X0_REG8	ALMHOUR;
+	S3C24X0_REG8	res6[3];
+	S3C24X0_REG8	ALMDATE;
+	S3C24X0_REG8	res7[3];
+	S3C24X0_REG8	ALMMON;
+	S3C24X0_REG8	res8[3];
+	S3C24X0_REG8	ALMYEAR;
+	S3C24X0_REG8	res9[3];
+	S3C24X0_REG8	RTCRST;
+	S3C24X0_REG8	res10[3];
+	S3C24X0_REG8	BCDSEC;
+	S3C24X0_REG8	res11[3];
+	S3C24X0_REG8	BCDMIN;
+	S3C24X0_REG8	res12[3];
+	S3C24X0_REG8	BCDHOUR;
+	S3C24X0_REG8	res13[3];
+	S3C24X0_REG8	BCDDATE;
+	S3C24X0_REG8	res14[3];
+	S3C24X0_REG8	BCDDAY;
+	S3C24X0_REG8	res15[3];
+	S3C24X0_REG8	BCDMON;
+	S3C24X0_REG8	res16[3];
+	S3C24X0_REG8	BCDYEAR;
+	S3C24X0_REG8	res17[3];
+#endif
+} /*__attribute__((__packed__))*/ S3C24X0_RTC;
+
+
+/* ADC (see manual chapter 16) */
+typedef struct {
+	S3C24X0_REG32	ADCCON;
+	S3C24X0_REG32	ADCDAT;
+} /*__attribute__((__packed__))*/ S3C2400_ADC;
+
+
+/* ADC (see manual chapter 16) */
+typedef struct {
+	S3C24X0_REG32	ADCCON;
+	S3C24X0_REG32	ADCTSC;
+	S3C24X0_REG32	ADCDLY;
+	S3C24X0_REG32	ADCDAT0;
+	S3C24X0_REG32	ADCDAT1;
+} /*__attribute__((__packed__))*/ S3C2410_ADC;
+
+
+/* SPI (see manual chapter 22) */
+typedef struct {
+	S3C24X0_REG32	SPCON;
+	S3C24X0_REG32	SPSTA;
+	S3C24X0_REG32	SPPIN;
+	S3C24X0_REG32	SPPRE;
+	S3C24X0_REG32	SPTDAT;
+	S3C24X0_REG32	SPRDAT;
+	S3C24X0_REG32	res[2];
+} __attribute__((__packed__)) S3C24X0_SPI_CHANNEL;
+
+typedef struct {
+	S3C24X0_SPI_CHANNEL	ch[S3C24X0_SPI_CHANNELS];
+} /*__attribute__((__packed__))*/ S3C24X0_SPI;
+
+
+/* MMC INTERFACE (see S3C2400 manual chapter 19) */
+typedef struct {
+#ifdef __BIG_ENDIAN
+	S3C24X0_REG8	res1[3];
+	S3C24X0_REG8	MMCON;
+	S3C24X0_REG8	res2[3];
+	S3C24X0_REG8	MMCRR;
+	S3C24X0_REG8	res3[3];
+	S3C24X0_REG8	MMFCON;
+	S3C24X0_REG8	res4[3];
+	S3C24X0_REG8	MMSTA;
+	S3C24X0_REG16	res5;
+	S3C24X0_REG16	MMFSTA;
+	S3C24X0_REG8	res6[3];
+	S3C24X0_REG8	MMPRE;
+	S3C24X0_REG16	res7;
+	S3C24X0_REG16	MMLEN;
+	S3C24X0_REG8	res8[3];
+	S3C24X0_REG8	MMCR7;
+	S3C24X0_REG32	MMRSP[4];
+	S3C24X0_REG8	res9[3];
+	S3C24X0_REG8	MMCMD0;
+	S3C24X0_REG32	MMCMD1;
+	S3C24X0_REG16	res10;
+	S3C24X0_REG16	MMCR16;
+	S3C24X0_REG8	res11[3];
+	S3C24X0_REG8	MMDAT;
+#else
+	S3C24X0_REG8	MMCON;
+	S3C24X0_REG8	res1[3];
+	S3C24X0_REG8	MMCRR;
+	S3C24X0_REG8	res2[3];
+	S3C24X0_REG8	MMFCON;
+	S3C24X0_REG8	res3[3];
+	S3C24X0_REG8	MMSTA;
+	S3C24X0_REG8	res4[3];
+	S3C24X0_REG16	MMFSTA;
+	S3C24X0_REG16	res5;
+	S3C24X0_REG8	MMPRE;
+	S3C24X0_REG8	res6[3];
+	S3C24X0_REG16	MMLEN;
+	S3C24X0_REG16	res7;
+	S3C24X0_REG8	MMCR7;
+	S3C24X0_REG8	res8[3];
+	S3C24X0_REG32	MMRSP[4];
+	S3C24X0_REG8	MMCMD0;
+	S3C24X0_REG8	res9[3];
+	S3C24X0_REG32	MMCMD1;
+	S3C24X0_REG16	MMCR16;
+	S3C24X0_REG16	res10;
+	S3C24X0_REG8	MMDAT;
+	S3C24X0_REG8	res11[3];
+#endif
+} /*__attribute__((__packed__))*/ S3C2400_MMC;
+
+
+/* SD INTERFACE (see S3C2410 manual chapter 19) */
+typedef struct {
+	S3C24X0_REG32	SDICON;
+	S3C24X0_REG32	SDIPRE;
+	S3C24X0_REG32	SDICARG;
+	S3C24X0_REG32	SDICCON;
+	S3C24X0_REG32	SDICSTA;
+	S3C24X0_REG32	SDIRSP0;
+	S3C24X0_REG32	SDIRSP1;
+	S3C24X0_REG32	SDIRSP2;
+	S3C24X0_REG32	SDIRSP3;
+	S3C24X0_REG32	SDIDTIMER;
+	S3C24X0_REG32	SDIBSIZE;
+	S3C24X0_REG32	SDIDCON;
+	S3C24X0_REG32	SDIDCNT;
+	S3C24X0_REG32	SDIDSTA;
+	S3C24X0_REG32	SDIFSTA;
+#ifdef __BIG_ENDIAN
+	S3C24X0_REG8	res[3];
+	S3C24X0_REG8	SDIDAT;
+#else
+	S3C24X0_REG8	SDIDAT;
+	S3C24X0_REG8	res[3];
+#endif
+	S3C24X0_REG32	SDIIMSK;
+} /*__attribute__((__packed__))*/ S3C2410_SDI;
+
+
+#if 0
+/* Memory control */
+#define rBWSCON			(*(volatile unsigned *)0x48000000)
+#define rBANKCON0		(*(volatile unsigned *)0x48000004)
+#define rBANKCON1		(*(volatile unsigned *)0x48000008)
+#define rBANKCON2		(*(volatile unsigned *)0x4800000C)
+#define rBANKCON3		(*(volatile unsigned *)0x48000010)
+#define rBANKCON4		(*(volatile unsigned *)0x48000014)
+#define rBANKCON5		(*(volatile unsigned *)0x48000018)
+#define rBANKCON6		(*(volatile unsigned *)0x4800001C)
+#define rBANKCON7		(*(volatile unsigned *)0x48000020)
+#define rREFRESH		(*(volatile unsigned *)0x48000024)
+#define rBANKSIZE		(*(volatile unsigned *)0x48000028)
+#define rMRSRB6			(*(volatile unsigned *)0x4800002C)
+#define rMRSRB7			(*(volatile unsigned *)0x48000030)
+
+
+/* USB HOST */
+#define rHcRevision		(*(volatile unsigned *)0x49000000)
+#define rHcControl		(*(volatile unsigned *)0x49000004)
+#define rHcCommonStatus		(*(volatile unsigned *)0x49000008)
+#define rHcInterruptStatus	(*(volatile unsigned *)0x4900000C)
+#define rHcInterruptEnable	(*(volatile unsigned *)0x49000010)
+#define rHcInterruptDisable	(*(volatile unsigned *)0x49000014)
+#define rHcHCCA			(*(volatile unsigned *)0x49000018)
+#define rHcPeriodCuttendED	(*(volatile unsigned *)0x4900001C)
+#define rHcControlHeadED	(*(volatile unsigned *)0x49000020)
+#define rHcControlCurrentED	(*(volatile unsigned *)0x49000024)
+#define rHcBulkHeadED		(*(volatile unsigned *)0x49000028)
+#define rHcBuldCurrentED	(*(volatile unsigned *)0x4900002C)
+#define rHcDoneHead		(*(volatile unsigned *)0x49000030)
+#define rHcRmInterval		(*(volatile unsigned *)0x49000034)
+#define rHcFmRemaining		(*(volatile unsigned *)0x49000038)
+#define rHcFmNumber		(*(volatile unsigned *)0x4900003C)
+#define rHcPeriodicStart	(*(volatile unsigned *)0x49000040)
+#define rHcLSThreshold		(*(volatile unsigned *)0x49000044)
+#define rHcRhDescriptorA	(*(volatile unsigned *)0x49000048)
+#define rHcRhDescriptorB	(*(volatile unsigned *)0x4900004C)
+#define rHcRhStatus		(*(volatile unsigned *)0x49000050)
+#define rHcRhPortStatus1	(*(volatile unsigned *)0x49000054)
+#define rHcRhPortStatus2	(*(volatile unsigned *)0x49000058)
+
+
+/* INTERRUPT */
+#define rSRCPND			(*(volatile unsigned *)0x4A000000)
+#define rINTMOD			(*(volatile unsigned *)0x4A000004)
+#define rINTMSK			(*(volatile unsigned *)0x4A000008)
+#define rPRIORITY		(*(volatile unsigned *)0x4A00000C)
+#define rINTPND			(*(volatile unsigned *)0x4A000010)
+#define rINTOFFSET		(*(volatile unsigned *)0x4A000014)
+#define rSUBSRCPND		(*(volatile unsigned *)0x4A000018)
+#define rINTSUBMSK		(*(volatile unsigned *)0x4A00001C)
+
+
+/* DMA */
+#define rDISRC0			(*(volatile unsigned *)0x4B000000)
+#define rDISRCC0		(*(volatile unsigned *)0x4B000004)
+#define rDIDST0			(*(volatile unsigned *)0x4B000008)
+#define rDIDSTC0		(*(volatile unsigned *)0x4B00000C)
+#define rDCON0			(*(volatile unsigned *)0x4B000010)
+#define rDSTAT0			(*(volatile unsigned *)0x4B000014)
+#define rDCSRC0			(*(volatile unsigned *)0x4B000018)
+#define rDCDST0			(*(volatile unsigned *)0x4B00001C)
+#define rDMASKTRIG0		(*(volatile unsigned *)0x4B000020)
+#define rDISRC1			(*(volatile unsigned *)0x4B000040)
+#define rDISRCC1		(*(volatile unsigned *)0x4B000044)
+#define rDIDST1			(*(volatile unsigned *)0x4B000048)
+#define rDIDSTC1		(*(volatile unsigned *)0x4B00004C)
+#define rDCON1			(*(volatile unsigned *)0x4B000050)
+#define rDSTAT1			(*(volatile unsigned *)0x4B000054)
+#define rDCSRC1			(*(volatile unsigned *)0x4B000058)
+#define rDCDST1			(*(volatile unsigned *)0x4B00005C)
+#define rDMASKTRIG1		(*(volatile unsigned *)0x4B000060)
+#define rDISRC2			(*(volatile unsigned *)0x4B000080)
+#define rDISRCC2		(*(volatile unsigned *)0x4B000084)
+#define rDIDST2			(*(volatile unsigned *)0x4B000088)
+#define rDIDSTC2		(*(volatile unsigned *)0x4B00008C)
+#define rDCON2			(*(volatile unsigned *)0x4B000090)
+#define rDSTAT2			(*(volatile unsigned *)0x4B000094)
+#define rDCSRC2			(*(volatile unsigned *)0x4B000098)
+#define rDCDST2			(*(volatile unsigned *)0x4B00009C)
+#define rDMASKTRIG2		(*(volatile unsigned *)0x4B0000A0)
+#define rDISRC3			(*(volatile unsigned *)0x4B0000C0)
+#define rDISRCC3		(*(volatile unsigned *)0x4B0000C4)
+#define rDIDST3			(*(volatile unsigned *)0x4B0000C8)
+#define rDIDSTC3		(*(volatile unsigned *)0x4B0000CC)
+#define rDCON3			(*(volatile unsigned *)0x4B0000D0)
+#define rDSTAT3			(*(volatile unsigned *)0x4B0000D4)
+#define rDCSRC3			(*(volatile unsigned *)0x4B0000D8)
+#define rDCDST3			(*(volatile unsigned *)0x4B0000DC)
+#define rDMASKTRIG3		(*(volatile unsigned *)0x4B0000E0)
+
+
+/* CLOCK & POWER MANAGEMENT */
+#define rLOCKTIME		(*(volatile unsigned *)0x4C000000)
+#define rMPLLCON		(*(volatile unsigned *)0x4C000004)
+#define rUPLLCON		(*(volatile unsigned *)0x4C000008)
+#define rCLKCON			(*(volatile unsigned *)0x4C00000C)
+#define rCLKSLOW		(*(volatile unsigned *)0x4C000010)
+#define rCLKDIVN		(*(volatile unsigned *)0x4C000014)
+
+
+/* LCD CONTROLLER */
+#define rLCDCON1		(*(volatile unsigned *)0x4D000000)
+#define rLCDCON2		(*(volatile unsigned *)0x4D000004)
+#define rLCDCON3		(*(volatile unsigned *)0x4D000008)
+#define rLCDCON4		(*(volatile unsigned *)0x4D00000C)
+#define rLCDCON5		(*(volatile unsigned *)0x4D000010)
+#define rLCDSADDR1		(*(volatile unsigned *)0x4D000014)
+#define rLCDSADDR2		(*(volatile unsigned *)0x4D000018)
+#define rLCDSADDR3		(*(volatile unsigned *)0x4D00001C)
+#define rREDLUT			(*(volatile unsigned *)0x4D000020)
+#define rGREENLUT		(*(volatile unsigned *)0x4D000024)
+#define rBLUELUT		(*(volatile unsigned *)0x4D000028)
+#define rDITHMODE		(*(volatile unsigned *)0x4D00004C)
+#define rTPAL			(*(volatile unsigned *)0x4D000050)
+#define rLCDINTPND		(*(volatile unsigned *)0x4D000054)
+#define rLCDSRCPND		(*(volatile unsigned *)0x4D000058)
+#define rLCDINTMSK		(*(volatile unsigned *)0x4D00005C)
+
+
+/* NAND FLASH */
+#define rNFCONF			(*(volatile unsigned *)0x4E000000)
+#define rNFCMD			(*(volatile unsigned *)0x4E000004)
+#define rNFADDR			(*(volatile unsigned *)0x4E000008)
+#define rNFDATA			(*(volatile unsigned *)0x4E00000C)
+#define rNFSTAT			(*(volatile unsigned *)0x4E000010)
+#define rNFECC			(*(volatile unsigned *)0x4E000014)
+
+
+/* UART */
+#define rULCON0			(*(volatile unsigned *)0x50000000)
+#define rUCON0			(*(volatile unsigned *)0x50000004)
+#define rUFCON0			(*(volatile unsigned *)0x50000008)
+#define rUMCON0			(*(volatile unsigned *)0x5000000C)
+#define rUTRSTAT0		(*(volatile unsigned *)0x50000010)
+#define rUERSTAT0		(*(volatile unsigned *)0x50000014)
+#define rUFSTAT0		(*(volatile unsigned *)0x50000018)
+#define rUMSTAT0		(*(volatile unsigned *)0x5000001C)
+#define rUBRDIV0		(*(volatile unsigned *)0x50000028)
+
+#define rULCON1			(*(volatile unsigned *)0x50004000)
+#define rUCON1			(*(volatile unsigned *)0x50004004)
+#define rUFCON1			(*(volatile unsigned *)0x50004008)
+#define rUMCON1			(*(volatile unsigned *)0x5000400C)
+#define rUTRSTAT1		(*(volatile unsigned *)0x50004010)
+#define rUERSTAT1		(*(volatile unsigned *)0x50004014)
+#define rUFSTAT1		(*(volatile unsigned *)0x50004018)
+#define rUMSTAT1		(*(volatile unsigned *)0x5000401C)
+#define rUBRDIV1		(*(volatile unsigned *)0x50004028)
+
+#define rULCON2			(*(volatile unsigned *)0x50008000)
+#define rUCON2			(*(volatile unsigned *)0x50008004)
+#define rUFCON2			(*(volatile unsigned *)0x50008008)
+#define rUTRSTAT2		(*(volatile unsigned *)0x50008010)
+#define rUERSTAT2		(*(volatile unsigned *)0x50008014)
+#define rUFSTAT2		(*(volatile unsigned *)0x50008018)
+#define rUBRDIV2		(*(volatile unsigned *)0x50008028)
+
+#ifdef __BIG_ENDIAN
+#define rUTXH0			(*(volatile unsigned char *)0x50000023)
+#define rURXH0			(*(volatile unsigned char *)0x50000027)
+#define rUTXH1			(*(volatile unsigned char *)0x50004023)
+#define rURXH1			(*(volatile unsigned char *)0x50004027)
+#define rUTXH2			(*(volatile unsigned char *)0x50008023)
+#define rURXH2			(*(volatile unsigned char *)0x50008027)
+
+#define WrUTXH0(ch)		(*(volatile unsigned char *)0x50000023)=(unsigned char)(ch)
+#define RdURXH0()		(*(volatile unsigned char *)0x50000027)
+#define WrUTXH1(ch)		(*(volatile unsigned char *)0x50004023)=(unsigned char)(ch)
+#define RdURXH1()		(*(volatile unsigned char *)0x50004027)
+#define WrUTXH2(ch)		(*(volatile unsigned char *)0x50008023)=(unsigned char)(ch)
+#define RdURXH2()		(*(volatile unsigned char *)0x50008027)
+
+#define UTXH0			(0x50000020+3)  /* byte_access address by DMA */
+#define URXH0			(0x50000024+3)
+#define UTXH1			(0x50004020+3)
+#define URXH1			(0x50004024+3)
+#define UTXH2			(0x50008020+3)
+#define URXH2			(0x50008024+3)
+
+#else /* Little Endian */
+#define rUTXH0			(*(volatile unsigned char *)0x50000020)
+#define rURXH0			(*(volatile unsigned char *)0x50000024)
+#define rUTXH1			(*(volatile unsigned char *)0x50004020)
+#define rURXH1			(*(volatile unsigned char *)0x50004024)
+#define rUTXH2			(*(volatile unsigned char *)0x50008020)
+#define rURXH2			(*(volatile unsigned char *)0x50008024)
+
+#define WrUTXH0(ch)		(*(volatile unsigned char *)0x50000020)=(unsigned char)(ch)
+#define RdURXH0()		(*(volatile unsigned char *)0x50000024)
+#define WrUTXH1(ch)		(*(volatile unsigned char *)0x50004020)=(unsigned char)(ch)
+#define RdURXH1()		(*(volatile unsigned char *)0x50004024)
+#define WrUTXH2(ch)		(*(volatile unsigned char *)0x50008020)=(unsigned char)(ch)
+#define RdURXH2()		(*(volatile unsigned char *)0x50008024)
+
+#define UTXH0			(0x50000020)    /* byte_access address by DMA */
+#define URXH0			(0x50000024)
+#define UTXH1			(0x50004020)
+#define URXH1			(0x50004024)
+#define UTXH2			(0x50008020)
+#define URXH2			(0x50008024)
+#endif
+
+
+/* PWM TIMER */
+#define rTCFG0			(*(volatile unsigned *)0x51000000)
+#define rTCFG1			(*(volatile unsigned *)0x51000004)
+#define rTCON			(*(volatile unsigned *)0x51000008)
+#define rTCNTB0			(*(volatile unsigned *)0x5100000C)
+#define rTCMPB0			(*(volatile unsigned *)0x51000010)
+#define rTCNTO0			(*(volatile unsigned *)0x51000014)
+#define rTCNTB1			(*(volatile unsigned *)0x51000018)
+#define rTCMPB1			(*(volatile unsigned *)0x5100001C)
+#define rTCNTO1			(*(volatile unsigned *)0x51000020)
+#define rTCNTB2			(*(volatile unsigned *)0x51000024)
+#define rTCMPB2			(*(volatile unsigned *)0x51000028)
+#define rTCNTO2			(*(volatile unsigned *)0x5100002C)
+#define rTCNTB3			(*(volatile unsigned *)0x51000030)
+#define rTCMPB3			(*(volatile unsigned *)0x51000034)
+#define rTCNTO3			(*(volatile unsigned *)0x51000038)
+#define rTCNTB4			(*(volatile unsigned *)0x5100003C)
+#define rTCNTO4			(*(volatile unsigned *)0x51000040)
+
+
+/* USB DEVICE */
+#ifdef __BIG_ENDIAN
+#define rFUNC_ADDR_REG		(*(volatile unsigned char *)0x52000143)
+#define rPWR_REG		(*(volatile unsigned char *)0x52000147)
+#define rEP_INT_REG		(*(volatile unsigned char *)0x5200014B)
+#define rUSB_INT_REG		(*(volatile unsigned char *)0x5200015B)
+#define rEP_INT_EN_REG		(*(volatile unsigned char *)0x5200015F)
+#define rUSB_INT_EN_REG		(*(volatile unsigned char *)0x5200016F)
+#define rFRAME_NUM1_REG		(*(volatile unsigned char *)0x52000173)
+#define rFRAME_NUM2_REG		(*(volatile unsigned char *)0x52000177)
+#define rINDEX_REG		(*(volatile unsigned char *)0x5200017B)
+#define rMAXP_REG		(*(volatile unsigned char *)0x52000183)
+#define rEP0_CSR		(*(volatile unsigned char *)0x52000187)
+#define rIN_CSR1_REG		(*(volatile unsigned char *)0x52000187)
+#define rIN_CSR2_REG		(*(volatile unsigned char *)0x5200018B)
+#define rOUT_CSR1_REG		(*(volatile unsigned char *)0x52000193)
+#define rOUT_CSR2_REG		(*(volatile unsigned char *)0x52000197)
+#define rOUT_FIFO_CNT1_REG	(*(volatile unsigned char *)0x5200019B)
+#define rOUT_FIFO_CNT2_REG	(*(volatile unsigned char *)0x5200019F)
+#define rEP0_FIFO		(*(volatile unsigned char *)0x520001C3)
+#define rEP1_FIFO		(*(volatile unsigned char *)0x520001C7)
+#define rEP2_FIFO		(*(volatile unsigned char *)0x520001CB)
+#define rEP3_FIFO		(*(volatile unsigned char *)0x520001CF)
+#define rEP4_FIFO		(*(volatile unsigned char *)0x520001D3)
+#define rEP1_DMA_CON		(*(volatile unsigned char *)0x52000203)
+#define rEP1_DMA_UNIT		(*(volatile unsigned char *)0x52000207)
+#define rEP1_DMA_FIFO		(*(volatile unsigned char *)0x5200020B)
+#define rEP1_DMA_TX_LO		(*(volatile unsigned char *)0x5200020F)
+#define rEP1_DMA_TX_MD		(*(volatile unsigned char *)0x52000213)
+#define rEP1_DMA_TX_HI		(*(volatile unsigned char *)0x52000217)
+#define rEP2_DMA_CON		(*(volatile unsigned char *)0x5200021B)
+#define rEP2_DMA_UNIT		(*(volatile unsigned char *)0x5200021F)
+#define rEP2_DMA_FIFO		(*(volatile unsigned char *)0x52000223)
+#define rEP2_DMA_TX_LO		(*(volatile unsigned char *)0x52000227)
+#define rEP2_DMA_TX_MD		(*(volatile unsigned char *)0x5200022B)
+#define rEP2_DMA_TX_HI		(*(volatile unsigned char *)0x5200022F)
+#define rEP3_DMA_CON		(*(volatile unsigned char *)0x52000243)
+#define rEP3_DMA_UNIT		(*(volatile unsigned char *)0x52000247)
+#define rEP3_DMA_FIFO		(*(volatile unsigned char *)0x5200024B)
+#define rEP3_DMA_TX_LO		(*(volatile unsigned char *)0x5200024F)
+#define rEP3_DMA_TX_MD		(*(volatile unsigned char *)0x52000253)
+#define rEP3_DMA_TX_HI		(*(volatile unsigned char *)0x52000257)
+#define rEP4_DMA_CON		(*(volatile unsigned char *)0x5200025B)
+#define rEP4_DMA_UNIT		(*(volatile unsigned char *)0x5200025F)
+#define rEP4_DMA_FIFO		(*(volatile unsigned char *)0x52000263)
+#define rEP4_DMA_TX_LO		(*(volatile unsigned char *)0x52000267)
+#define rEP4_DMA_TX_MD		(*(volatile unsigned char *)0x5200026B)
+#define rEP4_DMA_TX_HI		(*(volatile unsigned char *)0x5200026F)
+#else /*  little endian */
+#define rFUNC_ADDR_REG		(*(volatile unsigned char *)0x52000140)
+#define rPWR_REG		(*(volatile unsigned char *)0x52000144)
+#define rEP_INT_REG		(*(volatile unsigned char *)0x52000148)
+#define rUSB_INT_REG		(*(volatile unsigned char *)0x52000158)
+#define rEP_INT_EN_REG		(*(volatile unsigned char *)0x5200015C)
+#define rUSB_INT_EN_REG		(*(volatile unsigned char *)0x5200016C)
+#define rFRAME_NUM1_REG		(*(volatile unsigned char *)0x52000170)
+#define rFRAME_NUM2_REG		(*(volatile unsigned char *)0x52000174)
+#define rINDEX_REG		(*(volatile unsigned char *)0x52000178)
+#define rMAXP_REG		(*(volatile unsigned char *)0x52000180)
+#define rEP0_CSR		(*(volatile unsigned char *)0x52000184)
+#define rIN_CSR1_REG		(*(volatile unsigned char *)0x52000184)
+#define rIN_CSR2_REG		(*(volatile unsigned char *)0x52000188)
+#define rOUT_CSR1_REG		(*(volatile unsigned char *)0x52000190)
+#define rOUT_CSR2_REG		(*(volatile unsigned char *)0x52000194)
+#define rOUT_FIFO_CNT1_REG	(*(volatile unsigned char *)0x52000198)
+#define rOUT_FIFO_CNT2_REG	(*(volatile unsigned char *)0x5200019C)
+#define rEP0_FIFO		(*(volatile unsigned char *)0x520001C0)
+#define rEP1_FIFO		(*(volatile unsigned char *)0x520001C4)
+#define rEP2_FIFO		(*(volatile unsigned char *)0x520001C8)
+#define rEP3_FIFO		(*(volatile unsigned char *)0x520001CC)
+#define rEP4_FIFO		(*(volatile unsigned char *)0x520001D0)
+#define rEP1_DMA_CON		(*(volatile unsigned char *)0x52000200)
+#define rEP1_DMA_UNIT		(*(volatile unsigned char *)0x52000204)
+#define rEP1_DMA_FIFO		(*(volatile unsigned char *)0x52000208)
+#define rEP1_DMA_TX_LO		(*(volatile unsigned char *)0x5200020C)
+#define rEP1_DMA_TX_MD		(*(volatile unsigned char *)0x52000210)
+#define rEP1_DMA_TX_HI		(*(volatile unsigned char *)0x52000214)
+#define rEP2_DMA_CON		(*(volatile unsigned char *)0x52000218)
+#define rEP2_DMA_UNIT		(*(volatile unsigned char *)0x5200021C)
+#define rEP2_DMA_FIFO		(*(volatile unsigned char *)0x52000220)
+#define rEP2_DMA_TX_LO		(*(volatile unsigned char *)0x52000224)
+#define rEP2_DMA_TX_MD		(*(volatile unsigned char *)0x52000228)
+#define rEP2_DMA_TX_HI		(*(volatile unsigned char *)0x5200022C)
+#define rEP3_DMA_CON		(*(volatile unsigned char *)0x52000240)
+#define rEP3_DMA_UNIT		(*(volatile unsigned char *)0x52000244)
+#define rEP3_DMA_FIFO		(*(volatile unsigned char *)0x52000248)
+#define rEP3_DMA_TX_LO		(*(volatile unsigned char *)0x5200024C)
+#define rEP3_DMA_TX_MD		(*(volatile unsigned char *)0x52000250)
+#define rEP3_DMA_TX_HI		(*(volatile unsigned char *)0x52000254)
+#define rEP4_DMA_CON		(*(volatile unsigned char *)0x52000258)
+#define rEP4_DMA_UNIT		(*(volatile unsigned char *)0x5200025C)
+#define rEP4_DMA_FIFO		(*(volatile unsigned char *)0x52000260)
+#define rEP4_DMA_TX_LO		(*(volatile unsigned char *)0x52000264)
+#define rEP4_DMA_TX_MD		(*(volatile unsigned char *)0x52000268)
+#define rEP4_DMA_TX_HI		(*(volatile unsigned char *)0x5200026C)
+#endif /*  __BIG_ENDIAN */
+
+
+/* WATCH DOG TIMER */
+#define rWTCON			(*(volatile unsigned *)0x53000000)
+#define rWTDAT			(*(volatile unsigned *)0x53000004)
+#define rWTCNT			(*(volatile unsigned *)0x53000008)
+
+
+/* IIC */
+#define rIICCON			(*(volatile unsigned *)0x54000000)
+#define rIICSTAT		(*(volatile unsigned *)0x54000004)
+#define rIICADD			(*(volatile unsigned *)0x54000008)
+#define rIICDS			(*(volatile unsigned *)0x5400000C)
+
+
+/* IIS */
+#define rIISCON			(*(volatile unsigned *)0x55000000)
+#define rIISMOD			(*(volatile unsigned *)0x55000004)
+#define rIISPSR			(*(volatile unsigned *)0x55000008)
+#define rIISFCON		(*(volatile unsigned *)0x5500000C)
+
+#ifdef __BIG_ENDIAN
+#define IISFIF			((volatile unsigned short *)0x55000012)
+#else /*  little endian */
+#define IISFIF			((volatile unsigned short *)0x55000010)
+#endif
+
+
+/* I/O PORT */
+#define rGPACON			(*(volatile unsigned *)0x56000000)
+#define rGPADAT			(*(volatile unsigned *)0x56000004)
+
+#define rGPBCON			(*(volatile unsigned *)0x56000010)
+#define rGPBDAT			(*(volatile unsigned *)0x56000014)
+#define rGPBUP			(*(volatile unsigned *)0x56000018)
+
+#define rGPCCON			(*(volatile unsigned *)0x56000020)
+#define rGPCDAT			(*(volatile unsigned *)0x56000024)
+#define rGPCUP			(*(volatile unsigned *)0x56000028)
+
+#define rGPDCON			(*(volatile unsigned *)0x56000030)
+#define rGPDDAT			(*(volatile unsigned *)0x56000034)
+#define rGPDUP			(*(volatile unsigned *)0x56000038)
+
+#define rGPECON			(*(volatile unsigned *)0x56000040)
+#define rGPEDAT			(*(volatile unsigned *)0x56000044)
+#define rGPEUP			(*(volatile unsigned *)0x56000048)
+
+#define rGPFCON			(*(volatile unsigned *)0x56000050)
+#define rGPFDAT			(*(volatile unsigned *)0x56000054)
+#define rGPFUP			(*(volatile unsigned *)0x56000058)
+
+#define rGPGCON			(*(volatile unsigned *)0x56000060)
+#define rGPGDAT			(*(volatile unsigned *)0x56000064)
+#define rGPGUP			(*(volatile unsigned *)0x56000068)
+
+#define rGPHCON			(*(volatile unsigned *)0x56000070)
+#define rGPHDAT			(*(volatile unsigned *)0x56000074)
+#define rGPHUP			(*(volatile unsigned *)0x56000078)
+
+#define rMISCCR			(*(volatile unsigned *)0x56000080)
+#define rDCLKCON		(*(volatile unsigned *)0x56000084)
+#define rEXTINT0		(*(volatile unsigned *)0x56000088)
+#define rEXTINT1		(*(volatile unsigned *)0x5600008C)
+#define rEXTINT2		(*(volatile unsigned *)0x56000090)
+#define rEINTFLT0		(*(volatile unsigned *)0x56000094)
+#define rEINTFLT1		(*(volatile unsigned *)0x56000098)
+#define rEINTFLT2		(*(volatile unsigned *)0x5600009C)
+#define rEINTFLT3		(*(volatile unsigned *)0x560000A0)
+#define rEINTMASK		(*(volatile unsigned *)0x560000A4)
+#define rEINTPEND		(*(volatile unsigned *)0x560000A8)
+#define rGSTATUS0		(*(volatile unsigned *)0x560000AC)
+#define rGSTATUS1		(*(volatile unsigned *)0x560000B0)
+
+
+/* RTC */
+#ifdef __BIG_ENDIAN
+#define rRTCCON			(*(volatile unsigned char *)0x57000043)
+#define rTICNT			(*(volatile unsigned char *)0x57000047)
+#define rRTCALM			(*(volatile unsigned char *)0x57000053)
+#define rALMSEC			(*(volatile unsigned char *)0x57000057)
+#define rALMMIN			(*(volatile unsigned char *)0x5700005B)
+#define rALMHOUR		(*(volatile unsigned char *)0x5700005F)
+#define rALMDATE		(*(volatile unsigned char *)0x57000063)
+#define rALMMON			(*(volatile unsigned char *)0x57000067)
+#define rALMYEAR		(*(volatile unsigned char *)0x5700006B)
+#define rRTCRST			(*(volatile unsigned char *)0x5700006F)
+#define rBCDSEC			(*(volatile unsigned char *)0x57000073)
+#define rBCDMIN			(*(volatile unsigned char *)0x57000077)
+#define rBCDHOUR		(*(volatile unsigned char *)0x5700007B)
+#define rBCDDATE		(*(volatile unsigned char *)0x5700007F)
+#define rBCDDAY			(*(volatile unsigned char *)0x57000083)
+#define rBCDMON			(*(volatile unsigned char *)0x57000087)
+#define rBCDYEAR		(*(volatile unsigned char *)0x5700008B)
+#else /*  little endian */
+#define rRTCCON			(*(volatile unsigned char *)0x57000040)
+#define rTICNT			(*(volatile unsigned char *)0x57000044)
+#define rRTCALM			(*(volatile unsigned char *)0x57000050)
+#define rALMSEC			(*(volatile unsigned char *)0x57000054)
+#define rALMMIN			(*(volatile unsigned char *)0x57000058)
+#define rALMHOUR		(*(volatile unsigned char *)0x5700005C)
+#define rALMDATE		(*(volatile unsigned char *)0x57000060)
+#define rALMMON			(*(volatile unsigned char *)0x57000064)
+#define rALMYEAR		(*(volatile unsigned char *)0x57000068)
+#define rRTCRST			(*(volatile unsigned char *)0x5700006C)
+#define rBCDSEC			(*(volatile unsigned char *)0x57000070)
+#define rBCDMIN			(*(volatile unsigned char *)0x57000074)
+#define rBCDHOUR		(*(volatile unsigned char *)0x57000078)
+#define rBCDDATE		(*(volatile unsigned char *)0x5700007C)
+#define rBCDDAY			(*(volatile unsigned char *)0x57000080)
+#define rBCDMON			(*(volatile unsigned char *)0x57000084)
+#define rBCDYEAR		(*(volatile unsigned char *)0x57000088)
+#endif
+
+
+/* ADC */
+#define rADCCON			(*(volatile unsigned *)0x58000000)
+#define rADCTSC			(*(volatile unsigned *)0x58000004)
+#define rADCDLY			(*(volatile unsigned *)0x58000008)
+#define rADCDAT0		(*(volatile unsigned *)0x5800000C)
+#define rADCDAT1		(*(volatile unsigned *)0x58000010)
+
+
+/* SPI */
+#define rSPCON0			(*(volatile unsigned *)0x59000000)
+#define rSPSTA0			(*(volatile unsigned *)0x59000004)
+#define rSPPIN0			(*(volatile unsigned *)0x59000008)
+#define rSPPRE0			(*(volatile unsigned *)0x5900000C)
+#define rSPTDAT0		(*(volatile unsigned *)0x59000010)
+#define rSPRDAT0		(*(volatile unsigned *)0x59000014)
+#define rSPCON1			(*(volatile unsigned *)0x59000020)
+#define rSPSTA1			(*(volatile unsigned *)0x59000024)
+#define rSPPIN1			(*(volatile unsigned *)0x59000028)
+#define rSPPRE1			(*(volatile unsigned *)0x5900002C)
+#define rSPTDAT1		(*(volatile unsigned *)0x59000030)
+#define rSPRDAT1		(*(volatile unsigned *)0x59000034)
+
+
+/* SD INTERFACE */
+#define rSDICON			(*(volatile unsigned *)0x5A000000)
+#define rSDIPRE			(*(volatile unsigned *)0x5A000004)
+#define rSDICmdArg		(*(volatile unsigned *)0x5A000008)
+#define rSDICmdCon		(*(volatile unsigned *)0x5A00000C)
+#define rSDICmdSta		(*(volatile unsigned *)0x5A000010)
+#define rSDIRSP0		(*(volatile unsigned *)0x5A000014)
+#define rSDIRSP1		(*(volatile unsigned *)0x5A000018)
+#define rSDIRSP2		(*(volatile unsigned *)0x5A00001C)
+#define rSDIRSP3		(*(volatile unsigned *)0x5A000020)
+#define rSDIDTimer		(*(volatile unsigned *)0x5A000024)
+#define rSDIBSize		(*(volatile unsigned *)0x5A000028)
+#define rSDIDatCon		(*(volatile unsigned *)0x5A00002C)
+#define rSDIDatCnt		(*(volatile unsigned *)0x5A000030)
+#define rSDIDatSta		(*(volatile unsigned *)0x5A000034)
+#define rSDIFSTA		(*(volatile unsigned *)0x5A000038)
+#ifdef __BIG_ENDIAN
+#define rSDIDAT			(*(volatile unsigned char *)0x5A00003F)
+#else
+#define rSDIDAT			(*(volatile unsigned char *)0x5A00003C)
+#endif
+#define rSDIIntMsk		(*(volatile unsigned *)0x5A000040)
+
+#endif
+
+#endif /*__S3C24X0_H__*/

include/status_led.h

@@ -321,6 +321,10 @@ void status_led_set  (int led, int state);
 #endif
 /************************************************************************/
 
+#ifndef CONFIG_BOARD_SPECIFIC_LED
+# include <asm/status_led.h>
+#endif
+
 #endif	/* CONFIG_STATUS_LED	*/
 
 #endif	/* _STATUS_LED_H_	*/

lib_arm/board.c

@@ -42,8 +42,12 @@ extern int  AT91F_DataflashInit(void);
 extern void dataflash_print_info(void);
 #endif
 
+#ifndef CONFIG_IDENT_STRING
+#define CONFIG_IDENT_STRING ""
+#endif
+
 const char version_string[] =
-	U_BOOT_VERSION" (" __DATE__ " - " __TIME__ ")";
+	U_BOOT_VERSION" (" __DATE__ " - " __TIME__ ")"CONFIG_IDENT_STRING;
 
 #ifdef CONFIG_DRIVER_CS8900
 extern void cs8900_get_enetaddr (uchar * addr);
@@ -150,7 +154,6 @@ static void display_flash_config (ulong size)
 }
 
 
-
 /*
  * Breath some life into the board...
  *

rtc/Makefile

@@ -31,7 +31,7 @@ OBJS	= date.o   \
 	  ds12887.o ds1302.o ds1306.o ds1307.o ds1337.o \
 	  ds1556.o ds164x.o ds174x.o \
 	  m41t11.o m48t35ax.o mc146818.o mk48t59.o \
-	  mpc8xx.o pcf8563.o
+	  mpc8xx.o pcf8563.o s3c24x0_rtc.o
 
 all:	$(LIB)
 

rtc/s3c24x0_rtc.c

@@ -0,0 +1,178 @@
+/*
+ * (C) Copyright 2003
+ * David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Date & Time support for the built-in Samsung S3C24X0 RTC
+ */
+
+#include <common.h>
+#include <command.h>
+
+#if defined(CONFIG_RTC_S3C24X0) && (CONFIG_COMMANDS & CFG_CMD_DATE)
+
+#if defined(CONFIG_S3C2400)
+#include <s3c2400.h>
+#elif defined(CONFIG_S3C2410)
+#include <s3c2410.h>
+#endif
+
+#include <rtc.h>
+
+/*#define	DEBUG*/
+
+typedef enum {
+	RTC_ENABLE,
+	RTC_DISABLE
+} RTC_ACCESS;
+
+
+static inline void SetRTC_Access(RTC_ACCESS a)
+{
+	S3C24X0_RTC * const rtc = S3C24X0_GetBase_RTC();
+	switch (a) {
+		case RTC_ENABLE:
+			rtc->RTCCON |= 0x01; break;
+
+		case RTC_DISABLE:
+			rtc->RTCCON &= ~0x01; break;
+	}
+}
+
+static unsigned bcd2bin (uchar n)
+{
+	return ((((n >> 4) & 0x0F) * 10) + (n & 0x0F));
+}
+
+static unsigned char bin2bcd (unsigned int n)
+{
+	return (((n / 10) << 4) | (n % 10));
+}
+
+/* ------------------------------------------------------------------------- */
+
+void rtc_get (struct rtc_time *tmp)
+{
+	S3C24X0_RTC * const rtc = S3C24X0_GetBase_RTC();
+	uchar sec, min, hour, mday, wday, mon, year;
+	uchar a_sec,a_min, a_hour, a_date, a_mon, a_year, a_armed;
+
+	/* enable access to RTC registers */
+	SetRTC_Access(RTC_ENABLE);
+
+	/* read RTC registers */
+	sec	= rtc->BCDSEC;
+	min	= rtc->BCDMIN;
+	hour	= rtc->BCDHOUR;
+	mday	= rtc->BCDDATE;
+	wday	= rtc->BCDDAY;
+	mon	= rtc->BCDMON;
+	year	= rtc->BCDYEAR;
+
+	/* read ALARM registers */
+	a_sec	= rtc->ALMSEC;
+	a_min	= rtc->ALMMIN;
+	a_hour	= rtc->ALMHOUR;
+	a_date	= rtc->ALMDATE;
+	a_mon	= rtc->ALMMON;
+	a_year	= rtc->ALMYEAR;
+	a_armed	= rtc->RTCALM;
+
+	/* disable access to RTC registers */
+	SetRTC_Access(RTC_DISABLE);
+
+#ifdef RTC_DEBUG
+	printf ( "Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x "
+		"hr: %02x min: %02x sec: %02x\n",
+		year, mon, mday, wday,
+		hour, min, sec);
+	printf ( "Alarms: %02x: year: %02x month: %02x date: %02x hour: %02x min: %02x sec: %02x\n",
+		a_armed,
+		a_year, a_mon, a_date,
+		a_hour, a_min, a_sec);
+#endif
+
+	tmp->tm_sec  = bcd2bin(sec  & 0x7F);
+	tmp->tm_min  = bcd2bin(min  & 0x7F);
+	tmp->tm_hour = bcd2bin(hour & 0x3F);
+	tmp->tm_mday = bcd2bin(mday & 0x3F);
+	tmp->tm_mon  = bcd2bin(mon & 0x1F);
+	tmp->tm_year = bcd2bin(year);
+	tmp->tm_wday = bcd2bin(wday & 0x07);
+	if(tmp->tm_year<70)
+		tmp->tm_year+=2000;
+	else
+		tmp->tm_year+=1900;
+	tmp->tm_yday = 0;
+	tmp->tm_isdst= 0;
+#ifdef RTC_DEBUG
+	printf ( "Get DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
+		tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
+		tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
+#endif
+}
+
+void rtc_set (struct rtc_time *tmp)
+{
+	S3C24X0_RTC * const rtc = S3C24X0_GetBase_RTC();
+	uchar sec, min, hour, mday, wday, mon, year;
+
+#ifdef RTC_DEBUG
+	printf ( "Set DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
+		tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
+		tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
+#endif
+	year	= bin2bcd(tmp->tm_year % 100);
+	mon	= bin2bcd(tmp->tm_mon);
+	wday	= bin2bcd(tmp->tm_wday);
+	mday	= bin2bcd(tmp->tm_mday);
+	hour	= bin2bcd(tmp->tm_hour);
+	min	= bin2bcd(tmp->tm_min);
+	sec	= bin2bcd(tmp->tm_sec);
+
+	/* enable access to RTC registers */
+	SetRTC_Access(RTC_ENABLE);
+
+	/* write RTC registers */
+	rtc->BCDSEC	= sec;
+	rtc->BCDMIN	= min;
+	rtc->BCDHOUR	= hour;
+	rtc->BCDDATE	= mday;
+	rtc->BCDDAY	= wday;
+	rtc->BCDMON	= mon;
+	rtc->BCDYEAR	= year;
+
+	/* disable access to RTC registers */
+	SetRTC_Access(RTC_DISABLE);
+}
+
+void rtc_reset (void)
+{
+	S3C24X0_RTC * const rtc = S3C24X0_GetBase_RTC();
+
+	rtc->RTCCON = (rtc->RTCCON & ~0x06) | 0x08;
+	rtc->RTCCON &= ~0x08;
+}
+
+/* ------------------------------------------------------------------------- */
+
+#endif	/* CONFIG_RTC_S3C24X0 && CFG_CMD_DATE */