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  1. /*
  2. * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
  3. * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
  4. * Copyright (C) 2000, 2001,2002 Wolfgang Denk <wd@denx.de>
  5. *
  6. * See file CREDITS for list of people who contributed to this
  7. * project.
  8. *
  9. * This program is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License as
  11. * published by the Free Software Foundation; either version 2 of
  12. * the License, or (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22. * MA 02111-1307 USA
  23. */
  24. /*
  25. * U-Boot - Startup Code for MPC8260 PowerPC based Embedded Boards
  26. */
  27. #include <config.h>
  28. #include <mpc8260.h>
  29. #include <version.h>
  30. #define CONFIG_8260 1 /* needed for Linux kernel header files */
  31. #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
  32. #include <ppc_asm.tmpl>
  33. #include <ppc_defs.h>
  34. #include <asm/cache.h>
  35. #include <asm/mmu.h>
  36. #ifndef CONFIG_IDENT_STRING
  37. #define CONFIG_IDENT_STRING ""
  38. #endif
  39. /* We don't want the MMU yet.
  40. */
  41. #undef MSR_KERNEL
  42. /* Floating Point enable, Machine Check and Recoverable Interr. */
  43. #ifdef DEBUG
  44. #define MSR_KERNEL (MSR_FP|MSR_RI)
  45. #else
  46. #define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
  47. #endif
  48. /*
  49. * Set up GOT: Global Offset Table
  50. *
  51. * Use r14 to access the GOT
  52. */
  53. START_GOT
  54. GOT_ENTRY(_GOT2_TABLE_)
  55. GOT_ENTRY(_FIXUP_TABLE_)
  56. GOT_ENTRY(_start)
  57. GOT_ENTRY(_start_of_vectors)
  58. GOT_ENTRY(_end_of_vectors)
  59. GOT_ENTRY(transfer_to_handler)
  60. GOT_ENTRY(__init_end)
  61. GOT_ENTRY(_end)
  62. GOT_ENTRY(__bss_start)
  63. #if defined(CONFIG_HYMOD)
  64. GOT_ENTRY(environment)
  65. #endif
  66. END_GOT
  67. /*
  68. * Version string - must be in data segment because MPC8260 uses the first
  69. * 256 bytes for the Hard Reset Configuration Word table (see below).
  70. * Similarly, can't have the U-Boot Magic Number as the first thing in
  71. * the image - don't know how this will affect the image tools, but I guess
  72. * I'll find out soon
  73. */
  74. .data
  75. .globl version_string
  76. version_string:
  77. .ascii U_BOOT_VERSION
  78. .ascii " (", __DATE__, " - ", __TIME__, ")"
  79. .ascii CONFIG_IDENT_STRING, "\0"
  80. /*
  81. * Hard Reset Configuration Word (HRCW) table
  82. *
  83. * The Hard Reset Configuration Word (HRCW) sets a number of useful things
  84. * such as whether there is an external memory controller, whether the
  85. * PowerPC core is disabled (i.e. only the communications processor is
  86. * active, accessed by another CPU on the bus), whether using external
  87. * arbitration, external bus mode, boot port size, core initial prefix,
  88. * internal space base, boot memory space, etc.
  89. *
  90. * These things dictate where the processor begins execution, where the
  91. * boot ROM appears in memory, the memory controller setup when access
  92. * boot ROM, etc. The HRCW is *extremely* important.
  93. *
  94. * The HRCW is read from the bus during reset. One CPU on the bus will
  95. * be a hard reset configuration master, any others will be hard reset
  96. * configuration slaves. The master reads eight HRCWs from flash during
  97. * reset - the first it uses for itself, the other 7 it communicates to
  98. * up to 7 configuration slaves by some complicated mechanism, which is
  99. * not really important here.
  100. *
  101. * The configuration master performs 32 successive reads starting at address
  102. * 0 and incrementing by 8 each read (i.e. on 64 bit boundaries) but only 8
  103. * bits is read, and always from byte lane D[0-7] (so that port size of the
  104. * boot device does not matter). The first four reads form the 32 bit HRCW
  105. * for the master itself. The second four reads form the HRCW for the first
  106. * slave, and so on, up to seven slaves. The 32 bit HRCW is formed by
  107. * concatenating the four bytes, with the first read placed in byte 0 (the
  108. * most significant byte), and so on with the fourth read placed in byte 3
  109. * (the least significant byte).
  110. */
  111. #define _HRCW_TABLE_ENTRY(w) \
  112. .fill 8,1,(((w)>>24)&0xff); \
  113. .fill 8,1,(((w)>>16)&0xff); \
  114. .fill 8,1,(((w)>> 8)&0xff); \
  115. .fill 8,1,(((w) )&0xff)
  116. .text
  117. .globl _hrcw_table
  118. _hrcw_table:
  119. _HRCW_TABLE_ENTRY(CFG_HRCW_MASTER)
  120. _HRCW_TABLE_ENTRY(CFG_HRCW_SLAVE1)
  121. _HRCW_TABLE_ENTRY(CFG_HRCW_SLAVE2)
  122. _HRCW_TABLE_ENTRY(CFG_HRCW_SLAVE3)
  123. _HRCW_TABLE_ENTRY(CFG_HRCW_SLAVE4)
  124. _HRCW_TABLE_ENTRY(CFG_HRCW_SLAVE5)
  125. _HRCW_TABLE_ENTRY(CFG_HRCW_SLAVE6)
  126. _HRCW_TABLE_ENTRY(CFG_HRCW_SLAVE7)
  127. /*
  128. * After configuration, a system reset exception is executed using the
  129. * vector at offset 0x100 relative to the base set by MSR[IP]. If MSR[IP]
  130. * is 0, the base address is 0x00000000. If MSR[IP] is 1, the base address
  131. * is 0xfff00000. In the case of a Power On Reset or Hard Reset, the value
  132. * of MSR[IP] is determined by the CIP field in the HRCW.
  133. *
  134. * Other bits in the HRCW set up the Base Address and Port Size in BR0.
  135. * This determines the location of the boot ROM (flash or EPROM) in the
  136. * processor's address space at boot time. As long as the HRCW is set up
  137. * so that we eventually end up executing the code below when the processor
  138. * executes the reset exception, the actual values used should not matter.
  139. *
  140. * Once we have got here, the address mask in OR0 is cleared so that the
  141. * bottom 32K of the boot ROM is effectively repeated all throughout the
  142. * processor's address space, after which we can jump to the absolute
  143. * address at which the boot ROM was linked at compile time, and proceed
  144. * to initialise the memory controller without worrying if the rug will be
  145. * pulled out from under us, so to speak (it will be fine as long as we
  146. * configure BR0 with the same boot ROM link address).
  147. */
  148. . = EXC_OFF_SYS_RESET
  149. .globl _start
  150. _start:
  151. li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH*/
  152. nop
  153. b boot_cold
  154. . = EXC_OFF_SYS_RESET + 0x10
  155. .globl _start_warm
  156. _start_warm:
  157. li r21, BOOTFLAG_WARM /* Software reboot */
  158. b boot_warm
  159. boot_cold:
  160. #if defined(CONFIG_MPC8260ADS)
  161. lis r3, CFG_DEFAULT_IMMR@h
  162. nop
  163. lwz r4, 0(r3)
  164. nop
  165. rlwinm r4, r4, 0, 8, 5
  166. nop
  167. oris r4, r4, 0x0200
  168. nop
  169. stw r4, 0(r3)
  170. nop
  171. #endif /* CONFIG_MPC8260ADS */
  172. boot_warm:
  173. mfmsr r5 /* save msr contents */
  174. #if defined(CONFIG_COGENT)
  175. /* this is what the cogent EPROM does */
  176. li r0, 0
  177. mtmsr r0
  178. isync
  179. bl cogent_init_8260
  180. #endif /* CONFIG_COGENT */
  181. #if defined(CFG_DEFAULT_IMMR)
  182. lis r3, CFG_IMMR@h
  183. ori r3, r3, CFG_IMMR@l
  184. lis r4, CFG_DEFAULT_IMMR@h
  185. stw r3, 0x1A8(r4)
  186. #endif /* CFG_DEFAULT_IMMR */
  187. /* Initialise the MPC8260 processor core */
  188. /*--------------------------------------------------------------*/
  189. bl init_8260_core
  190. #ifndef CFG_RAMBOOT
  191. /* When booting from ROM (Flash or EPROM), clear the */
  192. /* Address Mask in OR0 so ROM appears everywhere */
  193. /*--------------------------------------------------------------*/
  194. lis r3, (CFG_IMMR+IM_REGBASE)@h
  195. lwz r4, IM_OR0@l(r3)
  196. li r5, 0x7fff
  197. and r4, r4, r5
  198. stw r4, IM_OR0@l(r3)
  199. /* Calculate absolute address in FLASH and jump there */
  200. /*--------------------------------------------------------------*/
  201. lis r3, CFG_MONITOR_BASE@h
  202. ori r3, r3, CFG_MONITOR_BASE@l
  203. addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
  204. mtlr r3
  205. blr
  206. in_flash:
  207. #endif /* CFG_RAMBOOT */
  208. /* initialize some things that are hard to access from C */
  209. /*--------------------------------------------------------------*/
  210. lis r3, CFG_IMMR@h /* set up stack in internal DPRAM */
  211. ori r1, r3, CFG_INIT_SP_OFFSET
  212. li r0, 0 /* Make room for stack frame header and */
  213. stwu r0, -4(r1) /* clear final stack frame so that */
  214. stwu r0, -4(r1) /* stack backtraces terminate cleanly */
  215. /* let the C-code set up the rest */
  216. /* */
  217. /* Be careful to keep code relocatable ! */
  218. /*--------------------------------------------------------------*/
  219. GET_GOT /* initialize GOT access */
  220. /* r3: IMMR */
  221. bl cpu_init_f /* run low-level CPU init code (in Flash)*/
  222. #ifdef DEBUG
  223. bl init_debug /* set up debugging stuff */
  224. #endif
  225. mr r3, r21
  226. /* r3: BOOTFLAG */
  227. bl board_init_f /* run 1st part of board init code (in Flash)*/
  228. /*
  229. * Vector Table
  230. */
  231. .globl _start_of_vectors
  232. _start_of_vectors:
  233. /* Machine check */
  234. STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
  235. /* Data Storage exception. */
  236. STD_EXCEPTION(0x300, DataStorage, UnknownException)
  237. /* Instruction Storage exception. */
  238. STD_EXCEPTION(0x400, InstStorage, UnknownException)
  239. /* External Interrupt exception. */
  240. STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
  241. /* Alignment exception. */
  242. . = 0x600
  243. Alignment:
  244. EXCEPTION_PROLOG
  245. mfspr r4,DAR
  246. stw r4,_DAR(r21)
  247. mfspr r5,DSISR
  248. stw r5,_DSISR(r21)
  249. addi r3,r1,STACK_FRAME_OVERHEAD
  250. li r20,MSR_KERNEL
  251. rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
  252. rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */
  253. lwz r6,GOT(transfer_to_handler)
  254. mtlr r6
  255. blrl
  256. .L_Alignment:
  257. .long AlignmentException - _start + EXC_OFF_SYS_RESET
  258. .long int_return - _start + EXC_OFF_SYS_RESET
  259. /* Program check exception */
  260. . = 0x700
  261. ProgramCheck:
  262. EXCEPTION_PROLOG
  263. addi r3,r1,STACK_FRAME_OVERHEAD
  264. li r20,MSR_KERNEL
  265. rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
  266. rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */
  267. lwz r6,GOT(transfer_to_handler)
  268. mtlr r6
  269. blrl
  270. .L_ProgramCheck:
  271. .long ProgramCheckException - _start + EXC_OFF_SYS_RESET
  272. .long int_return - _start + EXC_OFF_SYS_RESET
  273. STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
  274. /* I guess we could implement decrementer, and may have
  275. * to someday for timekeeping.
  276. */
  277. STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
  278. STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
  279. STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
  280. . = 0xc00
  281. /*
  282. * r0 - SYSCALL number
  283. * r3-... arguments
  284. */
  285. SystemCall:
  286. addis r11,r0,0 /* get functions table addr */
  287. ori r11,r11,0 /* Note: this code is patched in trap_init */
  288. addis r12,r0,0 /* get number of functions */
  289. ori r12,r12,0
  290. cmplw 0, r0, r12
  291. bge 1f
  292. rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */
  293. add r11,r11,r0
  294. lwz r11,0(r11)
  295. li r20,0xd00-4 /* Get stack pointer */
  296. lwz r12,0(r20)
  297. subi r12,r12,12 /* Adjust stack pointer */
  298. li r0,0xc00+_end_back-SystemCall
  299. cmplw 0, r0, r12 /* Check stack overflow */
  300. bgt 1f
  301. stw r12,0(r20)
  302. mflr r0
  303. stw r0,0(r12)
  304. mfspr r0,SRR0
  305. stw r0,4(r12)
  306. mfspr r0,SRR1
  307. stw r0,8(r12)
  308. li r12,0xc00+_back-SystemCall
  309. mtlr r12
  310. mtspr SRR0,r11
  311. 1: SYNC
  312. rfi
  313. _back:
  314. mfmsr r11 /* Disable interrupts */
  315. li r12,0
  316. ori r12,r12,MSR_EE
  317. andc r11,r11,r12
  318. SYNC /* Some chip revs need this... */
  319. mtmsr r11
  320. SYNC
  321. li r12,0xd00-4 /* restore regs */
  322. lwz r12,0(r12)
  323. lwz r11,0(r12)
  324. mtlr r11
  325. lwz r11,4(r12)
  326. mtspr SRR0,r11
  327. lwz r11,8(r12)
  328. mtspr SRR1,r11
  329. addi r12,r12,12 /* Adjust stack pointer */
  330. li r20,0xd00-4
  331. stw r12,0(r20)
  332. SYNC
  333. rfi
  334. _end_back:
  335. STD_EXCEPTION(0xd00, SingleStep, UnknownException)
  336. STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
  337. STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
  338. STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException)
  339. STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException)
  340. STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException)
  341. #ifdef DEBUG
  342. . = 0x1300
  343. /*
  344. * This exception occurs when the program counter matches the
  345. * Instruction Address Breakpoint Register (IABR).
  346. *
  347. * I want the cpu to halt if this occurs so I can hunt around
  348. * with the debugger and look at things.
  349. *
  350. * When DEBUG is defined, both machine check enable (in the MSR)
  351. * and checkstop reset enable (in the reset mode register) are
  352. * turned off and so a checkstop condition will result in the cpu
  353. * halting.
  354. *
  355. * I force the cpu into a checkstop condition by putting an illegal
  356. * instruction here (at least this is the theory).
  357. *
  358. * well - that didnt work, so just do an infinite loop!
  359. */
  360. 1: b 1b
  361. #else
  362. STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException)
  363. #endif
  364. STD_EXCEPTION(0x1400, SMI, UnknownException)
  365. STD_EXCEPTION(0x1500, Trap_15, UnknownException)
  366. STD_EXCEPTION(0x1600, Trap_16, UnknownException)
  367. STD_EXCEPTION(0x1700, Trap_17, UnknownException)
  368. STD_EXCEPTION(0x1800, Trap_18, UnknownException)
  369. STD_EXCEPTION(0x1900, Trap_19, UnknownException)
  370. STD_EXCEPTION(0x1a00, Trap_1a, UnknownException)
  371. STD_EXCEPTION(0x1b00, Trap_1b, UnknownException)
  372. STD_EXCEPTION(0x1c00, Trap_1c, UnknownException)
  373. STD_EXCEPTION(0x1d00, Trap_1d, UnknownException)
  374. STD_EXCEPTION(0x1e00, Trap_1e, UnknownException)
  375. STD_EXCEPTION(0x1f00, Trap_1f, UnknownException)
  376. STD_EXCEPTION(0x2000, Trap_20, UnknownException)
  377. STD_EXCEPTION(0x2100, Trap_21, UnknownException)
  378. STD_EXCEPTION(0x2200, Trap_22, UnknownException)
  379. STD_EXCEPTION(0x2300, Trap_23, UnknownException)
  380. STD_EXCEPTION(0x2400, Trap_24, UnknownException)
  381. STD_EXCEPTION(0x2500, Trap_25, UnknownException)
  382. STD_EXCEPTION(0x2600, Trap_26, UnknownException)
  383. STD_EXCEPTION(0x2700, Trap_27, UnknownException)
  384. STD_EXCEPTION(0x2800, Trap_28, UnknownException)
  385. STD_EXCEPTION(0x2900, Trap_29, UnknownException)
  386. STD_EXCEPTION(0x2a00, Trap_2a, UnknownException)
  387. STD_EXCEPTION(0x2b00, Trap_2b, UnknownException)
  388. STD_EXCEPTION(0x2c00, Trap_2c, UnknownException)
  389. STD_EXCEPTION(0x2d00, Trap_2d, UnknownException)
  390. STD_EXCEPTION(0x2e00, Trap_2e, UnknownException)
  391. STD_EXCEPTION(0x2f00, Trap_2f, UnknownException)
  392. .globl _end_of_vectors
  393. _end_of_vectors:
  394. . = 0x3000
  395. /*
  396. * This code finishes saving the registers to the exception frame
  397. * and jumps to the appropriate handler for the exception.
  398. * Register r21 is pointer into trap frame, r1 has new stack pointer.
  399. */
  400. .globl transfer_to_handler
  401. transfer_to_handler:
  402. stw r22,_NIP(r21)
  403. lis r22,MSR_POW@h
  404. andc r23,r23,r22
  405. stw r23,_MSR(r21)
  406. SAVE_GPR(7, r21)
  407. SAVE_4GPRS(8, r21)
  408. SAVE_8GPRS(12, r21)
  409. SAVE_8GPRS(24, r21)
  410. mflr r23
  411. andi. r24,r23,0x3f00 /* get vector offset */
  412. stw r24,TRAP(r21)
  413. li r22,0
  414. stw r22,RESULT(r21)
  415. lwz r24,0(r23) /* virtual address of handler */
  416. lwz r23,4(r23) /* where to go when done */
  417. mtspr SRR0,r24
  418. mtspr SRR1,r20
  419. mtlr r23
  420. SYNC
  421. rfi /* jump to handler, enable MMU */
  422. int_return:
  423. mfmsr r28 /* Disable interrupts */
  424. li r4,0
  425. ori r4,r4,MSR_EE
  426. andc r28,r28,r4
  427. SYNC /* Some chip revs need this... */
  428. mtmsr r28
  429. SYNC
  430. lwz r2,_CTR(r1)
  431. lwz r0,_LINK(r1)
  432. mtctr r2
  433. mtlr r0
  434. lwz r2,_XER(r1)
  435. lwz r0,_CCR(r1)
  436. mtspr XER,r2
  437. mtcrf 0xFF,r0
  438. REST_10GPRS(3, r1)
  439. REST_10GPRS(13, r1)
  440. REST_8GPRS(23, r1)
  441. REST_GPR(31, r1)
  442. lwz r2,_NIP(r1) /* Restore environment */
  443. lwz r0,_MSR(r1)
  444. mtspr SRR0,r2
  445. mtspr SRR1,r0
  446. lwz r0,GPR0(r1)
  447. lwz r2,GPR2(r1)
  448. lwz r1,GPR1(r1)
  449. SYNC
  450. rfi
  451. #if defined(CONFIG_COGENT)
  452. /*
  453. * This code initialises the MPC8260 processor core
  454. * (conforms to PowerPC 603e spec)
  455. */
  456. .globl cogent_init_8260
  457. cogent_init_8260:
  458. /* Taken from page 14 of CMA282 manual */
  459. /*--------------------------------------------------------------*/
  460. lis r4, (CFG_IMMR+IM_REGBASE)@h
  461. lis r3, CFG_IMMR@h
  462. stw r3, IM_IMMR@l(r4)
  463. lwz r3, IM_IMMR@l(r4)
  464. stw r3, 0(r0)
  465. lis r3, CFG_SYPCR@h
  466. ori r3, r3, CFG_SYPCR@l
  467. stw r3, IM_SYPCR@l(r4)
  468. lwz r3, IM_SYPCR@l(r4)
  469. stw r3, 4(r0)
  470. lis r3, CFG_SCCR@h
  471. ori r3, r3, CFG_SCCR@l
  472. stw r3, IM_SCCR@l(r4)
  473. lwz r3, IM_SCCR@l(r4)
  474. stw r3, 8(r0)
  475. /* the rest of this was disassembled from the */
  476. /* EPROM code that came with my CMA282 CPU module */
  477. /*--------------------------------------------------------------*/
  478. lis r1, 0x1234
  479. ori r1, r1, 0x5678
  480. stw r1, 0x20(r0)
  481. lwz r1, 0x20(r0)
  482. stw r1, 0x24(r0)
  483. lwz r1, 0x24(r0)
  484. lis r3, 0x0e80
  485. ori r3, r3, 0
  486. stw r1, 4(r3)
  487. lwz r1, 4(r3)
  488. /* Done! */
  489. /*--------------------------------------------------------------*/
  490. blr
  491. #endif /* CONFIG_COGENT */
  492. /*
  493. * This code initialises the MPC8260 processor core
  494. * (conforms to PowerPC 603e spec)
  495. * Note: expects original MSR contents to be in r5.
  496. */
  497. .globl init_8260_core
  498. init_8260_core:
  499. /* Initialize machine status; enable machine check interrupt */
  500. /*--------------------------------------------------------------*/
  501. li r3, MSR_KERNEL /* Set ME and RI flags */
  502. rlwimi r3, r5, 0, 25, 25 /* preserve IP bit set by HRCW */
  503. #ifdef DEBUG
  504. rlwimi r3, r5, 0, 21, 22 /* debugger might set SE & BE bits */
  505. #endif
  506. SYNC /* Some chip revs need this... */
  507. mtmsr r3
  508. SYNC
  509. mtspr SRR1, r3 /* Make SRR1 match MSR */
  510. /* Initialise the SYPCR early, and reset the watchdog (if req) */
  511. /*--------------------------------------------------------------*/
  512. lis r3, (CFG_IMMR+IM_REGBASE)@h
  513. #if !defined(CONFIG_COGENT)
  514. lis r4, CFG_SYPCR@h
  515. ori r4, r4, CFG_SYPCR@l
  516. stw r4, IM_SYPCR@l(r3)
  517. #endif /* !CONFIG_COGENT */
  518. #if defined(CONFIG_WATCHDOG)
  519. li r4, 21868 /* = 0x556c */
  520. sth r4, IM_SWSR@l(r3)
  521. li r4, -21959 /* = 0xaa39 */
  522. sth r4, IM_SWSR@l(r3)
  523. #endif /* CONFIG_WATCHDOG */
  524. /* Initialize the Hardware Implementation-dependent Registers */
  525. /* HID0 also contains cache control */
  526. /*--------------------------------------------------------------*/
  527. lis r3, CFG_HID0_INIT@h
  528. ori r3, r3, CFG_HID0_INIT@l
  529. SYNC
  530. mtspr HID0, r3
  531. lis r3, CFG_HID0_FINAL@h
  532. ori r3, r3, CFG_HID0_FINAL@l
  533. SYNC
  534. mtspr HID0, r3
  535. lis r3, CFG_HID2@h
  536. ori r3, r3, CFG_HID2@l
  537. mtspr HID2, r3
  538. /* clear all BAT's */
  539. /*--------------------------------------------------------------*/
  540. li r0, 0
  541. mtspr DBAT0U, r0
  542. mtspr DBAT0L, r0
  543. mtspr DBAT1U, r0
  544. mtspr DBAT1L, r0
  545. mtspr DBAT2U, r0
  546. mtspr DBAT2L, r0
  547. mtspr DBAT3U, r0
  548. mtspr DBAT3L, r0
  549. mtspr IBAT0U, r0
  550. mtspr IBAT0L, r0
  551. mtspr IBAT1U, r0
  552. mtspr IBAT1L, r0
  553. mtspr IBAT2U, r0
  554. mtspr IBAT2L, r0
  555. mtspr IBAT3U, r0
  556. mtspr IBAT3L, r0
  557. SYNC
  558. /* invalidate all tlb's */
  559. /* */
  560. /* From the 603e User Manual: "The 603e provides the ability to */
  561. /* invalidate a TLB entry. The TLB Invalidate Entry (tlbie) */
  562. /* instruction invalidates the TLB entry indexed by the EA, and */
  563. /* operates on both the instruction and data TLBs simultaneously*/
  564. /* invalidating four TLB entries (both sets in each TLB). The */
  565. /* index corresponds to bits 15-19 of the EA. To invalidate all */
  566. /* entries within both TLBs, 32 tlbie instructions should be */
  567. /* issued, incrementing this field by one each time." */
  568. /* */
  569. /* "Note that the tlbia instruction is not implemented on the */
  570. /* 603e." */
  571. /* */
  572. /* bits 15-19 correspond to addresses 0x00000000 to 0x0001F000 */
  573. /* incrementing by 0x1000 each time. The code below is sort of */
  574. /* based on code in "flush_tlbs" from arch/ppc/kernel/head.S */
  575. /* */
  576. /*--------------------------------------------------------------*/
  577. li r3, 32
  578. mtctr r3
  579. li r3, 0
  580. 1: tlbie r3
  581. addi r3, r3, 0x1000
  582. bdnz 1b
  583. SYNC
  584. /* Done! */
  585. /*--------------------------------------------------------------*/
  586. blr
  587. #ifdef DEBUG
  588. /*
  589. * initialise things related to debugging.
  590. *
  591. * must be called after the global offset table (GOT) is initialised
  592. * (GET_GOT) and after cpu_init_f() has executed.
  593. */
  594. .globl init_debug
  595. init_debug:
  596. lis r3, (CFG_IMMR+IM_REGBASE)@h
  597. /* Quick and dirty hack to enable the RAM and copy the */
  598. /* vectors so that we can take exceptions. */
  599. /*--------------------------------------------------------------*/
  600. /* write Memory Refresh Prescaler */
  601. li r4, CFG_MPTPR
  602. sth r4, IM_MPTPR@l(r3)
  603. /* write 60x Refresh Timer */
  604. li r4, CFG_PSRT
  605. stb r4, IM_PSRT@l(r3)
  606. /* init the 60x SDRAM Mode Register */
  607. lis r4, (CFG_PSDMR|PSDMR_OP_NORM)@h
  608. ori r4, r4, (CFG_PSDMR|PSDMR_OP_NORM)@l
  609. stw r4, IM_PSDMR@l(r3)
  610. /* write Precharge All Banks command */
  611. lis r4, (CFG_PSDMR|PSDMR_OP_PREA)@h
  612. ori r4, r4, (CFG_PSDMR|PSDMR_OP_PREA)@l
  613. stw r4, IM_PSDMR@l(r3)
  614. stb r0, 0(0)
  615. /* write eight CBR Refresh commands */
  616. lis r4, (CFG_PSDMR|PSDMR_OP_CBRR)@h
  617. ori r4, r4, (CFG_PSDMR|PSDMR_OP_CBRR)@l
  618. stw r4, IM_PSDMR@l(r3)
  619. stb r0, 0(0)
  620. stb r0, 0(0)
  621. stb r0, 0(0)
  622. stb r0, 0(0)
  623. stb r0, 0(0)
  624. stb r0, 0(0)
  625. stb r0, 0(0)
  626. stb r0, 0(0)
  627. /* write Mode Register Write command */
  628. lis r4, (CFG_PSDMR|PSDMR_OP_MRW)@h
  629. ori r4, r4, (CFG_PSDMR|PSDMR_OP_MRW)@l
  630. stw r4, IM_PSDMR@l(r3)
  631. stb r0, 0(0)
  632. /* write Normal Operation command and enable Refresh */
  633. lis r4, (CFG_PSDMR|PSDMR_OP_NORM|PSDMR_RFEN)@h
  634. ori r4, r4, (CFG_PSDMR|PSDMR_OP_NORM|PSDMR_RFEN)@l
  635. stw r4, IM_PSDMR@l(r3)
  636. stb r0, 0(0)
  637. /* RAM should now be operational */
  638. #define VEC_WRD_CNT ((_end_of_vectors - _start + EXC_OFF_SYS_RESET) / 4)
  639. lwz r3, GOT(_end_of_vectors)
  640. rlwinm r4, r3, 0, 18, 31 /* _end_of_vectors & 0x3FFF */
  641. lis r5, VEC_WRD_CNT@h
  642. ori r5, r5, VEC_WRD_CNT@l
  643. mtctr r5
  644. 1:
  645. lwzu r5, -4(r3)
  646. stwu r5, -4(r4)
  647. bdnz 1b
  648. /* Load the Instruction Address Breakpoint Register (IABR). */
  649. /* */
  650. /* The address to load is stored in the first word of dual port */
  651. /* ram and should be preserved while the power is on, so you */
  652. /* can plug addresses into that location then reset the cpu and */
  653. /* this code will load that address into the IABR after the */
  654. /* reset. */
  655. /* */
  656. /* When the program counter matches the contents of the IABR, */
  657. /* an exception is generated (before the instruction at that */
  658. /* location completes). The vector for this exception is 0x1300 */
  659. /*--------------------------------------------------------------*/
  660. lis r3, CFG_IMMR@h
  661. lwz r3, 0(r3)
  662. mtspr IABR, r3
  663. /* Set the entire dual port RAM (where the initial stack */
  664. /* resides) to a known value - makes it easier to see where */
  665. /* the stack has been written */
  666. /*--------------------------------------------------------------*/
  667. lis r3, (CFG_IMMR + CFG_INIT_SP_OFFSET)@h
  668. ori r3, r3, (CFG_IMMR + CFG_INIT_SP_OFFSET)@l
  669. li r4, ((CFG_INIT_SP_OFFSET - 4) / 4)
  670. mtctr r4
  671. lis r4, 0xdeadbeaf@h
  672. ori r4, r4, 0xdeadbeaf@l
  673. 1:
  674. stwu r4, -4(r3)
  675. bdnz 1b
  676. /* Done! */
  677. /*--------------------------------------------------------------*/
  678. blr
  679. #endif
  680. /* Cache functions.
  681. *
  682. * Note: requires that all cache bits in
  683. * HID0 are in the low half word.
  684. */
  685. .globl icache_enable
  686. icache_enable:
  687. mfspr r3, HID0
  688. ori r3, r3, HID0_ICE
  689. lis r4, 0
  690. ori r4, r4, HID0_ILOCK
  691. andc r3, r3, r4
  692. ori r4, r3, HID0_ICFI
  693. isync
  694. mtspr HID0, r4 /* sets enable and invalidate, clears lock */
  695. isync
  696. mtspr HID0, r3 /* clears invalidate */
  697. blr
  698. .globl icache_disable
  699. icache_disable:
  700. mfspr r3, HID0
  701. lis r4, 0
  702. ori r4, r4, HID0_ICE|HID0_ILOCK
  703. andc r3, r3, r4
  704. ori r4, r3, HID0_ICFI
  705. isync
  706. mtspr HID0, r4 /* sets invalidate, clears enable and lock */
  707. isync
  708. mtspr HID0, r3 /* clears invalidate */
  709. blr
  710. .globl icache_status
  711. icache_status:
  712. mfspr r3, HID0
  713. rlwinm r3, r3, HID0_ICE_BITPOS + 1, 31, 31
  714. blr
  715. .globl dcache_enable
  716. dcache_enable:
  717. mfspr r3, HID0
  718. ori r3, r3, HID0_DCE
  719. lis r4, 0
  720. ori r4, r4, HID0_DLOCK
  721. andc r3, r3, r4
  722. ori r4, r3, HID0_DCI
  723. sync
  724. mtspr HID0, r4 /* sets enable and invalidate, clears lock */
  725. sync
  726. mtspr HID0, r3 /* clears invalidate */
  727. blr
  728. .globl dcache_disable
  729. dcache_disable:
  730. mfspr r3, HID0
  731. lis r4, 0
  732. ori r4, r4, HID0_DCE|HID0_DLOCK
  733. andc r3, r3, r4
  734. ori r4, r3, HID0_DCI
  735. sync
  736. mtspr HID0, r4 /* sets invalidate, clears enable and lock */
  737. sync
  738. mtspr HID0, r3 /* clears invalidate */
  739. blr
  740. .globl dcache_status
  741. dcache_status:
  742. mfspr r3, HID0
  743. rlwinm r3, r3, HID0_DCE_BITPOS + 1, 31, 31
  744. blr
  745. .globl get_pvr
  746. get_pvr:
  747. mfspr r3, PVR
  748. blr
  749. /*------------------------------------------------------------------------------*/
  750. /*
  751. * void relocate_code (addr_sp, gd, addr_moni)
  752. *
  753. * This "function" does not return, instead it continues in RAM
  754. * after relocating the monitor code.
  755. *
  756. * r3 = dest
  757. * r4 = src
  758. * r5 = length in bytes
  759. * r6 = cachelinesize
  760. */
  761. .globl relocate_code
  762. relocate_code:
  763. mr r1, r3 /* Set new stack pointer */
  764. mr r9, r4 /* Save copy of Global Data pointer */
  765. mr r10, r5 /* Save copy of Destination Address */
  766. mr r3, r5 /* Destination Address */
  767. lis r4, CFG_MONITOR_BASE@h /* Source Address */
  768. ori r4, r4, CFG_MONITOR_BASE@l
  769. lwz r5, GOT(__init_end)
  770. sub r5, r5, r4
  771. li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
  772. /*
  773. * Fix GOT pointer:
  774. *
  775. * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
  776. *
  777. * Offset:
  778. */
  779. sub r15, r10, r4
  780. /* First our own GOT */
  781. add r14, r14, r15
  782. /* then the one used by the C code */
  783. add r30, r30, r15
  784. /*
  785. * Now relocate code
  786. */
  787. cmplw cr1,r3,r4
  788. addi r0,r5,3
  789. srwi. r0,r0,2
  790. beq cr1,4f /* In place copy is not necessary */
  791. beq 7f /* Protect against 0 count */
  792. mtctr r0
  793. bge cr1,2f
  794. la r8,-4(r4)
  795. la r7,-4(r3)
  796. 1: lwzu r0,4(r8)
  797. stwu r0,4(r7)
  798. bdnz 1b
  799. b 4f
  800. 2: slwi r0,r0,2
  801. add r8,r4,r0
  802. add r7,r3,r0
  803. 3: lwzu r0,-4(r8)
  804. stwu r0,-4(r7)
  805. bdnz 3b
  806. /*
  807. * Now flush the cache: note that we must start from a cache aligned
  808. * address. Otherwise we might miss one cache line.
  809. */
  810. 4: cmpwi r6,0
  811. add r5,r3,r5
  812. beq 7f /* Always flush prefetch queue in any case */
  813. subi r0,r6,1
  814. andc r3,r3,r0
  815. mfspr r7,HID0 /* don't do dcbst if dcache is disabled */
  816. rlwinm r7,r7,HID0_DCE_BITPOS+1,31,31
  817. cmpwi r7,0
  818. beq 9f
  819. mr r4,r3
  820. 5: dcbst 0,r4
  821. add r4,r4,r6
  822. cmplw r4,r5
  823. blt 5b
  824. sync /* Wait for all dcbst to complete on bus */
  825. 9: mfspr r7,HID0 /* don't do icbi if icache is disabled */
  826. rlwinm r7,r7,HID0_ICE_BITPOS+1,31,31
  827. cmpwi r7,0
  828. beq 7f
  829. mr r4,r3
  830. 6: icbi 0,r4
  831. add r4,r4,r6
  832. cmplw r4,r5
  833. blt 6b
  834. 7: sync /* Wait for all icbi to complete on bus */
  835. isync
  836. /*
  837. * We are done. Do not return, instead branch to second part of board
  838. * initialization, now running from RAM.
  839. */
  840. addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
  841. mtlr r0
  842. blr
  843. in_ram:
  844. /*
  845. * Relocation Function, r14 point to got2+0x8000
  846. *
  847. * Adjust got2 pointers, no need to check for 0, this code
  848. * already puts a few entries in the table.
  849. */
  850. li r0,__got2_entries@sectoff@l
  851. la r3,GOT(_GOT2_TABLE_)
  852. lwz r11,GOT(_GOT2_TABLE_)
  853. mtctr r0
  854. sub r11,r3,r11
  855. addi r3,r3,-4
  856. 1: lwzu r0,4(r3)
  857. add r0,r0,r11
  858. stw r0,0(r3)
  859. bdnz 1b
  860. /*
  861. * Now adjust the fixups and the pointers to the fixups
  862. * in case we need to move ourselves again.
  863. */
  864. 2: li r0,__fixup_entries@sectoff@l
  865. lwz r3,GOT(_FIXUP_TABLE_)
  866. cmpwi r0,0
  867. mtctr r0
  868. addi r3,r3,-4
  869. beq 4f
  870. 3: lwzu r4,4(r3)
  871. lwzux r0,r4,r11
  872. add r0,r0,r11
  873. stw r10,0(r3)
  874. stw r0,0(r4)
  875. bdnz 3b
  876. 4:
  877. clear_bss:
  878. /*
  879. * Now clear BSS segment
  880. */
  881. lwz r3,GOT(__bss_start)
  882. #if defined(CONFIG_HYMOD)
  883. /*
  884. * For HYMOD - the environment is the very last item in flash.
  885. * The real .bss stops just before environment starts, so only
  886. * clear up to that point.
  887. *
  888. * taken from mods for FADS board
  889. */
  890. lwz r4,GOT(environment)
  891. #else
  892. lwz r4,GOT(_end)
  893. #endif
  894. cmplw 0, r3, r4
  895. beq 6f
  896. li r0, 0
  897. 5:
  898. stw r0, 0(r3)
  899. addi r3, r3, 4
  900. cmplw 0, r3, r4
  901. bne 5b
  902. 6:
  903. mr r3, r9 /* Global Data pointer */
  904. mr r4, r10 /* Destination Address */
  905. bl board_init_r
  906. /*
  907. * Copy exception vector code to low memory
  908. *
  909. * r3: dest_addr
  910. * r7: source address, r8: end address, r9: target address
  911. */
  912. .globl trap_init
  913. trap_init:
  914. lwz r7, GOT(_start)
  915. lwz r8, GOT(_end_of_vectors)
  916. li r9, 0x100 /* reset vector always at 0x100 */
  917. cmplw 0, r7, r8
  918. bgelr /* return if r7>=r8 - just in case */
  919. mflr r4 /* save link register */
  920. 1:
  921. lwz r0, 0(r7)
  922. stw r0, 0(r9)
  923. addi r7, r7, 4
  924. addi r9, r9, 4
  925. cmplw 0, r7, r8
  926. bne 1b
  927. /*
  928. * relocate `hdlr' and `int_return' entries
  929. */
  930. li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
  931. li r8, Alignment - _start + EXC_OFF_SYS_RESET
  932. 2:
  933. bl trap_reloc
  934. addi r7, r7, 0x100 /* next exception vector */
  935. cmplw 0, r7, r8
  936. blt 2b
  937. li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
  938. bl trap_reloc
  939. li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
  940. bl trap_reloc
  941. li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
  942. li r8, SystemCall - _start + EXC_OFF_SYS_RESET
  943. 3:
  944. bl trap_reloc
  945. addi r7, r7, 0x100 /* next exception vector */
  946. cmplw 0, r7, r8
  947. blt 3b
  948. li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
  949. li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
  950. 4:
  951. bl trap_reloc
  952. addi r7, r7, 0x100 /* next exception vector */
  953. cmplw 0, r7, r8
  954. blt 4b
  955. mfmsr r3 /* now that the vectors have */
  956. lis r7, MSR_IP@h /* relocated into low memory */
  957. ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */
  958. andc r3, r3, r7 /* (if it was on) */
  959. SYNC /* Some chip revs need this... */
  960. mtmsr r3
  961. SYNC
  962. mtlr r4 /* restore link register */
  963. blr
  964. /*
  965. * Function: relocate entries for one exception vector
  966. */
  967. trap_reloc:
  968. lwz r0, 0(r7) /* hdlr ... */
  969. add r0, r0, r3 /* ... += dest_addr */
  970. stw r0, 0(r7)
  971. lwz r0, 4(r7) /* int_return ... */
  972. add r0, r0, r3 /* ... += dest_addr */
  973. stw r0, 4(r7)
  974. blr