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@@ -4,11 +4,6 @@
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compatible = "nvidia,tegra30";
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interrupt-parent = <&intc>;
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- pmc {
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- compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc";
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- reg = <0x7000e400 0x400>;
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- };
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-
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intc: interrupt-controller {
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compatible = "arm,cortex-a9-gic";
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interrupt-controller;
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@@ -17,14 +12,6 @@
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0x50040100 0x0100>;
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};
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- pmu {
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- compatible = "arm,cortex-a9-pmu";
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- interrupts = <0 144 0x04
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- 0 145 0x04
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- 0 146 0x04
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- 0 147 0x04>;
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- };
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-
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apbdma: dma {
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compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
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reg = <0x6000a000 0x1400>;
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@@ -62,44 +49,9 @@
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0 143 0x04>;
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};
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- i2c@7000c000 {
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- #address-cells = <1>;
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- #size-cells = <0>;
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- compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
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- reg = <0x7000c000 0x100>;
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- interrupts = <0 38 0x04>;
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- };
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-
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- i2c@7000c400 {
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- #address-cells = <1>;
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- #size-cells = <0>;
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- compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
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- reg = <0x7000c400 0x100>;
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- interrupts = <0 84 0x04>;
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- };
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-
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- i2c@7000c500 {
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- #address-cells = <1>;
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- #size-cells = <0>;
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- compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
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- reg = <0x7000c500 0x100>;
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- interrupts = <0 92 0x04>;
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- };
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-
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- i2c@7000c700 {
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- #address-cells = <1>;
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- #size-cells = <0>;
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- compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
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- reg = <0x7000c700 0x100>;
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- interrupts = <0 120 0x04>;
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- };
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-
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- i2c@7000d000 {
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- #address-cells = <1>;
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- #size-cells = <0>;
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- compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
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- reg = <0x7000d000 0x100>;
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- interrupts = <0 53 0x04>;
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+ ahb: ahb {
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+ compatible = "nvidia,tegra30-ahb";
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+ reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */
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};
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gpio: gpio {
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@@ -119,6 +71,12 @@
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interrupt-controller;
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};
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+ pinmux: pinmux {
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+ compatible = "nvidia,tegra30-pinmux";
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+ reg = <0x70000868 0xd0 /* Pad control registers */
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+ 0x70003000 0x3e0>; /* Mux registers */
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+ };
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+
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serial@70006000 {
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compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
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reg = <0x70006000 0x40>;
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@@ -154,34 +112,68 @@
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interrupts = <0 91 0x04>;
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};
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- sdhci@78000000 {
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- compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
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- reg = <0x78000000 0x200>;
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- interrupts = <0 14 0x04>;
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+ i2c@7000c000 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
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+ reg = <0x7000c000 0x100>;
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+ interrupts = <0 38 0x04>;
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};
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- sdhci@78000200 {
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- compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
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- reg = <0x78000200 0x200>;
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- interrupts = <0 15 0x04>;
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+ i2c@7000c400 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
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+ reg = <0x7000c400 0x100>;
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+ interrupts = <0 84 0x04>;
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};
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- sdhci@78000400 {
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- compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
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- reg = <0x78000400 0x200>;
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- interrupts = <0 19 0x04>;
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+ i2c@7000c500 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
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+ reg = <0x7000c500 0x100>;
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+ interrupts = <0 92 0x04>;
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};
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- sdhci@78000600 {
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- compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
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- reg = <0x78000600 0x200>;
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- interrupts = <0 31 0x04>;
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+ i2c@7000c700 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
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+ reg = <0x7000c700 0x100>;
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+ interrupts = <0 120 0x04>;
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};
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- pinmux: pinmux {
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- compatible = "nvidia,tegra30-pinmux";
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- reg = <0x70000868 0xd0 /* Pad control registers */
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- 0x70003000 0x3e0>; /* Mux registers */
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+ i2c@7000d000 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
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+ reg = <0x7000d000 0x100>;
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+ interrupts = <0 53 0x04>;
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+ };
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+
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+ pmc {
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+ compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc";
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+ reg = <0x7000e400 0x400>;
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+ };
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+
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+ mc {
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+ compatible = "nvidia,tegra30-mc";
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+ reg = <0x7000f000 0x010
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+ 0x7000f03c 0x1b4
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+ 0x7000f200 0x028
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+ 0x7000f284 0x17c>;
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+ interrupts = <0 77 0x04>;
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+ };
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+
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+ smmu {
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+ compatible = "nvidia,tegra30-smmu";
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+ reg = <0x7000f010 0x02c
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+ 0x7000f1f0 0x010
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+ 0x7000f228 0x05c>;
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+ nvidia,#asids = <4>; /* # of ASIDs */
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+ dma-window = <0 0x40000000>; /* IOVA start & length */
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+ nvidia,ahb = <&ahb>;
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};
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ahub {
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@@ -226,27 +218,35 @@
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};
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};
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- ahb: ahb {
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- compatible = "nvidia,tegra30-ahb";
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- reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */
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+ sdhci@78000000 {
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+ compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
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+ reg = <0x78000000 0x200>;
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+ interrupts = <0 14 0x04>;
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};
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- mc {
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- compatible = "nvidia,tegra30-mc";
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- reg = <0x7000f000 0x010
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- 0x7000f03c 0x1b4
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- 0x7000f200 0x028
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- 0x7000f284 0x17c>;
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- interrupts = <0 77 0x04>;
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+ sdhci@78000200 {
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+ compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
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+ reg = <0x78000200 0x200>;
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+ interrupts = <0 15 0x04>;
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};
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- smmu {
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- compatible = "nvidia,tegra30-smmu";
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- reg = <0x7000f010 0x02c
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- 0x7000f1f0 0x010
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- 0x7000f228 0x05c>;
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- nvidia,#asids = <4>; /* # of ASIDs */
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- dma-window = <0 0x40000000>; /* IOVA start & length */
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- nvidia,ahb = <&ahb>;
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+ sdhci@78000400 {
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+ compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
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+ reg = <0x78000400 0x200>;
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+ interrupts = <0 19 0x04>;
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+ };
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+
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+ sdhci@78000600 {
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+ compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
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+ reg = <0x78000600 0x200>;
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+ interrupts = <0 31 0x04>;
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+ };
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+
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+ pmu {
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+ compatible = "arm,cortex-a9-pmu";
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+ interrupts = <0 144 0x04
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+ 0 145 0x04
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+ 0 146 0x04
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+ 0 147 0x04>;
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};
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};
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