tegra20.dtsi 4.6 KB

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  1. /include/ "skeleton.dtsi"
  2. / {
  3. compatible = "nvidia,tegra20";
  4. interrupt-parent = <&intc>;
  5. intc: interrupt-controller {
  6. compatible = "arm,cortex-a9-gic";
  7. interrupt-controller;
  8. #interrupt-cells = <3>;
  9. reg = <0x50041000 0x1000
  10. 0x50040100 0x0100>;
  11. };
  12. apbdma: dma {
  13. compatible = "nvidia,tegra20-apbdma";
  14. reg = <0x6000a000 0x1200>;
  15. interrupts = <0 104 0x04
  16. 0 105 0x04
  17. 0 106 0x04
  18. 0 107 0x04
  19. 0 108 0x04
  20. 0 109 0x04
  21. 0 110 0x04
  22. 0 111 0x04
  23. 0 112 0x04
  24. 0 113 0x04
  25. 0 114 0x04
  26. 0 115 0x04
  27. 0 116 0x04
  28. 0 117 0x04
  29. 0 118 0x04
  30. 0 119 0x04>;
  31. };
  32. ahb {
  33. compatible = "nvidia,tegra20-ahb";
  34. reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
  35. };
  36. gpio: gpio {
  37. compatible = "nvidia,tegra20-gpio";
  38. reg = <0x6000d000 0x1000>;
  39. interrupts = <0 32 0x04
  40. 0 33 0x04
  41. 0 34 0x04
  42. 0 35 0x04
  43. 0 55 0x04
  44. 0 87 0x04
  45. 0 89 0x04>;
  46. #gpio-cells = <2>;
  47. gpio-controller;
  48. #interrupt-cells = <2>;
  49. interrupt-controller;
  50. };
  51. pinmux: pinmux {
  52. compatible = "nvidia,tegra20-pinmux";
  53. reg = <0x70000014 0x10 /* Tri-state registers */
  54. 0x70000080 0x20 /* Mux registers */
  55. 0x700000a0 0x14 /* Pull-up/down registers */
  56. 0x70000868 0xa8>; /* Pad control registers */
  57. };
  58. das {
  59. compatible = "nvidia,tegra20-das";
  60. reg = <0x70000c00 0x80>;
  61. };
  62. tegra_i2s1: i2s@70002800 {
  63. compatible = "nvidia,tegra20-i2s";
  64. reg = <0x70002800 0x200>;
  65. interrupts = <0 13 0x04>;
  66. nvidia,dma-request-selector = <&apbdma 2>;
  67. };
  68. tegra_i2s2: i2s@70002a00 {
  69. compatible = "nvidia,tegra20-i2s";
  70. reg = <0x70002a00 0x200>;
  71. interrupts = <0 3 0x04>;
  72. nvidia,dma-request-selector = <&apbdma 1>;
  73. };
  74. serial@70006000 {
  75. compatible = "nvidia,tegra20-uart";
  76. reg = <0x70006000 0x40>;
  77. reg-shift = <2>;
  78. interrupts = <0 36 0x04>;
  79. };
  80. serial@70006040 {
  81. compatible = "nvidia,tegra20-uart";
  82. reg = <0x70006040 0x40>;
  83. reg-shift = <2>;
  84. interrupts = <0 37 0x04>;
  85. };
  86. serial@70006200 {
  87. compatible = "nvidia,tegra20-uart";
  88. reg = <0x70006200 0x100>;
  89. reg-shift = <2>;
  90. interrupts = <0 46 0x04>;
  91. };
  92. serial@70006300 {
  93. compatible = "nvidia,tegra20-uart";
  94. reg = <0x70006300 0x100>;
  95. reg-shift = <2>;
  96. interrupts = <0 90 0x04>;
  97. };
  98. serial@70006400 {
  99. compatible = "nvidia,tegra20-uart";
  100. reg = <0x70006400 0x100>;
  101. reg-shift = <2>;
  102. interrupts = <0 91 0x04>;
  103. };
  104. i2c@7000c000 {
  105. #address-cells = <1>;
  106. #size-cells = <0>;
  107. compatible = "nvidia,tegra20-i2c";
  108. reg = <0x7000c000 0x100>;
  109. interrupts = <0 38 0x04>;
  110. };
  111. i2c@7000c400 {
  112. #address-cells = <1>;
  113. #size-cells = <0>;
  114. compatible = "nvidia,tegra20-i2c";
  115. reg = <0x7000c400 0x100>;
  116. interrupts = <0 84 0x04>;
  117. };
  118. i2c@7000c500 {
  119. #address-cells = <1>;
  120. #size-cells = <0>;
  121. compatible = "nvidia,tegra20-i2c";
  122. reg = <0x7000c500 0x100>;
  123. interrupts = <0 92 0x04>;
  124. };
  125. i2c@7000d000 {
  126. #address-cells = <1>;
  127. #size-cells = <0>;
  128. compatible = "nvidia,tegra20-i2c-dvc";
  129. reg = <0x7000d000 0x200>;
  130. interrupts = <0 53 0x04>;
  131. };
  132. pmc {
  133. compatible = "nvidia,tegra20-pmc";
  134. reg = <0x7000e400 0x400>;
  135. };
  136. mc {
  137. compatible = "nvidia,tegra20-mc";
  138. reg = <0x7000f000 0x024
  139. 0x7000f03c 0x3c4>;
  140. interrupts = <0 77 0x04>;
  141. };
  142. gart {
  143. compatible = "nvidia,tegra20-gart";
  144. reg = <0x7000f024 0x00000018 /* controller registers */
  145. 0x58000000 0x02000000>; /* GART aperture */
  146. };
  147. emc {
  148. #address-cells = <1>;
  149. #size-cells = <0>;
  150. compatible = "nvidia,tegra20-emc";
  151. reg = <0x7000f400 0x200>;
  152. };
  153. usb@c5000000 {
  154. compatible = "nvidia,tegra20-ehci", "usb-ehci";
  155. reg = <0xc5000000 0x4000>;
  156. interrupts = <0 20 0x04>;
  157. phy_type = "utmi";
  158. nvidia,has-legacy-mode;
  159. };
  160. usb@c5004000 {
  161. compatible = "nvidia,tegra20-ehci", "usb-ehci";
  162. reg = <0xc5004000 0x4000>;
  163. interrupts = <0 21 0x04>;
  164. phy_type = "ulpi";
  165. };
  166. usb@c5008000 {
  167. compatible = "nvidia,tegra20-ehci", "usb-ehci";
  168. reg = <0xc5008000 0x4000>;
  169. interrupts = <0 97 0x04>;
  170. phy_type = "utmi";
  171. };
  172. sdhci@c8000000 {
  173. compatible = "nvidia,tegra20-sdhci";
  174. reg = <0xc8000000 0x200>;
  175. interrupts = <0 14 0x04>;
  176. };
  177. sdhci@c8000200 {
  178. compatible = "nvidia,tegra20-sdhci";
  179. reg = <0xc8000200 0x200>;
  180. interrupts = <0 15 0x04>;
  181. };
  182. sdhci@c8000400 {
  183. compatible = "nvidia,tegra20-sdhci";
  184. reg = <0xc8000400 0x200>;
  185. interrupts = <0 19 0x04>;
  186. };
  187. sdhci@c8000600 {
  188. compatible = "nvidia,tegra20-sdhci";
  189. reg = <0xc8000600 0x200>;
  190. interrupts = <0 31 0x04>;
  191. };
  192. pmu {
  193. compatible = "arm,cortex-a9-pmu";
  194. interrupts = <0 56 0x04
  195. 0 57 0x04>;
  196. };
  197. };