tegra-ventana.dts 7.1 KB

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  1. /dts-v1/;
  2. /include/ "tegra20.dtsi"
  3. / {
  4. model = "NVIDIA Tegra2 Ventana evaluation board";
  5. compatible = "nvidia,ventana", "nvidia,tegra20";
  6. memory {
  7. reg = <0x00000000 0x40000000>;
  8. };
  9. pinmux {
  10. pinctrl-names = "default";
  11. pinctrl-0 = <&state_default>;
  12. state_default: pinmux {
  13. ata {
  14. nvidia,pins = "ata";
  15. nvidia,function = "ide";
  16. };
  17. atb {
  18. nvidia,pins = "atb", "gma", "gme";
  19. nvidia,function = "sdio4";
  20. };
  21. atc {
  22. nvidia,pins = "atc";
  23. nvidia,function = "nand";
  24. };
  25. atd {
  26. nvidia,pins = "atd", "ate", "gmb", "spia",
  27. "spib", "spic";
  28. nvidia,function = "gmi";
  29. };
  30. cdev1 {
  31. nvidia,pins = "cdev1";
  32. nvidia,function = "plla_out";
  33. };
  34. cdev2 {
  35. nvidia,pins = "cdev2";
  36. nvidia,function = "pllp_out4";
  37. };
  38. crtp {
  39. nvidia,pins = "crtp", "lm1";
  40. nvidia,function = "crt";
  41. };
  42. csus {
  43. nvidia,pins = "csus";
  44. nvidia,function = "vi_sensor_clk";
  45. };
  46. dap1 {
  47. nvidia,pins = "dap1";
  48. nvidia,function = "dap1";
  49. };
  50. dap2 {
  51. nvidia,pins = "dap2";
  52. nvidia,function = "dap2";
  53. };
  54. dap3 {
  55. nvidia,pins = "dap3";
  56. nvidia,function = "dap3";
  57. };
  58. dap4 {
  59. nvidia,pins = "dap4";
  60. nvidia,function = "dap4";
  61. };
  62. ddc {
  63. nvidia,pins = "ddc", "owc", "spdi", "spdo",
  64. "uac";
  65. nvidia,function = "rsvd2";
  66. };
  67. dta {
  68. nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
  69. nvidia,function = "vi";
  70. };
  71. dtf {
  72. nvidia,pins = "dtf";
  73. nvidia,function = "i2c3";
  74. };
  75. gmc {
  76. nvidia,pins = "gmc";
  77. nvidia,function = "uartd";
  78. };
  79. gmd {
  80. nvidia,pins = "gmd";
  81. nvidia,function = "sflash";
  82. };
  83. gpu {
  84. nvidia,pins = "gpu";
  85. nvidia,function = "pwm";
  86. };
  87. gpu7 {
  88. nvidia,pins = "gpu7";
  89. nvidia,function = "rtck";
  90. };
  91. gpv {
  92. nvidia,pins = "gpv", "slxa", "slxk";
  93. nvidia,function = "pcie";
  94. };
  95. hdint {
  96. nvidia,pins = "hdint", "pta";
  97. nvidia,function = "hdmi";
  98. };
  99. i2cp {
  100. nvidia,pins = "i2cp";
  101. nvidia,function = "i2cp";
  102. };
  103. irrx {
  104. nvidia,pins = "irrx", "irtx";
  105. nvidia,function = "uartb";
  106. };
  107. kbca {
  108. nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
  109. "kbce", "kbcf";
  110. nvidia,function = "kbc";
  111. };
  112. lcsn {
  113. nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
  114. "lsdi", "lvp0";
  115. nvidia,function = "rsvd4";
  116. };
  117. ld0 {
  118. nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
  119. "ld5", "ld6", "ld7", "ld8", "ld9",
  120. "ld10", "ld11", "ld12", "ld13", "ld14",
  121. "ld15", "ld16", "ld17", "ldi", "lhp0",
  122. "lhp1", "lhp2", "lhs", "lpp", "lpw0",
  123. "lpw2", "lsc0", "lsc1", "lsck", "lsda",
  124. "lspi", "lvp1", "lvs";
  125. nvidia,function = "displaya";
  126. };
  127. pmc {
  128. nvidia,pins = "pmc";
  129. nvidia,function = "pwr_on";
  130. };
  131. rm {
  132. nvidia,pins = "rm";
  133. nvidia,function = "i2c1";
  134. };
  135. sdb {
  136. nvidia,pins = "sdb", "sdc", "sdd", "slxc";
  137. nvidia,function = "sdio3";
  138. };
  139. sdio1 {
  140. nvidia,pins = "sdio1";
  141. nvidia,function = "sdio1";
  142. };
  143. slxd {
  144. nvidia,pins = "slxd";
  145. nvidia,function = "spdif";
  146. };
  147. spid {
  148. nvidia,pins = "spid", "spie", "spif";
  149. nvidia,function = "spi1";
  150. };
  151. spig {
  152. nvidia,pins = "spig", "spih";
  153. nvidia,function = "spi2_alt";
  154. };
  155. uaa {
  156. nvidia,pins = "uaa", "uab", "uda";
  157. nvidia,function = "ulpi";
  158. };
  159. uad {
  160. nvidia,pins = "uad";
  161. nvidia,function = "irda";
  162. };
  163. uca {
  164. nvidia,pins = "uca", "ucb";
  165. nvidia,function = "uartc";
  166. };
  167. conf_ata {
  168. nvidia,pins = "ata", "atb", "atc", "atd",
  169. "cdev1", "cdev2", "dap1", "dap2",
  170. "dap4", "ddc", "dtf", "gma", "gmc",
  171. "gme", "gpu", "gpu7", "i2cp", "irrx",
  172. "irtx", "pta", "rm", "sdc", "sdd",
  173. "slxc", "slxd", "slxk", "spdi", "spdo",
  174. "uac", "uad", "uca", "ucb", "uda";
  175. nvidia,pull = <0>;
  176. nvidia,tristate = <0>;
  177. };
  178. conf_ate {
  179. nvidia,pins = "ate", "csus", "dap3", "gmd",
  180. "gpv", "owc", "spia", "spib", "spic",
  181. "spid", "spie", "spig";
  182. nvidia,pull = <0>;
  183. nvidia,tristate = <1>;
  184. };
  185. conf_ck32 {
  186. nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
  187. "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
  188. nvidia,pull = <0>;
  189. };
  190. conf_crtp {
  191. nvidia,pins = "crtp", "gmb", "slxa", "spih";
  192. nvidia,pull = <2>;
  193. nvidia,tristate = <1>;
  194. };
  195. conf_dta {
  196. nvidia,pins = "dta", "dtb", "dtc", "dtd";
  197. nvidia,pull = <1>;
  198. nvidia,tristate = <0>;
  199. };
  200. conf_dte {
  201. nvidia,pins = "dte", "spif";
  202. nvidia,pull = <1>;
  203. nvidia,tristate = <1>;
  204. };
  205. conf_hdint {
  206. nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
  207. "lpw1", "lsck", "lsda", "lsdi", "lvp0";
  208. nvidia,tristate = <1>;
  209. };
  210. conf_kbca {
  211. nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
  212. "kbce", "kbcf", "sdio1", "uaa", "uab";
  213. nvidia,pull = <2>;
  214. nvidia,tristate = <0>;
  215. };
  216. conf_lc {
  217. nvidia,pins = "lc", "ls";
  218. nvidia,pull = <2>;
  219. };
  220. conf_ld0 {
  221. nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
  222. "ld5", "ld6", "ld7", "ld8", "ld9",
  223. "ld10", "ld11", "ld12", "ld13", "ld14",
  224. "ld15", "ld16", "ld17", "ldi", "lhp0",
  225. "lhp1", "lhp2", "lhs", "lm0", "lpp",
  226. "lpw0", "lpw2", "lsc0", "lsc1", "lspi",
  227. "lvp1", "lvs", "pmc", "sdb";
  228. nvidia,tristate = <0>;
  229. };
  230. conf_ld17_0 {
  231. nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
  232. "ld23_22";
  233. nvidia,pull = <1>;
  234. };
  235. };
  236. };
  237. i2s@70002a00 {
  238. status = "disable";
  239. };
  240. serial@70006000 {
  241. status = "disable";
  242. };
  243. serial@70006040 {
  244. status = "disable";
  245. };
  246. serial@70006200 {
  247. status = "disable";
  248. };
  249. serial@70006300 {
  250. clock-frequency = <216000000>;
  251. };
  252. serial@70006400 {
  253. status = "disable";
  254. };
  255. i2c@7000c000 {
  256. clock-frequency = <400000>;
  257. wm8903: wm8903@1a {
  258. compatible = "wlf,wm8903";
  259. reg = <0x1a>;
  260. interrupt-parent = <&gpio>;
  261. interrupts = <187 0x04>;
  262. gpio-controller;
  263. #gpio-cells = <2>;
  264. micdet-cfg = <0>;
  265. micdet-delay = <100>;
  266. gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
  267. };
  268. /* ALS and proximity sensor */
  269. isl29018@44 {
  270. compatible = "isil,isl29018";
  271. reg = <0x44>;
  272. interrupt-parent = <&gpio>;
  273. interrupts = <202 0x04>; /*gpio PZ2 */
  274. };
  275. };
  276. i2c@7000c400 {
  277. clock-frequency = <400000>;
  278. };
  279. i2c@7000c500 {
  280. clock-frequency = <400000>;
  281. };
  282. i2c@7000d000 {
  283. clock-frequency = <400000>;
  284. };
  285. usb@c5004000 {
  286. nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
  287. };
  288. sdhci@c8000000 {
  289. status = "disable";
  290. };
  291. sdhci@c8000200 {
  292. status = "disable";
  293. };
  294. sdhci@c8000400 {
  295. cd-gpios = <&gpio 69 0>; /* gpio PI5 */
  296. wp-gpios = <&gpio 57 0>; /* gpio PH1 */
  297. power-gpios = <&gpio 70 0>; /* gpio PI6 */
  298. };
  299. sdhci@c8000600 {
  300. support-8bit;
  301. };
  302. sound {
  303. compatible = "nvidia,tegra-audio-wm8903-ventana",
  304. "nvidia,tegra-audio-wm8903";
  305. nvidia,model = "NVIDIA Tegra Ventana";
  306. nvidia,audio-routing =
  307. "Headphone Jack", "HPOUTR",
  308. "Headphone Jack", "HPOUTL",
  309. "Int Spk", "ROP",
  310. "Int Spk", "RON",
  311. "Int Spk", "LOP",
  312. "Int Spk", "LON",
  313. "Mic Jack", "MICBIAS",
  314. "IN1L", "Mic Jack";
  315. nvidia,i2s-controller = <&tegra_i2s1>;
  316. nvidia,audio-codec = <&wm8903>;
  317. nvidia,spkr-en-gpios = <&wm8903 2 0>;
  318. nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
  319. nvidia,int-mic-en-gpios = <&gpio 184 0>; /* gpio PX0 */
  320. nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
  321. };
  322. };