tegra-seaboard.dts 9.7 KB

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  1. /dts-v1/;
  2. /include/ "tegra20.dtsi"
  3. / {
  4. model = "NVIDIA Seaboard";
  5. compatible = "nvidia,seaboard", "nvidia,tegra20";
  6. memory {
  7. reg = <0x00000000 0x40000000>;
  8. };
  9. pinmux {
  10. pinctrl-names = "default";
  11. pinctrl-0 = <&state_default>;
  12. state_default: pinmux {
  13. ata {
  14. nvidia,pins = "ata";
  15. nvidia,function = "ide";
  16. };
  17. atb {
  18. nvidia,pins = "atb", "gma", "gme";
  19. nvidia,function = "sdio4";
  20. };
  21. atc {
  22. nvidia,pins = "atc";
  23. nvidia,function = "nand";
  24. };
  25. atd {
  26. nvidia,pins = "atd", "ate", "gmb", "spia",
  27. "spib", "spic";
  28. nvidia,function = "gmi";
  29. };
  30. cdev1 {
  31. nvidia,pins = "cdev1";
  32. nvidia,function = "plla_out";
  33. };
  34. cdev2 {
  35. nvidia,pins = "cdev2";
  36. nvidia,function = "pllp_out4";
  37. };
  38. crtp {
  39. nvidia,pins = "crtp", "lm1";
  40. nvidia,function = "crt";
  41. };
  42. csus {
  43. nvidia,pins = "csus";
  44. nvidia,function = "vi_sensor_clk";
  45. };
  46. dap1 {
  47. nvidia,pins = "dap1";
  48. nvidia,function = "dap1";
  49. };
  50. dap2 {
  51. nvidia,pins = "dap2";
  52. nvidia,function = "dap2";
  53. };
  54. dap3 {
  55. nvidia,pins = "dap3";
  56. nvidia,function = "dap3";
  57. };
  58. dap4 {
  59. nvidia,pins = "dap4";
  60. nvidia,function = "dap4";
  61. };
  62. ddc {
  63. nvidia,pins = "ddc", "owc", "spdi", "spdo",
  64. "uac";
  65. nvidia,function = "rsvd2";
  66. };
  67. dta {
  68. nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
  69. nvidia,function = "vi";
  70. };
  71. dtf {
  72. nvidia,pins = "dtf";
  73. nvidia,function = "i2c3";
  74. };
  75. gmc {
  76. nvidia,pins = "gmc";
  77. nvidia,function = "uartd";
  78. };
  79. gmd {
  80. nvidia,pins = "gmd";
  81. nvidia,function = "sflash";
  82. };
  83. gpu {
  84. nvidia,pins = "gpu";
  85. nvidia,function = "pwm";
  86. };
  87. gpu7 {
  88. nvidia,pins = "gpu7";
  89. nvidia,function = "rtck";
  90. };
  91. gpv {
  92. nvidia,pins = "gpv", "slxa", "slxk";
  93. nvidia,function = "pcie";
  94. };
  95. hdint {
  96. nvidia,pins = "hdint", "lpw0", "lpw2", "lsc1",
  97. "lsck", "lsda";
  98. nvidia,function = "hdmi";
  99. };
  100. i2cp {
  101. nvidia,pins = "i2cp";
  102. nvidia,function = "i2cp";
  103. };
  104. irrx {
  105. nvidia,pins = "irrx", "irtx";
  106. nvidia,function = "uartb";
  107. };
  108. kbca {
  109. nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
  110. "kbce", "kbcf";
  111. nvidia,function = "kbc";
  112. };
  113. lcsn {
  114. nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
  115. "lsdi", "lvp0";
  116. nvidia,function = "rsvd4";
  117. };
  118. ld0 {
  119. nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
  120. "ld5", "ld6", "ld7", "ld8", "ld9",
  121. "ld10", "ld11", "ld12", "ld13", "ld14",
  122. "ld15", "ld16", "ld17", "ldi", "lhp0",
  123. "lhp1", "lhp2", "lhs", "lpp", "lsc0",
  124. "lspi", "lvp1", "lvs";
  125. nvidia,function = "displaya";
  126. };
  127. pmc {
  128. nvidia,pins = "pmc";
  129. nvidia,function = "pwr_on";
  130. };
  131. pta {
  132. nvidia,pins = "pta";
  133. nvidia,function = "i2c2";
  134. };
  135. rm {
  136. nvidia,pins = "rm";
  137. nvidia,function = "i2c1";
  138. };
  139. sdb {
  140. nvidia,pins = "sdb", "sdc", "sdd";
  141. nvidia,function = "sdio3";
  142. };
  143. sdio1 {
  144. nvidia,pins = "sdio1";
  145. nvidia,function = "sdio1";
  146. };
  147. slxc {
  148. nvidia,pins = "slxc", "slxd";
  149. nvidia,function = "spdif";
  150. };
  151. spid {
  152. nvidia,pins = "spid", "spie", "spif";
  153. nvidia,function = "spi1";
  154. };
  155. spig {
  156. nvidia,pins = "spig", "spih";
  157. nvidia,function = "spi2_alt";
  158. };
  159. uaa {
  160. nvidia,pins = "uaa", "uab", "uda";
  161. nvidia,function = "ulpi";
  162. };
  163. uad {
  164. nvidia,pins = "uad";
  165. nvidia,function = "irda";
  166. };
  167. uca {
  168. nvidia,pins = "uca", "ucb";
  169. nvidia,function = "uartc";
  170. };
  171. conf_ata {
  172. nvidia,pins = "ata", "atb", "atc", "atd",
  173. "cdev1", "cdev2", "dap1", "dap2",
  174. "dap4", "dtf", "gma", "gmc", "gmd",
  175. "gme", "gpu", "gpu7", "i2cp", "irrx",
  176. "irtx", "pta", "rm", "sdc", "sdd",
  177. "slxd", "slxk", "spdi", "spdo", "uac",
  178. "uad", "uca", "ucb", "uda";
  179. nvidia,pull = <0>;
  180. nvidia,tristate = <0>;
  181. };
  182. conf_ate {
  183. nvidia,pins = "ate", "csus", "dap3", "ddc",
  184. "gpv", "owc", "slxc", "spib", "spid",
  185. "spie";
  186. nvidia,pull = <0>;
  187. nvidia,tristate = <1>;
  188. };
  189. conf_ck32 {
  190. nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
  191. "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
  192. nvidia,pull = <0>;
  193. };
  194. conf_crtp {
  195. nvidia,pins = "crtp", "gmb", "slxa", "spia",
  196. "spig", "spih";
  197. nvidia,pull = <2>;
  198. nvidia,tristate = <1>;
  199. };
  200. conf_dta {
  201. nvidia,pins = "dta", "dtb", "dtc", "dtd";
  202. nvidia,pull = <1>;
  203. nvidia,tristate = <0>;
  204. };
  205. conf_dte {
  206. nvidia,pins = "dte", "spif";
  207. nvidia,pull = <1>;
  208. nvidia,tristate = <1>;
  209. };
  210. conf_hdint {
  211. nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
  212. "lpw1", "lsc1", "lsck", "lsda", "lsdi",
  213. "lvp0";
  214. nvidia,tristate = <1>;
  215. };
  216. conf_kbca {
  217. nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
  218. "kbce", "kbcf", "sdio1", "spic", "uaa",
  219. "uab";
  220. nvidia,pull = <2>;
  221. nvidia,tristate = <0>;
  222. };
  223. conf_lc {
  224. nvidia,pins = "lc", "ls";
  225. nvidia,pull = <2>;
  226. };
  227. conf_ld0 {
  228. nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
  229. "ld5", "ld6", "ld7", "ld8", "ld9",
  230. "ld10", "ld11", "ld12", "ld13", "ld14",
  231. "ld15", "ld16", "ld17", "ldi", "lhp0",
  232. "lhp1", "lhp2", "lhs", "lm0", "lpp",
  233. "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
  234. "lvs", "pmc", "sdb";
  235. nvidia,tristate = <0>;
  236. };
  237. conf_ld17_0 {
  238. nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
  239. "ld23_22";
  240. nvidia,pull = <1>;
  241. };
  242. drive_sdio1 {
  243. nvidia,pins = "drive_sdio1";
  244. nvidia,high-speed-mode = <0>;
  245. nvidia,schmitt = <0>;
  246. nvidia,low-power-mode = <3>;
  247. nvidia,pull-down-strength = <31>;
  248. nvidia,pull-up-strength = <31>;
  249. nvidia,slew-rate-rising = <3>;
  250. nvidia,slew-rate-falling = <3>;
  251. };
  252. };
  253. };
  254. i2s@70002a00 {
  255. status = "disable";
  256. };
  257. serial@70006000 {
  258. status = "disable";
  259. };
  260. serial@70006040 {
  261. status = "disable";
  262. };
  263. serial@70006200 {
  264. status = "disable";
  265. };
  266. serial@70006300 {
  267. clock-frequency = <216000000>;
  268. };
  269. serial@70006400 {
  270. status = "disable";
  271. };
  272. i2c@7000c000 {
  273. clock-frequency = <400000>;
  274. wm8903: wm8903@1a {
  275. compatible = "wlf,wm8903";
  276. reg = <0x1a>;
  277. interrupt-parent = <&gpio>;
  278. interrupts = <187 0x04>;
  279. gpio-controller;
  280. #gpio-cells = <2>;
  281. micdet-cfg = <0>;
  282. micdet-delay = <100>;
  283. gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
  284. };
  285. /* ALS and proximity sensor */
  286. isl29018@44 {
  287. compatible = "isil,isl29018";
  288. reg = <0x44>;
  289. interrupt-parent = <&gpio>;
  290. interrupts = <202 0x04>; /* GPIO PZ2 */
  291. };
  292. gyrometer@68 {
  293. compatible = "invn,mpu3050";
  294. reg = <0x68>;
  295. interrupt-parent = <&gpio>;
  296. interrupts = <204 0x04>; /* gpio PZ4 */
  297. };
  298. };
  299. i2c@7000c400 {
  300. clock-frequency = <100000>;
  301. smart-battery@b {
  302. compatible = "ti,bq20z75", "smart-battery-1.1";
  303. reg = <0xb>;
  304. ti,i2c-retry-count = <2>;
  305. ti,poll-retry-count = <10>;
  306. };
  307. };
  308. i2c@7000c500 {
  309. clock-frequency = <400000>;
  310. };
  311. i2c@7000d000 {
  312. clock-frequency = <400000>;
  313. temperature-sensor@4c {
  314. compatible = "nct1008";
  315. reg = <0x4c>;
  316. };
  317. magnetometer@c {
  318. compatible = "ak8975";
  319. reg = <0xc>;
  320. interrupt-parent = <&gpio>;
  321. interrupts = <109 0x04>; /* gpio PN5 */
  322. };
  323. };
  324. emc {
  325. emc-table@190000 {
  326. reg = <190000>;
  327. compatible = "nvidia,tegra20-emc-table";
  328. clock-frequency = <190000>;
  329. nvidia,emc-registers = <0x0000000c 0x00000026
  330. 0x00000009 0x00000003 0x00000004 0x00000004
  331. 0x00000002 0x0000000c 0x00000003 0x00000003
  332. 0x00000002 0x00000001 0x00000004 0x00000005
  333. 0x00000004 0x00000009 0x0000000d 0x0000059f
  334. 0x00000000 0x00000003 0x00000003 0x00000003
  335. 0x00000003 0x00000001 0x0000000b 0x000000c8
  336. 0x00000003 0x00000007 0x00000004 0x0000000f
  337. 0x00000002 0x00000000 0x00000000 0x00000002
  338. 0x00000000 0x00000000 0x00000083 0xa06204ae
  339. 0x007dc010 0x00000000 0x00000000 0x00000000
  340. 0x00000000 0x00000000 0x00000000 0x00000000>;
  341. };
  342. emc-table@380000 {
  343. reg = <380000>;
  344. compatible = "nvidia,tegra20-emc-table";
  345. clock-frequency = <380000>;
  346. nvidia,emc-registers = <0x00000017 0x0000004b
  347. 0x00000012 0x00000006 0x00000004 0x00000005
  348. 0x00000003 0x0000000c 0x00000006 0x00000006
  349. 0x00000003 0x00000001 0x00000004 0x00000005
  350. 0x00000004 0x00000009 0x0000000d 0x00000b5f
  351. 0x00000000 0x00000003 0x00000003 0x00000006
  352. 0x00000006 0x00000001 0x00000011 0x000000c8
  353. 0x00000003 0x0000000e 0x00000007 0x0000000f
  354. 0x00000002 0x00000000 0x00000000 0x00000002
  355. 0x00000000 0x00000000 0x00000083 0xe044048b
  356. 0x007d8010 0x00000000 0x00000000 0x00000000
  357. 0x00000000 0x00000000 0x00000000 0x00000000>;
  358. };
  359. };
  360. usb@c5000000 {
  361. nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */
  362. dr_mode = "otg";
  363. };
  364. usb@c5004000 {
  365. nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
  366. };
  367. sdhci@c8000000 {
  368. status = "disable";
  369. };
  370. sdhci@c8000200 {
  371. status = "disable";
  372. };
  373. sdhci@c8000400 {
  374. cd-gpios = <&gpio 69 0>; /* gpio PI5 */
  375. wp-gpios = <&gpio 57 0>; /* gpio PH1 */
  376. power-gpios = <&gpio 70 0>; /* gpio PI6 */
  377. };
  378. sdhci@c8000600 {
  379. support-8bit;
  380. };
  381. gpio-keys {
  382. compatible = "gpio-keys";
  383. power {
  384. label = "Power";
  385. gpios = <&gpio 170 1>; /* gpio PV2, active low */
  386. linux,code = <116>; /* KEY_POWER */
  387. gpio-key,wakeup;
  388. };
  389. lid {
  390. label = "Lid";
  391. gpios = <&gpio 23 0>; /* gpio PC7 */
  392. linux,input-type = <5>; /* EV_SW */
  393. linux,code = <0>; /* SW_LID */
  394. debounce-interval = <1>;
  395. gpio-key,wakeup;
  396. };
  397. };
  398. sound {
  399. compatible = "nvidia,tegra-audio-wm8903-seaboard",
  400. "nvidia,tegra-audio-wm8903";
  401. nvidia,model = "NVIDIA Tegra Seaboard";
  402. nvidia,audio-routing =
  403. "Headphone Jack", "HPOUTR",
  404. "Headphone Jack", "HPOUTL",
  405. "Int Spk", "ROP",
  406. "Int Spk", "RON",
  407. "Int Spk", "LOP",
  408. "Int Spk", "LON",
  409. "Mic Jack", "MICBIAS",
  410. "IN1R", "Mic Jack";
  411. nvidia,i2s-controller = <&tegra_i2s1>;
  412. nvidia,audio-codec = <&wm8903>;
  413. nvidia,spkr-en-gpios = <&wm8903 2 0>;
  414. nvidia,hp-det-gpios = <&gpio 185 0>; /* gpio PX1 */
  415. };
  416. };