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@@ -75,14 +75,14 @@ static void rt61pci_bbp_write(struct rt2x00_dev *rt2x00dev,
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{
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{
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u32 reg;
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u32 reg;
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+ mutex_lock(&rt2x00dev->csr_mutex);
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+
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/*
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/*
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* Wait until the BBP becomes ready.
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* Wait until the BBP becomes ready.
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*/
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*/
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reg = rt61pci_bbp_check(rt2x00dev);
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reg = rt61pci_bbp_check(rt2x00dev);
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- if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
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- ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n");
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- return;
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- }
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+ if (rt2x00_get_field32(reg, PHY_CSR3_BUSY))
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+ goto exit_fail;
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/*
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/*
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* Write the data into the BBP.
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* Write the data into the BBP.
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@@ -94,6 +94,14 @@ static void rt61pci_bbp_write(struct rt2x00_dev *rt2x00dev,
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rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 0);
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rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 0);
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rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
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rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
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+ mutex_unlock(&rt2x00dev->csr_mutex);
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+
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+ return;
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+
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+exit_fail:
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+ mutex_unlock(&rt2x00dev->csr_mutex);
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+
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+ ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n");
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}
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}
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static void rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev,
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static void rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev,
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@@ -101,14 +109,14 @@ static void rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev,
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{
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{
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u32 reg;
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u32 reg;
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+ mutex_lock(&rt2x00dev->csr_mutex);
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+
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/*
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/*
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* Wait until the BBP becomes ready.
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* Wait until the BBP becomes ready.
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*/
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*/
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reg = rt61pci_bbp_check(rt2x00dev);
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reg = rt61pci_bbp_check(rt2x00dev);
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- if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
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- ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
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- return;
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- }
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+ if (rt2x00_get_field32(reg, PHY_CSR3_BUSY))
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+ goto exit_fail;
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/*
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/*
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* Write the request into the BBP.
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* Write the request into the BBP.
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@@ -124,13 +132,19 @@ static void rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev,
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* Wait until the BBP becomes ready.
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* Wait until the BBP becomes ready.
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*/
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*/
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reg = rt61pci_bbp_check(rt2x00dev);
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reg = rt61pci_bbp_check(rt2x00dev);
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- if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
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- ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
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- *value = 0xff;
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- return;
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- }
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+ if (rt2x00_get_field32(reg, PHY_CSR3_BUSY))
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+ goto exit_fail;
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*value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
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*value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
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+ mutex_unlock(&rt2x00dev->csr_mutex);
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+
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+ return;
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+
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+exit_fail:
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+ mutex_unlock(&rt2x00dev->csr_mutex);
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+
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+ ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
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+ *value = 0xff;
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}
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}
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static void rt61pci_rf_write(struct rt2x00_dev *rt2x00dev,
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static void rt61pci_rf_write(struct rt2x00_dev *rt2x00dev,
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@@ -142,6 +156,8 @@ static void rt61pci_rf_write(struct rt2x00_dev *rt2x00dev,
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if (!word)
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if (!word)
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return;
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return;
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+ mutex_lock(&rt2x00dev->csr_mutex);
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+
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for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
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for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
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rt2x00pci_register_read(rt2x00dev, PHY_CSR4, ®);
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rt2x00pci_register_read(rt2x00dev, PHY_CSR4, ®);
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if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY))
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if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY))
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@@ -149,6 +165,7 @@ static void rt61pci_rf_write(struct rt2x00_dev *rt2x00dev,
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udelay(REGISTER_BUSY_DELAY);
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udelay(REGISTER_BUSY_DELAY);
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}
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}
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+ mutex_unlock(&rt2x00dev->csr_mutex);
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ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n");
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ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n");
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return;
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return;
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@@ -161,6 +178,8 @@ rf_write:
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rt2x00pci_register_write(rt2x00dev, PHY_CSR4, reg);
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rt2x00pci_register_write(rt2x00dev, PHY_CSR4, reg);
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rt2x00_rf_write(rt2x00dev, word, value);
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rt2x00_rf_write(rt2x00dev, word, value);
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+
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+ mutex_unlock(&rt2x00dev->csr_mutex);
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}
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}
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#ifdef CONFIG_RT2X00_LIB_LEDS
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#ifdef CONFIG_RT2X00_LIB_LEDS
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@@ -175,14 +194,12 @@ static void rt61pci_mcu_request(struct rt2x00_dev *rt2x00dev,
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{
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{
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u32 reg;
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u32 reg;
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+ mutex_lock(&rt2x00dev->csr_mutex);
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+
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rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CSR, ®);
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rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CSR, ®);
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- if (rt2x00_get_field32(reg, H2M_MAILBOX_CSR_OWNER)) {
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- ERROR(rt2x00dev, "mcu request error. "
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- "Request 0x%02x failed for token 0x%02x.\n",
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- command, token);
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- return;
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- }
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+ if (rt2x00_get_field32(reg, H2M_MAILBOX_CSR_OWNER))
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+ goto exit_fail;
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rt2x00_set_field32(®, H2M_MAILBOX_CSR_OWNER, 1);
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rt2x00_set_field32(®, H2M_MAILBOX_CSR_OWNER, 1);
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rt2x00_set_field32(®, H2M_MAILBOX_CSR_CMD_TOKEN, token);
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rt2x00_set_field32(®, H2M_MAILBOX_CSR_CMD_TOKEN, token);
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@@ -194,6 +211,17 @@ static void rt61pci_mcu_request(struct rt2x00_dev *rt2x00dev,
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rt2x00_set_field32(®, HOST_CMD_CSR_HOST_COMMAND, command);
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rt2x00_set_field32(®, HOST_CMD_CSR_HOST_COMMAND, command);
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rt2x00_set_field32(®, HOST_CMD_CSR_INTERRUPT_MCU, 1);
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rt2x00_set_field32(®, HOST_CMD_CSR_INTERRUPT_MCU, 1);
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rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
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rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
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+
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+ mutex_unlock(&rt2x00dev->csr_mutex);
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+
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+ return;
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+
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+exit_fail:
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+ mutex_unlock(&rt2x00dev->csr_mutex);
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+
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+ ERROR(rt2x00dev,
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+ "mcu request error. Request 0x%02x failed for token 0x%02x.\n",
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+ command, token);
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}
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}
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#endif /* CONFIG_RT2X00_LIB_LEDS */
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#endif /* CONFIG_RT2X00_LIB_LEDS */
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