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@@ -327,7 +327,7 @@ static void rt2500pci_config_intf(struct rt2x00_dev *rt2x00dev,
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/*
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* Enable beacon config
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*/
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- bcn_preload = PREAMBLE + get_duration(IEEE80211_HEADER, 20);
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+ bcn_preload = PREAMBLE + GET_DURATION(IEEE80211_HEADER, 20);
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rt2x00pci_register_read(rt2x00dev, BCNCSR1, ®);
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rt2x00_set_field32(®, BCNCSR1_PRELOAD, bcn_preload);
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rt2x00_set_field32(®, BCNCSR1_BEACON_CWMIN, queue->cw_min);
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@@ -373,25 +373,25 @@ static void rt2500pci_config_erp(struct rt2x00_dev *rt2x00dev,
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rt2x00pci_register_read(rt2x00dev, ARCSR2, ®);
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rt2x00_set_field32(®, ARCSR2_SIGNAL, 0x00);
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rt2x00_set_field32(®, ARCSR2_SERVICE, 0x04);
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- rt2x00_set_field32(®, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
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+ rt2x00_set_field32(®, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 10));
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rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
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rt2x00pci_register_read(rt2x00dev, ARCSR3, ®);
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rt2x00_set_field32(®, ARCSR3_SIGNAL, 0x01 | preamble_mask);
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rt2x00_set_field32(®, ARCSR3_SERVICE, 0x04);
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- rt2x00_set_field32(®, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
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+ rt2x00_set_field32(®, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 20));
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rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
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rt2x00pci_register_read(rt2x00dev, ARCSR4, ®);
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rt2x00_set_field32(®, ARCSR4_SIGNAL, 0x02 | preamble_mask);
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rt2x00_set_field32(®, ARCSR4_SERVICE, 0x04);
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- rt2x00_set_field32(®, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
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+ rt2x00_set_field32(®, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 55));
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rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
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rt2x00pci_register_read(rt2x00dev, ARCSR5, ®);
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rt2x00_set_field32(®, ARCSR5_SIGNAL, 0x03 | preamble_mask);
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rt2x00_set_field32(®, ARCSR5_SERVICE, 0x84);
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- rt2x00_set_field32(®, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
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+ rt2x00_set_field32(®, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 110));
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rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
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rt2x00pci_register_write(rt2x00dev, ARCSR1, erp->basic_rates);
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