This website works better with JavaScript
Home
Explore
Help
Register
Sign In
phyus
/
uboot-vybrid_public
Watch
8
Star
0
Fork
0
Files
Issues
0
Pull Requests
0
Wiki
Tree:
15e2697c9f
Branches
Tags
master
phyCORE-Vybrid-PD15.1-rc1
vphyCORE-Vybrid-PD15.1-rc1
Commit History
Find
Author
SHA1
Message
Date
Haiying Wang
1f293b417a
Add debug information for DDR controller registers
16 years ago
Haiying Wang
dbbbb3abef
Make DDR interleaving mode work correctly
16 years ago
Kumar Gala
302e52e0b1
Fix compiler warning in mpc8xxx ddr code
16 years ago
Kumar Gala
58e5e9aff1
FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code.
16 years ago