Merge branch 'master' of git://git.denx.de/u-boot-arm

board/omap3/beagle/beagle.h

@@ -24,8 +24,6 @@
 #define _BEAGLE_H_
 
 const omap3_sysinfo sysinfo = {
-	SDP_3430_V1,
-	SDP_3430_V2,
 	DDR_STACKED,
 	"OMAP3 Beagle board",
 #if defined(CONFIG_ENV_IS_IN_ONENAND)

board/omap3/evm/evm.h

@@ -24,8 +24,6 @@
 #define _EVM_H_
 
 const omap3_sysinfo sysinfo = {
-	OMAP3EVM_V1,
-	OMAP3EVM_V2,
 	DDR_DISCRETE,
 	"OMAP3 EVM board",
 #if defined(CONFIG_ENV_IS_IN_ONENAND)

board/omap3/overo/overo.h

@@ -24,8 +24,6 @@
 #define _OVERO_H_
 
 const omap3_sysinfo sysinfo = {
-	SDP_3430_V1,
-	SDP_3430_V2,
 	DDR_STACKED,
 	"Gumstix Overo board",
 #if defined(CONFIG_ENV_IS_IN_ONENAND)

board/omap3/pandora/pandora.h

@@ -24,8 +24,6 @@
 #define _PANDORA_H_
 
 const omap3_sysinfo sysinfo = {
-	SDP_3430_V1,
-	SDP_3430_V2,
 	DDR_STACKED,
 	"OMAP3 Pandora",
 	"NAND",

board/omap3/zoom1/zoom1.h

@@ -28,8 +28,6 @@
 #define _BOARD_ZOOM1_H_
 
 const omap3_sysinfo sysinfo = {
-	SDP_3430_V1,
-	SDP_3430_V2,
 	DDR_STACKED,
 	"OMAP3 Zoom MDK Rev 1",
 	"NAND",

cpu/arm925t/interrupts.c

@@ -1,4 +1,7 @@
 /*
+ * (C) Copyright 2009
+ * 2N Telekomunikace, <www.2n.cz>
+ *
  * (C) Copyright 2003
  * Texas Instruments, <www.ti.com>
  *
@@ -37,7 +40,8 @@
 #include <configs/omap1510.h>
 #include <asm/io.h>
 
-#define TIMER_LOAD_VAL 0xffffffff
+#define TIMER_LOAD_VAL	0xffffffff
+#define TIMER_CLOCK	(CONFIG_SYS_CLK_FREQ / (2 << CONFIG_SYS_PTV))
 
 static uint32_t timestamp;
 static uint32_t lastdec;
@@ -79,85 +83,41 @@ void set_timer (ulong t)
 /* delay x useconds AND preserve advance timestamp value */
 void udelay (unsigned long usec)
 {
-	ulong tmo, tmp;
-
-	if (usec >= 1000) {		/* if "big" number, spread normalization to seconds */
-		tmo = usec / 1000;	/* start to normalize for usec to ticks per sec */
-		tmo *= CONFIG_SYS_HZ;	/* find number of "ticks" to wait to achieve target */
-		tmo /= 1000;		/* finish normalize. */
-	} else {			/* else small number, don't kill it prior to HZ multiply */
-		tmo = usec * CONFIG_SYS_HZ;
-		tmo /= (1000*1000);
+	int32_t tmo = usec * (TIMER_CLOCK / 1000) / 1000;
+	uint32_t now, last = __raw_readl(CONFIG_SYS_TIMERBASE + READ_TIM);
+
+	while (tmo > 0) {
+		now = __raw_readl(CONFIG_SYS_TIMERBASE + READ_TIM);
+		if (last < now) /* count down timer underflow */
+			tmo -= TIMER_LOAD_VAL - now + last;
+		else
+			tmo -= last - now;
+		last = now;
 	}
-
-	tmp = get_timer (0);		/* get current timestamp */
-	if ((tmo + tmp + 1) < tmp)	/* if setting this fordward will roll time stamp */
-		reset_timer_masked ();	/* reset "advancing" timestamp to 0, set lastdec value */
-	else
-		tmo += tmp;		/* else, set advancing stamp wake up time */
-
-	while (get_timer_masked () < tmo) /* loop till event */
-		/*NOP*/;
 }
 
 void reset_timer_masked (void)
 {
 	/* reset time */
-	lastdec = __raw_readl(CONFIG_SYS_TIMERBASE + READ_TIM);
+	lastdec = __raw_readl(CONFIG_SYS_TIMERBASE + READ_TIM) /
+			(TIMER_CLOCK / CONFIG_SYS_HZ);
 	timestamp = 0;	       /* start "advancing" time stamp from 0 */
 }
 
 ulong get_timer_masked (void)
 {
-	uint32_t now = __raw_readl(CONFIG_SYS_TIMERBASE + READ_TIM);
-
-	if (lastdec >= now) {		/* normal mode (non roll) */
-		/* normal mode */
-		timestamp += lastdec - now; /* move stamp fordward with absoulte diff ticks */
-	} else {			/* we have overflow of the count down timer */
-		/* nts = ts + ld + (TLV - now)
-		 * ts=old stamp, ld=time that passed before passing through -1
-		 * (TLV-now) amount of time after passing though -1
-		 * nts = new "advancing time stamp"...it could also roll and cause problems.
-		 */
-		timestamp += lastdec + TIMER_LOAD_VAL - now;
-	}
+	uint32_t now = __raw_readl(CONFIG_SYS_TIMERBASE + READ_TIM) /
+			(TIMER_CLOCK / CONFIG_SYS_HZ);
+	if (lastdec < now)	/* count down timer underflow */
+		timestamp += TIMER_LOAD_VAL / (TIMER_CLOCK / CONFIG_SYS_HZ) -
+				now + lastdec;
+	else
+		timestamp += lastdec - now;
 	lastdec = now;
 
 	return timestamp;
 }
 
-/* waits specified delay value and resets timestamp */
-void udelay_masked (unsigned long usec)
-{
-#ifdef CONFIG_INNOVATOROMAP1510
-	#define LOOPS_PER_MSEC 60 /* tuned on omap1510 */
-	volatile int i, time_remaining = LOOPS_PER_MSEC*usec;
-	for (i=time_remaining; i>0; i--) { }
-#else
-
-	ulong tmo;
-	ulong endtime;
-	signed long diff;
-
-	if (usec >= 1000) {		/* if "big" number, spread normalization to seconds */
-		tmo = usec / 1000;	/* start to normalize for usec to ticks per sec */
-		tmo *= CONFIG_SYS_HZ;	/* find number of "ticks" to wait to achieve target */
-		tmo /= 1000;		/* finish normalize. */
-	} else {			/* else small number, don't kill it prior to HZ multiply */
-		tmo = usec * CONFIG_SYS_HZ;
-		tmo /= (1000*1000);
-	}
-
-	endtime = get_timer_masked () + tmo;
-
-	do {
-		ulong now = get_timer_masked ();
-		diff = endtime - now;
-	} while (diff >= 0);
-#endif
-}
-
 /*
  * This function is derived from PowerPC code (read timebase as long long).
  * On ARM it just returns the timer value.

cpu/arm926ejs/at91/clock.c

@@ -126,6 +126,7 @@ static unsigned at91_pll_calc(unsigned main_freq, unsigned out_freq)
 fail:
 	return 0;
 }
+#endif
 
 static u32 at91_pll_rate(u32 freq, u32 reg)
 {
@@ -141,7 +142,6 @@ static u32 at91_pll_rate(u32 freq, u32 reg)
 
 	return freq;
 }
-#endif
 
 int at91_clock_init(unsigned long main_clock)
 {

cpu/arm_cortexa8/cpu.c

@@ -101,7 +101,7 @@ void l2cache_enable()
 	volatile unsigned int j;
 
 	/* ES2 onwards we can disable/enable L2 ourselves */
-	if (get_cpu_rev() == CPU_3430_ES2) {
+	if (get_cpu_rev() >= CPU_3XX_ES20) {
 		__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
 		__asm__ __volatile__("orr %0, %0, #0x2":"=r"(i));
 		__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
@@ -131,7 +131,7 @@ void l2cache_disable()
 	volatile unsigned int j;
 
 	/* ES2 onwards we can disable/enable L2 ourselves */
-	if (get_cpu_rev() == CPU_3430_ES2) {
+	if (get_cpu_rev() >= CPU_3XX_ES20) {
 		__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
 		__asm__ __volatile__("bic %0, %0, #0x2":"=r"(i));
 		__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));

cpu/arm_cortexa8/omap3/board.c

@@ -39,6 +39,8 @@
 
 extern omap3_sysinfo sysinfo;
 
+extern u32 is_mem_sdr(void);
+
 /******************************************************************************
  * Routine: delay
  * Description: spinning delay to use before udelay works
@@ -272,11 +274,6 @@ int dram_init(void)
 {
 	DECLARE_GLOBAL_DATA_PTR;
 	unsigned int size0 = 0, size1 = 0;
-	u32 btype;
-
-	btype = get_board_type();
-
-	display_board_info(btype);
 
 	/*
 	 * If a second bank of DDR is attached to CS1 this is
@@ -342,3 +339,23 @@ U_BOOT_CMD(
 	);
 
 #endif /* CONFIG_NAND_OMAP_GPMC */
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+/**
+ * Print board information
+ */
+int checkboard (void)
+{
+	char *mem_s ;
+
+	if (is_mem_sdr())
+		mem_s = "mSDR";
+	else
+		mem_s = "LPDDR";
+
+	printf("%s + %s/%s\n", sysinfo.board_string, mem_s,
+			sysinfo.nand_string);
+
+	return 0;
+}
+#endif	/* CONFIG_DISPLAY_BOARDINFO */

cpu/arm_cortexa8/omap3/clock.c

@@ -132,7 +132,7 @@ void prcm_init(void)
 	void (*f_lock_pll) (u32, u32, u32, u32);
 	int xip_safe, p0, p1, p2, p3;
 	u32 osc_clk = 0, sys_clkin_sel;
-	u32 clk_index, sil_index;
+	u32 clk_index, sil_index = 0;
 	prm_t *prm_base = (prm_t *)PRM_BASE;
 	prcm_t *prcm_base = (prcm_t *)PRCM_BASE;
 	dpll_param *dpll_param_p;
@@ -170,7 +170,8 @@ void prcm_init(void)
 	 * and sil_index will get the values for that SysClk for the
 	 * appropriate silicon rev.
 	 */
-	sil_index = get_cpu_rev() - 1;
+	if (get_cpu_rev())
+		sil_index = 1;
 
 	/* Unlock MPU DPLL (slows things down, and needed later) */
 	sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOW_POWER_BYPASS);

cpu/arm_cortexa8/omap3/sys_info.c

@@ -35,6 +35,12 @@ extern omap3_sysinfo sysinfo;
 static gpmc_csx_t *gpmc_cs_base = (gpmc_csx_t *)GPMC_CONFIG_CS0_BASE;
 static sdrc_t *sdrc_base = (sdrc_t *)OMAP34XX_SDRC_BASE;
 static ctrl_t *ctrl_base = (ctrl_t *)OMAP34XX_CTRL_BASE;
+static char *rev_s[CPU_3XX_MAX_REV] = {
+				"1.0",
+				"2.0",
+				"2.1",
+				"3.0",
+				"3.1"};
 
 /*****************************************************************
  * dieid_num_r(void) - read and set die ID
@@ -76,18 +82,27 @@ u32 get_cpu_type(void)
 u32 get_cpu_rev(void)
 {
 	u32 cpuid = 0;
+	ctrl_id_t *id_base;
 
 	/*
 	 * On ES1.0 the IDCODE register is not exposed on L4
-	 * so using CPU ID to differentiate
-	 * between ES2.0 and ES1.0.
+	 * so using CPU ID to differentiate between ES1.0 and > ES1.0.
 	 */
 	__asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r"(cpuid));
 	if ((cpuid & 0xf) == 0x0)
-		return CPU_3430_ES1;
-	else
-		return CPU_3430_ES2;
+		return CPU_3XX_ES10;
+	else {
+		/* Decode the IDs on > ES1.0 */
+		id_base = (ctrl_id_t *) OMAP34XX_ID_L4_IO_BASE;
 
+		cpuid = (readl(&id_base->idcode) >> CPU_3XX_ID_SHIFT) & 0xf;
+
+		/* Some early ES2.0 seem to report ID 0, fix this */
+		if(cpuid == 0)
+			cpuid = CPU_3XX_ES20;
+
+		return cpuid;
+	}
 }
 
 /****************************************************
@@ -130,23 +145,6 @@ u32 get_sdr_cs_offset(u32 cs)
 	return offset;
 }
 
-/***********************************************************************
- * get_board_type() - get board type based on current production stats.
- *  - NOTE-1-: 2 I2C EEPROMs will someday be populated with proper info.
- *    when they are available we can get info from there.  This should
- *    be correct of all known boards up until today.
- *  - NOTE-2- EEPROMs are populated but they are updated very slowly.  To
- *    avoid waiting on them we will use ES version of the chip to get info.
- *    A later version of the FPGA migth solve their speed issue.
- ************************************************************************/
-u32 get_board_type(void)
-{
-	if (get_cpu_rev() == CPU_3430_ES2)
-		return sysinfo.board_type_v2;
-	else
-		return sysinfo.board_type_v1;
-}
-
 /***************************************************************************
  *  get_gpmc0_base() - Return current address hardware will be
  *     fetching from. The below effectively gives what is correct, its a bit
@@ -185,61 +183,6 @@ u32 get_board_rev(void)
 	return 0x20;
 }
 
-/*********************************************************************
- *  display_board_info() - print banner with board info.
- *********************************************************************/
-void display_board_info(u32 btype)
-{
-	char *cpu_s, *mem_s, *sec_s;
-
-	switch (get_cpu_type()) {
-	case OMAP3503:
-		cpu_s = "3503";
-		break;
-	case OMAP3515:
-		cpu_s = "3515";
-		break;
-	case OMAP3525:
-		cpu_s = "3525";
-		break;
-	case OMAP3530:
-		cpu_s = "3530";
-		break;
-	default:
-		cpu_s = "35XX";
-		break;
-	}
-
-	if (is_mem_sdr())
-		mem_s = "mSDR";
-	else
-		mem_s = "LPDDR";
-
-	switch (get_device_type()) {
-	case TST_DEVICE:
-		sec_s = "TST";
-		break;
-	case EMU_DEVICE:
-		sec_s = "EMU";
-		break;
-	case HS_DEVICE:
-		sec_s = "HS";
-		break;
-	case GP_DEVICE:
-		sec_s = "GP";
-		break;
-	default:
-		sec_s = "?";
-	}
-
-
-	printf("OMAP%s-%s rev %d, CPU-OPP2 L3-165MHz\n", cpu_s,
-	       sec_s, get_cpu_rev());
-	printf("%s + %s/%s\n", sysinfo.board_string,
-	       mem_s, sysinfo.nand_string);
-
-}
-
 /********************************************************
  *  get_base(); get upper addr of current execution
  *******************************************************/
@@ -305,3 +248,53 @@ u32 get_device_type(void)
 {
 	return ((readl(&ctrl_base->status) & (DEVICE_MASK)) >> 8);
 }
+
+#ifdef CONFIG_DISPLAY_CPUINFO
+/**
+ * Print CPU information
+ */
+int print_cpuinfo (void)
+{
+	char *cpu_s, *sec_s;
+
+	switch (get_cpu_type()) {
+	case OMAP3503:
+		cpu_s = "3503";
+		break;
+	case OMAP3515:
+		cpu_s = "3515";
+		break;
+	case OMAP3525:
+		cpu_s = "3525";
+		break;
+	case OMAP3530:
+		cpu_s = "3530";
+		break;
+	default:
+		cpu_s = "35XX";
+		break;
+	}
+
+	switch (get_device_type()) {
+	case TST_DEVICE:
+		sec_s = "TST";
+		break;
+	case EMU_DEVICE:
+		sec_s = "EMU";
+		break;
+	case HS_DEVICE:
+		sec_s = "HS";
+		break;
+	case GP_DEVICE:
+		sec_s = "GP";
+		break;
+	default:
+		sec_s = "?";
+	}
+
+	printf("OMAP%s-%s ES%s, CPU-OPP2 L3-165MHz\n",
+			cpu_s, sec_s, rev_s[get_cpu_rev()]);
+
+	return 0;
+}
+#endif	/* CONFIG_DISPLAY_CPUINFO */

include/asm-arm/arch-omap3/omap3.h

@@ -167,24 +167,20 @@ typedef struct gpio {
  * 343x real hardware:
  *  ES1     = rev 0
  *
- * 343x code defines:
- * ES1     = 0+1 = 1
- * ES1     = 1+1 = 1
+ *  ES2 onwards, the value maps to contents of IDCODE register [31:28].
  */
-#define CPU_3430_ES1		1
-#define CPU_3430_ES2		2
+#define CPU_3XX_ES10		0
+#define CPU_3XX_ES20		1
+#define CPU_3XX_ES21		2
+#define CPU_3XX_ES30		3
+#define CPU_3XX_ES31		4
+#define CPU_3XX_MAX_REV		(CPU_3XX_ES31 + 1)
+
+#define CPU_3XX_ID_SHIFT	28
 
 #define WIDTH_8BIT		0x0000
 #define WIDTH_16BIT		0x1000	/* bit pos for 16 bit in gpmc */
 
-/* SDP definitions according to FPGA Rev. Is this OK?? */
-#define SDP_3430_V1		0x1
-#define SDP_3430_V2		0x2
-
-/* EVM definitions */
-#define OMAP3EVM_V1		0x1
-#define OMAP3EVM_V2		0x2
-
 /* I2C power management companion definitions */
 #define PWRMGT_ADDR_ID1		0x48
 #define PWRMGT_ADDR_ID2		0x49

include/asm-arm/arch-omap3/sys_proto.h

@@ -22,8 +22,6 @@
 #define _SYS_PROTO_H_
 
 typedef struct {
-	u32 board_type_v1;
-	u32 board_type_v2;
 	u32 mtype;
 	char *board_string;
 	char *nand_string;
@@ -46,8 +44,6 @@ u32 get_sysboot_value(void);
 u32 is_gpmc_muxed(void);
 u32 get_gpmc0_type(void);
 u32 get_gpmc0_width(void);
-u32 get_board_type(void);
-void display_board_info(u32);
 u32 get_sdr_cs_size(u32);
 u32 get_sdr_cs_offset(u32);
 u32 is_running_in_sdram(void);

include/configs/SX1.h

@@ -135,12 +135,12 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0x10000000	/* default load address */
 
-/* The 1510 has 3 timers, they can be driven by the RefClk (12Mhz) or by DPLL1.
+/* The 1510 has 3 timers, they can be driven by the RefClk (12MHz) or by DPLL1.
  * This time is further subdivided by a local divisor.
  */
 #define CONFIG_SYS_TIMERBASE	OMAP1510_TIMER1_BASE	/* use timer 1 */
-#define CONFIG_SYS_PTV		7	/* 2^(PTV+1), divide by 256 */
-#define CONFIG_SYS_HZ		((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV))
+#define CONFIG_SYS_PTV		2	/* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ		1000
 
 /*-----------------------------------------------------------------------
  * Stack sizes

include/configs/davinci_dvevm.h

@@ -56,7 +56,6 @@
 /* SoC Configuration */
 /*===================*/
 #define CONFIG_ARM926EJS			/* arm926ejs CPU core */
-#define CONFIG_SYS_CLK_FREQ	297000000	/* Arm Clock frequency */
 #define CONFIG_SYS_TIMERBASE		0x01c21400	/* use timer 0 */
 #define CONFIG_SYS_HZ_CLOCK		27000000	/* Timer Input clock freq */
 #define CONFIG_SYS_HZ			1000
@@ -87,7 +86,7 @@
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	-4	/* NS16550 register size, byteorder */
 #define CONFIG_SYS_NS16550_COM1	0x01c20000	/* Base address of UART0 */
-#define CONFIG_SYS_NS16550_CLK		27000000	/* Input clock to NS16550 */
+#define CONFIG_SYS_NS16550_CLK	CONFIG_SYS_HZ_CLOCK	/* Input clock to NS16550 */
 #define CONFIG_CONS_INDEX	1		/* use UART0 for console */
 #define CONFIG_BAUDRATE		115200		/* Default baud rate */
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

include/configs/davinci_schmoogie.h

@@ -31,7 +31,6 @@
 /* SoC Configuration */
 /*===================*/
 #define CONFIG_ARM926EJS			/* arm926ejs CPU core */
-#define CONFIG_SYS_CLK_FREQ	297000000	/* Arm Clock frequency */
 #define CONFIG_SYS_TIMERBASE		0x01c21400	/* use timer 0 */
 #define CONFIG_SYS_HZ_CLOCK		27000000	/* Timer Input clock freq */
 #define CONFIG_SYS_HZ			1000
@@ -54,7 +53,7 @@
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	-4	/* NS16550 register size, byteorder */
 #define CONFIG_SYS_NS16550_COM1	0x01c20000	/* Base address of UART0 */
-#define CONFIG_SYS_NS16550_CLK		27000000	/* Input clock to NS16550 */
+#define CONFIG_SYS_NS16550_CLK	CONFIG_SYS_HZ_CLOCK	/* Input clock to NS16550 */
 #define CONFIG_CONS_INDEX	1		/* use UART0 for console */
 #define CONFIG_BAUDRATE		115200		/* Default baud rate */
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

include/configs/davinci_sffsdr.h

@@ -32,7 +32,6 @@
 				 * powering ON the DSP. */
 /* SoC Configuration */
 #define CONFIG_ARM926EJS			/* arm926ejs CPU core */
-#define CONFIG_SYS_CLK_FREQ	297000000	/* Arm Clock frequency */
 #define CONFIG_SYS_TIMERBASE		0x01c21400	/* use timer 0 */
 #define CONFIG_SYS_HZ_CLOCK		27000000	/* Timer Input clock freq */
 #define CONFIG_SYS_HZ			1000
@@ -56,7 +55,7 @@
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	-4	/* NS16550 register size, byteorder */
 #define CONFIG_SYS_NS16550_COM1	0x01c20000	/* Base address of UART0 */
-#define CONFIG_SYS_NS16550_CLK		27000000	/* Input clock to NS16550 */
+#define CONFIG_SYS_NS16550_CLK	CONFIG_SYS_HZ_CLOCK	/* Input clock to NS16550 */
 #define CONFIG_CONS_INDEX	1		/* use UART0 for console */
 #define CONFIG_BAUDRATE		115200		/* Default baud rate */
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

include/configs/davinci_sonata.h

@@ -56,7 +56,6 @@
 /* SoC Configuration */
 /*===================*/
 #define CONFIG_ARM926EJS			/* arm926ejs CPU core */
-#define CONFIG_SYS_CLK_FREQ	297000000	/* Arm Clock frequency */
 #define CONFIG_SYS_TIMERBASE		0x01c21400	/* use timer 0 */
 #define CONFIG_SYS_HZ_CLOCK		27000000	/* Timer Input clock freq */
 #define CONFIG_SYS_HZ			1000
@@ -87,7 +86,7 @@
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	-4	/* NS16550 register size, byteorder */
 #define CONFIG_SYS_NS16550_COM1	0x01c20000	/* Base address of UART0 */
-#define CONFIG_SYS_NS16550_CLK		27000000	/* Input clock to NS16550 */
+#define CONFIG_SYS_NS16550_CLK	CONFIG_SYS_HZ_CLOCK	/* Input clock to NS16550 */
 #define CONFIG_CONS_INDEX	1		/* use UART0 for console */
 #define CONFIG_BAUDRATE		115200		/* Default baud rate */
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

include/configs/netstar.h

@@ -222,12 +222,12 @@
 
 #define CONFIG_SYS_LOAD_ADDR		PHYS_SDRAM_1 + 0x400000	/* default load address */
 
-/* The 1510 has 3 timers, they can be driven by the RefClk (12Mhz) or by DPLL1.
+/* The 1510 has 3 timers, they can be driven by the RefClk (12MHz) or by DPLL1.
  * This time is further subdivided by a local divisor.
  */
 #define CONFIG_SYS_TIMERBASE		OMAP1510_TIMER1_BASE
-#define CONFIG_SYS_PTV			7		/* 2^(pvt+1), divide by 256 */
-#define CONFIG_SYS_HZ			((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV))
+#define CONFIG_SYS_PTV			7
+#define CONFIG_SYS_HZ			1000
 
 #define OMAP5910_DPLL_DIV	1
 #define OMAP5910_DPLL_MUL	((CONFIG_SYS_CLK_FREQ * \

include/configs/omap1510inn.h

@@ -132,12 +132,12 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0x10000000	/* default load address */
 
-/* The 1510 has 3 timers, they can be driven by the RefClk (12Mhz) or by DPLL1.
+/* The 1510 has 3 timers, they can be driven by the RefClk (12MHz) or by DPLL1.
  * This time is further subdivided by a local divisor.
  */
 #define CONFIG_SYS_TIMERBASE	OMAP1510_TIMER1_BASE	/* use timer 1 */
-#define CONFIG_SYS_PTV		7	/* 2^(PTV+1), divide by 256 */
-#define CONFIG_SYS_HZ		((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV))
+#define CONFIG_SYS_PTV		2	/* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ		1000
 
 /*-----------------------------------------------------------------------
  * Stack sizes

include/configs/omap3_beagle.h

@@ -41,6 +41,12 @@
 #include <asm/arch/cpu.h>		/* get chip and board defs */
 #include <asm/arch/omap3.h>
 
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO		1
+#define CONFIG_DISPLAY_BOARDINFO	1
+
 /* Clock Defines */
 #define V_OSCK			26000000	/* Clock output from T2 */
 #define V_SCLK			(V_OSCK >> 1)
@@ -135,18 +141,6 @@
 
 #define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
 							/* devices */
-#define SECTORSIZE			512
-
-#define NAND_ALLOW_ERASE_ALL
-#define ADDR_COLUMN			1
-#define ADDR_PAGE			2
-#define ADDR_COLUMN_PAGE		3
-
-#define NAND_ChipID_UNKNOWN		0x00
-#define NAND_MAX_FLOORS			1
-#define NAND_MAX_CHIPS			1
-#define NAND_NO_RB			1
-#define CONFIG_SYS_NAND_WP
 
 #define CONFIG_JFFS2_NAND
 /* nand device jffs2 lives on */
@@ -185,7 +179,7 @@
 		"bootm ${loadaddr}\0" \
 
 #define CONFIG_BOOTCOMMAND \
-	"if mmcinit; then " \
+	"if mmc init; then " \
 		"if run loadbootscript; then " \
 			"run bootscript; " \
 		"else " \
@@ -306,21 +300,4 @@ extern unsigned int boot_flash_sec;
 extern unsigned int boot_flash_type;
 #endif
 
-
-#define WRITE_NAND_COMMAND(d, adr)\
-			writel(d, &nand_cs_base->nand_cmd)
-#define WRITE_NAND_ADDRESS(d, adr)\
-			writel(d, &nand_cs_base->nand_adr)
-#define WRITE_NAND(d, adr) writew(d, &nand_cs_base->nand_dat)
-#define READ_NAND(adr) readl(&nand_cs_base->nand_dat)
-
-/* Other NAND Access APIs */
-#define NAND_WP_OFF() do {readl(&gpmc_cfg_base->config) |= GPMC_CONFIG_WP; } \
-			while (0)
-#define NAND_WP_ON() do {readl(&gpmc_cfg_base->config) &= ~GPMC_CONFIG_WP; } \
-			while (0)
-#define NAND_DISABLE_CE(nand)
-#define NAND_ENABLE_CE(nand)
-#define NAND_WAIT_READY(nand)	udelay(10)
-
 #endif /* __CONFIG_H */

include/configs/omap3_evm.h

@@ -46,6 +46,12 @@
 #include <asm/arch/cpu.h>	/* get chip and board defs */
 #include <asm/arch/omap3.h>
 
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO		1
+#define CONFIG_DISPLAY_BOARDINFO	1
+
 /* Clock Defines */
 #define V_OSCK			26000000	/* Clock output from T2 */
 #define V_SCLK			(V_OSCK >> 1)
@@ -66,7 +72,6 @@
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + SZ_128K)
 #define CONFIG_SYS_GBL_DATA_SIZE	128	/* bytes reserved for */
 						/* initial data */
-
 /*
  * Hardware drivers
  */
@@ -133,18 +138,6 @@
 
 #define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of */
 							/* NAND devices */
-#define SECTORSIZE			512
-
-#define NAND_ALLOW_ERASE_ALL
-#define ADDR_COLUMN			1
-#define ADDR_PAGE			2
-#define ADDR_COLUMN_PAGE		3
-
-#define NAND_ChipID_UNKNOWN		0x00
-#define NAND_MAX_FLOORS			1
-#define NAND_MAX_CHIPS			1
-#define NAND_NO_RB			1
-#define CONFIG_SYS_NAND_WP
 
 #define CONFIG_JFFS2_NAND
 /* nand device jffs2 lives on */
@@ -178,7 +171,7 @@
 		"bootm ${loadaddr}\0" \
 
 #define CONFIG_BOOTCOMMAND \
-	"if mmcinit; then " \
+	"if mmc init; then " \
 		"if run loadbootscript; then " \
 			"run bootscript; " \
 		"else " \
@@ -299,23 +292,6 @@ extern unsigned int boot_flash_sec;
 extern unsigned int boot_flash_type;
 #endif
 
-
-#define WRITE_NAND_COMMAND(d, adr)\
-			writel(d, &nand_cs_base->nand_cmd)
-#define WRITE_NAND_ADDRESS(d, adr)\
-			writel(d, &nand_cs_base->nand_adr)
-#define WRITE_NAND(d, adr) writew(d, &nand_cs_base->nand_dat)
-#define READ_NAND(adr) readl(&nand_cs_base->nand_dat)
-
-/* Other NAND Access APIs */
-#define NAND_WP_OFF() do {readl(&gpmc_cfg_base->config) |= GPMC_CONFIG_WP; } \
-			while (0)
-#define NAND_WP_ON() do {readl(&gpmc_cfg_base->config) &= ~GPMC_CONFIG_WP; } \
-			while (0)
-#define NAND_DISABLE_CE(nand)
-#define NAND_ENABLE_CE(nand)
-#define NAND_WAIT_READY(nand)	udelay(10)
-
 /*----------------------------------------------------------------------------
  * SMSC9115 Ethernet from SMSC9118 family
  *----------------------------------------------------------------------------

include/configs/omap3_overo.h

@@ -33,6 +33,12 @@
 #include <asm/arch/cpu.h>	/* get chip and board defs */
 #include <asm/arch/omap3.h>
 
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO		1
+#define CONFIG_DISPLAY_BOARDINFO	1
+
 /* Clock Defines */
 #define V_OSCK			26000000	/* Clock output from T2 */
 #define V_SCLK			(V_OSCK >> 1)
@@ -122,19 +128,6 @@
 
 #define CONFIG_SYS_MAX_NAND_DEVICE	1	/* Max number of NAND */
 						/* devices */
-#define SECTORSIZE			512
-
-#define NAND_ALLOW_ERASE_ALL
-#define ADDR_COLUMN			1
-#define ADDR_PAGE			2
-#define ADDR_COLUMN_PAGE		3
-
-#define NAND_ChipID_UNKNOWN		0x00
-#define NAND_MAX_FLOORS			1
-#define NAND_MAX_CHIPS			1
-#define NAND_NO_RB			1
-#define CONFIG_SYS_NAND_WP
-
 #define CONFIG_JFFS2_NAND
 /* nand device jffs2 lives on */
 #define CONFIG_JFFS2_DEV		"nand0"
@@ -172,7 +165,7 @@
 		"bootm ${loadaddr}\0" \
 
 #define CONFIG_BOOTCOMMAND \
-	"if mmcinit; then " \
+	"if mmc init; then " \
 		"if run loadbootscript; then " \
 			"run bootscript; " \
 		"else " \
@@ -293,21 +286,4 @@ extern unsigned int boot_flash_sec;
 extern unsigned int boot_flash_type;
 #endif
 
-
-#define WRITE_NAND_COMMAND(d, adr)\
-			writel(d, &nand_cs_base->nand_cmd)
-#define WRITE_NAND_ADDRESS(d, adr)\
-			writel(d, &nand_cs_base->nand_adr)
-#define WRITE_NAND(d, adr) writew(d, &nand_cs_base->nand_dat)
-#define READ_NAND(adr) readl(&nand_cs_base->nand_dat)
-
-/* Other NAND Access APIs */
-#define NAND_WP_OFF() do {readl(&gpmc_cfg_base->config) |= GPMC_CONFIG_WP; } \
-			while (0)
-#define NAND_WP_ON() do {readl(&gpmc_cfg_base->config) &= ~GPMC_CONFIG_WP; } \
-			while (0)
-#define NAND_DISABLE_CE(nand)
-#define NAND_ENABLE_CE(nand)
-#define NAND_WAIT_READY(nand)	udelay(10)
-
 #endif				/* __CONFIG_H */

include/configs/omap3_pandora.h

@@ -36,6 +36,12 @@
 #include <asm/arch/cpu.h>	/* get chip and board defs */
 #include <asm/arch/omap3.h>
 
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO		1
+#define CONFIG_DISPLAY_BOARDINFO	1
+
 /* Clock Defines */
 #define V_OSCK			26000000	/* Clock output from T2 */
 #define V_SCLK			(V_OSCK >> 1)
@@ -125,18 +131,6 @@
 
 #define CONFIG_SYS_MAX_NAND_DEVICE	1	/* Max number of NAND */
 						/* devices */
-#define SECTORSIZE			512
-
-#define NAND_ALLOW_ERASE_ALL
-#define ADDR_COLUMN			1
-#define ADDR_PAGE			2
-#define ADDR_COLUMN_PAGE		3
-
-#define NAND_ChipID_UNKNOWN		0x00
-#define NAND_MAX_FLOORS			1
-#define NAND_MAX_CHIPS			1
-#define NAND_NO_RB			1
-#define CONFIG_SYS_NAND_WP
 
 #define CONFIG_JFFS2_NAND
 /* nand device jffs2 lives on */
@@ -174,7 +168,7 @@
 		"bootm ${loadaddr}\0" \
 
 #define CONFIG_BOOTCOMMAND \
-	"if mmcinit; then " \
+	"if mmc init; then " \
 		"if run loadbootscript; then " \
 			"run bootscript; " \
 		"else " \
@@ -295,21 +289,4 @@ extern unsigned int boot_flash_sec;
 extern unsigned int boot_flash_type;
 #endif
 
-
-#define WRITE_NAND_COMMAND(d, adr)\
-			writel(d, &nand_cs_base->nand_cmd)
-#define WRITE_NAND_ADDRESS(d, adr)\
-			writel(d, &nand_cs_base->nand_adr)
-#define WRITE_NAND(d, adr) writew(d, &nand_cs_base->nand_dat)
-#define READ_NAND(adr) readl(&nand_cs_base->nand_dat)
-
-/* Other NAND Access APIs */
-#define NAND_WP_OFF() do {readl(&gpmc_cfg_base->config) |= GPMC_CONFIG_WP; } \
-			while (0)
-#define NAND_WP_ON() do {readl(&gpmc_cfg_base->config) &= ~GPMC_CONFIG_WP; } \
-			while (0)
-#define NAND_DISABLE_CE(nand)
-#define NAND_ENABLE_CE(nand)
-#define NAND_WAIT_READY(nand)	udelay(10)
-
 #endif				/* __CONFIG_H */

include/configs/omap3_zoom1.h

@@ -42,6 +42,12 @@
 #include <asm/arch/cpu.h>		/* get chip and board defs */
 #include <asm/arch/omap3.h>
 
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO		1
+#define CONFIG_DISPLAY_BOARDINFO	1
+
 /* Clock Defines */
 #define V_OSCK			26000000	/* Clock output from T2 */
 #define V_SCLK			(V_OSCK >> 1)
@@ -182,7 +188,7 @@
 		"bootm ${loadaddr}\0" \
 
 #define CONFIG_BOOTCOMMAND \
-	"if mmcinit; then " \
+	"if mmc init; then " \
 		"if run loadbootscript; then " \
 			"run bootscript; " \
 		"else " \

include/configs/voiceblue.h

@@ -210,12 +210,12 @@
 #define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_1
 #define CONFIG_SYS_MEMTEST_END		PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE - PHYS_SDRAM_1_RESERVED
 
-/* The 1510 has 3 timers, they can be driven by the RefClk (12Mhz) or by DPLL1.
+/* The 1510 has 3 timers, they can be driven by the RefClk (12MHz) or by DPLL1.
  * This time is further subdivided by a local divisor.
  */
 #define CONFIG_SYS_TIMERBASE	OMAP1510_TIMER1_BASE
 #define CONFIG_SYS_PTV		7	/* 2^(PTV+1), divide by 256 */
-#define CONFIG_SYS_HZ		((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV))
+#define CONFIG_SYS_HZ		1000
 
 #define OMAP5910_DPLL_DIV	1
 #define OMAP5910_DPLL_MUL	((CONFIG_SYS_CLK_FREQ * \

include/s3c6400.h

@@ -31,10 +31,6 @@
 #ifndef __S3C6400_H__
 #define __S3C6400_H__
 
-#ifndef CONFIG_S3C6400
-#define CONFIG_S3C6400		1
-#endif
-
 #define S3C64XX_UART_CHANNELS	3
 #define S3C64XX_SPI_CHANNELS	2