Merge remote-tracking branch 'u-boot/master'

.gitignore

@@ -75,10 +75,5 @@ cscope.*
 /ctags
 /etags
 
-# OneNAND IPL files
-/onenand_ipl/onenand-ipl*
-/onenand_ipl/board/*/onenand*
-/onenand_ipl/board/*/*.S
-
 # spl ais files
 /spl/*.ais

MAINTAINERS

@@ -777,10 +777,6 @@ Nagendra T S  <nagendra@mistralsolutions.com>
 
    am3517_crane    ARM ARMV7 (AM35x SoC)
 
-Kyungmin Park <kyungmin.park@samsung.com>
-
-	apollon		ARM1136EJS
-
 Sandeep Paulraj <s-paulraj@ti.com>
 
 	davinci_dm355evm	ARM926EJS
@@ -1112,6 +1108,7 @@ Wolfgang Wegner <w.wegner@astro-kom.de>
 
 Andreas Bießmann <andreas.devel@googlemail.com>
 	grasshopper		AT32AP7000
+	atngw100mkii		AT32AP7000
 
 Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com>
 

MAKEALL

@@ -333,6 +333,12 @@ LIST_ppc="		\
 
 LIST_SA="$(boards_by_cpu sa1100)"
 
+#########################################################################
+## ARM7 Systems
+#########################################################################
+
+LIST_ARM7="$(boards_by_cpu arm720t)"
+
 #########################################################################
 ## ARM9 Systems
 #########################################################################
@@ -340,12 +346,15 @@ LIST_SA="$(boards_by_cpu sa1100)"
 LIST_ARM9="$(boards_by_cpu arm920t)	\
 	$(boards_by_cpu arm926ejs)	\
 	$(boards_by_cpu arm925t)	\
+	$(boards_by_cpu arm946es)	\
 "
 
 #########################################################################
 ## ARM11 Systems
 #########################################################################
-LIST_ARM11="$(boards_by_cpu arm1136)"
+LIST_ARM11="$(boards_by_cpu arm1136)	\
+	$(boards_by_cpu arm1176)	\
+"
 
 #########################################################################
 ## ARMV7 Systems
@@ -371,16 +380,7 @@ LIST_ixp="$(boards_by_cpu ixp)"
 ## ARM groups
 #########################################################################
 
-LIST_arm="			\
-	${LIST_SA}		\
-	${LIST_ARM9}		\
-	${LIST_ARM10}		\
-	${LIST_ARM11}		\
-	${LIST_ARMV7}	\
-	${LIST_at91}		\
-	${LIST_pxa}		\
-	${LIST_ixp}		\
-"
+LIST_arm="$(boards_by_arch arm)"
 
 #########################################################################
 ## MIPS Systems		(default = big endian)
@@ -388,6 +388,9 @@ LIST_arm="			\
 
 LIST_mips4kc="		\
 	incaip		\
+	incaip_100MHz	\
+	incaip_133MHz	\
+	incaip_150MHz	\
 	qemu_mips	\
 	vct_platinum	\
 	vct_platinum_small	\
@@ -461,14 +464,7 @@ LIST_microblaze="$(boards_by_arch microblaze)"
 ## ColdFire Systems
 #########################################################################
 
-LIST_m68k="$(boards_by_arch m68k)
-	EB+MCF-EV123		\
-	EB+MCF-EV123_internal	\
-	M52277EVB		\
-	M5235EVB		\
-	M54451EVB		\
-	M54455EVB		\
-"
+LIST_m68k="$(boards_by_arch m68k)"
 LIST_coldfire=${LIST_m68k}
 
 #########################################################################

Makefile

@@ -22,9 +22,9 @@
 #
 
 VERSION = 2012
-PATCHLEVEL = 07
+PATCHLEVEL = 10
 SUBLEVEL =
-EXTRAVERSION =
+EXTRAVERSION = -rc1
 ifneq "$(SUBLEVEL)" ""
 U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
 else
@@ -238,13 +238,19 @@ ifdef SOC
 LIBS-y += $(CPUDIR)/$(SOC)/lib$(SOC).o
 endif
 ifeq ($(CPU),ixp)
-LIBS-y += arch/arm/cpu/ixp/npe/libnpe.o
+LIBS-y += drivers/net/npe/libnpe.o
 endif
 LIBS-$(CONFIG_OF_EMBED) += dts/libdts.o
 LIBS-y += arch/$(ARCH)/lib/lib$(ARCH).o
-LIBS-y += fs/cramfs/libcramfs.o fs/fat/libfat.o fs/fdos/libfdos.o fs/jffs2/libjffs2.o \
-	fs/reiserfs/libreiserfs.o fs/ext2/libext2fs.o fs/yaffs2/libyaffs2.o \
-	fs/ubifs/libubifs.o fs/zfs/libzfs.o
+LIBS-y += fs/cramfs/libcramfs.o \
+	fs/ext4/libext4fs.o \
+	fs/fat/libfat.o \
+	fs/fdos/libfdos.o \
+	fs/jffs2/libjffs2.o \
+	fs/reiserfs/libreiserfs.o \
+	fs/ubifs/libubifs.o \
+	fs/yaffs2/libyaffs2.o \
+	fs/zfs/libzfs.o
 LIBS-y += net/libnet.o
 LIBS-y += disk/libdisk.o
 LIBS-y += drivers/bios_emulator/libatibiosemu.o
@@ -269,6 +275,7 @@ LIBS-y += drivers/pci/libpci.o
 LIBS-y += drivers/pcmcia/libpcmcia.o
 LIBS-y += drivers/power/libpower.o
 LIBS-y += drivers/spi/libspi.o
+LIBS-y += drivers/dfu/libdfu.o
 ifeq ($(CPU),mpc83xx)
 LIBS-y += drivers/qe/libqe.o
 LIBS-y += arch/powerpc/cpu/mpc8xxx/ddr/libddr.o
@@ -374,7 +381,6 @@ ALL-y += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map
 
 ALL-$(CONFIG_NAND_U_BOOT) += $(obj)u-boot-nand.bin
 ALL-$(CONFIG_ONENAND_U_BOOT) += $(obj)u-boot-onenand.bin
-ONENAND_BIN ?= $(obj)onenand_ipl/onenand-ipl-2k.bin
 ALL-$(CONFIG_SPL) += $(obj)spl/u-boot-spl.bin
 ALL-$(CONFIG_OF_SEPARATE) += $(obj)u-boot.dtb $(obj)u-boot-dtb.bin
 
@@ -432,6 +438,11 @@ $(obj)u-boot.kwb:       $(obj)u-boot.bin
 		$(obj)tools/mkimage -n $(CONFIG_SYS_KWD_CONFIG) -T kwbimage \
 		-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) -d $< $@
 
+$(obj)u-boot.pbl:	$(obj)u-boot.bin
+		$(obj)tools/mkimage -n $(CONFIG_PBLRCW_CONFIG) \
+		-R $(CONFIG_PBLPBI_CONFIG) -T pblimage \
+		-d $< $@
+
 $(obj)u-boot.sha1:	$(obj)u-boot.bin
 		$(obj)tools/ubsha1 $(obj)u-boot.bin
 
@@ -446,7 +457,7 @@ $(obj)u-boot.ubl:       $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
 		rm $(obj)u-boot-ubl.bin
 		rm $(obj)spl/u-boot-spl-pad.bin
 
-$(obj)u-boot.ais:       $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
+$(obj)u-boot.ais:       $(obj)spl/u-boot-spl.bin $(obj)u-boot.img
 		$(obj)tools/mkimage -s -n $(if $(CONFIG_AIS_CONFIG_FILE),$(CONFIG_AIS_CONFIG_FILE),"/dev/null") \
 			-T aisimage \
 			-e $(CONFIG_SPL_TEXT_BASE) \
@@ -455,7 +466,7 @@ $(obj)u-boot.ais:       $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
 		$(OBJCOPY) ${OBJCFLAGS} -I binary \
 			--pad-to=$(CONFIG_SPL_MAX_SIZE) -O binary \
 			$(obj)spl/u-boot-spl.ais $(obj)spl/u-boot-spl-pad.ais
-		cat $(obj)spl/u-boot-spl-pad.ais $(obj)u-boot.bin > \
+		cat $(obj)spl/u-boot-spl-pad.ais $(obj)u-boot.img > \
 			$(obj)u-boot.ais
 
 # Specify the target for use in elftosb call
@@ -513,7 +524,7 @@ $(obj)u-boot:	depend \
 		$(SUBDIR_TOOLS) $(OBJS) $(LIBBOARD) $(LIBS) $(LDSCRIPT) $(obj)u-boot.lds
 		$(GEN_UBOOT)
 ifeq ($(CONFIG_KALLSYMS),y)
-		smap=`$(call SYSTEM_MAP,u-boot) | \
+		smap=`$(call SYSTEM_MAP,$(obj)u-boot) | \
 			awk '$$2 ~ /[tTwW]/ {printf $$1 $$3 "\\\\000"}'` ; \
 		$(CC) $(CFLAGS) -DSYSTEM_MAP="\"$${smap}\"" \
 			-c common/system_map.c -o $(obj)common/system_map.o
@@ -546,12 +557,6 @@ nand_spl:	$(TIMESTAMP_FILE) $(VERSION_FILE) depend
 $(obj)u-boot-nand.bin:	nand_spl $(obj)u-boot.bin
 		cat $(obj)nand_spl/u-boot-spl-16k.bin $(obj)u-boot.bin > $(obj)u-boot-nand.bin
 
-onenand_ipl:	$(TIMESTAMP_FILE) $(VERSION_FILE) $(obj)include/autoconf.mk
-		$(MAKE) -C onenand_ipl/board/$(BOARDDIR) all
-
-$(obj)u-boot-onenand.bin:	onenand_ipl $(obj)u-boot.bin
-		cat $(ONENAND_BIN) $(obj)u-boot.bin > $(obj)u-boot-onenand.bin
-
 $(obj)spl/u-boot-spl.bin:	$(SUBDIR_TOOLS) depend
 		$(MAKE) -C spl all
 
@@ -786,12 +791,6 @@ clean:
 	@rm -f $(obj)lib/asm-offsets.s
 	@rm -f $(obj)include/generated/asm-offsets.h
 	@rm -f $(obj)$(CPUDIR)/$(SOC)/asm-offsets.s
-	@rm -f $(obj)nand_spl/{u-boot.lds,u-boot-nand_spl.lds,u-boot-spl,u-boot-spl.map,System.map}
-	@rm -f $(obj)onenand_ipl/onenand-{ipl,ipl.bin,ipl.map}
-	@rm -f $(ONENAND_BIN)
-	@rm -f $(obj)onenand_ipl/u-boot.lds
-	@rm -f $(obj)spl/{u-boot-spl,u-boot-spl.bin,u-boot-spl.lds,u-boot-spl.map}
-	@rm -f $(obj)MLO
 	@rm -f $(TIMESTAMP_FILE) $(VERSION_FILE)
 	@find $(OBJTREE) -type f \
 		\( -name 'core' -o -name '*.bak' -o -name '*~' -o -name '*.su' \
@@ -810,19 +809,22 @@ clobber:	tidy
 		$(obj)cscope.* $(obj)*.*~
 	@rm -f $(obj)u-boot $(obj)u-boot.map $(obj)u-boot.hex $(ALL-y)
 	@rm -f $(obj)u-boot.kwb
+	@rm -f $(obj)u-boot.pbl
 	@rm -f $(obj)u-boot.imx
 	@rm -f $(obj)u-boot.ubl
 	@rm -f $(obj)u-boot.ais
 	@rm -f $(obj)u-boot.dtb
 	@rm -f $(obj)u-boot.sb
 	@rm -f $(obj)u-boot.spr
+	@rm -f $(obj)nand_spl/{u-boot.lds,u-boot-nand_spl.lds,u-boot-spl,u-boot-spl.map,System.map}
+	@rm -f $(obj)spl/{u-boot-spl,u-boot-spl.bin,u-boot-spl.lds,u-boot-spl.map}
+	@rm -f $(obj)MLO
 	@rm -f $(obj)tools/xway-swap-bytes
 	@rm -f $(obj)arch/powerpc/cpu/mpc824x/bedbug_603e.c
 	@rm -f $(obj)arch/powerpc/cpu/mpc83xx/ddr-gen?.c
 	@rm -fr $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm
 	@rm -fr $(obj)include/generated
 	@[ ! -d $(obj)nand_spl ] || find $(obj)nand_spl -name "*" -type l -print | xargs rm -f
-	@[ ! -d $(obj)onenand_ipl ] || find $(obj)onenand_ipl -name "*" -type l -print | xargs rm -f
 	@rm -f $(obj)dts/*.tmp
 	@rm -f $(obj)spl/u-boot-spl{,-pad}.ais
 

README

@@ -383,6 +383,31 @@ The following options need to be configured:
 		symbol should be set to the TLB1 entry to be used for this
 		purpose.
 
+		CONFIG_SYS_FSL_ERRATUM_A004510
+
+		Enables a workaround for erratum A004510.  If set,
+		then CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV and
+		CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY must be set.
+
+		CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV
+		CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 (optional)
+
+		Defines one or two SoC revisions (low 8 bits of SVR)
+		for which the A004510 workaround should be applied.
+
+		The rest of SVR is either not relevant to the decision
+		of whether the erratum is present (e.g. p2040 versus
+		p2041) or is implied by the build target, which controls
+		whether CONFIG_SYS_FSL_ERRATUM_A004510 is set.
+
+		See Freescale App Note 4493 for more information about
+		this erratum.
+
+		CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
+
+		This is the value to write into CCSR offset 0x18600
+		according to the A004510 workaround.
+
 - Generic CPU options:
 		CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
 
@@ -907,7 +932,8 @@ The following options need to be configured:
 		If this variable is defined, an environment variable
 		named "ver" is created by U-Boot showing the U-Boot
 		version as printed by the "version" command.
-		This variable is readonly.
+		Any change to this variable will be reverted at the
+		next reset.
 
 - Real-Time Clock:
 
@@ -950,13 +976,20 @@ The following options need to be configured:
 		commands like bootm or iminfo. This option is
 		automatically enabled when you select CONFIG_CMD_DATE .
 
-- Partition Support:
-		CONFIG_MAC_PARTITION and/or CONFIG_DOS_PARTITION
-		and/or CONFIG_ISO_PARTITION and/or CONFIG_EFI_PARTITION
+- Partition Labels (disklabels) Supported:
+		Zero or more of the following:
+		CONFIG_MAC_PARTITION   Apple's MacOS partition table.
+		CONFIG_DOS_PARTITION   MS Dos partition table, traditional on the
+				       Intel architecture, USB sticks, etc.
+		CONFIG_ISO_PARTITION   ISO partition table, used on CDROM etc.
+		CONFIG_EFI_PARTITION   GPT partition table, common when EFI is the
+				       bootloader.  Note 2TB partition limit; see
+				       disk/part_efi.c
+		CONFIG_MTD_PARTITIONS  Memory Technology Device partition table.
 
 		If IDE or SCSI support is enabled (CONFIG_CMD_IDE or
 		CONFIG_CMD_SCSI) you must configure support for at
-		least one partition type as well.
+		least one non-MTD partition type as well.
 
 - IDE Reset method:
 		CONFIG_IDE_RESET_ROUTINE - this is defined in several
@@ -1450,6 +1483,12 @@ The following options need to be configured:
 		can be displayed via the splashscreen support or the
 		bmp command.
 
+- Do compresssing for memory range:
+		CONFIG_CMD_ZIP
+
+		If this option is set, it would use zlib deflate method
+		to compress the specified memory at its best effort.
+
 - Compression support:
 		CONFIG_BZIP2
 
@@ -2564,6 +2603,15 @@ FIT uImage format:
 		CONFIG_SYS_SPL_MALLOC_SIZE
 		The size of the malloc pool used in SPL.
 
+		CONFIG_SPL_FRAMEWORK
+		Enable the SPL framework under common/.  This framework
+		supports MMC, NAND and YMODEM loading of U-Boot and NAND
+		NAND loading of the Linux Kernel.
+
+		CONFIG_SPL_DISPLAY_PRINT
+		For ARM, enable an optional function to print more information
+		about the running system.
+
 		CONFIG_SPL_LIBCOMMON_SUPPORT
 		Support for common/libcommon.o in SPL binary
 
@@ -2627,6 +2675,9 @@ FIT uImage format:
 		CONFIG_SPL_SPI_SUPPORT
 		Support for drivers/spi/libspi.o in SPL binary
 
+		CONFIG_SPL_RAM_DEVICE
+		Support for running image already present in ram, in SPL binary
+
 		CONFIG_SPL_LIBGENERIC_SUPPORT
 		Support for lib/libgeneric.o in SPL binary
 
@@ -3092,12 +3143,12 @@ to save the current settings.
 	  These two #defines specify the address and size of the
 	  environment area within the remote memory space. The
 	  local device can get the environment from remote memory
-	  space by SRIO or other links.
+	  space by SRIO or PCIE links.
 
 BE CAREFUL! For some special cases, the local device can not use
 "saveenv" command. For example, the local device will get the
-environment stored in a remote NOR flash by SRIO link, but it can
-not erase, write this NOR flash by SRIO interface.
+environment stored in a remote NOR flash by SRIO or PCIE link,
+but it can not erase, write this NOR flash by SRIO or PCIE interface.
 
 - CONFIG_ENV_IS_IN_NAND:
 
@@ -3377,6 +3428,13 @@ Low Level (hardware related) configuration options:
 		Disable PCI-Express on systems where it is supported but not
 		required.
 
+- CONFIG_PCI_ENUM_ONLY
+		Only scan through and get the devices on the busses.
+		Don't do any setup work, presumably because someone or
+		something has already done it, and we don't need to do it
+		a second time.	Useful for platforms that are pre-booted
+		by coreboot or similar.
+
 - CONFIG_SYS_SRIO:
 		Chip has SRIO or not
 
@@ -3538,9 +3596,9 @@ within that device.
 - CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 	Specifies that QE/FMAN firmware is located in the remote (master)
 	memory space.	CONFIG_SYS_FMAN_FW_ADDR is a virtual address which
-	can be mapped from slave TLB->slave LAW->slave SRIO outbound window
-	->master inbound window->master LAW->the ucode address in master's
-	NOR flash.
+	can be mapped from slave TLB->slave LAW->slave SRIO or PCIE outbound
+	window->master inbound window->master LAW->the ucode address in
+	master's memory space.
 
 Building the Software:
 ======================

arch/arm/cpu/arm1176/bcm2835/Makefile

@@ -17,7 +17,7 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(SOC).o
 
 SOBJS	:= lowlevel_init.o
-COBJS	:= reset.o timer.o
+COBJS	:= init.o reset.o timer.o
 
 SRCS	:= $(SOBJS:.o=.c) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))

arch/arm/cpu/arm1176/bcm2835/init.c

@@ -0,0 +1,24 @@
+/*
+ * (C) Copyright 2012 Stephen Warren
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+
+int arch_cpu_init(void)
+{
+	icache_enable();
+
+	return 0;
+}

arch/arm/cpu/arm1176/cpu.c

@@ -65,10 +65,3 @@ static void cache_flush (void)
 	/* mem barrier to sync things */
 	asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (0));
 }
-
-int arch_cpu_init(void)
-{
-	icache_enable();
-
-	return 0;
-}

arch/arm/cpu/arm926ejs/davinci/Makefile

@@ -37,7 +37,7 @@ COBJS-$(CONFIG_SOC_DA850)	+= da850_pinmux.o
 COBJS-$(CONFIG_DRIVER_TI_EMAC)	+= lxt972.o dp83848.o et1011c.o ksz8873.o
 
 ifdef CONFIG_SPL_BUILD
-COBJS-y	+= spl.o
+COBJS-$(CONFIG_SPL_FRAMEWORK)	+= spl.o
 COBJS-$(CONFIG_SOC_DM365)	+= dm365_lowlevel.o
 COBJS-$(CONFIG_SOC_DA8XX)	+= da850_lowlevel.o
 endif

arch/arm/cpu/arm926ejs/davinci/config.mk

@@ -0,0 +1,16 @@
+#
+# Copyright (C) 2012, Texas Instruments, Incorporated - http://www.ti.com/
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed "as is" WITHOUT ANY WARRANTY of any
+# kind, whether express or implied; without even the implied warranty
+# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+ifndef CONFIG_SPL_BUILD
+ALL-$(CONFIG_SPL_FRAMEWORK)	+= $(obj)u-boot.ais
+endif

arch/arm/cpu/arm926ejs/davinci/spl.c

@@ -21,6 +21,8 @@
  * MA 02111-1307 USA
  */
 #include <common.h>
+#include <config.h>
+#include <spl.h>
 #include <asm/u-boot.h>
 #include <asm/utils.h>
 #include <nand.h>
@@ -30,15 +32,9 @@
 #include <spi_flash.h>
 #include <mmc.h>
 
-#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
-
 DECLARE_GLOBAL_DATA_PTR;
-/* Define global data structure pointer to it*/
-static gd_t gdata __attribute__ ((section(".data")));
-static bd_t bdata __attribute__ ((section(".data")));
-
-#else
 
+#ifndef CONFIG_SPL_LIBCOMMON_SUPPORT
 void puts(const char *str)
 {
 	while (*str)
@@ -52,53 +48,49 @@ void putc(char c)
 
 	NS16550_putc((NS16550_t)(CONFIG_SYS_NS16550_COM1), c);
 }
-
 #endif /* CONFIG_SPL_LIBCOMMON_SUPPORT */
 
-inline void hang(void)
-{
-	puts("### ERROR ### Please RESET the board ###\n");
-	for (;;)
-		;
-}
-
 void board_init_f(ulong dummy)
 {
+	/* First, setup our stack pointer. */
+	asm volatile("mov sp, %0\n" : : "r"(CONFIG_SPL_STACK));
+
+	/* Second, perform our low-level init. */
 #ifdef CONFIG_SOC_DM365
 	dm36x_lowlevel_init(0);
 #endif
 #ifdef CONFIG_SOC_DA8XX
 	arch_cpu_init();
 #endif
-	relocate_code(CONFIG_SPL_STACK, NULL, CONFIG_SPL_TEXT_BASE);
-}
 
-void board_init_r(gd_t *id, ulong dummy)
-{
-#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
-	mem_malloc_init(CONFIG_SYS_TEXT_BASE - CONFIG_SYS_MALLOC_LEN,
-			CONFIG_SYS_MALLOC_LEN);
+	/* Third, we clear the BSS. */
+	memset(__bss_start, 0, __bss_end__ - __bss_start);
 
+	/* Finally, setup gd and move to the next step. */
 	gd = &gdata;
-	gd->bd = &bdata;
-	gd->flags |= GD_FLG_RELOC;
-	gd->baudrate = CONFIG_BAUDRATE;
-	serial_init();          /* serial communications setup */
-	gd->have_console = 1;
+	board_init_r(NULL, 0);
+}
 
-#endif
+void spl_board_init(void)
+{
+	preloader_console_init();
+}
 
-#ifdef CONFIG_SPL_NAND_LOAD
-	nand_init();
-	puts("Nand boot...\n");
-	nand_boot();
-#endif
-#ifdef CONFIG_SPL_SPI_LOAD
-	puts("SPI boot...\n");
-	spi_boot();
-#endif
-#ifdef CONFIG_SPL_MMC_LOAD
-	puts("MMC boot...\n");
-	spl_mmc_load();
+u32 spl_boot_mode(void)
+{
+	return MMCSD_MODE_RAW;
+}
+
+u32 spl_boot_device(void)
+{
+#ifdef CONFIG_SPL_NAND_SIMPLE
+	return BOOT_DEVICE_NAND;
+#elif defined(CONFIG_SPL_SPI_LOAD)
+	return BOOT_DEVICE_SPI;
+#elif defined(CONFIG_SPL_MMC_LOAD)
+	return BOOT_DEVICE_MMC1;
+#else
+	puts("Unknown boot device\n");
+	hang();
 #endif
 }

arch/arm/cpu/arm926ejs/start.S

@@ -215,6 +215,7 @@ call_board_init_f:
 
 /*------------------------------------------------------------------------------*/
 
+#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_NAND_SPL)
 /*
  * void relocate_code (addr_sp, gd, addr_moni)
  *
@@ -344,6 +345,7 @@ _rel_dyn_end_ofs:
 	.word __rel_dyn_end - _start
 _dynsym_start_ofs:
 	.word __dynsym_start - _start
+#endif
 
 /*
  *************************************************************************

arch/arm/cpu/armv7/am33xx/board.c

@@ -18,6 +18,7 @@
 
 #include <common.h>
 #include <errno.h>
+#include <spl.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/omap.h>
@@ -27,7 +28,6 @@
 #include <asm/arch/mmc_host_def.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/io.h>
-#include <asm/omap_common.h>
 #include <asm/emif.h>
 #include <asm/gpio.h>
 #include <i2c.h>
@@ -166,6 +166,8 @@ void s_init(void)
 	regVal |= UART_SMART_IDLE_EN;
 	writel(regVal, &uart_base->uartsyscfg);
 
+	gd = &gdata;
+
 	preloader_console_init();
 
 	/* Initalize the board header */

arch/arm/cpu/armv7/omap-common/Makefile

@@ -42,19 +42,6 @@ COBJS	+= boot-common.o
 SOBJS	+= lowlevel_init.o
 endif
 
-ifdef CONFIG_SPL_BUILD
-COBJS	+= spl.o
-ifdef CONFIG_SPL_NAND_SUPPORT
-COBJS	+= spl_nand.o
-endif
-ifdef CONFIG_SPL_MMC_SUPPORT
-COBJS	+= spl_mmc.o
-endif
-ifdef CONFIG_SPL_YMODEM_SUPPORT
-COBJS	+= spl_ymodem.o
-endif
-endif
-
 ifndef CONFIG_SPL_BUILD
 ifneq ($(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
 COBJS	+= mem-common.o

arch/arm/cpu/armv7/omap-common/boot-common.c

@@ -17,8 +17,10 @@
  */
 
 #include <common.h>
+#include <spl.h>
 #include <asm/omap_common.h>
 #include <asm/arch/omap.h>
+#include <asm/arch/mmc_host_def.h>
 
 /*
  * This is used to verify if the configuration header
@@ -37,13 +39,34 @@ struct omap_boot_parameters boot_params __attribute__ ((section(".data")));
  */
 u32 omap_bootmode = MMCSD_MODE_FAT;
 
-u32 omap_boot_device(void)
+u32 spl_boot_device(void)
 {
 	return (u32) (boot_params.omap_bootdevice);
 }
 
-u32 omap_boot_mode(void)
+u32 spl_boot_mode(void)
 {
 	return omap_bootmode;
 }
+
+void spl_board_init(void)
+{
+#ifdef CONFIG_SPL_NAND_SUPPORT
+	gpmc_init();
+#endif
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	switch (spl_boot_device()) {
+	case BOOT_DEVICE_MMC1:
+		omap_mmc_init(0, 0, 0);
+		break;
+	case BOOT_DEVICE_MMC2:
+	case BOOT_DEVICE_MMC2_2:
+		omap_mmc_init(1, 0, 0);
+		break;
+	}
+	return 0;
+}
 #endif

arch/arm/cpu/armv7/omap-common/hwinit-common.c

@@ -28,10 +28,10 @@
  * MA 02111-1307 USA
  */
 #include <common.h>
+#include <spl.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/sizes.h>
 #include <asm/emif.h>
-#include <asm/omap_common.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -92,6 +92,11 @@ static void init_boot_params(void)
 {
 	boot_params_ptr = (u32 *) &boot_params;
 }
+
+void spl_display_print(void)
+{
+	omap_rev_string();
+}
 #endif
 
 /*
@@ -119,6 +124,9 @@ void s_init(void)
 	set_mux_conf_regs();
 #ifdef CONFIG_SPL_BUILD
 	setup_clocks_for_console();
+
+	gd = &gdata;
+
 	preloader_console_init();
 	do_io_settings();
 #endif

arch/arm/cpu/armv7/omap-common/lowlevel_init.S

@@ -52,18 +52,18 @@ ENTRY(save_boot_params)
 	ldr	r1, =boot_params
 	str	r0, [r1]
 #ifdef CONFIG_SPL_BUILD
-	/* Store the boot device in omap_boot_device */
+	/* Store the boot device in spl_boot_device */
 	ldrb	r2, [r0, #BOOT_DEVICE_OFFSET]	@ r1 <- value of boot device
 	and	r2, #BOOT_DEVICE_MASK
 	ldr	r3, =boot_params
-	strb	r2, [r3, #BOOT_DEVICE_OFFSET]	@ omap_boot_device <- r1
+	strb	r2, [r3, #BOOT_DEVICE_OFFSET]	@ spl_boot_device <- r1
 
 	/* boot mode is passed only for devices that can raw/fat mode */
 	cmp	r2, #2
 	blt	2f
 	cmp	r2, #7
 	bgt	2f
-	/* Store the boot mode (raw/FAT) in omap_boot_mode */
+	/* Store the boot mode (raw/FAT) in omap_bootmode */
 	ldr	r2, [r0, #DEV_DESC_PTR_OFFSET]	@ get the device descriptor ptr
 	ldr	r2, [r2, #DEV_DATA_PTR_OFFSET]	@ get the pDeviceData ptr
 	ldr	r2, [r2, #BOOT_MODE_OFFSET]	@ get the boot mode

arch/arm/cpu/armv7/omap-common/u-boot-spl.lds

@@ -37,9 +37,9 @@ SECTIONS
 {
 	.text      :
 	{
-	__start = .;
-	  arch/arm/cpu/armv7/start.o	(.text)
-	  *(.text*)
+		__start = .;
+		arch/arm/cpu/armv7/start.o	(.text)
+		*(.text*)
 	} >.sram
 
 	. = ALIGN(4);

arch/arm/cpu/armv7/omap3/board.c

@@ -33,6 +33,7 @@
  * MA 02111-1307 USA
  */
 #include <common.h>
+#include <spl.h>
 #include <asm/io.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/mem.h>
@@ -40,9 +41,12 @@
 #include <asm/armv7.h>
 #include <asm/arch/gpio.h>
 #include <asm/omap_common.h>
+#include <asm/arch/mmc_host_def.h>
 #include <i2c.h>
 #include <linux/compiler.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* Declarations */
 extern omap3_sysinfo sysinfo;
 static void omap3_setup_aux_cr(void);
@@ -69,30 +73,44 @@ const struct gpio_bank *const omap_gpio_bank = gpio_bank_34xx;
 u32 omap3_boot_device = BOOT_DEVICE_NAND;
 
 /* auto boot mode detection is not possible for OMAP3 - hard code */
-u32 omap_boot_mode(void)
+u32 spl_boot_mode(void)
 {
-	switch (omap_boot_device()) {
+	switch (spl_boot_device()) {
 	case BOOT_DEVICE_MMC2:
 		return MMCSD_MODE_RAW;
 	case BOOT_DEVICE_MMC1:
 		return MMCSD_MODE_FAT;
 		break;
-	case BOOT_DEVICE_NAND:
-		return NAND_MODE_HW_ECC;
-		break;
 	default:
 		puts("spl: ERROR:  unknown device - can't select boot mode\n");
 		hang();
 	}
 }
 
-u32 omap_boot_device(void)
+u32 spl_boot_device(void)
 {
 	return omap3_boot_device;
 }
 
+int board_mmc_init(bd_t *bis)
+{
+	switch (spl_boot_device()) {
+	case BOOT_DEVICE_MMC1:
+		omap_mmc_init(0, 0, 0);
+		break;
+	case BOOT_DEVICE_MMC2:
+	case BOOT_DEVICE_MMC2_2:
+		omap_mmc_init(1, 0, 0);
+		break;
+	}
+	return 0;
+}
+
 void spl_board_init(void)
 {
+#ifdef CONFIG_SPL_NAND_SUPPORT
+	gpmc_init();
+#endif
 #ifdef CONFIG_SPL_I2C_SUPPORT
 	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 #endif
@@ -236,6 +254,8 @@ void s_init(void)
 #endif
 
 #ifdef CONFIG_SPL_BUILD
+	gd = &gdata;
+
 	preloader_console_init();
 
 	timer_init();

arch/arm/cpu/armv7/start.S

@@ -164,6 +164,7 @@ call_board_init_f:
 
 /*------------------------------------------------------------------------------*/
 
+#ifndef CONFIG_SPL_BUILD
 /*
  * void relocate_code (addr_sp, gd, addr_moni)
  *
@@ -194,7 +195,6 @@ copy_loop:
 	cmp	r0, r2			/* until source end address [r2]    */
 	blo	copy_loop
 
-#ifndef CONFIG_SPL_BUILD
 	/*
 	 * fix .rel.dyn relocations
 	 */
@@ -241,20 +241,12 @@ _rel_dyn_end_ofs:
 _dynsym_start_ofs:
 	.word __dynsym_start - _start
 
-#endif	/* #ifndef CONFIG_SPL_BUILD */
-
 clear_bss:
-#ifdef CONFIG_SPL_BUILD
-	/* No relocation for SPL */
-	ldr	r0, =__bss_start
-	ldr	r1, =__bss_end__
-#else
 	ldr	r0, _bss_start_ofs
 	ldr	r1, _bss_end_ofs
 	mov	r4, r6			/* reloc addr */
 	add	r0, r0, r4
 	add	r1, r1, r4
-#endif
 	mov	r2, #0x00000000		/* clear			    */
 
 clbss_l:cmp	r0, r1			/* clear loop... */
@@ -281,12 +273,10 @@ jump_2_ram:
  * Move vector table
  */
 #if !defined(CONFIG_TEGRA20)
-#if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD))
 	/* Set vector address in CP15 VBAR register */
 	ldr     r0, =_start
 	add     r0, r0, r9
 	mcr     p15, 0, r0, c12, c0, 0  @Set VBAR
-#endif
 #endif /* !Tegra20 */
 
 	ldr	r0, _board_init_r_ofs
@@ -302,6 +292,7 @@ jump_2_ram:
 _board_init_r_ofs:
 	.word board_init_r - _start
 ENDPROC(relocate_code)
+#endif
 
 /*************************************************************************
  *

arch/arm/include/asm/arch-am33xx/spl.h

@@ -0,0 +1,31 @@
+/*
+ * (C) Copyright 2012
+ * Texas Instruments, <www.ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef	_ASM_ARCH_SPL_H_
+#define	_ASM_SPL_H_
+
+#define BOOT_DEVICE_NAND	5
+#define BOOT_DEVICE_MMC1	8
+#define BOOT_DEVICE_MMC2	9	/* eMMC or daughter card */
+#define BOOT_DEVICE_UART	65
+#define BOOT_DEVICE_MMC2_2      0xFF
+#endif

onenand_ipl/board/apollon/u-boot.onenand.lds → arch/arm/include/asm/arch-davinci/spl.h

@@ -1,8 +1,6 @@
 /*
- * (C) Copyright 2005-2008 Samsung Electronics
- * Kyungmin Park <kyungmin.park@samsung.com>
- *
- * Derived from X-loader
+ * (C) Copyright 2012
+ * Texas Instruments, <www.ti.com>
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -14,7 +12,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -22,32 +20,13 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
+#ifndef	_ASM_ARCH_SPL_H_
+#define	_ASM_SPL_H_
 
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN(4);
-	.text      :
-	{
-	  start.o	(.text)
-	  *(.text)
-	}
-
-	. = ALIGN(4);
-	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
-	. = ALIGN(4);
-	.data : { *(.data) }
-
-	. = ALIGN(4);
-	.got : { *(.got) }
+#define BOOT_DEVICE_NAND	1
+#define BOOT_DEVICE_SPI		2
+#define BOOT_DEVICE_MMC1	3
+#define BOOT_DEVICE_MMC2	4	/* dummy */
+#define BOOT_DEVICE_MMC2_2	5	/* dummy */
 
-	. = ALIGN(4);
-	__bss_start = .;
-	.bss : { *(.bss) . = ALIGN(4); }
-	__bss_end__ = .;
-}
+#endif

arch/arm/include/asm/arch-exynos/mmc.h

@@ -64,11 +64,11 @@
 #define SDHCI_CTRL4_DRIVE_MASK(_x)	((_x) << 16)
 #define SDHCI_CTRL4_DRIVE_SHIFT		(16)
 
-int s5p_sdhci_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks);
+int s5p_sdhci_init(u32 regbase, int index, int bus_width);
 
 static inline unsigned int s5p_mmc_init(int index, int bus_width)
 {
 	unsigned int base = samsung_get_base_mmc() + (0x10000 * index);
-	return s5p_sdhci_init(base, 52000000, 400000, index);
+	return s5p_sdhci_init(base, index, bus_width);
 }
 #endif

arch/arm/include/asm/arch-omap24xx/omap2420.h

@@ -228,16 +228,6 @@
 #define LAN_RESET_REGISTER    (H4_CS1_BASE+0x1c)
 #endif  /* endif CONFIG_2420H4 */
 
-#if defined(CONFIG_APOLLON)
-#define APOLLON_CS0_BASE	0x00000000	/* OneNAND */
-#define APOLLON_CS1_BASE	0x08000000	/* ethernet */
-#define APOLLON_CS2_BASE	0x10000000	/* OneNAND */
-#define APOLLON_CS3_BASE	0x18000000	/* NOR */
-
-#define ETH_CONTROL_REG		(APOLLON_CS1_BASE + 0x30b)
-#define LAN_RESET_REGISTER	(APOLLON_CS1_BASE + 0x1c)
-#endif	/* endif CONFIG_APOLLON */
-
 /* Common */
 #define LOW_LEVEL_SRAM_STACK  0x4020FFFC
 

arch/arm/include/asm/arch-omap3/spl.h

@@ -0,0 +1,34 @@
+/*
+ * (C) Copyright 2012
+ * Texas Instruments, <www.ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef	_ASM_ARCH_SPL_H_
+#define	_ASM_SPL_H_
+
+#define BOOT_DEVICE_NONE	0
+#define BOOT_DEVICE_XIP		1
+#define BOOT_DEVICE_NAND	2
+#define BOOT_DEVICE_ONE_NAND	3
+#define BOOT_DEVICE_MMC2	5 /*emmc*/
+#define BOOT_DEVICE_MMC1	6
+#define BOOT_DEVICE_XIPWAIT	7
+#define BOOT_DEVICE_MMC2_2      0xFF
+#endif

arch/arm/include/asm/arch-omap4/cpu.h

@@ -138,6 +138,7 @@ struct watchdog {
 #define I2C_BASE1		(OMAP44XX_L4_PER_BASE + 0x70000)
 #define I2C_BASE2		(OMAP44XX_L4_PER_BASE + 0x72000)
 #define I2C_BASE3		(OMAP44XX_L4_PER_BASE + 0x60000)
+#define I2C_BASE4		(OMAP44XX_L4_PER_BASE + 0x350000)
 
 /* MUSB base */
 #define MUSB_BASE		(OMAP44XX_L4_CORE_BASE + 0xAB000)

arch/arm/include/asm/arch-omap4/i2c.h

@@ -23,7 +23,7 @@
 #ifndef _OMAP4_I2C_H_
 #define _OMAP4_I2C_H_
 
-#define I2C_BUS_MAX	3
+#define I2C_BUS_MAX	4
 #define I2C_DEFAULT_BASE	I2C_BASE1
 
 struct i2c {

include/configs/P3060QDS.h → arch/arm/include/asm/arch-omap4/spl.h

@@ -1,5 +1,6 @@
 /*
- * Copyright 2011 Freescale Semiconductor, Inc.
+ * (C) Copyright 2012
+ * Texas Instruments, <www.ti.com>
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -19,30 +20,16 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
+#ifndef	_ASM_ARCH_SPL_H_
+#define	_ASM_SPL_H_
 
-/*
- * P3060 QDS board configuration file
- */
-#define CONFIG_P3060QDS
-#define CONFIG_PHYS_64BIT
-#define CONFIG_PPC_P3060
-#define CONFIG_FSL_QIXIS
-
-#define CONFIG_NAND_FSL_ELBC
-
-#define CONFIG_ICS307_REFCLK_HZ	25000000  /* ICS307 ref clk freq */
-
-#define CONFIG_SPI_FLASH_ATMEL
-#define CONFIG_SPI_FLASH_EON
-#define CONFIG_SPI_FLASH_SST
-
-#include "corenet_ds.h"
-
-#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
-#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
-#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
-#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
+#define BOOT_DEVICE_NONE	0
+#define BOOT_DEVICE_XIP		1
+#define BOOT_DEVICE_XIPWAIT	2
+#define BOOT_DEVICE_NAND	3
+#define BOOT_DEVICE_ONE_NAND	4
+#define BOOT_DEVICE_MMC1	5
+#define BOOT_DEVICE_MMC2	6
+#define BOOT_DEVICE_MMC2_2	0xFF
 
-/* There is a PCA9547 8-channel I2C-bus multiplexer on P3060QDS board */
-#define CONFIG_I2C_MUX
-#define CONFIG_I2C_MULTI_BUS
+#endif

arch/arm/include/asm/arch-omap4/sys_proto.h

@@ -42,7 +42,6 @@ void sr32(void *, u32, u32, u32);
 u32 wait_on_value(u32, u32, void *, u32);
 void sdelay(unsigned long);
 void set_pl310_ctrl_reg(u32 val);
-void omap_rev_string(void);
 void setup_clocks_for_console(void);
 void prcm_init(void);
 void bypass_dpll(u32 *const base);

arch/arm/include/asm/arch-omap5/spl.h

@@ -0,0 +1,35 @@
+/*
+ * (C) Copyright 2012
+ * Texas Instruments, <www.ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef	_ASM_ARCH_SPL_H_
+#define	_ASM_SPL_H_
+
+#define BOOT_DEVICE_NONE        0
+#define BOOT_DEVICE_XIP         1
+#define BOOT_DEVICE_XIPWAIT     2
+#define BOOT_DEVICE_NAND        3
+#define BOOT_DEVICE_ONE_NAND    4
+#define BOOT_DEVICE_MMC1        5
+#define BOOT_DEVICE_MMC2        6
+#define BOOT_DEVICE_MMC2_2	7
+
+#endif

arch/arm/include/asm/arch-omap5/sys_proto.h

@@ -42,7 +42,6 @@ void set_muxconf_regs_non_essential(void);
 void sr32(void *, u32, u32, u32);
 u32 wait_on_value(u32, u32, void *, u32);
 void sdelay(unsigned long);
-void omap_rev_string(void);
 void setup_clocks_for_console(void);
 void prcm_init(void);
 void bypass_dpll(u32 *const base);

arch/arm/include/asm/arch-pxa/regs-usb.h

@@ -0,0 +1,159 @@
+/*
+ * PXA25x UDC definitions
+ *
+ * Copyright (C) 2012 Łukasz Dałek <luk0104@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __REGS_USB_H__
+#define __REGS_USB_H__
+
+struct pxa25x_udc_regs {
+	/* UDC Control Register */
+	uint32_t	udccr; /* 0x000 */
+	uint32_t	reserved1;
+
+	/* UDC Control Function Register */
+	uint32_t	udccfr; /* 0x008 */
+	uint32_t	reserved2;
+
+	/* UDC Endpoint Control/Status Registers */
+	uint32_t	udccs[16]; /* 0x010 - 0x04c */
+
+	/* UDC Interrupt Control/Status Registers */
+	uint32_t	uicr0; /* 0x050 */
+	uint32_t	uicr1; /* 0x054 */
+	uint32_t	usir0; /* 0x058 */
+	uint32_t	usir1; /* 0x05c */
+
+	/* UDC Frame Number/Byte Count Registers */
+	uint32_t	ufnrh;  /* 0x060 */
+	uint32_t	ufnrl;  /* 0x064 */
+	uint32_t	ubcr2;  /* 0x068 */
+	uint32_t	ubcr4;  /* 0x06c */
+	uint32_t	ubcr7;  /* 0x070 */
+	uint32_t	ubcr9;  /* 0x074 */
+	uint32_t	ubcr12; /* 0x078 */
+	uint32_t	ubcr14; /* 0x07c */
+
+	/* UDC Endpoint Data Registers */
+	uint32_t	uddr0;  /* 0x080 */
+	uint32_t	reserved3[7];
+	uint32_t	uddr5;  /* 0x0a0 */
+	uint32_t	reserved4[7];
+	uint32_t	uddr10; /* 0x0c0 */
+	uint32_t	reserved5[7];
+	uint32_t	uddr15; /* 0x0e0 */
+	uint32_t	reserved6[7];
+	uint32_t	uddr1;  /* 0x100 */
+	uint32_t	reserved7[31];
+	uint32_t	uddr2;  /* 0x180 */
+	uint32_t	reserved8[31];
+	uint32_t	uddr3;  /* 0x200 */
+	uint32_t	reserved9[127];
+	uint32_t	uddr4;  /* 0x400 */
+	uint32_t	reserved10[127];
+	uint32_t	uddr6;  /* 0x600 */
+	uint32_t	reserved11[31];
+	uint32_t	uddr7;  /* 0x680 */
+	uint32_t	reserved12[31];
+	uint32_t	uddr8;  /* 0x700 */
+	uint32_t	reserved13[127];
+	uint32_t	uddr9;  /* 0x900 */
+	uint32_t	reserved14[127];
+	uint32_t	uddr11; /* 0xb00 */
+	uint32_t	reserved15[31];
+	uint32_t	uddr12; /* 0xb80 */
+	uint32_t	reserved16[31];
+	uint32_t	uddr13; /* 0xc00 */
+	uint32_t	reserved17[127];
+	uint32_t	uddr14; /* 0xe00 */
+
+};
+
+#define PXA25X_UDC_BASE		0x40600000
+
+#define UDCCR_UDE		(1 << 0)
+#define UDCCR_UDA		(1 << 1)
+#define UDCCR_RSM		(1 << 2)
+#define UDCCR_RESIR		(1 << 3)
+#define UDCCR_SUSIR		(1 << 4)
+#define UDCCR_SRM		(1 << 5)
+#define UDCCR_RSTIR		(1 << 6)
+#define UDCCR_REM		(1 << 7)
+
+/* Bulk IN endpoint 1/6/11 */
+#define UDCCS_BI_TSP		(1 << 7)
+#define UDCCS_BI_FST		(1 << 5)
+#define UDCCS_BI_SST		(1 << 4)
+#define UDCCS_BI_TUR		(1 << 3)
+#define UDCCS_BI_FTF		(1 << 2)
+#define UDCCS_BI_TPC		(1 << 1)
+#define UDCCS_BI_TFS		(1 << 0)
+
+/* Bulk OUT endpoint 2/7/12 */
+#define UDCCS_BO_RSP		(1 << 7)
+#define UDCCS_BO_RNE		(1 << 6)
+#define UDCCS_BO_FST		(1 << 5)
+#define UDCCS_BO_SST		(1 << 4)
+#define UDCCS_BO_DME		(1 << 3)
+#define UDCCS_BO_RPC		(1 << 1)
+#define UDCCS_BO_RFS		(1 << 0)
+
+/* Isochronous OUT endpoint 4/9/14 */
+#define UDCCS_IO_RSP		(1 << 7)
+#define UDCCS_IO_RNE		(1 << 6)
+#define UDCCS_IO_DME		(1 << 3)
+#define UDCCS_IO_ROF		(1 << 2)
+#define UDCCS_IO_RPC		(1 << 1)
+#define UDCCS_IO_RFS		(1 << 0)
+
+/* Control endpoint 0 */
+#define UDCCS0_OPR		(1 << 0)
+#define UDCCS0_IPR		(1 << 1)
+#define UDCCS0_FTF		(1 << 2)
+#define UDCCS0_DRWF		(1 << 3)
+#define UDCCS0_SST		(1 << 4)
+#define UDCCS0_FST		(1 << 5)
+#define UDCCS0_RNE		(1 << 6)
+#define UDCCS0_SA		(1 << 7)
+
+#define UICR0_IM0		(1 << 0)
+
+#define USIR0_IR0		(1 << 0)
+#define USIR0_IR1		(1 << 1)
+#define USIR0_IR2		(1 << 2)
+#define USIR0_IR3		(1 << 3)
+#define USIR0_IR4		(1 << 4)
+#define USIR0_IR5		(1 << 5)
+#define USIR0_IR6		(1 << 6)
+#define USIR0_IR7		(1 << 7)
+
+#define UDCCFR_AREN		(1 << 7) /* ACK response enable (now) */
+#define UDCCFR_ACM		(1 << 2) /* ACK control mode (wait for AREN) */
+/*
+ * Intel(R) PXA255 Processor Specification, September 2003 (page 31)
+ * define new "must be one" bits in UDCCFR (see Table 12-13.)
+ */
+#define UDCCFR_MB1		(0xff & ~(UDCCFR_AREN | UDCCFR_ACM))
+
+#define UFNRH_SIR		(1 << 7)	/* SOF interrupt request */
+#define UFNRH_SIM		(1 << 6)	/* SOF interrupt mask */
+#define UFNRH_IPE14		(1 << 5)	/* ISO packet error, ep14 */
+#define UFNRH_IPE9		(1 << 4)	/* ISO packet error, ep9 */
+#define UFNRH_IPE4		(1 << 3)	/* ISO packet error, ep4 */
+
+#endif /* __REGS_USB_H__ */

arch/arm/include/asm/arch-s5pc1xx/mmc.h

@@ -64,11 +64,11 @@
 #define SDHCI_CTRL4_DRIVE_MASK(_x)	((_x) << 16)
 #define SDHCI_CTRL4_DRIVE_SHIFT		(16)
 
-int s5p_sdhci_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks);
+int s5p_sdhci_init(u32 regbase, int index, int bus_width);
 
 static inline unsigned int s5p_mmc_init(int index, int bus_width)
 {
 	unsigned int base = samsung_get_base_mmc() + (0x10000 * index);
-	return s5p_sdhci_init(base, 52000000, 400000, index);
+	return s5p_sdhci_init(base, index, bus_width);
 }
 #endif

arch/arm/include/asm/omap_common.h

@@ -34,83 +34,6 @@
 #define OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL	2
 #define OMAP_INIT_CONTEXT_UBOOT_AFTER_CH	3
 
-void preloader_console_init(void);
-
-/* Boot device */
-#ifdef CONFIG_OMAP54XX
-#define BOOT_DEVICE_NONE        0
-#define BOOT_DEVICE_XIP         1
-#define BOOT_DEVICE_XIPWAIT     2
-#define BOOT_DEVICE_NAND        3
-#define BOOT_DEVICE_ONE_NAND    4
-#define BOOT_DEVICE_MMC1        5
-#define BOOT_DEVICE_MMC2        6
-#define BOOT_DEVICE_MMC2_2	7
-#elif defined(CONFIG_OMAP44XX) /* OMAP4 */
-#define BOOT_DEVICE_NONE	0
-#define BOOT_DEVICE_XIP		1
-#define BOOT_DEVICE_XIPWAIT	2
-#define BOOT_DEVICE_NAND	3
-#define BOOT_DEVICE_ONE_NAND	4
-#define BOOT_DEVICE_MMC1	5
-#define BOOT_DEVICE_MMC2	6
-#define BOOT_DEVICE_MMC2_2	0xFF
-#elif defined(CONFIG_OMAP34XX)	/* OMAP3 */
-#define BOOT_DEVICE_NONE	0
-#define BOOT_DEVICE_XIP		1
-#define BOOT_DEVICE_NAND	2
-#define BOOT_DEVICE_ONE_NAND	3
-#define BOOT_DEVICE_MMC2	5 /*emmc*/
-#define BOOT_DEVICE_MMC1	6
-#define BOOT_DEVICE_XIPWAIT	7
-#define BOOT_DEVICE_MMC2_2      0xFF
-#elif defined(CONFIG_AM33XX)	/* AM33XX */
-#define BOOT_DEVICE_NAND	5
-#define BOOT_DEVICE_MMC1	8
-#define BOOT_DEVICE_MMC2	9 /* eMMC or daughter card */
-#define BOOT_DEVICE_UART	65
-#define BOOT_DEVICE_MMC2_2      0xFF
-#endif
-
-/* Boot type */
-#define	MMCSD_MODE_UNDEFINED	0
-#define MMCSD_MODE_RAW		1
-#define MMCSD_MODE_FAT		2
-#define NAND_MODE_HW_ECC	3
-
-struct spl_image_info {
-	const char *name;
-	u8 os;
-	u32 load_addr;
-	u32 entry_point;
-	u32 size;
-};
-
-extern struct spl_image_info spl_image;
-
-extern u32* boot_params_ptr;
-u32 omap_boot_device(void);
-u32 omap_boot_mode(void);
-
-/* SPL common function s*/
-void spl_parse_image_header(const struct image_header *header);
-void omap_rev_string(void);
-void spl_board_prepare_for_linux(void);
-int spl_start_uboot(void);
-
-/* NAND SPL functions */
-void spl_nand_load_image(void);
-
-/* MMC SPL functions */
-void spl_mmc_load_image(void);
-
-/* YMODEM SPL functions */
-void spl_ymodem_load_image(void);
-
-#ifdef CONFIG_SPL_BOARD_INIT
-void spl_board_init(void);
-#endif
-
 static inline u32 omap_revision(void)
 {
 	extern u32 *const omap_si_rev;

board/freescale/p3060qds/p3060qds.h → arch/arm/include/asm/spl.h

@@ -1,5 +1,9 @@
 /*
- * Copyright 2011 Freescale Semiconductor, Inc.
+ * (C) Copyright 2012
+ * Texas Instruments, <www.ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
@@ -8,7 +12,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -16,15 +20,15 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
+#ifndef	_ASM_SPL_H_
+#define	_ASM_SPL_H_
 
-#ifndef __P3060QDS_H__
-#define __P3060QDS_H__
+/* Platform-specific defines */
+#include <asm/arch/spl.h>
 
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/u-boot.h>
+/* Linker symbols. */
+extern char __bss_start[], __bss_end__[];
 
-void fdt_fixup_board_enet(void *blob);
-void pci_of_setup(void *blob, bd_t *bd);
-extern fixed_ddr_parm_t fixed_ddr_parm_0[];
+extern gd_t gdata;
 
 #endif

arch/arm/lib/Makefile

@@ -44,6 +44,8 @@ COBJS-y	+= interrupts.o
 COBJS-y	+= reset.o
 SOBJS-$(CONFIG_USE_ARCH_MEMSET) += memset.o
 SOBJS-$(CONFIG_USE_ARCH_MEMCPY) += memcpy.o
+else
+COBJS-$(CONFIG_SPL_FRAMEWORK) += spl.o
 endif
 
 COBJS-y	+= cache.o

arch/arm/lib/spl.c

@@ -0,0 +1,72 @@
+/*
+ * (C) Copyright 2010-2012
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <aneesh@ti.com>
+ * Tom Rini <trini@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <config.h>
+#include <spl.h>
+#include <image.h>
+#include <linux/compiler.h>
+
+/* Pointer to as well as the global data structure for SPL */
+DECLARE_GLOBAL_DATA_PTR;
+gd_t gdata __attribute__ ((section(".data")));
+
+/*
+ * In the context of SPL, board_init_f must ensure that any clocks/etc for
+ * DDR are enabled, ensure that the stack pointer is valid, clear the BSS
+ * and call board_init_f.  We provide this version by default but mark it
+ * as __weak to allow for platforms to do this in their own way if needed.
+ */
+void __weak board_init_f(ulong dummy)
+{
+	/* Set the stack pointer. */
+	asm volatile("mov sp, %0\n" : : "r"(CONFIG_SPL_STACK));
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end__ - __bss_start);
+
+	/* Set global data pointer. */
+	gd = &gdata;
+
+	board_init_r(NULL, 0);
+}
+
+/*
+ * This function jumps to an image with argument. Normally an FDT or ATAGS
+ * image.
+ * arg: Pointer to paramter image in RAM
+ */
+#ifdef CONFIG_SPL_OS_BOOT
+void __noreturn jump_to_image_linux(void *arg)
+{
+	debug("Entering kernel arg pointer: 0x%p\n", arg);
+	typedef void (*image_entry_arg_t)(int, int, void *)
+		__attribute__ ((noreturn));
+	image_entry_arg_t image_entry =
+		(image_entry_arg_t) spl_image.entry_point;
+	cleanup_before_linux();
+	image_entry(0, CONFIG_MACH_TYPE, arg);
+}
+#endif

arch/avr32/config.mk

@@ -29,5 +29,3 @@ PLATFORM_RELFLAGS	+= -ffixed-r5 -fPIC -mno-init-got -mrelax
 PLATFORM_RELFLAGS	+= -ffunction-sections -fdata-sections
 
 LDFLAGS_u-boot		= --gc-sections --relax
-
-LDSCRIPT			= $(SRCTREE)/$(CPUDIR)/u-boot.lds

arch/avr32/cpu/at32ap700x/portmux.c

@@ -122,7 +122,7 @@ void portmux_enable_macb1(unsigned long flags, unsigned long drive_strength)
 		portd_mask |= (1 << 15);/* SPD	*/
 
 	/* REVISIT: Some pins are probably pure outputs */
-	portmux_select_peripheral(PORTMUX_PORT_D, portc_mask,
+	portmux_select_peripheral(PORTMUX_PORT_D, portd_mask,
 			PORTMUX_FUNC_B, PORTMUX_BUSKEEPER);
 	portmux_select_peripheral(PORTMUX_PORT_C, portc_mask,
 			PORTMUX_FUNC_B, PORTMUX_BUSKEEPER);

arch/avr32/lib/board.c

@@ -250,7 +250,6 @@ void board_init_f(ulong board_type)
 
 void board_init_r(gd_t *new_gd, ulong dest_addr)
 {
-	extern void malloc_bin_reloc (void);
 #ifndef CONFIG_ENV_IS_NOWHERE
 	extern char * env_name_spec;
 #endif

arch/m68k/cpu/mcf5227x/cpu.c

@@ -3,7 +3,7 @@
  * (C) Copyright 2000-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -30,14 +30,15 @@
 #include <command.h>
 
 #include <asm/immap.h>
+#include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
-	volatile rcm_t *rcm = (rcm_t *) (MMAP_RCM);
+	rcm_t *rcm = (rcm_t *) (MMAP_RCM);
 	udelay(1000);
-	rcm->rcr |= RCM_RCR_SOFTRST;
+	setbits_8(&rcm->rcr, RCM_RCR_SOFTRST);
 
 	/* we don't return! */
 	return 0;
@@ -45,14 +46,14 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 int checkcpu(void)
 {
-	volatile ccm_t *ccm = (ccm_t *) MMAP_CCM;
+	ccm_t *ccm = (ccm_t *) MMAP_CCM;
 	u16 msk;
 	u16 id = 0;
 	u8 ver;
 
 	puts("CPU:   ");
-	msk = (ccm->cir >> 6);
-	ver = (ccm->cir & 0x003f);
+	msk = (in_be16(&ccm->cir) >> 6);
+	ver = (in_be16(&ccm->cir) & 0x003f);
 	switch (msk) {
 	case 0x6c:
 		id = 52277;

arch/m68k/cpu/mcf5227x/cpu_init.c

@@ -3,7 +3,7 @@
  * (C) Copyright 2000-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * (C) Copyright 2004-2007 Freescale Semiconductor, Inc.
+ * (C) Copyright 2004-2007, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -29,6 +29,7 @@
 #include <watchdog.h>
 
 #include <asm/immap.h>
+#include <asm/io.h>
 #include <asm/rtc.h>
 
 /*
@@ -40,70 +41,70 @@
  */
 void cpu_init_f(void)
 {
-	volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
-	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-	volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
-	volatile pll_t *pll = (volatile pll_t *)MMAP_PLL;
+	scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
+	pll_t *pll = (pll_t *)MMAP_PLL;
 
 #if !defined(CONFIG_CF_SBF)
 	/* Workaround, must place before fbcs */
-	pll->psr = 0x12;
-
-	scm1->mpr = 0x77777777;
-	scm1->pacra = 0;
-	scm1->pacrb = 0;
-	scm1->pacrc = 0;
-	scm1->pacrd = 0;
-	scm1->pacre = 0;
-	scm1->pacrf = 0;
-	scm1->pacrg = 0;
-	scm1->pacri = 0;
+	out_be32(&pll->psr, 0x12);
+
+	out_be32(&scm1->mpr, 0x77777777);
+	out_be32(&scm1->pacra, 0);
+	out_be32(&scm1->pacrb, 0);
+	out_be32(&scm1->pacrc, 0);
+	out_be32(&scm1->pacrd, 0);
+	out_be32(&scm1->pacre, 0);
+	out_be32(&scm1->pacrf, 0);
+	out_be32(&scm1->pacrg, 0);
+	out_be32(&scm1->pacri, 0);
 
 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
      && defined(CONFIG_SYS_CS0_CTRL))
-	fbcs->csar0 = CONFIG_SYS_CS0_BASE;
-	fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
-	fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
+	out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
+	out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
+	out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
 #endif
 #endif				/* CONFIG_CF_SBF */
 
 #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
      && defined(CONFIG_SYS_CS1_CTRL))
-	fbcs->csar1 = CONFIG_SYS_CS1_BASE;
-	fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
-	fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
+	out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
+	out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
+	out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
      && defined(CONFIG_SYS_CS2_CTRL))
-	fbcs->csar2 = CONFIG_SYS_CS2_BASE;
-	fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
-	fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
+	out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
+	out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
+	out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
      && defined(CONFIG_SYS_CS3_CTRL))
-	fbcs->csar3 = CONFIG_SYS_CS3_BASE;
-	fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
-	fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
+	out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
+	out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
+	out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
      && defined(CONFIG_SYS_CS4_CTRL))
-	fbcs->csar4 = CONFIG_SYS_CS4_BASE;
-	fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
-	fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
+	out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
+	out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
+	out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
      && defined(CONFIG_SYS_CS5_CTRL))
-	fbcs->csar5 = CONFIG_SYS_CS5_BASE;
-	fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
-	fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
+	out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
+	out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
+	out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
 #endif
 
 #ifdef CONFIG_FSL_I2C
-	gpio->par_i2c = GPIO_PAR_I2C_SCL_SCL | GPIO_PAR_I2C_SDA_SDA;
+	out_8(&gpio->par_i2c, GPIO_PAR_I2C_SCL_SCL | GPIO_PAR_I2C_SDA_SDA);
 #endif
 
 	icache_enable();
@@ -115,11 +116,11 @@ void cpu_init_f(void)
 int cpu_init_r(void)
 {
 #ifdef CONFIG_MCFRTC
-	volatile rtc_t *rtc = (volatile rtc_t *)(CONFIG_SYS_MCFRTC_BASE);
-	volatile rtcex_t *rtcex = (volatile rtcex_t *)&rtc->extended;
+	rtc_t *rtc = (rtc_t *)(CONFIG_SYS_MCFRTC_BASE);
+	rtcex_t *rtcex = (rtcex_t *)&rtc->extended;
 
-	rtcex->gocu = (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xFFFF;
-	rtcex->gocl = CONFIG_SYS_RTC_OSCILLATOR & 0xFFFF;
+	out_be32(&rtcex->gocu, (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xffff);
+	out_be32(&rtcex->gocl, CONFIG_SYS_RTC_OSCILLATOR & 0xffff);
 #endif
 
 	return (0);
@@ -127,27 +128,27 @@ int cpu_init_r(void)
 
 void uart_port_conf(int port)
 {
-	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 
 	/* Setup Ports: */
 	switch (port) {
 	case 0:
-		gpio->par_uart &=
-		    (GPIO_PAR_UART_U0TXD_UNMASK & GPIO_PAR_UART_U0RXD_UNMASK);
-		gpio->par_uart |=
-		    (GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
+		clrbits_be16(&gpio->par_uart,
+			~(GPIO_PAR_UART_U0TXD_UNMASK & GPIO_PAR_UART_U0RXD_UNMASK));
+		setbits_be16(&gpio->par_uart,
+			GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
 		break;
 	case 1:
-		gpio->par_uart &=
-		    (GPIO_PAR_UART_U1TXD_UNMASK & GPIO_PAR_UART_U1RXD_UNMASK);
-		gpio->par_uart |=
-		    (GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
+		clrbits_be16(&gpio->par_uart,
+			~(GPIO_PAR_UART_U1TXD_UNMASK & GPIO_PAR_UART_U1RXD_UNMASK));
+		setbits_be16(&gpio->par_uart,
+			GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
 		break;
 	case 2:
-		gpio->par_dspi &=
-		    (GPIO_PAR_DSPI_SIN_UNMASK & GPIO_PAR_DSPI_SOUT_UNMASK);
-		gpio->par_dspi =
-		    (GPIO_PAR_DSPI_SIN_U2RXD | GPIO_PAR_DSPI_SOUT_U2TXD);
+		clrbits_8(&gpio->par_dspi,
+			~(GPIO_PAR_DSPI_SIN_UNMASK & GPIO_PAR_DSPI_SOUT_UNMASK));
+		out_8(&gpio->par_dspi,
+			GPIO_PAR_DSPI_SIN_U2RXD | GPIO_PAR_DSPI_SOUT_U2TXD);
 		break;
 	}
 }
@@ -155,32 +156,32 @@ void uart_port_conf(int port)
 #ifdef CONFIG_CF_DSPI
 void cfspi_port_conf(void)
 {
-	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 
-	gpio->par_dspi =
-	    GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT |
-	    GPIO_PAR_DSPI_SCK_SCK;
+	out_8(&gpio->par_dspi,
+		GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT |
+		GPIO_PAR_DSPI_SCK_SCK);
 }
 
 int cfspi_claim_bus(uint bus, uint cs)
 {
-	volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
-	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	dspi_t *dspi = (dspi_t *) MMAP_DSPI;
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 
-	if ((dspi->sr & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
+	if ((in_be32(&dspi->sr) & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
 		return -1;
 
 	/* Clear FIFO and resume transfer */
-	dspi->mcr &= ~(DSPI_MCR_CTXF | DSPI_MCR_CRXF);
+	clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
 
 	switch (cs) {
 	case 0:
-		gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_UNMASK;
-		gpio->par_dspi |= GPIO_PAR_DSPI_PCS0_PCS0;
+		clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_UNMASK);
+		setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
 		break;
 	case 2:
-		gpio->par_timer &= GPIO_PAR_TIMER_T2IN_UNMASK;
-		gpio->par_timer |= GPIO_PAR_TIMER_T2IN_DSPIPCS2;
+		clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK);
+		setbits_8(&gpio->par_timer, GPIO_PAR_TIMER_T2IN_DSPIPCS2);
 		break;
 	}
 
@@ -189,17 +190,18 @@ int cfspi_claim_bus(uint bus, uint cs)
 
 void cfspi_release_bus(uint bus, uint cs)
 {
-	volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
-	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	dspi_t *dspi = (dspi_t *) MMAP_DSPI;
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 
-	dspi->mcr &= ~(DSPI_MCR_CTXF | DSPI_MCR_CRXF);	/* Clear FIFO */
+	/* Clear FIFO */
+	clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
 
 	switch (cs) {
 	case 0:
-		gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0;
+		clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
 		break;
 	case 2:
-		gpio->par_timer &= GPIO_PAR_TIMER_T2IN_UNMASK;
+		clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK);
 		break;
 	}
 }

arch/m68k/cpu/mcf5227x/interrupts.c

@@ -3,7 +3,7 @@
  * (C) Copyright 2000-2004
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -28,14 +28,15 @@
 /* CPU specific interrupt routine */
 #include <common.h>
 #include <asm/immap.h>
+#include <asm/io.h>
 
 int interrupt_init(void)
 {
-	volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+	int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
 
 	/* Make sure all interrupts are disabled */
-	intp->imrh0 |= 0xFFFFFFFF;
-	intp->imrl0 |= 0xFFFFFFFF;
+	setbits_be32(&intp->imrh0, 0xffffffff);
+	setbits_be32(&intp->imrl0, 0xffffffff);
 
 	enable_interrupts();
 	return 0;
@@ -44,9 +45,9 @@ int interrupt_init(void)
 #if defined(CONFIG_MCFTMR)
 void dtimer_intr_setup(void)
 {
-	volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+	int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
 
-	intp->icr0[CONFIG_SYS_TMRINTR_NO] = CONFIG_SYS_TMRINTR_PRI;
-	intp->imrh0 &= ~CONFIG_SYS_TMRINTR_MASK;
+	out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI);
+	clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK);
 }
 #endif

arch/m68k/cpu/mcf5227x/speed.c

@@ -1,6 +1,6 @@
 /*
  *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -26,6 +26,7 @@
 #include <asm/processor.h>
 
 #include <asm/immap.h>
+#include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -44,7 +45,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 void clock_enter_limp(int lpdiv)
 {
-	volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM;
+	ccm_t *ccm = (ccm_t *)MMAP_CCM;
 	int i, j;
 
 	/* Check bounds of divider */
@@ -57,10 +58,10 @@ void clock_enter_limp(int lpdiv)
 	for (i = 0, j = lpdiv; j != 1; j >>= 1, i++) ;
 
 	/* Apply the divider to the system clock */
-	ccm->cdr = (ccm->cdr & 0xF0FF) | CCM_CDR_LPDIV(i);
+	clrsetbits_be16(&ccm->cdr, 0x0f00, CCM_CDR_LPDIV(i));
 
 	/* Enable Limp Mode */
-	ccm->misccr |= CCM_MISCCR_LIMP;
+	setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
 }
 
 /*
@@ -69,14 +70,15 @@ void clock_enter_limp(int lpdiv)
  */
 void clock_exit_limp(void)
 {
-	volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM;
-	volatile pll_t *pll = (volatile pll_t *)MMAP_PLL;
+	ccm_t *ccm = (ccm_t *)MMAP_CCM;
+	pll_t *pll = (pll_t *)MMAP_PLL;
 
 	/* Exit Limp mode */
-	ccm->misccr &= ~CCM_MISCCR_LIMP;
+	clrbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
 
 	/* Wait for the PLL to lock */
-	while (!(pll->psr & PLL_PSR_LOCK)) ;
+	while (!(in_be32(&pll->psr) & PLL_PSR_LOCK))
+		;
 }
 
 /*
@@ -85,12 +87,12 @@ void clock_exit_limp(void)
 int get_clocks(void)
 {
 
-	volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM;
-	volatile pll_t *pll = (volatile pll_t *)MMAP_PLL;
+	ccm_t *ccm = (ccm_t *)MMAP_CCM;
+	pll_t *pll = (pll_t *)MMAP_PLL;
 	int vco, temp, pcrvalue, pfdr;
 	u8 bootmode;
 
-	pcrvalue = pll->pcr & 0xFF0F0FFF;
+	pcrvalue = in_be32(&pll->pcr) & 0xFF0F0FFF;
 	pfdr = pcrvalue >> 24;
 
 	if (pfdr == 0x1E)
@@ -102,32 +104,32 @@ int get_clocks(void)
 
 	if (bootmode == 0) {
 		/* Normal mode */
-		vco = ((pll->pcr & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
+		vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
 		if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) {
 			/* Default value */
-			pcrvalue = (pll->pcr & 0x00FFFFFF);
+			pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF);
 			pcrvalue |= 0x1E << 24;
-			pll->pcr = pcrvalue;
+			out_be32(&pll->pcr, pcrvalue);
 			vco =
-			    ((pll->pcr & 0xFF000000) >> 24) *
+			    ((in_be32(&pll->pcr) & 0xFF000000) >> 24) *
 			    CONFIG_SYS_INPUT_CLKSRC;
 		}
 		gd->vco_clk = vco;	/* Vco clock */
 	} else if (bootmode == 3) {
 		/* serial mode */
-		vco = ((pll->pcr & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
+		vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
 		gd->vco_clk = vco;	/* Vco clock */
 	}
 
-	if ((ccm->ccr & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) {
+	if ((in_be16(&ccm->ccr) & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) {
 		/* Limp mode */
 	} else {
 		gd->inp_clk = CONFIG_SYS_INPUT_CLKSRC;	/* Input clock */
 
-		temp = (pll->pcr & PLL_PCR_OUTDIV1_MASK) + 1;
+		temp = (in_be32(&pll->pcr) & PLL_PCR_OUTDIV1_MASK) + 1;
 		gd->cpu_clk = vco / temp;	/* cpu clock */
 
-		temp = ((pll->pcr & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
+		temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
 		gd->flb_clk = vco / temp;	/* flexbus clock */
 		gd->bus_clk = gd->flb_clk;
 	}

arch/m68k/cpu/mcf523x/cpu.c

@@ -3,7 +3,7 @@
  * (C) Copyright 2000-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -31,28 +31,29 @@
 #include <netdev.h>
 
 #include <asm/immap.h>
+#include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
-	volatile ccm_t *ccm = (ccm_t *) MMAP_CCM;
+	ccm_t *ccm = (ccm_t *) MMAP_CCM;
 
-	ccm->rcr = CCM_RCR_SOFTRST;
+	out_8(&ccm->rcr, CCM_RCR_SOFTRST);
 	/* we don't return! */
 	return 0;
-};
+}
 
 int checkcpu(void)
 {
-	volatile ccm_t *ccm = (ccm_t *) MMAP_CCM;
+	ccm_t *ccm = (ccm_t *) MMAP_CCM;
 	u16 msk;
 	u16 id = 0;
 	u8 ver;
 
 	puts("CPU:   ");
-	msk = (ccm->cir >> 6);
-	ver = (ccm->cir & 0x003f);
+	msk = (in_be16(&ccm->cir) >> 6);
+	ver = (in_be16(&ccm->cir) & 0x003f);
 	switch (msk) {
 	case 0x31:
 		id = 5235;
@@ -76,19 +77,21 @@ int checkcpu(void)
 /* Called by macro WATCHDOG_RESET */
 void watchdog_reset(void)
 {
-	volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
+	wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
 
-	wdp->sr = 0x5555;	/* Count register */
+	/* Count register */
+	out_be16(&wdp->sr, 0x5555);
 	asm("nop");
-	wdp->sr = 0xAAAA;	/* Count register */
+	out_be16(&wdp->sr, 0xaaaa);
 }
 
 int watchdog_disable(void)
 {
-	volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
+	wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
 
 	/* UserManual, once the wdog is disabled, wdog cannot be re-enabled */
-	wdp->cr |= WTM_WCR_HALTED;	/* halted watchdog timer */
+	/* halted watchdog timer */
+	setbits_be16(&wdp->cr, WTM_WCR_HALTED);
 
 	puts("WATCHDOG:disabled\n");
 	return (0);
@@ -96,15 +99,15 @@ int watchdog_disable(void)
 
 int watchdog_init(void)
 {
-	volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
+	wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
 	u32 wdog_module = 0;
 
 	/* set timeout and enable watchdog */
 	wdog_module = ((CONFIG_SYS_CLK / CONFIG_SYS_HZ) * CONFIG_WATCHDOG_TIMEOUT);
 	wdog_module |= (wdog_module / 8192);
-	wdp->mr = wdog_module;
+	out_be16(&wdp->mr, wdog_module);
 
-	wdp->cr = WTM_WCR_EN;
+	out_be16(&wdp->cr, WTM_WCR_EN);
 	puts("WATCHDOG:enabled\n");
 
 	return (0);

arch/m68k/cpu/mcf523x/cpu_init.c

@@ -3,7 +3,7 @@
  * (C) Copyright 2000-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * (C) Copyright 2007 Freescale Semiconductor, Inc.
+ * (C) Copyright 2007, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -28,6 +28,7 @@
 #include <common.h>
 #include <watchdog.h>
 #include <asm/immap.h>
+#include <asm/io.h>
 
 #if defined(CONFIG_CMD_NET)
 #include <config.h>
@@ -44,74 +45,74 @@
  */
 void cpu_init_f(void)
 {
-	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-	volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
-	volatile wdog_t *wdog = (wdog_t *) MMAP_WDOG;
-	volatile scm_t *scm = (scm_t *) MMAP_SCM;
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
+	wdog_t *wdog = (wdog_t *) MMAP_WDOG;
+	scm_t *scm = (scm_t *) MMAP_SCM;
 
 	/* watchdog is enabled by default - disable the watchdog */
 #ifndef CONFIG_WATCHDOG
-	wdog->cr = 0;
+	out_be16(&wdog->cr, 0);
 #endif
 
-	scm->rambar = (CONFIG_SYS_INIT_RAM_ADDR | SCM_RAMBAR_BDE);
+	out_be32(&scm->rambar, CONFIG_SYS_INIT_RAM_ADDR | SCM_RAMBAR_BDE);
 
 	/* Port configuration */
-	gpio->par_cs = 0;
+	out_8(&gpio->par_cs, 0);
 
 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
-	fbcs->csar0 = CONFIG_SYS_CS0_BASE;
-	fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
-	fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
+	out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
+	out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
+	out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
-	gpio->par_cs |= GPIO_PAR_CS_CS1;
-	fbcs->csar1 = CONFIG_SYS_CS1_BASE;
-	fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
-	fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
+	setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS1);
+	out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
+	out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
+	out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
-	gpio->par_cs |= GPIO_PAR_CS_CS2;
-	fbcs->csar2 = CONFIG_SYS_CS2_BASE;
-	fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
-	fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
+	setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS2);
+	out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
+	out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
+	out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
-	gpio->par_cs |= GPIO_PAR_CS_CS3;
-	fbcs->csar3 = CONFIG_SYS_CS3_BASE;
-	fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
-	fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
+	setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS3);
+	out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
+	out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
+	out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
-	gpio->par_cs |= GPIO_PAR_CS_CS4;
-	fbcs->csar4 = CONFIG_SYS_CS4_BASE;
-	fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
-	fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
+	setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS4);
+	out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
+	out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
+	out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
-	gpio->par_cs |= GPIO_PAR_CS_CS5;
-	fbcs->csar5 = CONFIG_SYS_CS5_BASE;
-	fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
-	fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
+	setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS5);
+	out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
+	out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
+	out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) && defined(CONFIG_SYS_CS6_CTRL))
-	gpio->par_cs |= GPIO_PAR_CS_CS6;
-	fbcs->csar6 = CONFIG_SYS_CS6_BASE;
-	fbcs->cscr6 = CONFIG_SYS_CS6_CTRL;
-	fbcs->csmr6 = CONFIG_SYS_CS6_MASK;
+	setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS6);
+	out_be32(&fbcs->csar6, CONFIG_SYS_CS6_BASE);
+	out_be32(&fbcs->cscr6, CONFIG_SYS_CS6_CTRL);
+	out_be32(&fbcs->csmr6, CONFIG_SYS_CS6_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) && defined(CONFIG_SYS_CS7_CTRL))
-	gpio->par_cs |= GPIO_PAR_CS_CS7;
-	fbcs->csar7 = CONFIG_SYS_CS7_BASE;
-	fbcs->cscr7 = CONFIG_SYS_CS7_CTRL;
-	fbcs->csmr7 = CONFIG_SYS_CS7_MASK;
+	setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS7);
+	out_be32(&fbcs->csar7, CONFIG_SYS_CS7_BASE);
+	out_be32(&fbcs->cscr7, CONFIG_SYS_CS7_CTRL);
+	out_be32(&fbcs->csmr7, CONFIG_SYS_CS7_MASK);
 #endif
 
 #ifdef CONFIG_FSL_I2C
@@ -132,29 +133,33 @@ int cpu_init_r(void)
 
 void uart_port_conf(int port)
 {
-	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 
 	/* Setup Ports: */
 	switch (port) {
 	case 0:
-		gpio->par_uart &= ~(GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD);
-		gpio->par_uart |= (GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD);
+		clrbits_be16(&gpio->par_uart,
+			GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD);
+		setbits_be16(&gpio->par_uart,
+			GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD);
 		break;
 	case 1:
-		gpio->par_uart &=
-		    ~(GPIO_PAR_UART_U1RXD_MASK | GPIO_PAR_UART_U1TXD_MASK);
-		gpio->par_uart |=
-		    (GPIO_PAR_UART_U1RXD_U1RXD | GPIO_PAR_UART_U1TXD_U1TXD);
+		clrbits_be16(&gpio->par_uart,
+			GPIO_PAR_UART_U1RXD_MASK | GPIO_PAR_UART_U1TXD_MASK);
+		setbits_be16(&gpio->par_uart,
+			GPIO_PAR_UART_U1RXD_U1RXD | GPIO_PAR_UART_U1TXD_U1TXD);
 		break;
 	case 2:
 #ifdef CONFIG_SYS_UART2_PRI_GPIO
-		gpio->par_uart &= ~(GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD);
-		gpio->par_uart |= (GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD);
+		clrbits_be16(&gpio->par_uart,
+			GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD);
+		setbits_be16(&gpio->par_uart,
+			GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD);
 #elif defined(CONFIG_SYS_UART2_ALT1_GPIO)
-		gpio->feci2c &=
-		    ~(GPIO_PAR_FECI2C_EMDC_MASK | GPIO_PAR_FECI2C_EMDIO_MASK);
-		gpio->feci2c |=
-		    (GPIO_PAR_FECI2C_EMDC_U2TXD | GPIO_PAR_FECI2C_EMDIO_U2RXD);
+		clrbits_8(&gpio->par_feci2c,
+			GPIO_PAR_FECI2C_EMDC_MASK | GPIO_PAR_FECI2C_EMDIO_MASK);
+		setbits_8(&gpio->par_feci2c,
+			GPIO_PAR_FECI2C_EMDC_U2TXD | GPIO_PAR_FECI2C_EMDIO_U2RXD);
 #endif
 		break;
 	}
@@ -163,15 +168,16 @@ void uart_port_conf(int port)
 #if defined(CONFIG_CMD_NET)
 int fecpin_setclear(struct eth_device *dev, int setclear)
 {
-	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 
 	if (setclear) {
-		gpio->par_feci2c |=
-		    (GPIO_PAR_FECI2C_EMDC_FECEMDC |
-		     GPIO_PAR_FECI2C_EMDIO_FECEMDIO);
+		setbits_8(&gpio->par_feci2c,
+			GPIO_PAR_FECI2C_EMDC_FECEMDC |
+			GPIO_PAR_FECI2C_EMDIO_FECEMDIO);
 	} else {
-		gpio->par_feci2c &=
-		    ~(GPIO_PAR_FECI2C_EMDC_MASK | GPIO_PAR_FECI2C_EMDIO_MASK);
+		clrbits_8(&gpio->par_feci2c,
+			GPIO_PAR_FECI2C_EMDC_MASK |
+			GPIO_PAR_FECI2C_EMDIO_MASK);
 	}
 
 	return 0;

arch/m68k/cpu/mcf523x/interrupts.c

@@ -1,6 +1,6 @@
 /*
  *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -25,13 +25,14 @@
 /* CPU specific interrupt routine */
 #include <common.h>
 #include <asm/immap.h>
+#include <asm/io.h>
 
 int interrupt_init(void)
 {
-	volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+	int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
 
 	/* Make sure all interrupts are disabled */
-	intp->imrl0 |= 0x1;
+	setbits_be32(&intp->imrl0, 0x1);
 
 	enable_interrupts();
 	return 0;
@@ -40,10 +41,10 @@ int interrupt_init(void)
 #if defined(CONFIG_MCFTMR)
 void dtimer_intr_setup(void)
 {
-	volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+	int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
 
-	intp->icr0[CONFIG_SYS_TMRINTR_NO] = CONFIG_SYS_TMRINTR_PRI;
-	intp->imrl0 &= ~INTC_IPRL_INT0;
-	intp->imrl0 &= ~CONFIG_SYS_TMRINTR_MASK;
+	out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI);
+	clrbits_be32(&intp->imrl0, INTC_IPRL_INT0);
+	clrbits_be32(&intp->imrl0, CONFIG_SYS_TMRINTR_MASK);
 }
 #endif

arch/m68k/cpu/mcf523x/speed.c

@@ -3,7 +3,7 @@
  * (C) Copyright 2000-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -29,6 +29,7 @@
 #include <asm/processor.h>
 
 #include <asm/immap.h>
+#include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 /*
@@ -36,11 +37,12 @@ DECLARE_GLOBAL_DATA_PTR;
  */
 int get_clocks(void)
 {
-	volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL);
+	pll_t *pll = (pll_t *)(MMAP_PLL);
 
-	pll->syncr = PLL_SYNCR_MFD(1);
+	out_be32(&pll->syncr, PLL_SYNCR_MFD(1));
 
-	while (!(pll->synsr & PLL_SYNSR_LOCK));
+	while (!(in_be32(&pll->synsr) & PLL_SYNSR_LOCK))
+		;
 
 	gd->bus_clk = CONFIG_SYS_CLK;
 	gd->cpu_clk = (gd->bus_clk * 2);

arch/m68k/cpu/mcf52x2/cpu.c

@@ -9,6 +9,8 @@
  * MCF5275 additions
  * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com)
  *
+ * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
@@ -32,6 +34,7 @@
 #include <watchdog.h>
 #include <command.h>
 #include <asm/immap.h>
+#include <asm/io.h>
 #include <netdev.h>
 #include "cpu.h"
 
@@ -40,11 +43,11 @@ DECLARE_GLOBAL_DATA_PTR;
 #ifdef	CONFIG_M5208
 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
-	volatile rcm_t *rcm = (rcm_t *)(MMAP_RCM);
+	rcm_t *rcm = (rcm_t *)(MMAP_RCM);
 
 	udelay(1000);
 
-	rcm->rcr = RCM_RCR_SOFTRST;
+	out_8(&rcm->rcr, RCM_RCR_SOFTRST);
 
 	/* we don't return! */
 	return 0;
@@ -65,18 +68,21 @@ int checkcpu(void)
 /* Called by macro WATCHDOG_RESET */
 void watchdog_reset(void)
 {
-	volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
-	wdt->sr = 0x5555;
-	wdt->sr = 0xAAAA;
+	wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
+
+	out_be16(&wdt->sr, 0x5555);
+	out_be16(&wdt->sr, 0xaaaa);
 }
 
 int watchdog_disable(void)
 {
-	volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
+	wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
 
-	wdt->sr = 0x5555; /* reset watchdog counter */
-	wdt->sr = 0xAAAA;
-	wdt->cr = 0;	/* disable watchdog timer */
+	/* reset watchdog counter */
+	out_be16(&wdt->sr, 0x5555);
+	out_be16(&wdt->sr, 0xaaaa);
+	/* disable watchdog timer */
+	out_be16(&wdt->cr, 0);
 
 	puts("WATCHDOG:disabled\n");
 	return (0);
@@ -84,15 +90,18 @@ int watchdog_disable(void)
 
 int watchdog_init(void)
 {
-	volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
+	wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
 
-	wdt->cr = 0;	/* disable watchdog */
+	/* disable watchdog */
+	out_be16(&wdt->cr, 0);
 
 	/* set timeout and enable watchdog */
-	wdt->mr =
-		((CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000)) - 1;
-	wdt->sr = 0x5555; /* reset watchdog counter */
-	wdt->sr = 0xAAAA;
+	out_be16(&wdt->mr,
+		(CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
+
+	/* reset watchdog counter */
+	out_be16(&wdt->sr, 0x5555);
+	out_be16(&wdt->sr, 0xaaaa);
 
 	puts("WATCHDOG:enabled\n");
 	return (0);
@@ -178,13 +187,13 @@ int watchdog_init(void)
 #ifdef	CONFIG_M5272
 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
-	volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
+	wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
 
-	wdp->wdog_wrrr = 0;
+	out_be16(&wdp->wdog_wrrr, 0);
 	udelay(1000);
 
 	/* enable watchdog, set timeout to 0 and wait */
-	wdp->wdog_wrrr = 1;
+	out_be16(&wdp->wdog_wrrr, 1);
 	while (1) ;
 
 	/* we don't return! */
@@ -193,12 +202,12 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 int checkcpu(void)
 {
-	volatile sysctrl_t *sysctrl = (sysctrl_t *) (MMAP_CFG);
+	sysctrl_t *sysctrl = (sysctrl_t *) (MMAP_CFG);
 	uchar msk;
 	char *suf;
 
 	puts("CPU:   ");
-	msk = (sysctrl->sc_dir > 28) & 0xf;
+	msk = (in_be32(&sysctrl->sc_dir) > 28) & 0xf;
 	switch (msk) {
 	case 0x2:
 		suf = "1K75N";
@@ -221,17 +230,21 @@ int checkcpu(void)
 /* Called by macro WATCHDOG_RESET */
 void watchdog_reset(void)
 {
-	volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
-	wdt->wdog_wcr = 0;
+	wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
+
+	out_be16(&wdt->wdog_wcr, 0);
 }
 
 int watchdog_disable(void)
 {
-	volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
+	wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
 
-	wdt->wdog_wcr = 0;	/* reset watchdog counter */
-	wdt->wdog_wirr = 0;	/* disable watchdog interrupt */
-	wdt->wdog_wrrr = 0;	/* disable watchdog timer */
+	/* reset watchdog counter */
+	out_be16(&wdt->wdog_wcr, 0);
+	/* disable watchdog interrupt */
+	out_be16(&wdt->wdog_wirr, 0);
+	/* disable watchdog timer */
+	out_be16(&wdt->wdog_wrrr, 0);
 
 	puts("WATCHDOG:disabled\n");
 	return (0);
@@ -239,14 +252,17 @@ int watchdog_disable(void)
 
 int watchdog_init(void)
 {
-	volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
+	wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
 
-	wdt->wdog_wirr = 0;	/* disable watchdog interrupt */
+	/* disable watchdog interrupt */
+	out_be16(&wdt->wdog_wirr, 0);
 
 	/* set timeout and enable watchdog */
-	wdt->wdog_wrrr =
-	    ((CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000)) - 1;
-	wdt->wdog_wcr = 0;	/* reset watchdog counter */
+	out_be16(&wdt->wdog_wrrr,
+		(CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
+
+	/* reset watchdog counter */
+	out_be16(&wdt->wdog_wcr, 0);
 
 	puts("WATCHDOG:enabled\n");
 	return (0);
@@ -258,11 +274,11 @@ int watchdog_init(void)
 #ifdef	CONFIG_M5275
 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
-	volatile rcm_t *rcm = (rcm_t *)(MMAP_RCM);
+	rcm_t *rcm = (rcm_t *)(MMAP_RCM);
 
 	udelay(1000);
 
-	rcm->rcr = RCM_RCR_SOFTRST;
+	out_8(&rcm->rcr, RCM_RCR_SOFTRST);
 
 	/* we don't return! */
 	return 0;
@@ -282,18 +298,22 @@ int checkcpu(void)
 /* Called by macro WATCHDOG_RESET */
 void watchdog_reset(void)
 {
-	volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
-	wdt->wsr = 0x5555;
-	wdt->wsr = 0xAAAA;
+	wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
+
+	out_be16(&wdt->wsr, 0x5555);
+	out_be16(&wdt->wsr, 0xaaaa);
 }
 
 int watchdog_disable(void)
 {
-	volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
+	wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
 
-	wdt->wsr = 0x5555; /* reset watchdog counter */
-	wdt->wsr = 0xAAAA;
-	wdt->wcr = 0;	/* disable watchdog timer */
+	/* reset watchdog counter */
+	out_be16(&wdt->wsr, 0x5555);
+	out_be16(&wdt->wsr, 0xaaaa);
+
+	/* disable watchdog timer */
+	out_be16(&wdt->wcr, 0);
 
 	puts("WATCHDOG:disabled\n");
 	return (0);
@@ -301,15 +321,18 @@ int watchdog_disable(void)
 
 int watchdog_init(void)
 {
-	volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
+	wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
 
-	wdt->wcr = 0;	/* disable watchdog */
+	/* disable watchdog */
+	out_be16(&wdt->wcr, 0);
 
 	/* set timeout and enable watchdog */
-	wdt->wmr =
-		((CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000)) - 1;
-	wdt->wsr = 0x5555; /* reset watchdog counter */
-	wdt->wsr = 0xAAAA;
+	out_be16(&wdt->wmr,
+		(CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
+
+	/* reset watchdog counter */
+	out_be16(&wdt->wsr, 0x5555);
+	out_be16(&wdt->wsr, 0xaaaa);
 
 	puts("WATCHDOG:enabled\n");
 	return (0);

arch/m68k/cpu/mcf52x2/cpu_init.c

@@ -8,7 +8,7 @@
  * (c) Copyright 2010
  * Arcturus Networks Inc. <www.arcturusnetworks.com>
  *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  * Hayden Fraser (Hayden.Fraser@freescale.com)
  *
@@ -37,6 +37,7 @@
 #include <common.h>
 #include <watchdog.h>
 #include <asm/immap.h>
+#include <asm/io.h>
 
 #if defined(CONFIG_CMD_NET)
 #include <config.h>
@@ -48,57 +49,57 @@
 /* Only 5272 Flexbus chipselect is different from the rest */
 void init_fbcs(void)
 {
-	volatile fbcs_t *fbcs = (fbcs_t *) (MMAP_FBCS);
+	fbcs_t *fbcs = (fbcs_t *) (MMAP_FBCS);
 
 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
      && defined(CONFIG_SYS_CS0_CTRL))
-	fbcs->csar0 = CONFIG_SYS_CS0_BASE;
-	fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
-	fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
+	out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
+	out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
+	out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
 #else
 #warning "Chip Select 0 are not initialized/used"
 #endif
 #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
      && defined(CONFIG_SYS_CS1_CTRL))
-	fbcs->csar1 = CONFIG_SYS_CS1_BASE;
-	fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
-	fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
+	out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
+	out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
+	out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
 #endif
 #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
      && defined(CONFIG_SYS_CS2_CTRL))
-	fbcs->csar2 = CONFIG_SYS_CS2_BASE;
-	fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
-	fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
+	out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
+	out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
+	out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
 #endif
 #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
      && defined(CONFIG_SYS_CS3_CTRL))
-	fbcs->csar3 = CONFIG_SYS_CS3_BASE;
-	fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
-	fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
+	out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
+	out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
+	out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
 #endif
 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
      && defined(CONFIG_SYS_CS4_CTRL))
-	fbcs->csar4 = CONFIG_SYS_CS4_BASE;
-	fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
-	fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
+	out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
+	out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
+	out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
 #endif
 #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
      && defined(CONFIG_SYS_CS5_CTRL))
-	fbcs->csar5 = CONFIG_SYS_CS5_BASE;
-	fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
-	fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
+	out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
+	out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
+	out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
 #endif
 #if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) \
      && defined(CONFIG_SYS_CS6_CTRL))
-	fbcs->csar6 = CONFIG_SYS_CS6_BASE;
-	fbcs->cscr6 = CONFIG_SYS_CS6_CTRL;
-	fbcs->csmr6 = CONFIG_SYS_CS6_MASK;
+	out_be32(&fbcs->csar6, CONFIG_SYS_CS6_BASE);
+	out_be32(&fbcs->cscr6, CONFIG_SYS_CS6_CTRL);
+	out_be32(&fbcs->csmr6, CONFIG_SYS_CS6_MASK);
 #endif
 #if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) \
      && defined(CONFIG_SYS_CS7_CTRL))
-	fbcs->csar7 = CONFIG_SYS_CS7_BASE;
-	fbcs->cscr7 = CONFIG_SYS_CS7_CTRL;
-	fbcs->csmr7 = CONFIG_SYS_CS7_MASK;
+	out_be32(&fbcs->csar7, CONFIG_SYS_CS7_BASE);
+	out_be32(&fbcs->cscr7, CONFIG_SYS_CS7_CTRL);
+	out_be32(&fbcs->csmr7, CONFIG_SYS_CS7_MASK);
 #endif
 }
 #endif
@@ -106,22 +107,22 @@ void init_fbcs(void)
 #if defined(CONFIG_M5208)
 void cpu_init_f(void)
 {
-	volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
+	scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
 
 #ifndef CONFIG_WATCHDOG
-	volatile wdog_t *wdg = (wdog_t *) MMAP_WDOG;
+	wdog_t *wdg = (wdog_t *) MMAP_WDOG;
 
 	/* Disable the watchdog if we aren't using it */
-	wdg->cr = 0;
+	out_be16(&wdg->cr, 0);
 #endif
 
-	scm1->mpr = 0x77777777;
-	scm1->pacra = 0;
-	scm1->pacrb = 0;
-	scm1->pacrc = 0;
-	scm1->pacrd = 0;
-	scm1->pacre = 0;
-	scm1->pacrf = 0;
+	out_be32(&scm1->mpr, 0x77777777);
+	out_be32(&scm1->pacra, 0);
+	out_be32(&scm1->pacrb, 0);
+	out_be32(&scm1->pacrc, 0);
+	out_be32(&scm1->pacrd, 0);
+	out_be32(&scm1->pacre, 0);
+	out_be32(&scm1->pacrf, 0);
 
 	/* FlexBus Chipselect */
 	init_fbcs();
@@ -137,36 +138,36 @@ int cpu_init_r(void)
 
 void uart_port_conf(int port)
 {
-	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 
 	/* Setup Ports: */
 	switch (port) {
 	case 0:
-		gpio->par_uart &= GPIO_PAR_UART0_UNMASK;
-		gpio->par_uart |= (GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
+		clrbits_be16(&gpio->par_uart, ~GPIO_PAR_UART0_UNMASK);
+		setbits_be16(&gpio->par_uart, GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
 		break;
 	case 1:
-		gpio->par_uart &= GPIO_PAR_UART0_UNMASK;
-		gpio->par_uart |= (GPIO_PAR_UART_U1TXD | GPIO_PAR_UART_U1RXD);
+		clrbits_be16(&gpio->par_uart, ~GPIO_PAR_UART0_UNMASK);
+		setbits_be16(&gpio->par_uart, GPIO_PAR_UART_U1TXD | GPIO_PAR_UART_U1RXD);
 		break;
 	case 2:
 #ifdef CONFIG_SYS_UART2_PRI_GPIO
-		gpio->par_timer &=
-		    (GPIO_PAR_TMR_TIN0_UNMASK | GPIO_PAR_TMR_TIN1_UNMASK);
-		gpio->par_timer |=
-		    (GPIO_PAR_TMR_TIN0_U2TXD | GPIO_PAR_TMR_TIN1_U2RXD);
+		clrbits_8(&gpio->par_timer,
+			~(GPIO_PAR_TMR_TIN0_UNMASK | GPIO_PAR_TMR_TIN1_UNMASK));
+		setbits_8(&gpio->par_timer,
+			GPIO_PAR_TMR_TIN0_U2TXD | GPIO_PAR_TMR_TIN1_U2RXD);
 #endif
 #ifdef CONFIG_SYS_UART2_ALT1_GPIO
-		gpio->par_feci2c &=
-		    (GPIO_PAR_FECI2C_MDC_UNMASK | GPIO_PAR_FECI2C_MDIO_UNMASK);
-		gpio->par_feci2c |=
-		    (GPIO_PAR_FECI2C_MDC_U2TXD | GPIO_PAR_FECI2C_MDIO_U2RXD);
+		clrbits_8(&gpio->par_feci2c,
+			~(GPIO_PAR_FECI2C_MDC_UNMASK | GPIO_PAR_FECI2C_MDIO_UNMASK));
+		setbits_8(&gpio->par_feci2c,
+			GPIO_PAR_FECI2C_MDC_U2TXD | GPIO_PAR_FECI2C_MDIO_U2RXD);
 #endif
 #ifdef CONFIG_SYS_UART2_ALT1_GPIO
-		gpio->par_feci2c &=
-		    (GPIO_PAR_FECI2C_SDA_UNMASK | GPIO_PAR_FECI2C_SCL_UNMASK);
-		gpio->par_feci2c |=
-		    (GPIO_PAR_FECI2C_SDA_U2TXD | GPIO_PAR_FECI2C_SCL_U2RXD);
+		clrbits_8(&gpio->par_feci2c,
+			~(GPIO_PAR_FECI2C_SDA_UNMASK | GPIO_PAR_FECI2C_SCL_UNMASK));
+		setbits_8(&gpio->par_feci2c,
+			GPIO_PAR_FECI2C_SDA_U2TXD | GPIO_PAR_FECI2C_SCL_U2RXD);
 #endif
 		break;
 	}
@@ -175,17 +176,17 @@ void uart_port_conf(int port)
 #if defined(CONFIG_CMD_NET)
 int fecpin_setclear(struct eth_device *dev, int setclear)
 {
-	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 
 	if (setclear) {
-		gpio->par_fec |=
-		    GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC;
-		gpio->par_feci2c |=
-		    GPIO_PAR_FECI2C_MDC_MDC | GPIO_PAR_FECI2C_MDIO_MDIO;
+		setbits_8(&gpio->par_fec,
+			GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC);
+		setbits_8(&gpio->par_feci2c,
+			GPIO_PAR_FECI2C_MDC_MDC | GPIO_PAR_FECI2C_MDIO_MDIO);
 	} else {
-		gpio->par_fec &=
-		    (GPIO_PAR_FEC_7W_UNMASK & GPIO_PAR_FEC_MII_UNMASK);
-		gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII_UNMASK;
+		clrbits_8(&gpio->par_fec,
+			~(GPIO_PAR_FEC_7W_UNMASK & GPIO_PAR_FEC_MII_UNMASK));
+		clrbits_8(&gpio->par_feci2c, ~GPIO_PAR_FECI2C_RMII_UNMASK);
 	}
 	return 0;
 }
@@ -249,17 +250,17 @@ int cpu_init_r(void)
 
 void uart_port_conf(int port)
 {
-	volatile u32 *par = (u32 *) MMAP_PAR;
+	u32 *par = (u32 *) MMAP_PAR;
 
 	/* Setup Ports: */
 	switch (port) {
 	case 1:
-		*par &= 0xFFE7FFFF;
-		*par |= 0x00180000;
+		clrbits_be32(par, 0x00180000);
+		setbits_be32(par, 0x00180000);
 		break;
 	case 2:
-		*par &= 0xFFFFFFFC;
-		*par &= 0x00000003;
+		clrbits_be32(par, 0x00000003);
+		clrbits_be32(par, 0xFFFFFFFC);
 		break;
 	}
 }
@@ -332,7 +333,20 @@ int fecpin_setclear(struct eth_device *dev, int setclear)
 	return 0;
 }
 #endif				/* CONFIG_CMD_NET */
-#endif
+
+#if defined(CONFIG_CF_QSPI)
+
+/* Configure PIOs for SIN, SOUT, and SCK */
+void cfspi_port_conf(void)
+{
+	mbar_writeByte(MCF_GPIO_PAR_QSPI,
+		       MCF_GPIO_PAR_QSPI_SIN_SIN   |
+		       MCF_GPIO_PAR_QSPI_SOUT_SOUT |
+		       MCF_GPIO_PAR_QSPI_SCK_SCK);
+}
+#endif				/* CONFIG_CF_QSPI */
+
+#endif				/* CONFIG_M5271 */
 
 #if defined(CONFIG_M5272)
 /*
@@ -348,59 +362,59 @@ void cpu_init_f(void)
 	 * already initialized.
 	 */
 #ifndef CONFIG_MONITOR_IS_IN_RAM
-	volatile sysctrl_t *sysctrl = (sysctrl_t *) (CONFIG_SYS_MBAR);
-	volatile gpio_t *gpio = (gpio_t *) (MMAP_GPIO);
-	volatile csctrl_t *csctrl = (csctrl_t *) (MMAP_FBCS);
+	sysctrl_t *sysctrl = (sysctrl_t *) (CONFIG_SYS_MBAR);
+	gpio_t *gpio = (gpio_t *) (MMAP_GPIO);
+	csctrl_t *csctrl = (csctrl_t *) (MMAP_FBCS);
 
-	sysctrl->sc_scr = CONFIG_SYS_SCR;
-	sysctrl->sc_spr = CONFIG_SYS_SPR;
+	out_be16(&sysctrl->sc_scr, CONFIG_SYS_SCR);
+	out_be16(&sysctrl->sc_spr, CONFIG_SYS_SPR);
 
 	/* Setup Ports: */
-	gpio->gpio_pacnt = CONFIG_SYS_PACNT;
-	gpio->gpio_paddr = CONFIG_SYS_PADDR;
-	gpio->gpio_padat = CONFIG_SYS_PADAT;
-	gpio->gpio_pbcnt = CONFIG_SYS_PBCNT;
-	gpio->gpio_pbddr = CONFIG_SYS_PBDDR;
-	gpio->gpio_pbdat = CONFIG_SYS_PBDAT;
-	gpio->gpio_pdcnt = CONFIG_SYS_PDCNT;
+	out_be32(&gpio->gpio_pacnt, CONFIG_SYS_PACNT);
+	out_be16(&gpio->gpio_paddr, CONFIG_SYS_PADDR);
+	out_be16(&gpio->gpio_padat, CONFIG_SYS_PADAT);
+	out_be32(&gpio->gpio_pbcnt, CONFIG_SYS_PBCNT);
+	out_be16(&gpio->gpio_pbddr, CONFIG_SYS_PBDDR);
+	out_be16(&gpio->gpio_pbdat, CONFIG_SYS_PBDAT);
+	out_be32(&gpio->gpio_pdcnt, CONFIG_SYS_PDCNT);
 
 	/* Memory Controller: */
-	csctrl->cs_br0 = CONFIG_SYS_BR0_PRELIM;
-	csctrl->cs_or0 = CONFIG_SYS_OR0_PRELIM;
+	out_be32(&csctrl->cs_br0, CONFIG_SYS_BR0_PRELIM);
+	out_be32(&csctrl->cs_or0, CONFIG_SYS_OR0_PRELIM);
 
 #if (defined(CONFIG_SYS_OR1_PRELIM) && defined(CONFIG_SYS_BR1_PRELIM))
-	csctrl->cs_br1 = CONFIG_SYS_BR1_PRELIM;
-	csctrl->cs_or1 = CONFIG_SYS_OR1_PRELIM;
+	out_be32(&csctrl->cs_br1, CONFIG_SYS_BR1_PRELIM);
+	out_be32(&csctrl->cs_or1, CONFIG_SYS_OR1_PRELIM);
 #endif
 
 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
-	csctrl->cs_br2 = CONFIG_SYS_BR2_PRELIM;
-	csctrl->cs_or2 = CONFIG_SYS_OR2_PRELIM;
+	out_be32(&csctrl->cs_br2, CONFIG_SYS_BR2_PRELIM);
+	out_be32(&csctrl->cs_or2, CONFIG_SYS_OR2_PRELIM);
 #endif
 
 #if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM)
-	csctrl->cs_br3 = CONFIG_SYS_BR3_PRELIM;
-	csctrl->cs_or3 = CONFIG_SYS_OR3_PRELIM;
+	out_be32(&csctrl->cs_br3, CONFIG_SYS_BR3_PRELIM);
+	out_be32(&csctrl->cs_or3, CONFIG_SYS_OR3_PRELIM);
 #endif
 
 #if defined(CONFIG_SYS_OR4_PRELIM) && defined(CONFIG_SYS_BR4_PRELIM)
-	csctrl->cs_br4 = CONFIG_SYS_BR4_PRELIM;
-	csctrl->cs_or4 = CONFIG_SYS_OR4_PRELIM;
+	out_be32(&csctrl->cs_br4, CONFIG_SYS_BR4_PRELIM);
+	out_be32(&csctrl->cs_or4, CONFIG_SYS_OR4_PRELIM);
 #endif
 
 #if defined(CONFIG_SYS_OR5_PRELIM) && defined(CONFIG_SYS_BR5_PRELIM)
-	csctrl->cs_br5 = CONFIG_SYS_BR5_PRELIM;
-	csctrl->cs_or5 = CONFIG_SYS_OR5_PRELIM;
+	out_be32(&csctrl->cs_br5, CONFIG_SYS_BR5_PRELIM);
+	out_be32(&csctrl->cs_or5, CONFIG_SYS_OR5_PRELIM);
 #endif
 
 #if defined(CONFIG_SYS_OR6_PRELIM) && defined(CONFIG_SYS_BR6_PRELIM)
-	csctrl->cs_br6 = CONFIG_SYS_BR6_PRELIM;
-	csctrl->cs_or6 = CONFIG_SYS_OR6_PRELIM;
+	out_be32(&csctrl->cs_br6, CONFIG_SYS_BR6_PRELIM);
+	out_be32(&csctrl->cs_or6, CONFIG_SYS_OR6_PRELIM);
 #endif
 
 #if defined(CONFIG_SYS_OR7_PRELIM) && defined(CONFIG_SYS_BR7_PRELIM)
-	csctrl->cs_br7 = CONFIG_SYS_BR7_PRELIM;
-	csctrl->cs_or7 = CONFIG_SYS_OR7_PRELIM;
+	out_be32(&csctrl->cs_br7, CONFIG_SYS_BR7_PRELIM);
+	out_be32(&csctrl->cs_or7, CONFIG_SYS_OR7_PRELIM);
 #endif
 
 #endif				/* #ifndef CONFIG_MONITOR_IS_IN_RAM */
@@ -420,17 +434,21 @@ int cpu_init_r(void)
 
 void uart_port_conf(int port)
 {
-	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 
 	/* Setup Ports: */
 	switch (port) {
 	case 0:
-		gpio->gpio_pbcnt &= ~(GPIO_PBCNT_PB0MSK | GPIO_PBCNT_PB1MSK);
-		gpio->gpio_pbcnt |= (GPIO_PBCNT_URT0_TXD | GPIO_PBCNT_URT0_RXD);
+		clrbits_be32(&gpio->gpio_pbcnt,
+			GPIO_PBCNT_PB0MSK | GPIO_PBCNT_PB1MSK);
+		setbits_be32(&gpio->gpio_pbcnt,
+			GPIO_PBCNT_URT0_TXD | GPIO_PBCNT_URT0_RXD);
 		break;
 	case 1:
-		gpio->gpio_pdcnt &= ~(GPIO_PDCNT_PD1MSK | GPIO_PDCNT_PD4MSK);
-		gpio->gpio_pdcnt |= (GPIO_PDCNT_URT1_RXD | GPIO_PDCNT_URT1_TXD);
+		clrbits_be32(&gpio->gpio_pdcnt,
+			GPIO_PDCNT_PD1MSK | GPIO_PDCNT_PD4MSK);
+		setbits_be32(&gpio->gpio_pdcnt,
+			GPIO_PDCNT_URT1_RXD | GPIO_PDCNT_URT1_TXD);
 		break;
 	}
 }
@@ -438,13 +456,14 @@ void uart_port_conf(int port)
 #if defined(CONFIG_CMD_NET)
 int fecpin_setclear(struct eth_device *dev, int setclear)
 {
-	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 
 	if (setclear) {
-		gpio->gpio_pbcnt |= GPIO_PBCNT_E_MDC | GPIO_PBCNT_E_RXER |
-				    GPIO_PBCNT_E_RXD1 | GPIO_PBCNT_E_RXD2 |
-				    GPIO_PBCNT_E_RXD3 | GPIO_PBCNT_E_TXD1 |
-				    GPIO_PBCNT_E_TXD2 | GPIO_PBCNT_E_TXD3;
+		setbits_be32(&gpio->gpio_pbcnt,
+			GPIO_PBCNT_E_MDC | GPIO_PBCNT_E_RXER |
+			GPIO_PBCNT_E_RXD1 | GPIO_PBCNT_E_RXD2 |
+			GPIO_PBCNT_E_RXD3 | GPIO_PBCNT_E_TXD1 |
+			GPIO_PBCNT_E_TXD2 | GPIO_PBCNT_E_TXD3);
 	} else {
 	}
 	return 0;
@@ -469,11 +488,11 @@ void cpu_init_f(void)
 	 */
 
 #ifndef CONFIG_MONITOR_IS_IN_RAM
-	volatile wdog_t *wdog_reg = (wdog_t *) (MMAP_WDOG);
-	volatile gpio_t *gpio_reg = (gpio_t *) (MMAP_GPIO);
+	wdog_t *wdog_reg = (wdog_t *) (MMAP_WDOG);
+	gpio_t *gpio_reg = (gpio_t *) (MMAP_GPIO);
 
 	/* Kill watchdog so we can initialize the PLL */
-	wdog_reg->wcr = 0;
+	out_be16(&wdog_reg->wcr, 0);
 
 	/* FlexBus Chipselect */
 	init_fbcs();
@@ -498,21 +517,21 @@ int cpu_init_r(void)
 
 void uart_port_conf(int port)
 {
-	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 
 	/* Setup Ports: */
 	switch (port) {
 	case 0:
-		gpio->par_uart &= ~UART0_ENABLE_MASK;
-		gpio->par_uart |= UART0_ENABLE_MASK;
+		clrbits_be16(&gpio->par_uart, UART0_ENABLE_MASK);
+		setbits_be16(&gpio->par_uart, UART0_ENABLE_MASK);
 		break;
 	case 1:
-		gpio->par_uart &= ~UART1_ENABLE_MASK;
-		gpio->par_uart |= UART1_ENABLE_MASK;
+		clrbits_be16(&gpio->par_uart, UART1_ENABLE_MASK);
+		setbits_be16(&gpio->par_uart, UART1_ENABLE_MASK);
 		break;
 	case 2:
-		gpio->par_uart &= ~UART2_ENABLE_MASK;
-		gpio->par_uart |= UART2_ENABLE_MASK;
+		clrbits_be16(&gpio->par_uart, UART2_ENABLE_MASK);
+		setbits_be16(&gpio->par_uart, UART2_ENABLE_MASK);
 		break;
 	}
 }
@@ -521,24 +540,24 @@ void uart_port_conf(int port)
 int fecpin_setclear(struct eth_device *dev, int setclear)
 {
 	struct fec_info_s *info = (struct fec_info_s *) dev->priv;
-	volatile gpio_t *gpio = (gpio_t *)MMAP_GPIO;
+	gpio_t *gpio = (gpio_t *)MMAP_GPIO;
 
 	if (setclear) {
 		/* Enable Ethernet pins */
 		if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
-			gpio->par_feci2c |= 0x0F00;
-			gpio->par_fec0hl |= 0xC0;
+			setbits_be16(&gpio->par_feci2c, 0x0f00);
+			setbits_8(&gpio->par_fec0hl, 0xc0);
 		} else {
-			gpio->par_feci2c |= 0x00A0;
-			gpio->par_fec1hl |= 0xC0;
+			setbits_be16(&gpio->par_feci2c, 0x00a0);
+			setbits_8(&gpio->par_fec1hl, 0xc0);
 		}
 	} else {
 		if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
-			gpio->par_feci2c &= ~0x0F00;
-			gpio->par_fec0hl &= ~0xC0;
+			clrbits_be16(&gpio->par_feci2c, 0x0f00);
+			clrbits_8(&gpio->par_fec0hl, 0xc0);
 		} else {
-			gpio->par_feci2c &= ~0x00A0;
-			gpio->par_fec1hl &= ~0xC0;
+			clrbits_be16(&gpio->par_feci2c, 0x00a0);
+			clrbits_8(&gpio->par_fec1hl, 0xc0);
 		}
 	}
 

arch/m68k/cpu/mcf52x2/interrupts.c

@@ -2,7 +2,7 @@
  * (C) Copyright 2000-2004
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -28,20 +28,22 @@
 #include <watchdog.h>
 #include <asm/processor.h>
 #include <asm/immap.h>
+#include <asm/io.h>
 
 #ifdef	CONFIG_M5272
 int interrupt_init(void)
 {
-	volatile intctrl_t *intp = (intctrl_t *) (MMAP_INTC);
+	intctrl_t *intp = (intctrl_t *) (MMAP_INTC);
 
 	/* disable all external interrupts */
-	intp->int_icr1 = 0x88888888;
-	intp->int_icr2 = 0x88888888;
-	intp->int_icr3 = 0x88888888;
-	intp->int_icr4 = 0x88888888;
-	intp->int_pitr = 0x00000000;
+	out_be32(&intp->int_icr1, 0x88888888);
+	out_be32(&intp->int_icr2, 0x88888888);
+	out_be32(&intp->int_icr3, 0x88888888);
+	out_be32(&intp->int_icr4, 0x88888888);
+	out_be32(&intp->int_pitr, 0x00000000);
+
 	/* initialize vector register */
-	intp->int_pivr = 0x40;
+	out_8(&intp->int_pivr, 0x40);
 
 	enable_interrupts();
 
@@ -51,10 +53,10 @@ int interrupt_init(void)
 #if defined(CONFIG_MCFTMR)
 void dtimer_intr_setup(void)
 {
-	volatile intctrl_t *intp = (intctrl_t *) (CONFIG_SYS_INTR_BASE);
+	intctrl_t *intp = (intctrl_t *) (CONFIG_SYS_INTR_BASE);
 
-	intp->int_icr1 &= ~INT_ICR1_TMR3MASK;
-	intp->int_icr1 |= CONFIG_SYS_TMRINTR_PRI;
+	clrbits_be32(&intp->int_icr1, INT_ICR1_TMR3MASK);
+	setbits_be32(&intp->int_icr1, CONFIG_SYS_TMRINTR_PRI);
 }
 #endif				/* CONFIG_MCFTMR */
 #endif				/* CONFIG_M5272 */
@@ -63,14 +65,14 @@ void dtimer_intr_setup(void)
     defined(CONFIG_M5271) || defined(CONFIG_M5275)
 int interrupt_init(void)
 {
-	volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+	int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
 
 	/* Make sure all interrupts are disabled */
 #if defined(CONFIG_M5208)
-	intp->imrl0 = 0xFFFFFFFF;
-	intp->imrh0 = 0xFFFFFFFF;
+	out_be32(&intp->imrl0, 0xffffffff);
+	out_be32(&intp->imrh0, 0xffffffff);
 #else
-	intp->imrl0 |= 0x1;
+	setbits_be32(&intp->imrl0, 0x1);
 #endif
 
 	enable_interrupts();
@@ -80,11 +82,11 @@ int interrupt_init(void)
 #if defined(CONFIG_MCFTMR)
 void dtimer_intr_setup(void)
 {
-	volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+	int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
 
-	intp->icr0[CONFIG_SYS_TMRINTR_NO] = CONFIG_SYS_TMRINTR_PRI;
-	intp->imrl0 &= 0xFFFFFFFE;
-	intp->imrl0 &= ~CONFIG_SYS_TMRINTR_MASK;
+	out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI);
+	clrbits_be32(&intp->imrl0, 0x00000001);
+	clrbits_be32(&intp->imrl0, CONFIG_SYS_TMRINTR_MASK);
 }
 #endif				/* CONFIG_MCFTMR */
 #endif				/* CONFIG_M5282 | CONFIG_M5271 | CONFIG_M5275 */

arch/m68k/cpu/mcf52x2/speed.c

@@ -2,7 +2,7 @@
  * (C) Copyright 2003
  * Josef Baumgartner <josef.baumgartner@telex.de>
  *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  * Hayden Fraser (Hayden.Fraser@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -27,6 +27,7 @@
 #include <common.h>
 #include <asm/processor.h>
 #include <asm/immap.h>
+#include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -34,10 +35,10 @@ DECLARE_GLOBAL_DATA_PTR;
 int get_clocks (void)
 {
 #if defined(CONFIG_M5208)
-	volatile pll_t *pll = (pll_t *) MMAP_PLL;
+	pll_t *pll = (pll_t *) MMAP_PLL;
 
-	pll->odr = CONFIG_SYS_PLL_ODR;
-	pll->fdr = CONFIG_SYS_PLL_FDR;
+	out_8(&pll->odr, CONFIG_SYS_PLL_ODR);
+	out_8(&pll->fdr, CONFIG_SYS_PLL_FDR);
 #endif
 
 #if defined(CONFIG_M5249) || defined(CONFIG_M5253)
@@ -70,14 +71,14 @@ int get_clocks (void)
 #endif				/* CONFIG_M5249 || CONFIG_M5253 */
 
 #if defined(CONFIG_M5275)
-	volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL);
+	pll_t *pll = (pll_t *)(MMAP_PLL);
 
 	/* Setup PLL */
-	pll->syncr = 0x01080000;
-	while (!(pll->synsr & FMPLL_SYNSR_LOCK))
+	out_be32(&pll->syncr, 0x01080000);
+	while (!(in_be32(&pll->synsr) & FMPLL_SYNSR_LOCK))
 		;
-	pll->syncr = 0x01000000;
-	while (!(pll->synsr & FMPLL_SYNSR_LOCK))
+	out_be32(&pll->syncr, 0x01000000);
+	while (!(in_be32(&pll->synsr) & FMPLL_SYNSR_LOCK))
 		;
 #endif
 

arch/m68k/cpu/mcf532x/cpu.c

@@ -3,7 +3,7 @@
  * (C) Copyright 2000-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -31,15 +31,16 @@
 #include <netdev.h>
 
 #include <asm/immap.h>
+#include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
-	volatile rcm_t *rcm = (rcm_t *) (MMAP_RCM);
+	rcm_t *rcm = (rcm_t *) (MMAP_RCM);
 
 	udelay(1000);
-	rcm->rcr |= RCM_RCR_SOFTRST;
+	setbits_8(&rcm->rcr, RCM_RCR_SOFTRST);
 
 	/* we don't return! */
 	return 0;
@@ -47,14 +48,14 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 int checkcpu(void)
 {
-	volatile ccm_t *ccm = (ccm_t *) MMAP_CCM;
+	ccm_t *ccm = (ccm_t *) MMAP_CCM;
 	u16 msk;
 	u16 id = 0;
 	u8 ver;
 
 	puts("CPU:   ");
-	msk = (ccm->cir >> 6);
-	ver = (ccm->cir & 0x003f);
+	msk = (in_be16(&ccm->cir) >> 6);
+	ver = (in_be16(&ccm->cir) & 0x003f);
 	switch (msk) {
 #ifdef CONFIG_MCF5301x
 	case 0x78:
@@ -115,18 +116,20 @@ int checkcpu(void)
 /* Called by macro WATCHDOG_RESET */
 void watchdog_reset(void)
 {
-	volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
+	wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
 
-	wdp->sr = 0x5555;	/* Count register */
-	wdp->sr = 0xAAAA;	/* Count register */
+	/* Count register */
+	out_be16(&wdp->sr, 0x5555);
+	out_be16(&wdp->sr, 0xaaaa);
 }
 
 int watchdog_disable(void)
 {
-	volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
+	wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
 
 	/* UserManual, once the wdog is disabled, wdog cannot be re-enabled */
-	wdp->cr |= WTM_WCR_HALTED;	/* halted watchdog timer */
+	/* halted watchdog timer */
+	setbits_be16(&wdp->cr, WTM_WCR_HALTED);
 
 	puts("WATCHDOG:disabled\n");
 	return (0);
@@ -134,18 +137,18 @@ int watchdog_disable(void)
 
 int watchdog_init(void)
 {
-	volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
+	wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
 	u32 wdog_module = 0;
 
 	/* set timeout and enable watchdog */
 	wdog_module = ((CONFIG_SYS_CLK / 1000) * CONFIG_WATCHDOG_TIMEOUT);
 #ifdef CONFIG_M5329
-	wdp->mr = (wdog_module / 8192);
+	out_be16(&wdp->mr, wdog_module / 8192);
 #else
-	wdp->mr = (wdog_module / 4096);
+	out_be16(&wdp->mr, wdog_module / 4096);
 #endif
 
-	wdp->cr = WTM_WCR_EN;
+	out_be16(&wdp->cr, WTM_WCR_EN);
 	puts("WATCHDOG:enabled\n");
 
 	return (0);

arch/m68k/cpu/mcf532x/cpu_init.c

@@ -3,7 +3,7 @@
  * (C) Copyright 2000-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * (C) Copyright 2004-2008 Freescale Semiconductor, Inc.
+ * (C) Copyright 2004-2008, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -28,6 +28,7 @@
 #include <common.h>
 #include <watchdog.h>
 #include <asm/immap.h>
+#include <asm/io.h>
 
 #if defined(CONFIG_CMD_NET)
 #include <config.h>
@@ -38,72 +39,68 @@
 #ifdef CONFIG_MCF5301x
 void cpu_init_f(void)
 {
-	volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
-	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-	volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
-
-	/* watchdog is enabled by default - disable the watchdog */
-#ifndef CONFIG_WATCHDOG
-	/*wdog->cr = 0; */
-#endif
-
-	scm1->mpr = 0x77777777;
-	scm1->pacra = 0;
-	scm1->pacrb = 0;
-	scm1->pacrc = 0;
-	scm1->pacrd = 0;
-	scm1->pacre = 0;
-	scm1->pacrf = 0;
-	scm1->pacrg = 0;
+	scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
+
+	out_be32(&scm1->mpr, 0x77777777);
+	out_be32(&scm1->pacra, 0);
+	out_be32(&scm1->pacrb, 0);
+	out_be32(&scm1->pacrc, 0);
+	out_be32(&scm1->pacrd, 0);
+	out_be32(&scm1->pacre, 0);
+	out_be32(&scm1->pacrf, 0);
+	out_be32(&scm1->pacrg, 0);
 
 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
      && defined(CONFIG_SYS_CS0_CTRL))
-	gpio->par_cs |= GPIO_PAR_CS0_CS0;
-	fbcs->csar0 = CONFIG_SYS_CS0_BASE;
-	fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
-	fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
+	setbits_8(&gpio->par_cs, GPIO_PAR_CS0_CS0);
+	out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
+	out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
+	out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
      && defined(CONFIG_SYS_CS1_CTRL))
-	gpio->par_cs |= GPIO_PAR_CS1_CS1;
-	fbcs->csar1 = CONFIG_SYS_CS1_BASE;
-	fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
-	fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
+	setbits_8(&gpio->par_cs, GPIO_PAR_CS1_CS1);
+	out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
+	out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
+	out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
      && defined(CONFIG_SYS_CS2_CTRL))
-	fbcs->csar2 = CONFIG_SYS_CS2_BASE;
-	fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
-	fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
+	out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
+	out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
+	out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
      && defined(CONFIG_SYS_CS3_CTRL))
-	fbcs->csar3 = CONFIG_SYS_CS3_BASE;
-	fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
-	fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
+	out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
+	out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
+	out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
      && defined(CONFIG_SYS_CS4_CTRL))
-	gpio->par_cs |= GPIO_PAR_CS4;
-	fbcs->csar4 = CONFIG_SYS_CS4_BASE;
-	fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
-	fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
+	setbits_8(&gpio->par_cs, GPIO_PAR_CS4);
+	out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
+	out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
+	out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
      && defined(CONFIG_SYS_CS5_CTRL))
-	gpio->par_cs |= GPIO_PAR_CS5;
-	fbcs->csar5 = CONFIG_SYS_CS5_BASE;
-	fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
-	fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
+	setbits_8(&gpio->par_cs, GPIO_PAR_CS5);
+	out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
+	out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
+	out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
 #endif
 
 #ifdef CONFIG_FSL_I2C
-	gpio->par_feci2c = GPIO_PAR_FECI2C_SDA_SDA | GPIO_PAR_FECI2C_SCL_SCL;
+	out_8(&gpio->par_feci2c,
+		GPIO_PAR_FECI2C_SDA_SDA | GPIO_PAR_FECI2C_SCL_SCL);
 #endif
 
 	icache_enable();
@@ -113,21 +110,21 @@ void cpu_init_f(void)
 int cpu_init_r(void)
 {
 #ifdef CONFIG_MCFFEC
-	volatile ccm_t *ccm = (ccm_t *) MMAP_CCM;
+	ccm_t *ccm = (ccm_t *) MMAP_CCM;
 #endif
 #ifdef CONFIG_MCFRTC
-	volatile rtc_t *rtc = (rtc_t *) (CONFIG_SYS_MCFRTC_BASE);
-	volatile rtcex_t *rtcex = (rtcex_t *) & rtc->extended;
+	rtc_t *rtc = (rtc_t *) (CONFIG_SYS_MCFRTC_BASE);
+	rtcex_t *rtcex = (rtcex_t *) &rtc->extended;
 
-	rtcex->gocu = CONFIG_SYS_RTC_CNT;
-	rtcex->gocl = CONFIG_SYS_RTC_SETUP;
+	out_be32(&rtcex->gocu, CONFIG_SYS_RTC_CNT);
+	out_be32(&rtcex->gocl, CONFIG_SYS_RTC_SETUP);
 
 #endif
 #ifdef CONFIG_MCFFEC
 	if (CONFIG_SYS_FEC0_MIIBASE != CONFIG_SYS_FEC1_MIIBASE)
-		ccm->misccr |= CCM_MISCCR_FECM;
+		setbits_be16(&ccm->misccr, CCM_MISCCR_FECM);
 	else
-		ccm->misccr &= ~CCM_MISCCR_FECM;
+		clrbits_be16(&ccm->misccr, CCM_MISCCR_FECM);
 #endif
 
 	return (0);
@@ -135,41 +132,52 @@ int cpu_init_r(void)
 
 void uart_port_conf(int port)
 {
-	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 
 	/* Setup Ports: */
 	switch (port) {
 	case 0:
-		gpio->par_uart &= ~(GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
-		gpio->par_uart |= (GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
+		clrbits_8(&gpio->par_uart,
+			GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
+		setbits_8(&gpio->par_uart,
+			GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
 		break;
 	case 1:
 #ifdef CONFIG_SYS_UART1_ALT1_GPIO
-		gpio->par_simp1h &=
-		    ~(GPIO_PAR_SIMP1H_DATA1_UNMASK |
-		      GPIO_PAR_SIMP1H_VEN1_UNMASK);
-		gpio->par_simp1h |=
-		    (GPIO_PAR_SIMP1H_DATA1_U1TXD | GPIO_PAR_SIMP1H_VEN1_U1RXD);
+		clrbits_8(&gpio->par_simp1h,
+			GPIO_PAR_SIMP1H_DATA1_UNMASK |
+			GPIO_PAR_SIMP1H_VEN1_UNMASK);
+		setbits_8(&gpio->par_simp1h,
+			GPIO_PAR_SIMP1H_DATA1_U1TXD |
+			GPIO_PAR_SIMP1H_VEN1_U1RXD);
 #elif defined(CONFIG_SYS_UART1_ALT2_GPIO)
-		gpio->par_ssih &=
-		    ~(GPIO_PAR_SSIH_RXD_UNMASK | GPIO_PAR_SSIH_TXD_UNMASK);
-		gpio->par_ssih |=
-		    (GPIO_PAR_SSIH_RXD_U1RXD | GPIO_PAR_SSIH_TXD_U1TXD);
+		clrbits_8(&gpio->par_ssih,
+			GPIO_PAR_SSIH_RXD_UNMASK |
+			GPIO_PAR_SSIH_TXD_UNMASK);
+		setbits_8(&gpio->par_ssih,
+			GPIO_PAR_SSIH_RXD_U1RXD |
+			GPIO_PAR_SSIH_TXD_U1TXD);
 #endif
 		break;
 	case 2:
 #ifdef CONFIG_SYS_UART2_PRI_GPIO
-		gpio->par_uart |= (GPIO_PAR_UART_U2TXD | GPIO_PAR_UART_U2RXD);
+		setbits_8(&gpio->par_uart,
+			GPIO_PAR_UART_U2TXD |
+			GPIO_PAR_UART_U2RXD);
 #elif defined(CONFIG_SYS_UART2_ALT1_GPIO)
-		gpio->par_dspih &=
-		    ~(GPIO_PAR_DSPIH_SIN_UNMASK | GPIO_PAR_DSPIH_SOUT_UNMASK);
-		gpio->par_dspih |=
-		    (GPIO_PAR_DSPIH_SIN_U2RXD | GPIO_PAR_DSPIH_SOUT_U2TXD);
+		clrbits_8(&gpio->par_dspih,
+			GPIO_PAR_DSPIH_SIN_UNMASK |
+			GPIO_PAR_DSPIH_SOUT_UNMASK);
+		setbits_8(&gpio->par_dspih,
+			GPIO_PAR_DSPIH_SIN_U2RXD |
+			GPIO_PAR_DSPIH_SOUT_U2TXD);
 #elif defined(CONFIG_SYS_UART2_ALT2_GPIO)
-		gpio->par_feci2c &=
-		    ~(GPIO_PAR_FECI2C_SDA_UNMASK | GPIO_PAR_FECI2C_SCL_UNMASK);
-		gpio->par_feci2c |=
-		    (GPIO_PAR_FECI2C_SDA_U2TXD | GPIO_PAR_FECI2C_SCL_U2RXD);
+		clrbits_8(&gpio->par_feci2c,
+			GPIO_PAR_FECI2C_SDA_UNMASK |
+			GPIO_PAR_FECI2C_SCL_UNMASK);
+		setbits_8(&gpio->par_feci2c,
+			GPIO_PAR_FECI2C_SDA_U2TXD |
+			GPIO_PAR_FECI2C_SCL_U2RXD);
 #endif
 		break;
 	}
@@ -178,30 +186,30 @@ void uart_port_conf(int port)
 #if defined(CONFIG_CMD_NET)
 int fecpin_setclear(struct eth_device *dev, int setclear)
 {
-	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 	struct fec_info_s *info = (struct fec_info_s *)dev->priv;
 
 	if (setclear) {
 		if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
-			gpio->par_fec |=
-			    GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC;
-			gpio->par_feci2c |=
-			    GPIO_PAR_FECI2C_MDC0 | GPIO_PAR_FECI2C_MDIO0;
+			setbits_8(&gpio->par_fec,
+				GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC);
+			setbits_8(&gpio->par_feci2c,
+				GPIO_PAR_FECI2C_MDC0 | GPIO_PAR_FECI2C_MDIO0);
 		} else {
-			gpio->par_fec |=
-			    GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC;
-			gpio->par_feci2c |=
-			    GPIO_PAR_FECI2C_MDC1 | GPIO_PAR_FECI2C_MDIO1;
+			setbits_8(&gpio->par_fec,
+				GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC);
+			setbits_8(&gpio->par_feci2c,
+				GPIO_PAR_FECI2C_MDC1 | GPIO_PAR_FECI2C_MDIO1);
 		}
 	} else {
 		if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
-			gpio->par_fec &=
-			    ~(GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC);
-			gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII0_UNMASK;
+			clrbits_8(&gpio->par_fec,
+				GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC);
+			clrbits_8(&gpio->par_feci2c, ~GPIO_PAR_FECI2C_RMII0_UNMASK);
 		} else {
-			gpio->par_fec &=
-			    ~(GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC);
-			gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII1_UNMASK;
+			clrbits_8(&gpio->par_fec,
+				GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC);
+			clrbits_8(&gpio->par_feci2c, ~GPIO_PAR_FECI2C_RMII1_UNMASK);
 		}
 	}
 	return 0;
@@ -212,80 +220,81 @@ int fecpin_setclear(struct eth_device *dev, int setclear)
 #ifdef CONFIG_MCF532x
 void cpu_init_f(void)
 {
-	volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
-	volatile scm2_t *scm2 = (scm2_t *) MMAP_SCM2;
-	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-	volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
-	volatile wdog_t *wdog = (wdog_t *) MMAP_WDOG;
+	scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
+	scm2_t *scm2 = (scm2_t *) MMAP_SCM2;
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
+	wdog_t *wdog = (wdog_t *) MMAP_WDOG;
 
 	/* watchdog is enabled by default - disable the watchdog */
 #ifndef CONFIG_WATCHDOG
-	wdog->cr = 0;
+	out_be16(&wdog->cr, 0);
 #endif
 
-	scm1->mpr0 = 0x77777777;
-	scm2->pacra = 0;
-	scm2->pacrb = 0;
-	scm2->pacrc = 0;
-	scm2->pacrd = 0;
-	scm2->pacre = 0;
-	scm2->pacrf = 0;
-	scm2->pacrg = 0;
-	scm1->pacrh = 0;
+	out_be32(&scm1->mpr0, 0x77777777);
+	out_be32(&scm2->pacra, 0);
+	out_be32(&scm2->pacrb, 0);
+	out_be32(&scm2->pacrc, 0);
+	out_be32(&scm2->pacrd, 0);
+	out_be32(&scm2->pacre, 0);
+	out_be32(&scm2->pacrf, 0);
+	out_be32(&scm2->pacrg, 0);
+	out_be32(&scm1->pacrh, 0);
 
 	/* Port configuration */
-	gpio->par_cs = 0;
+	out_8(&gpio->par_cs, 0);
 
 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
      && defined(CONFIG_SYS_CS0_CTRL))
-	fbcs->csar0 = CONFIG_SYS_CS0_BASE;
-	fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
-	fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
+	out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
+	out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
+	out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
      && defined(CONFIG_SYS_CS1_CTRL))
 	/* Latch chipselect */
-	gpio->par_cs |= GPIO_PAR_CS1;
-	fbcs->csar1 = CONFIG_SYS_CS1_BASE;
-	fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
-	fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
+	setbits_8(&gpio->par_cs, GPIO_PAR_CS1);
+	out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
+	out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
+	out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
      && defined(CONFIG_SYS_CS2_CTRL))
-	gpio->par_cs |= GPIO_PAR_CS2;
-	fbcs->csar2 = CONFIG_SYS_CS2_BASE;
-	fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
-	fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
+	setbits_8(&gpio->par_cs, GPIO_PAR_CS2);
+	out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
+	out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
+	out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
      && defined(CONFIG_SYS_CS3_CTRL))
-	gpio->par_cs |= GPIO_PAR_CS3;
-	fbcs->csar3 = CONFIG_SYS_CS3_BASE;
-	fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
-	fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
+	setbits_8(&gpio->par_cs, GPIO_PAR_CS3);
+	out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
+	out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
+	out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
      && defined(CONFIG_SYS_CS4_CTRL))
-	gpio->par_cs |= GPIO_PAR_CS4;
-	fbcs->csar4 = CONFIG_SYS_CS4_BASE;
-	fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
-	fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
+	setbits_8(&gpio->par_cs, GPIO_PAR_CS4);
+	out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
+	out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
+	out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
      && defined(CONFIG_SYS_CS5_CTRL))
-	gpio->par_cs |= GPIO_PAR_CS5;
-	fbcs->csar5 = CONFIG_SYS_CS5_BASE;
-	fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
-	fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
+	setbits_8(&gpio->par_cs, GPIO_PAR_CS5);
+	out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
+	out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
+	out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
 #endif
 
 #ifdef CONFIG_FSL_I2C
-	gpio->par_feci2c = GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA;
+	out_8(&gpio->par_feci2c,
+		GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA);
 #endif
 
 	icache_enable();
@@ -301,30 +310,35 @@ int cpu_init_r(void)
 
 void uart_port_conf(int port)
 {
-	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 
 	/* Setup Ports: */
 	switch (port) {
 	case 0:
-		gpio->par_uart &= ~(GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0);
-		gpio->par_uart |= (GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0);
+		clrbits_be16(&gpio->par_uart,
+			GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0);
+		setbits_be16(&gpio->par_uart,
+			GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0);
 		break;
 	case 1:
-		gpio->par_uart &=
-		    ~(GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3));
-		gpio->par_uart |=
-		    (GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3));
+		clrbits_be16(&gpio->par_uart,
+			GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3));
+		setbits_be16(&gpio->par_uart,
+			GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3));
 		break;
 	case 2:
 #ifdef CONFIG_SYS_UART2_ALT1_GPIO
-		gpio->par_timer &= 0x0F;
-		gpio->par_timer |= (GPIO_PAR_TIN3_URXD2 | GPIO_PAR_TIN2_UTXD2);
+		clrbits_8(&gpio->par_timer, 0xf0);
+		setbits_8(&gpio->par_timer,
+			GPIO_PAR_TIN3_URXD2 | GPIO_PAR_TIN2_UTXD2);
 #elif defined(CONFIG_SYS_UART2_ALT2_GPIO)
-		gpio->par_feci2c &= 0xFF00;
-		gpio->par_feci2c |= (GPIO_PAR_FECI2C_SCL_UTXD2 | GPIO_PAR_FECI2C_SDA_URXD2);
+		clrbits_8(&gpio->par_feci2c, 0x00ff);
+		setbits_8(&gpio->par_feci2c,
+			GPIO_PAR_FECI2C_SCL_UTXD2 | GPIO_PAR_FECI2C_SDA_URXD2);
 #elif defined(CONFIG_SYS_UART2_ALT3_GPIO)
-		gpio->par_ssi &= 0xF0FF;
-		gpio->par_ssi |= (GPIO_PAR_SSI_RXD(2) | GPIO_PAR_SSI_TXD(2));
+		clrbits_be16(&gpio->par_ssi, 0x0f00);
+		setbits_be16(&gpio->par_ssi,
+			GPIO_PAR_SSI_RXD(2) | GPIO_PAR_SSI_TXD(2));
 #endif
 		break;
 	}
@@ -333,16 +347,18 @@ void uart_port_conf(int port)
 #if defined(CONFIG_CMD_NET)
 int fecpin_setclear(struct eth_device *dev, int setclear)
 {
-	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 
 	if (setclear) {
-		gpio->par_fec |= GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC;
-		gpio->par_feci2c |=
-		    GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO;
+		setbits_8(&gpio->par_fec,
+			GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC);
+		setbits_8(&gpio->par_feci2c,
+			GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO);
 	} else {
-		gpio->par_fec &= ~(GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC);
-		gpio->par_feci2c &=
-		    ~(GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO);
+		clrbits_8(&gpio->par_fec,
+			GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC);
+		clrbits_8(&gpio->par_feci2c,
+			GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO);
 	}
 	return 0;
 }

arch/m68k/cpu/mcf532x/interrupts.c

@@ -1,6 +1,6 @@
 /*
  *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -25,14 +25,15 @@
 /* CPU specific interrupt routine */
 #include <common.h>
 #include <asm/immap.h>
+#include <asm/io.h>
 
 int interrupt_init(void)
 {
-	volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+	int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
 
 	/* Make sure all interrupts are disabled */
-	intp->imrh0 |= 0xFFFFFFFF;
-	intp->imrl0 |= 0xFFFFFFFF;
+	setbits_be32(&intp->imrh0, 0xffffffff);
+	setbits_be32(&intp->imrl0, 0xffffffff);
 
 	enable_interrupts();
 	return 0;
@@ -41,9 +42,9 @@ int interrupt_init(void)
 #if defined(CONFIG_MCFTMR)
 void dtimer_intr_setup(void)
 {
-	volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+	int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
 
-	intp->icr0[CONFIG_SYS_TMRINTR_NO] = CONFIG_SYS_TMRINTR_PRI;
-	intp->imrh0 &= ~CONFIG_SYS_TMRINTR_MASK;
+	out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI);
+	clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK);
 }
 #endif

arch/m68k/cpu/mcf532x/speed.c

@@ -3,7 +3,7 @@
  * (C) Copyright 2000-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -29,6 +29,7 @@
 #include <asm/processor.h>
 
 #include <asm/immap.h>
+#include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -65,13 +66,13 @@ DECLARE_GLOBAL_DATA_PTR;
 /* Get the value of the current system clock */
 int get_sys_clock(void)
 {
-	volatile ccm_t *ccm = (volatile ccm_t *)(MMAP_CCM);
-	volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL);
+	ccm_t *ccm = (ccm_t *)(MMAP_CCM);
+	pll_t *pll = (pll_t *)(MMAP_PLL);
 	int divider;
 
 	/* Test to see if device is in LIMP mode */
-	if (ccm->misccr & CCM_MISCCR_LIMP) {
-		divider = ccm->cdr & CCM_CDR_LPDIV(0xF);
+	if (in_be16(&ccm->misccr) & CCM_MISCCR_LIMP) {
+		divider = in_be16(&ccm->cdr) & CCM_CDR_LPDIV(0xF);
 #ifdef CONFIG_MCF5301x
 		return (FREF / (3 * (1 << divider)));
 #endif
@@ -80,14 +81,14 @@ int get_sys_clock(void)
 #endif
 	} else {
 #ifdef CONFIG_MCF5301x
-		u32 pfdr = (pll->pcr & 0x3F) + 1;
-		u32 refdiv = (1 << ((pll->pcr & PLL_PCR_REFDIV(7)) >> 8));
-		u32 busdiv = ((pll->pdr & 0x00F0) >> 4) + 1;
+		u32 pfdr = (in_be32(&pll->pcr) & 0x3F) + 1;
+		u32 refdiv = (1 << ((in_be32(&pll->pcr) & PLL_PCR_REFDIV(7)) >> 8));
+		u32 busdiv = ((in_be32(&pll->pdr) & 0x00F0) >> 4) + 1;
 
 		return (((FREF * pfdr) / refdiv) / busdiv);
 #endif
 #ifdef CONFIG_MCF532x
-		return ((FREF * pll->pfdr) / (BUSDIV * 4));
+		return (FREF * in_8(&pll->pfdr)) / (BUSDIV * 4);
 #endif
 	}
 }
@@ -103,7 +104,7 @@ int get_sys_clock(void)
  */
 int clock_limp(int div)
 {
-	volatile ccm_t *ccm = (volatile ccm_t *)(MMAP_CCM);
+	ccm_t *ccm = (ccm_t *)(MMAP_CCM);
 	u32 temp;
 
 	/* Check bounds of divider */
@@ -113,12 +114,12 @@ int clock_limp(int div)
 		div = MAX_LPD;
 
 	/* Save of the current value of the SSIDIV so we don't overwrite the value */
-	temp = (ccm->cdr & CCM_CDR_SSIDIV(0xFF));
+	temp = (in_be16(&ccm->cdr) & CCM_CDR_SSIDIV(0xFF));
 
 	/* Apply the divider to the system clock */
-	ccm->cdr = (CCM_CDR_LPDIV(div) | CCM_CDR_SSIDIV(temp));
+	out_be16(&ccm->cdr, CCM_CDR_LPDIV(div) | CCM_CDR_SSIDIV(temp));
 
-	ccm->misccr |= CCM_MISCCR_LIMP;
+	setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
 
 	return (FREF / (3 * (1 << div)));
 }
@@ -126,14 +127,15 @@ int clock_limp(int div)
 /* Exit low power LIMP mode */
 int clock_exit_limp(void)
 {
-	volatile ccm_t *ccm = (volatile ccm_t *)(MMAP_CCM);
+	ccm_t *ccm = (ccm_t *)(MMAP_CCM);
 	int fout;
 
 	/* Exit LIMP mode */
-	ccm->misccr &= (~CCM_MISCCR_LIMP);
+	clrbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
 
 	/* Wait for PLL to lock */
-	while (!(ccm->misccr & CCM_MISCCR_PLL_LOCK)) ;
+	while (!(in_be16(&ccm->misccr) & CCM_MISCCR_PLL_LOCK))
+		;
 
 	fout = get_sys_clock();
 
@@ -153,10 +155,10 @@ int clock_exit_limp(void)
 int clock_pll(int fsys, int flags)
 {
 #ifdef CONFIG_MCF532x
-	volatile u32 *sdram_workaround = (volatile u32 *)(MMAP_SDRAM + 0x80);
+	u32 *sdram_workaround = (u32 *)(MMAP_SDRAM + 0x80);
 #endif
-	volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
-	volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL);
+	sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
+	pll_t *pll = (pll_t *)(MMAP_PLL);
 	int fref, temp, fout, mfd;
 	u32 i;
 
@@ -165,13 +167,13 @@ int clock_pll(int fsys, int flags)
 	if (fsys == 0) {
 		/* Return current PLL output */
 #ifdef CONFIG_MCF5301x
-		u32 busdiv = ((pll->pdr >> 4) & 0x0F) + 1;
-		mfd = (pll->pcr & 0x3F) + 1;
+		u32 busdiv = ((in_be32(&pll->pdr) >> 4) & 0x0F) + 1;
+		mfd = (in_be32(&pll->pcr) & 0x3F) + 1;
 
 		return (fref * mfd) / busdiv;
 #endif
 #ifdef CONFIG_MCF532x
-		mfd = pll->pfdr;
+		mfd = in_8(&pll->pfdr);
 
 		return (fref * mfd / (BUSDIV * 4));
 #endif
@@ -211,8 +213,8 @@ int clock_pll(int fsys, int flags)
 	 * If it has then the SDRAM needs to be put into self refresh
 	 * mode before reprogramming the PLL.
 	 */
-	if (sdram->ctrl & SDRAMC_SDCR_REF)
-		sdram->ctrl &= ~SDRAMC_SDCR_CKE;
+	if (in_be32(&sdram->ctrl) & SDRAMC_SDCR_REF)
+		clrbits_be32(&sdram->ctrl, SDRAMC_SDCR_CKE);
 
 	/*
 	 * Initialize the PLL to generate the new system clock frequency.
@@ -223,35 +225,36 @@ int clock_pll(int fsys, int flags)
 	clock_limp(DEFAULT_LPD);
 
 #ifdef CONFIG_MCF5301x
-	pll->pdr =
-	    PLL_PDR_OUTDIV1((BUSDIV / 3) - 1)	|
-	    PLL_PDR_OUTDIV2(BUSDIV - 1)	|
-	    PLL_PDR_OUTDIV3((BUSDIV / 2) - 1)	|
-	    PLL_PDR_OUTDIV4(USBDIV - 1);
-
-	pll->pcr &= PLL_PCR_FBDIV_UNMASK;
-	pll->pcr |= PLL_PCR_FBDIV(mfd - 1);
+	out_be32(&pll->pdr,
+		PLL_PDR_OUTDIV1((BUSDIV / 3) - 1) |
+		PLL_PDR_OUTDIV2(BUSDIV - 1)	|
+		PLL_PDR_OUTDIV3((BUSDIV / 2) - 1) |
+		PLL_PDR_OUTDIV4(USBDIV - 1));
+
+	clrbits_be32(&pll->pcr, ~PLL_PCR_FBDIV_UNMASK);
+	setbits_be32(&pll->pcr, PLL_PCR_FBDIV(mfd - 1));
 #endif
 #ifdef CONFIG_MCF532x
 	/* Reprogram PLL for desired fsys */
-	pll->podr = (PLL_PODR_CPUDIV(BUSDIV / 3) | PLL_PODR_BUSDIV(BUSDIV));
+	out_8(&pll->podr,
+		PLL_PODR_CPUDIV(BUSDIV / 3) | PLL_PODR_BUSDIV(BUSDIV));
 
-	pll->pfdr = mfd;
+	out_8(&pll->pfdr, mfd);
 #endif
 
 	/* Exit LIMP mode */
 	clock_exit_limp();
 
 	/* Return the SDRAM to normal operation if it is in use. */
-	if (sdram->ctrl & SDRAMC_SDCR_REF)
-		sdram->ctrl |= SDRAMC_SDCR_CKE;
+	if (in_be32(&sdram->ctrl) & SDRAMC_SDCR_REF)
+		setbits_be32(&sdram->ctrl, SDRAMC_SDCR_CKE);
 
 #ifdef CONFIG_MCF532x
 	/*
 	 * software workaround for SDRAM opeartion after exiting LIMP
 	 * mode errata
 	 */
-	*sdram_workaround = CONFIG_SYS_SDRAM_BASE;
+	out_be32(sdram_workaround, CONFIG_SYS_SDRAM_BASE);
 #endif
 
 	/* wait for DQS logic to relock */

arch/m68k/cpu/mcf5445x/cpu.c

@@ -3,7 +3,7 @@
  * (C) Copyright 2000-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -31,14 +31,15 @@
 #include <netdev.h>
 
 #include <asm/immap.h>
+#include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
-	volatile rcm_t *rcm = (rcm_t *) (MMAP_RCM);
+	rcm_t *rcm = (rcm_t *) (MMAP_RCM);
 	udelay(1000);
-	rcm->rcr |= RCM_RCR_SOFTRST;
+	setbits_8(&rcm->rcr, RCM_RCR_SOFTRST);
 
 	/* we don't return! */
 	return 0;
@@ -46,14 +47,14 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 int checkcpu(void)
 {
-	volatile ccm_t *ccm = (ccm_t *) MMAP_CCM;
+	ccm_t *ccm = (ccm_t *) MMAP_CCM;
 	u16 msk;
 	u16 id = 0;
 	u8 ver;
 
 	puts("CPU:   ");
-	msk = (ccm->cir >> 6);
-	ver = (ccm->cir & 0x003f);
+	msk = (in_be16(&ccm->cir) >> 6);
+	ver = (in_be16(&ccm->cir) & 0x003f);
 	switch (msk) {
 	case 0x48:
 		id = 54455;

arch/m68k/cpu/mcf5445x/cpu_init.c

@@ -3,7 +3,7 @@
  * (C) Copyright 2000-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * (C) Copyright 2004-2007 Freescale Semiconductor, Inc.
+ * (C) Copyright 2004-2007, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -30,6 +30,7 @@
 #include <asm/immap.h>
 #include <asm/processor.h>
 #include <asm/rtc.h>
+#include <asm/io.h>
 
 #if defined(CONFIG_CMD_NET)
 #include <config.h>
@@ -46,64 +47,64 @@
  */
 void cpu_init_f(void)
 {
-	volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
-	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-	volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
-
-	scm1->mpr = 0x77777777;
-	scm1->pacra = 0;
-	scm1->pacrb = 0;
-	scm1->pacrc = 0;
-	scm1->pacrd = 0;
-	scm1->pacre = 0;
-	scm1->pacrf = 0;
-	scm1->pacrg = 0;
+	scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
+
+	out_be32(&scm1->mpr, 0x77777777);
+	out_be32(&scm1->pacra, 0);
+	out_be32(&scm1->pacrb, 0);
+	out_be32(&scm1->pacrc, 0);
+	out_be32(&scm1->pacrd, 0);
+	out_be32(&scm1->pacre, 0);
+	out_be32(&scm1->pacrf, 0);
+	out_be32(&scm1->pacrg, 0);
 
 	/* FlexBus */
-	gpio->par_be =
-	    GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 | GPIO_PAR_BE_BE1_BE1 |
-	    GPIO_PAR_BE_BE0_BE0;
-	gpio->par_fbctl =
-	    GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA | GPIO_PAR_FBCTL_RW_RW |
-	    GPIO_PAR_FBCTL_TS_TS;
+	out_8(&gpio->par_be,
+		GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 |
+		GPIO_PAR_BE_BE1_BE1 | GPIO_PAR_BE_BE0_BE0);
+	out_8(&gpio->par_fbctl,
+		GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA |
+		GPIO_PAR_FBCTL_RW_RW | GPIO_PAR_FBCTL_TS_TS);
 
 #if !defined(CONFIG_CF_SBF)
 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
-	fbcs->csar0 = CONFIG_SYS_CS0_BASE;
-	fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
-	fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
+	out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
+	out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
+	out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
 #endif
 #endif
 
 #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
 	/* Latch chipselect */
-	fbcs->csar1 = CONFIG_SYS_CS1_BASE;
-	fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
-	fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
+	out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
+	out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
+	out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
-	fbcs->csar2 = CONFIG_SYS_CS2_BASE;
-	fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
-	fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
+	out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
+	out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
+	out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
-	fbcs->csar3 = CONFIG_SYS_CS3_BASE;
-	fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
-	fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
+	out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
+	out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
+	out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
-	fbcs->csar4 = CONFIG_SYS_CS4_BASE;
-	fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
-	fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
+	out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
+	out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
+	out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
-	fbcs->csar5 = CONFIG_SYS_CS5_BASE;
-	fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
-	fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
+	out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
+	out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
+	out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
 #endif
 
 	/*
@@ -115,7 +116,8 @@ void cpu_init_f(void)
 		setvbr(CONFIG_SYS_CS0_BASE);
 
 #ifdef CONFIG_FSL_I2C
-	gpio->par_feci2c = GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA;
+	out_be16(&gpio->par_feci2c,
+		GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA);
 #endif
 
 	icache_enable();
@@ -127,11 +129,11 @@ void cpu_init_f(void)
 int cpu_init_r(void)
 {
 #ifdef CONFIG_MCFRTC
-	volatile rtc_t *rtc = (volatile rtc_t *)(CONFIG_SYS_MCFRTC_BASE);
-	volatile rtcex_t *rtcex = (volatile rtcex_t *)&rtc->extended;
+	rtc_t *rtc = (rtc_t *)(CONFIG_SYS_MCFRTC_BASE);
+	rtcex_t *rtcex = (rtcex_t *)&rtc->extended;
 
-	rtcex->gocu = (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xFFFF;
-	rtcex->gocl = CONFIG_SYS_RTC_OSCILLATOR & 0xFFFF;
+	out_be32(&rtcex->gocu, (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xffff);
+	out_be32(&rtcex->gocl, CONFIG_SYS_RTC_OSCILLATOR & 0xffff);
 #endif
 
 	return (0);
@@ -139,40 +141,40 @@ int cpu_init_r(void)
 
 void uart_port_conf(int port)
 {
-	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 
 	/* Setup Ports: */
 	switch (port) {
 	case 0:
-		gpio->par_uart &=
-		    ~(GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
-		gpio->par_uart |=
-		    (GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
+		clrbits_8(&gpio->par_uart,
+			GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
+		setbits_8(&gpio->par_uart,
+			GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
 		break;
 	case 1:
 #ifdef CONFIG_SYS_UART1_PRI_GPIO
-		gpio->par_uart &=
-		    ~(GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
-		gpio->par_uart |=
-		    (GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
+		clrbits_8(&gpio->par_uart,
+			GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
+		setbits_8(&gpio->par_uart,
+			GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
 #elif defined(CONFIG_SYS_UART1_ALT1_GPIO)
-		gpio->par_ssi &=
-		    (GPIO_PAR_SSI_SRXD_UNMASK | GPIO_PAR_SSI_STXD_UNMASK);
-		gpio->par_ssi |=
-		    (GPIO_PAR_SSI_SRXD_U1RXD | GPIO_PAR_SSI_STXD_U1TXD);
+		clrbits_be16(&gpio->par_ssi,
+			~(GPIO_PAR_SSI_SRXD_UNMASK | GPIO_PAR_SSI_STXD_UNMASK));
+		setbits_be16(&gpio->par_ssi,
+			GPIO_PAR_SSI_SRXD_U1RXD | GPIO_PAR_SSI_STXD_U1TXD);
 #endif
 		break;
 	case 2:
 #if defined(CONFIG_SYS_UART2_ALT1_GPIO)
-		gpio->par_timer &=
-		    (GPIO_PAR_TIMER_T3IN_UNMASK | GPIO_PAR_TIMER_T2IN_UNMASK);
-		gpio->par_timer |=
-		    (GPIO_PAR_TIMER_T3IN_U2RXD | GPIO_PAR_TIMER_T2IN_U2TXD);
+		clrbits_8(&gpio->par_timer,
+			~(GPIO_PAR_TIMER_T3IN_UNMASK | GPIO_PAR_TIMER_T2IN_UNMASK));
+		setbits_8(&gpio->par_timer,
+			GPIO_PAR_TIMER_T3IN_U2RXD | GPIO_PAR_TIMER_T2IN_U2TXD);
 #elif defined(CONFIG_SYS_UART2_ALT2_GPIO)
-		gpio->par_timer &=
-		    (GPIO_PAR_FECI2C_SCL_UNMASK | GPIO_PAR_FECI2C_SDA_UNMASK);
-		gpio->par_timer |=
-		    (GPIO_PAR_FECI2C_SCL_U2TXD | GPIO_PAR_FECI2C_SDA_U2RXD);
+		clrbits_8(&gpio->par_timer,
+			~(GPIO_PAR_FECI2C_SCL_UNMASK | GPIO_PAR_FECI2C_SDA_UNMASK));
+		setbits_8(&gpio->par_timer,
+			GPIO_PAR_FECI2C_SCL_U2TXD | GPIO_PAR_FECI2C_SDA_U2RXD);
 #endif
 		break;
 	}
@@ -181,43 +183,43 @@ void uart_port_conf(int port)
 #if defined(CONFIG_CMD_NET)
 int fecpin_setclear(struct eth_device *dev, int setclear)
 {
-	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 	struct fec_info_s *info = (struct fec_info_s *)dev->priv;
 
 	if (setclear) {
 #ifdef CONFIG_SYS_FEC_NO_SHARED_PHY
 		if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
-			gpio->par_feci2c |=
-			    (GPIO_PAR_FECI2C_MDC0_MDC0 |
-			     GPIO_PAR_FECI2C_MDIO0_MDIO0);
+			setbits_be16(&gpio->par_feci2c,
+				GPIO_PAR_FECI2C_MDC0_MDC0 |
+				GPIO_PAR_FECI2C_MDIO0_MDIO0);
 		else
-			gpio->par_feci2c |=
-			    (GPIO_PAR_FECI2C_MDC1_MDC1 |
-			     GPIO_PAR_FECI2C_MDIO1_MDIO1);
+			setbits_be16(&gpio->par_feci2c,
+				GPIO_PAR_FECI2C_MDC1_MDC1 |
+				GPIO_PAR_FECI2C_MDIO1_MDIO1);
 #else
-		gpio->par_feci2c |=
-		    (GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
+		setbits_be16(&gpio->par_feci2c,
+			GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
 #endif
 
 		if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
-			gpio->par_fec |= GPIO_PAR_FEC_FEC0_RMII_GPIO;
+			setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC0_RMII_GPIO);
 		else
-			gpio->par_fec |= GPIO_PAR_FEC_FEC1_RMII_ATA;
+			setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC1_RMII_ATA);
 	} else {
-		gpio->par_feci2c &=
-		    ~(GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
+		clrbits_be16(&gpio->par_feci2c,
+			GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
 
 		if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
 #ifdef CONFIG_SYS_FEC_FULL_MII
-			gpio->par_fec |= GPIO_PAR_FEC_FEC0_MII;
+			setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC0_MII);
 #else
-			gpio->par_fec &= GPIO_PAR_FEC_FEC0_UNMASK;
+			clrbits_8(&gpio->par_fec, ~GPIO_PAR_FEC_FEC0_UNMASK);
 #endif
 		} else {
 #ifdef CONFIG_SYS_FEC_FULL_MII
-			gpio->par_fec |= GPIO_PAR_FEC_FEC1_MII;
+			setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC1_MII);
 #else
-			gpio->par_fec &= GPIO_PAR_FEC_FEC1_UNMASK;
+			clrbits_8(&gpio->par_fec, ~GPIO_PAR_FEC_FEC1_UNMASK);
 #endif
 		}
 	}
@@ -228,43 +230,45 @@ int fecpin_setclear(struct eth_device *dev, int setclear)
 #ifdef CONFIG_CF_DSPI
 void cfspi_port_conf(void)
 {
-	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 
-	gpio->par_dspi = GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT |
-	    GPIO_PAR_DSPI_SCK_SCK;
+	out_8(&gpio->par_dspi,
+		GPIO_PAR_DSPI_SIN_SIN |
+		GPIO_PAR_DSPI_SOUT_SOUT |
+		GPIO_PAR_DSPI_SCK_SCK);
 }
 
 int cfspi_claim_bus(uint bus, uint cs)
 {
-	volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
-	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	dspi_t *dspi = (dspi_t *) MMAP_DSPI;
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 
-	if ((dspi->sr & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
+	if ((in_be32(&dspi->sr) & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
 		return -1;
 
 	/* Clear FIFO and resume transfer */
-	dspi->mcr &= ~(DSPI_MCR_CTXF | DSPI_MCR_CRXF);
+	clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
 
 	switch (cs) {
 	case 0:
-		gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0;
-		gpio->par_dspi |= GPIO_PAR_DSPI_PCS0_PCS0;
+		clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
+		setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
 		break;
 	case 1:
-		gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS1_PCS1;
-		gpio->par_dspi |= GPIO_PAR_DSPI_PCS1_PCS1;
+		clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
+		setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
 		break;
 	case 2:
-		gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS2_PCS2;
-		gpio->par_dspi |= GPIO_PAR_DSPI_PCS2_PCS2;
+		clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
+		setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
 		break;
 	case 3:
-		gpio->par_dma &= GPIO_PAR_DMA_DACK0_UNMASK;
-		gpio->par_dma |= GPIO_PAR_DMA_DACK0_PCS3;
+		clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK);
+		setbits_8(&gpio->par_dma, GPIO_PAR_DMA_DACK0_PCS3);
 		break;
 	case 5:
-		gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS5_PCS5;
-		gpio->par_dspi |= GPIO_PAR_DSPI_PCS5_PCS5;
+		clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
+		setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
 		break;
 	}
 
@@ -273,26 +277,27 @@ int cfspi_claim_bus(uint bus, uint cs)
 
 void cfspi_release_bus(uint bus, uint cs)
 {
-	volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
-	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	dspi_t *dspi = (dspi_t *) MMAP_DSPI;
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 
-	dspi->mcr &= ~(DSPI_MCR_CTXF | DSPI_MCR_CRXF);	/* Clear FIFO */
+	/* Clear FIFO */
+	clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
 
 	switch (cs) {
 	case 0:
-		gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0;
+		clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
 		break;
 	case 1:
-		gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS1_PCS1;
+		clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
 		break;
 	case 2:
-		gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS2_PCS2;
+		clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
 		break;
 	case 3:
-		gpio->par_dma &= GPIO_PAR_DMA_DACK0_UNMASK;
+		clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK);
 		break;
 	case 5:
-		gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS5_PCS5;
+		clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
 		break;
 	}
 }

arch/m68k/cpu/mcf5445x/interrupts.c

@@ -3,7 +3,7 @@
  * (C) Copyright 2000-2004
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -28,14 +28,15 @@
 /* CPU specific interrupt routine */
 #include <common.h>
 #include <asm/immap.h>
+#include <asm/io.h>
 
 int interrupt_init(void)
 {
-	volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+	int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
 
 	/* Make sure all interrupts are disabled */
-	intp->imrh0 |= 0xFFFFFFFF;
-	intp->imrl0 |= 0xFFFFFFFF;
+	setbits_be32(&intp->imrh0, 0xffffffff);
+	setbits_be32(&intp->imrl0, 0xffffffff);
 
 	enable_interrupts();
 	return 0;
@@ -44,9 +45,9 @@ int interrupt_init(void)
 #if defined(CONFIG_MCFTMR)
 void dtimer_intr_setup(void)
 {
-	volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+	int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
 
-	intp->icr0[CONFIG_SYS_TMRINTR_NO] = CONFIG_SYS_TMRINTR_PRI;
-	intp->imrh0 &= ~CONFIG_SYS_TMRINTR_MASK;
+	out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI);
+	clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK);
 }
 #endif

arch/m68k/cpu/mcf5445x/pci.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -60,78 +60,82 @@ PCI_OP(write, dword, u32, out_le32, 0)
 
 void pci_mcf5445x_init(struct pci_controller *hose)
 {
-	volatile pci_t *pci = (volatile pci_t *)MMAP_PCI;
-	volatile pciarb_t *pciarb = (volatile pciarb_t *)MMAP_PCIARB;
-	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	pci_t *pci = (pci_t *)MMAP_PCI;
+	pciarb_t *pciarb = (pciarb_t *)MMAP_PCIARB;
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 	u32 barEn = 0;
 
-	pciarb->acr = 0x001F001F;
+	out_be32(&pciarb->acr, 0x001f001f);
 
 	/* Set PCIGNT1, PCIREQ1, PCIREQ0/PCIGNTIN, PCIGNT0/PCIREQOUT,
 	   PCIREQ2, PCIGNT2 */
-	gpio->par_pci =
-	    GPIO_PAR_PCI_GNT3_GNT3 | GPIO_PAR_PCI_GNT2 | GPIO_PAR_PCI_GNT1 |
-	    GPIO_PAR_PCI_GNT0 | GPIO_PAR_PCI_REQ3_REQ3 | GPIO_PAR_PCI_REQ2 |
-	    GPIO_PAR_PCI_REQ1 | GPIO_PAR_PCI_REQ0;
+	out_be16(&gpio->par_pci,
+		GPIO_PAR_PCI_GNT3_GNT3 | GPIO_PAR_PCI_GNT2 |
+		GPIO_PAR_PCI_GNT1 | GPIO_PAR_PCI_GNT0 |
+		GPIO_PAR_PCI_REQ3_REQ3 | GPIO_PAR_PCI_REQ2 |
+		GPIO_PAR_PCI_REQ1 | GPIO_PAR_PCI_REQ0);
 
 	/* Assert reset bit */
-	pci->gscr |= PCI_GSCR_PR;
+	setbits_be32(&pci->gscr, PCI_GSCR_PR);
 
-	pci->tcr1 |= PCI_TCR1_P;
+	setbits_be32(&pci->tcr1, PCI_TCR1_P);
 
 	/* Initiator windows */
-	pci->iw0btar = CONFIG_SYS_PCI_MEM_PHYS | (CONFIG_SYS_PCI_MEM_PHYS >> 16);
-	pci->iw1btar = CONFIG_SYS_PCI_IO_PHYS | (CONFIG_SYS_PCI_IO_PHYS >> 16);
-	pci->iw2btar = CONFIG_SYS_PCI_CFG_PHYS | (CONFIG_SYS_PCI_CFG_PHYS >> 16);
+	out_be32(&pci->iw0btar,
+		CONFIG_SYS_PCI_MEM_PHYS | (CONFIG_SYS_PCI_MEM_PHYS >> 16));
+	out_be32(&pci->iw1btar,
+		CONFIG_SYS_PCI_IO_PHYS | (CONFIG_SYS_PCI_IO_PHYS >> 16));
+	out_be32(&pci->iw2btar,
+		CONFIG_SYS_PCI_CFG_PHYS | (CONFIG_SYS_PCI_CFG_PHYS >> 16));
 
-	pci->iwcr =
-	    PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO |
-	    PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO;
+	out_be32(&pci->iwcr,
+		PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO |
+		PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO);
 
-	pci->icr = 0;
+	out_be32(&pci->icr, 0);
 
 	/* Enable bus master and mem access */
-	pci->scr = PCI_SCR_B | PCI_SCR_M;
+	out_be32(&pci->scr, PCI_SCR_B | PCI_SCR_M);
 
 	/* Cache line size and master latency */
-	pci->cr1 = PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xF8);
-	pci->cr2 = 0;
+	out_be32(&pci->cr1, PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xF8));
+	out_be32(&pci->cr2, 0);
 
 #ifdef CONFIG_SYS_PCI_BAR0
-	pci->bar0 = PCI_BAR_BAR0(CONFIG_SYS_PCI_BAR0);
-	pci->tbatr0 = CONFIG_SYS_PCI_TBATR0 | PCI_TBATR_EN;
+	out_be32(&pci->bar0, PCI_BAR_BAR0(CONFIG_SYS_PCI_BAR0));
+	out_be32(&pci->tbatr0, CONFIG_SYS_PCI_TBATR0 | PCI_TBATR_EN);
 	barEn |= PCI_TCR2_B0E;
 #endif
 #ifdef CONFIG_SYS_PCI_BAR1
-	pci->bar1 = PCI_BAR_BAR1(CONFIG_SYS_PCI_BAR1);
-	pci->tbatr1 = CONFIG_SYS_PCI_TBATR1 | PCI_TBATR_EN;
+	out_be32(&pci->bar1, PCI_BAR_BAR1(CONFIG_SYS_PCI_BAR1));
+	out_be32(&pci->tbatr1, CONFIG_SYS_PCI_TBATR1 | PCI_TBATR_EN);
 	barEn |= PCI_TCR2_B1E;
 #endif
 #ifdef CONFIG_SYS_PCI_BAR2
-	pci->bar2 = PCI_BAR_BAR2(CONFIG_SYS_PCI_BAR2);
-	pci->tbatr2 = CONFIG_SYS_PCI_TBATR2 | PCI_TBATR_EN;
+	out_be32(&pci->bar2, PCI_BAR_BAR2(CONFIG_SYS_PCI_BAR2));
+	out_be32(&pci->tbatr2, CONFIG_SYS_PCI_TBATR2 | PCI_TBATR_EN);
 	barEn |= PCI_TCR2_B2E;
 #endif
 #ifdef CONFIG_SYS_PCI_BAR3
-	pci->bar3 = PCI_BAR_BAR3(CONFIG_SYS_PCI_BAR3);
-	pci->tbatr3 = CONFIG_SYS_PCI_TBATR3 | PCI_TBATR_EN;
+	out_be32(&pci->bar3, PCI_BAR_BAR3(CONFIG_SYS_PCI_BAR3));
+	out_be32(&pci->tbatr3, CONFIG_SYS_PCI_TBATR3 | PCI_TBATR_EN);
 	barEn |= PCI_TCR2_B3E;
 #endif
 #ifdef CONFIG_SYS_PCI_BAR4
-	pci->bar4 = PCI_BAR_BAR4(CONFIG_SYS_PCI_BAR4);
-	pci->tbatr4 = CONFIG_SYS_PCI_TBATR4 | PCI_TBATR_EN;
+	out_be32(&pci->bar4, PCI_BAR_BAR4(CONFIG_SYS_PCI_BAR4));
+	out_be32(&pci->tbatr4, CONFIG_SYS_PCI_TBATR4 | PCI_TBATR_EN);
 	barEn |= PCI_TCR2_B4E;
 #endif
 #ifdef CONFIG_SYS_PCI_BAR5
-	pci->bar5 = PCI_BAR_BAR5(CONFIG_SYS_PCI_BAR5);
-	pci->tbatr5 = CONFIG_SYS_PCI_TBATR5 | PCI_TBATR_EN;
+	out_be32(&pci->bar5, PCI_BAR_BAR5(CONFIG_SYS_PCI_BAR5));
+	out_be32(&pci->tbatr5, CONFIG_SYS_PCI_TBATR5 | PCI_TBATR_EN);
 	barEn |= PCI_TCR2_B5E;
 #endif
 
-	pci->tcr2 = barEn;
+	out_be32(&pci->tcr2, barEn);
 
 	/* Deassert reset bit */
-	pci->gscr &= ~PCI_GSCR_PR;
+	clrbits_be32(&pci->gscr, PCI_GSCR_PR);
 	udelay(1000);
 
 	/* Enable PCI bus master support */

arch/m68k/cpu/mcf5445x/speed.c

@@ -1,6 +1,6 @@
 /*
  *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -26,6 +26,7 @@
 #include <asm/processor.h>
 
 #include <asm/immap.h>
+#include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -44,7 +45,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 void clock_enter_limp(int lpdiv)
 {
-	volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM;
+	ccm_t *ccm = (ccm_t *)MMAP_CCM;
 	int i, j;
 
 	/* Check bounds of divider */
@@ -57,10 +58,10 @@ void clock_enter_limp(int lpdiv)
 	for (i = 0, j = lpdiv; j != 1; j >>= 1, i++) ;
 
 	/* Apply the divider to the system clock */
-	ccm->cdr = (ccm->cdr & 0xF0FF) | CCM_CDR_LPDIV(i);
+	clrsetbits_be16(&ccm->cdr, 0x0f00, CCM_CDR_LPDIV(i));
 
 	/* Enable Limp Mode */
-	ccm->misccr |= CCM_MISCCR_LIMP;
+	setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
 }
 
 /*
@@ -69,14 +70,15 @@ void clock_enter_limp(int lpdiv)
  */
 void clock_exit_limp(void)
 {
-	volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM;
-	volatile pll_t *pll = (volatile pll_t *)MMAP_PLL;
+	ccm_t *ccm = (ccm_t *)MMAP_CCM;
+	pll_t *pll = (pll_t *)MMAP_PLL;
 
 	/* Exit Limp mode */
-	ccm->misccr &= ~CCM_MISCCR_LIMP;
+	clrbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
 
 	/* Wait for the PLL to lock */
-	while (!(pll->psr & PLL_PSR_LOCK)) ;
+	while (!(in_be32(&pll->psr) & PLL_PSR_LOCK))
+		;
 }
 
 /*
@@ -85,8 +87,8 @@ void clock_exit_limp(void)
 int get_clocks(void)
 {
 
-	volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM;
-	volatile pll_t *pll = (volatile pll_t *)MMAP_PLL;
+	ccm_t *ccm = (ccm_t *)MMAP_CCM;
+	pll_t *pll = (pll_t *)MMAP_PLL;
 	int pllmult_nopci[] = { 20, 10, 24, 18, 12, 6, 16, 8 };
 	int pllmult_pci[] = { 12, 6, 16, 8 };
 	int vco = 0, bPci, temp, fbtemp, pcrvalue;
@@ -94,13 +96,13 @@ int get_clocks(void)
 	u16 fbpll_mask;
 
 #ifdef CONFIG_M54455EVB
-	volatile u8 *cpld = (volatile u8 *)(CONFIG_SYS_CS2_BASE + 3);
+	u8 *cpld = (u8 *)(CONFIG_SYS_CS2_BASE + 3);
 #endif
 	u8 bootmode;
 
 	/* To determine PCI is present or not */
-	if (((ccm->ccr & CCM_CCR_360_FBCONFIG_MASK) == 0x00e0) ||
-	    ((ccm->ccr & CCM_CCR_360_FBCONFIG_MASK) == 0x0060)) {
+	if (((in_be16(&ccm->ccr) & CCM_CCR_360_FBCONFIG_MASK) == 0x00e0) ||
+	    ((in_be16(&ccm->ccr) & CCM_CCR_360_FBCONFIG_MASK) == 0x0060)) {
 		pPllmult = &pllmult_pci[0];
 		fbpll_mask = 3;		/* 11b */
 		bPci = 1;
@@ -114,7 +116,7 @@ int get_clocks(void)
 	}
 
 #ifdef CONFIG_M54455EVB
-	bootmode = (*cpld & 0x03);
+	bootmode = (in_8(cpld) & 0x03);
 
 	if (bootmode != 3) {
 		/* Temporary read from CCR- fixed fb issue, must be the same clock
@@ -122,11 +124,11 @@ int get_clocks(void)
 		fbtemp = pPllmult[ccm->ccr & fbpll_mask];
 
 		/* Break down into small pieces, code still in flex bus */
-		pcrvalue = pll->pcr & 0xFFFFF0FF;
+		pcrvalue = in_be32(&pll->pcr) & 0xFFFFF0FF;
 		temp = fbtemp - 1;
 		pcrvalue |= PLL_PCR_OUTDIV3(temp);
 
-		pll->pcr = pcrvalue;
+		out_be32(&pll->pcr, pcrvalue);
 	}
 #endif
 #ifdef CONFIG_M54451EVB
@@ -137,9 +139,10 @@ int get_clocks(void)
 	bootmode = 2;
 
 	/* default value is 16 mul, set to 20 mul */
-	pcrvalue = (pll->pcr & 0x00FFFFFF) | 0x14000000;
-	pll->pcr = pcrvalue;
-	while ((pll->psr & PLL_PSR_LOCK) != PLL_PSR_LOCK);
+	pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF) | 0x14000000;
+	out_be32(&pll->pcr, pcrvalue);
+	while ((in_be32(&pll->psr) & PLL_PSR_LOCK) != PLL_PSR_LOCK)
+		;
 #endif
 #endif
 
@@ -149,10 +152,10 @@ int get_clocks(void)
 
 		if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) {
 			/* invaild range, re-set in PCR */
-			int temp = ((pll->pcr & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
+			int temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
 			int i, j, bus;
 
-			j = (pll->pcr & 0xFF000000) >> 24;
+			j = (in_be32(&pll->pcr) & 0xFF000000) >> 24;
 			for (i = j; i < 0xFF; i++) {
 				vco = i * CONFIG_SYS_INPUT_CLKSRC;
 				if (vco >= CLOCK_PLL_FVCO_MIN) {
@@ -163,47 +166,47 @@ int get_clocks(void)
 						break;
 				}
 			}
-			pcrvalue = pll->pcr & 0x00FF00FF;
+			pcrvalue = in_be32(&pll->pcr) & 0x00FF00FF;
 			fbtemp = ((i - 1) << 8) | ((i - 1) << 12);
 			pcrvalue |= ((i << 24) | fbtemp);
 
-			pll->pcr = pcrvalue;
+			out_be32(&pll->pcr, pcrvalue);
 		}
 		gd->vco_clk = vco;	/* Vco clock */
 	} else if (bootmode == 2) {
 		/* Normal mode */
-		vco =  ((pll->pcr & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
+		vco =  ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
 		if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) {
 			/* Default value */
-			pcrvalue = (pll->pcr & 0x00FFFFFF);
-			pcrvalue |= pPllmult[ccm->ccr & fbpll_mask] << 24;
-			pll->pcr = pcrvalue;
-			vco =  ((pll->pcr & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
+			pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF);
+			pcrvalue |= pPllmult[in_be16(&ccm->ccr) & fbpll_mask] << 24;
+			out_be32(&pll->pcr, pcrvalue);
+			vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
 		}
 		gd->vco_clk = vco;	/* Vco clock */
 	} else if (bootmode == 3) {
 		/* serial mode */
-		vco =  ((pll->pcr & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
+		vco =  ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
 		gd->vco_clk = vco;	/* Vco clock */
 	}
 
-	if ((ccm->ccr & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) {
+	if ((in_be16(&ccm->ccr) & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) {
 		/* Limp mode */
 	} else {
 		gd->inp_clk = CONFIG_SYS_INPUT_CLKSRC;	/* Input clock */
 
-		temp = (pll->pcr & PLL_PCR_OUTDIV1_MASK) + 1;
+		temp = (in_be32(&pll->pcr) & PLL_PCR_OUTDIV1_MASK) + 1;
 		gd->cpu_clk = vco / temp;	/* cpu clock */
 
-		temp = ((pll->pcr & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
+		temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
 		gd->bus_clk = vco / temp;	/* bus clock */
 
-		temp = ((pll->pcr & PLL_PCR_OUTDIV3_MASK) >> 8) + 1;
+		temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV3_MASK) >> 8) + 1;
 		gd->flb_clk = vco / temp;	/* FlexBus clock */
 
 #ifdef CONFIG_PCI
 		if (bPci) {
-			temp = ((pll->pcr & PLL_PCR_OUTDIV4_MASK) >> 12) + 1;
+			temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV4_MASK) >> 12) + 1;
 			gd->pci_clk = vco / temp;	/* PCI clock */
 		}
 #endif

arch/m68k/cpu/mcf547x_8x/cpu.c

@@ -3,7 +3,7 @@
  * (C) Copyright 2000-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -31,19 +31,20 @@
 #include <netdev.h>
 
 #include <asm/immap.h>
+#include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
-	volatile gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
+	gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
 
-	gptmr->pre = 10;
-	gptmr->cnt = 1;
+	out_be16(&gptmr->pre, 10);
+	out_be16(&gptmr->cnt, 1);
 
 	/* enable watchdog, set timeout to 0 and wait */
-	gptmr->mode = GPT_TMS_SGPIO;
-	gptmr->ctrl = GPT_CTRL_WDEN | GPT_CTRL_CE;
+	out_8(&gptmr->mode, GPT_TMS_SGPIO);
+	out_8(&gptmr->ctrl, GPT_CTRL_WDEN | GPT_CTRL_CE);
 
 	/* we don't return! */
 	return 1;
@@ -51,12 +52,12 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 int checkcpu(void)
 {
-	volatile siu_t *siu = (siu_t *) MMAP_SIU;
+	siu_t *siu = (siu_t *) MMAP_SIU;
 	u16 id = 0;
 
 	puts("CPU:   ");
 
-	switch ((siu->jtagid & 0x000FF000) >> 12) {
+	switch ((in_be32(&siu->jtagid) & 0x000FF000) >> 12) {
 	case 0x0C:
 		id = 5485;
 		break;
@@ -111,18 +112,18 @@ int checkcpu(void)
 /* Called by macro WATCHDOG_RESET */
 void hw_watchdog_reset(void)
 {
-	volatile gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
+	gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
 
-	gptmr->ocpw = 0xa5;
+	out_8(&gptmr->ocpw, 0xa5);
 }
 
 int watchdog_disable(void)
 {
-	volatile gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
+	gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
 
 	/* UserManual, once the wdog is disabled, wdog cannot be re-enabled */
-	gptmr->mode = 0;
-	gptmr->ctrl = 0;
+	out_8(&gptmr->mode, 0);
+	out_8(&gptmr->ctrl, 0);
 
 	puts("WATCHDOG:disabled\n");
 
@@ -131,14 +132,13 @@ int watchdog_disable(void)
 
 int watchdog_init(void)
 {
+	gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
 
-	volatile gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
+	out_be16(&gptmr->pre, CONFIG_WATCHDOG_TIMEOUT);
+	out_be16(&gptmr->cnt, CONFIG_SYS_TIMER_PRESCALER * 1000);
 
-	gptmr->pre = CONFIG_WATCHDOG_TIMEOUT;
-	gptmr->cnt = CONFIG_SYS_TIMER_PRESCALER * 1000;
-
-	gptmr->mode = GPT_TMS_SGPIO;
-	gptmr->ctrl = GPT_CTRL_CE | GPT_CTRL_WDEN;
+	out_8(&gptmr->mode, GPT_TMS_SGPIO);
+	out_8(&gptmr->ctrl, GPT_CTRL_CE | GPT_CTRL_WDEN);
 	puts("WATCHDOG:enabled\n");
 
 	return (0);

arch/m68k/cpu/mcf547x_8x/cpu_init.c

@@ -3,7 +3,7 @@
  * (C) Copyright 2000-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * (C) Copyright 2007 Freescale Semiconductor, Inc.
+ * (C) Copyright 2007, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -28,6 +28,7 @@
 #include <common.h>
 #include <MCD_dma.h>
 #include <asm/immap.h>
+#include <asm/io.h>
 
 #if defined(CONFIG_CMD_NET)
 #include <config.h>
@@ -44,58 +45,59 @@
  */
 void cpu_init_f(void)
 {
-	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-	volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
-	volatile xlbarb_t *xlbarb = (volatile xlbarb_t *) MMAP_XARB;
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
+	xlbarb_t *xlbarb = (xlbarb_t *) MMAP_XARB;
 
-	xlbarb->adrto = 0x2000;
-	xlbarb->datto = 0x2500;
-	xlbarb->busto = 0x3000;
+	out_be32(&xlbarb->adrto, 0x2000);
+	out_be32(&xlbarb->datto, 0x2500);
+	out_be32(&xlbarb->busto, 0x3000);
 
-	xlbarb->cfg = XARB_CFG_AT | XARB_CFG_DT;
+	out_be32(&xlbarb->cfg, XARB_CFG_AT | XARB_CFG_DT);
 
 	/* Master Priority Enable */
-	xlbarb->prien = 0xff;
-	xlbarb->pri = 0;
+	out_be32(&xlbarb->prien, 0xff);
+	out_be32(&xlbarb->pri, 0);
 
 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
-	fbcs->csar0 = CONFIG_SYS_CS0_BASE;
-	fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
-	fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
+	out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
+	out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
+	out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
-	fbcs->csar1 = CONFIG_SYS_CS1_BASE;
-	fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
-	fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
+	out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
+	out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
+	out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
-	fbcs->csar2 = CONFIG_SYS_CS2_BASE;
-	fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
-	fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
+	out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
+	out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
+	out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
-	fbcs->csar3 = CONFIG_SYS_CS3_BASE;
-	fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
-	fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
+	out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
+	out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
+	out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
-	fbcs->csar4 = CONFIG_SYS_CS4_BASE;
-	fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
-	fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
+	out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
+	out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
+	out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
-	fbcs->csar5 = CONFIG_SYS_CS5_BASE;
-	fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
-	fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
+	out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
+	out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
+	out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
 #endif
 
 #ifdef CONFIG_FSL_I2C
-	gpio->par_feci2cirq = GPIO_PAR_FECI2CIRQ_SCL | GPIO_PAR_FECI2CIRQ_SDA;
+	out_be16(&gpio->par_feci2cirq,
+		GPIO_PAR_FECI2CIRQ_SCL | GPIO_PAR_FECI2CIRQ_SDA);
 #endif
 
 	icache_enable();
@@ -115,44 +117,44 @@ int cpu_init_r(void)
 
 void uart_port_conf(int port)
 {
-	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-	volatile u8 *pscsicr = (u8 *) (CONFIG_SYS_UART_BASE + 0x40);
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	u8 *pscsicr = (u8 *) (CONFIG_SYS_UART_BASE + 0x40);
 
 	/* Setup Ports: */
 	switch (port) {
 	case 0:
-		gpio->par_psc0 = (GPIO_PAR_PSC0_TXD0 | GPIO_PAR_PSC0_RXD0);
+		out_8(&gpio->par_psc0, GPIO_PAR_PSC0_TXD0 | GPIO_PAR_PSC0_RXD0);
 		break;
 	case 1:
-		gpio->par_psc1 = (GPIO_PAR_PSC1_TXD1 | GPIO_PAR_PSC1_RXD1);
+		out_8(&gpio->par_psc1, GPIO_PAR_PSC1_TXD1 | GPIO_PAR_PSC1_RXD1);
 		break;
 	case 2:
-		gpio->par_psc2 = (GPIO_PAR_PSC2_TXD2 | GPIO_PAR_PSC2_RXD2);
+		out_8(&gpio->par_psc2, GPIO_PAR_PSC2_TXD2 | GPIO_PAR_PSC2_RXD2);
 		break;
 	case 3:
-		gpio->par_psc3 = (GPIO_PAR_PSC3_TXD3 | GPIO_PAR_PSC3_RXD3);
+		out_8(&gpio->par_psc3, GPIO_PAR_PSC3_TXD3 | GPIO_PAR_PSC3_RXD3);
 		break;
 	}
 
-	*pscsicr &= 0xF8;
+	clrbits_8(pscsicr, 0x07);
 }
 
 #if defined(CONFIG_CMD_NET)
 int fecpin_setclear(struct eth_device *dev, int setclear)
 {
-	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 	struct fec_info_dma *info = (struct fec_info_dma *)dev->priv;
 
 	if (setclear) {
 		if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
-			gpio->par_feci2cirq |= 0xF000;
+			setbits_be16(&gpio->par_feci2cirq, 0xf000);
 		else
-			gpio->par_feci2cirq |= 0x0FC0;
+			setbits_be16(&gpio->par_feci2cirq, 0x0fc0);
 	} else {
 		if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
-			gpio->par_feci2cirq &= 0x0FFF;
+			clrbits_be16(&gpio->par_feci2cirq, 0xf000);
 		else
-			gpio->par_feci2cirq &= 0xF03F;
+			clrbits_be16(&gpio->par_feci2cirq, 0x0fc0);
 	}
 	return 0;
 }

arch/m68k/cpu/mcf547x_8x/interrupts.c

@@ -1,6 +1,6 @@
 /*
  *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -25,14 +25,15 @@
 /* CPU specific interrupt routine */
 #include <common.h>
 #include <asm/immap.h>
+#include <asm/io.h>
 
 int interrupt_init(void)
 {
-	volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+	int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
 
 	/* Make sure all interrupts are disabled */
-	intp->imrh0 |= 0xFFFFFFFF;
-	intp->imrl0 |= 0xFFFFFFFF;
+	setbits_be32(&intp->imrh0, 0xffffffff);
+	setbits_be32(&intp->imrl0, 0xffffffff);
 
 	enable_interrupts();
 
@@ -42,9 +43,9 @@ int interrupt_init(void)
 #if defined(CONFIG_SLTTMR)
 void dtimer_intr_setup(void)
 {
-	volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+	int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
 
-	intp->icr0[CONFIG_SYS_TMRINTR_NO] = CONFIG_SYS_TMRINTR_PRI;
-	intp->imrh0 &= ~CONFIG_SYS_TMRINTR_MASK;
+	out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI);
+	clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK);
 }
 #endif

arch/m68k/cpu/mcf547x_8x/pci.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -88,53 +88,56 @@ int pci_read_cfg_dword(struct pci_controller *hose, pci_dev_t dev,
 
 void pci_mcf547x_8x_init(struct pci_controller *hose)
 {
-	volatile pci_t *pci = (volatile pci_t *) MMAP_PCI;
-	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	pci_t *pci = (pci_t *) MMAP_PCI;
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 
 	/* Port configuration */
-	gpio->par_pcibg =
-	    GPIO_PAR_PCIBG_PCIBG0(3) | GPIO_PAR_PCIBG_PCIBG1(3) |
-	    GPIO_PAR_PCIBG_PCIBG2(3) | GPIO_PAR_PCIBG_PCIBG3(3) |
-	    GPIO_PAR_PCIBG_PCIBG4(3);
-	gpio->par_pcibr =
-	    GPIO_PAR_PCIBR_PCIBR0(3) | GPIO_PAR_PCIBR_PCIBR1(3) |
-	    GPIO_PAR_PCIBR_PCIBR2(3) | GPIO_PAR_PCIBR_PCIBR3(3) |
-	    GPIO_PAR_PCIBR_PCIBR4(3);
+	out_be16(&gpio->par_pcibg,
+		GPIO_PAR_PCIBG_PCIBG0(3) | GPIO_PAR_PCIBG_PCIBG1(3) |
+		GPIO_PAR_PCIBG_PCIBG2(3) | GPIO_PAR_PCIBG_PCIBG3(3) |
+		GPIO_PAR_PCIBG_PCIBG4(3));
+	out_be16(&gpio->par_pcibr,
+		GPIO_PAR_PCIBR_PCIBR0(3) | GPIO_PAR_PCIBR_PCIBR1(3) |
+		GPIO_PAR_PCIBR_PCIBR2(3) | GPIO_PAR_PCIBR_PCIBR3(3) |
+		GPIO_PAR_PCIBR_PCIBR4(3));
 
 	/* Assert reset bit */
-	pci->gscr |= PCI_GSCR_PR;
+	setbits_be32(&pci->gscr, PCI_GSCR_PR);
 
-	pci->tcr1 = PCI_TCR1_P;
+	out_be32(&pci->tcr1, PCI_TCR1_P);
 
 	/* Initiator windows */
-	pci->iw0btar = CONFIG_SYS_PCI_MEM_PHYS | (CONFIG_SYS_PCI_MEM_PHYS >> 16);
-	pci->iw1btar = CONFIG_SYS_PCI_IO_PHYS | (CONFIG_SYS_PCI_IO_PHYS >> 16);
-	pci->iw2btar = CONFIG_SYS_PCI_CFG_PHYS | (CONFIG_SYS_PCI_CFG_PHYS >> 16);
+	out_be32(&pci->iw0btar,
+		CONFIG_SYS_PCI_MEM_PHYS | (CONFIG_SYS_PCI_MEM_PHYS >> 16));
+	out_be32(&pci->iw1btar,
+		CONFIG_SYS_PCI_IO_PHYS | (CONFIG_SYS_PCI_IO_PHYS >> 16));
+	out_be32(&pci->iw2btar,
+		CONFIG_SYS_PCI_CFG_PHYS | (CONFIG_SYS_PCI_CFG_PHYS >> 16));
 
-	pci->iwcr =
-	    PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO |
-	    PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO;
+	out_be32(&pci->iwcr,
+		PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO |
+		PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO);
 
-	pci->icr = 0;
+	out_be32(&pci->icr, 0);
 
 	/* Enable bus master and mem access */
-	pci->scr = PCI_SCR_B | PCI_SCR_M;
+	out_be32(&pci->scr, PCI_SCR_B | PCI_SCR_M);
 
 	/* Cache line size and master latency */
-	pci->cr1 = PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xF8);
-	pci->cr2 = 0;
+	out_be32(&pci->cr1, PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xf8));
+	out_be32(&pci->cr2, 0);
 
 #ifdef CONFIG_SYS_PCI_BAR0
-	pci->bar0 = PCI_BAR_BAR0(CONFIG_SYS_PCI_BAR0);
-	pci->tbatr0a = CONFIG_SYS_PCI_TBATR0 | PCI_TBATR_EN;
+	out_be32(&pci->bar0, PCI_BAR_BAR0(CONFIG_SYS_PCI_BAR0));
+	out_be32(&pci->tbatr0a, CONFIG_SYS_PCI_TBATR0 | PCI_TBATR_EN);
 #endif
 #ifdef CONFIG_SYS_PCI_BAR1
-	pci->bar1 = PCI_BAR_BAR1(CONFIG_SYS_PCI_BAR1);
-	pci->tbatr1a = CONFIG_SYS_PCI_TBATR1 | PCI_TBATR_EN;
+	out_be32(&pci->bar1, PCI_BAR_BAR1(CONFIG_SYS_PCI_BAR1));
+	out_be32(&pci->tbatr1a, CONFIG_SYS_PCI_TBATR1 | PCI_TBATR_EN);
 #endif
 
 	/* Deassert reset bit */
-	pci->gscr &= ~PCI_GSCR_PR;
+	clrbits_be32(&pci->gscr, PCI_GSCR_PR);
 	udelay(1000);
 
 	/* Enable PCI bus master support */

arch/m68k/cpu/mcf547x_8x/slicetimer.c

@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2007 Freescale Semiconductor, Inc.
+ * (C) Copyright 2007, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -25,6 +25,7 @@
 
 #include <asm/timer.h>
 #include <asm/immap.h>
+#include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -42,31 +43,32 @@ extern void dtimer_intr_setup(void);
 
 void __udelay(unsigned long usec)
 {
-	volatile slt_t *timerp = (slt_t *) (CONFIG_SYS_UDELAY_BASE);
+	slt_t *timerp = (slt_t *) (CONFIG_SYS_UDELAY_BASE);
 	u32 now, freq;
 
 	/* 1 us period */
 	freq = CONFIG_SYS_TIMER_PRESCALER;
 
-	timerp->cr = 0;		/* Disable */
-	timerp->tcnt = usec * freq;
-	timerp->cr = SLT_CR_TEN;
+	/* Disable */
+	out_be32(&timerp->cr, 0);
+	out_be32(&timerp->tcnt, usec * freq);
+	out_be32(&timerp->cr, SLT_CR_TEN);
 
-	now = timerp->cnt;
+	now = in_be32(&timerp->cnt);
 	while (now != 0)
-		now = timerp->cnt;
+		now = in_be32(&timerp->cnt);
 
-	timerp->sr |= SLT_SR_ST;
-	timerp->cr = 0;
+	setbits_be32(&timerp->sr, SLT_SR_ST);
+	out_be32(&timerp->cr, 0);
 }
 
 void dtimer_interrupt(void *not_used)
 {
-	volatile slt_t *timerp = (slt_t *) (CONFIG_SYS_TMR_BASE);
+	slt_t *timerp = (slt_t *) (CONFIG_SYS_TMR_BASE);
 
 	/* check for timer interrupt asserted */
 	if ((CONFIG_SYS_TMRPND_REG & CONFIG_SYS_TMRINTR_MASK) == CONFIG_SYS_TMRINTR_PEND) {
-		timerp->sr |= SLT_SR_ST;
+		setbits_be32(&timerp->sr, SLT_SR_ST);
 		timestamp++;
 		return;
 	}
@@ -74,25 +76,27 @@ void dtimer_interrupt(void *not_used)
 
 int timer_init(void)
 {
-	volatile slt_t *timerp = (slt_t *) (CONFIG_SYS_TMR_BASE);
+	slt_t *timerp = (slt_t *) (CONFIG_SYS_TMR_BASE);
 
 	timestamp = 0;
 
-	timerp->cr = 0;		/* disable timer */
-	timerp->tcnt = 0;
-	timerp->sr = SLT_SR_BE | SLT_SR_ST;	/* clear status */
+	/* disable timer */
+	out_be32(&timerp->cr, 0);
+	out_be32(&timerp->tcnt, 0);
+	/* clear status */
+	out_be32(&timerp->sr, SLT_SR_BE | SLT_SR_ST);
 
 	/* initialize and enable timer interrupt */
 	irq_install_handler(CONFIG_SYS_TMRINTR_NO, dtimer_interrupt, 0);
 
 	/* Interrupt every ms */
-	timerp->tcnt = 1000 * CONFIG_SYS_TIMER_PRESCALER;
+	out_be32(&timerp->tcnt, 1000 * CONFIG_SYS_TIMER_PRESCALER);
 
 	dtimer_intr_setup();
 
 	/* set a period of 1us, set timer mode to restart and
 	   enable timer and interrupt */
-	timerp->cr = SLT_CR_RUN | SLT_CR_IEN | SLT_CR_TEN;
+	out_be32(&timerp->cr, SLT_CR_RUN | SLT_CR_IEN | SLT_CR_TEN);
 	return 0;
 }
 

arch/m68k/include/asm/bitops.h

@@ -17,41 +17,36 @@ extern int test_and_change_bit(int nr, volatile void *addr);
 
 #ifdef __KERNEL__
 
-/*
- * ffs: find first bit set. This is defined the same way as
- * the libc and compiler builtin ffs routines, therefore
- * differs in spirit from the above ffz (man ffs).
- */
-extern __inline__ int ffs(int x)
+
+extern inline int test_bit(int nr, __const__ volatile void *addr)
 {
-	int r = 1;
-
-	if (!x)
-		return 0;
-	if (!(x & 0xffff)) {
-		x >>= 16;
-		r += 16;
-	}
-	if (!(x & 0xff)) {
-		x >>= 8;
-		r += 8;
-	}
-	if (!(x & 0xf)) {
-		x >>= 4;
-		r += 4;
-	}
-	if (!(x & 3)) {
-		x >>= 2;
-		r += 2;
-	}
-	if (!(x & 1)) {
-		x >>= 1;
-		r += 1;
-	}
-	return r;
+	__const__ unsigned int *p = (__const__ unsigned int *) addr;
+
+	return (p[nr >> 5] & (1UL << (nr & 31))) != 0;
 }
+
+extern inline int test_and_set_bit(int nr, volatile void *vaddr)
+{
+	char retval;
+
+	volatile char *p = &((volatile char *)vaddr)[(nr^31) >> 3];
+	__asm__ __volatile__ ("bset %2,(%4); sne %0"
+	     : "=d" (retval), "=m" (*p)
+	     : "di" (nr & 7), "m" (*p), "a" (p));
+
+	return retval;
+}
+
 #define __ffs(x) (ffs(x) - 1)
-#define PLATFORM_FFS
+
+/*
+ *  * hweightN: returns the hamming weight (i.e. the number
+ *   * of bits set) of a N-bit word
+ *    */
+
+#define hweight32(x) generic_hweight32(x)
+#define hweight16(x) generic_hweight16(x)
+#define hweight8(x) generic_hweight8(x)
 
 #endif /* __KERNEL__ */
 

arch/m68k/include/asm/coldfire/flexbus.h

@@ -29,7 +29,57 @@
 /*********************************************************************
 * FlexBus Chip Selects (FBCS)
 *********************************************************************/
+#ifdef CONFIG_M5235
+typedef struct fbcs {
+    u16 csar0;      /* Chip-select Address */
+    u16 res1;
+    u32 csmr0;      /* Chip-select Mask */
+    u16 res2;
+    u16 cscr0;      /* Chip-select Control */
+
+    u16 csar1;
+    u16 res3;
+    u32 csmr1;
+    u16 res4;
+    u16 cscr1;
+
+    u16 csar2;
+    u16 res5;
+    u32 csmr2;
+    u16 res6;
+    u16 cscr2;
+
+    u16 csar3;
+    u16 res7;
+    u32 csmr3;
+    u16 res8;
+    u16 cscr3;
+
+    u16 csar4;
+    u16 res9;
+    u32 csmr4;
+    u16 res10;
+    u16 cscr4;
+
+    u16 csar5;
+    u16 res11;
+    u32 csmr5;
+    u16 res12;
+    u16 cscr5;
 
+    u16 csar6;
+    u16 res13;
+    u32 csmr6;
+    u16 res14;
+    u16 cscr6;
+
+    u16 csar7;
+    u16 res15;
+    u32 csmr7;
+    u16 res16;
+    u16 cscr7;
+} fbcs_t;
+#else
 typedef struct fbcs {
 	u32 csar0;		/* Chip-select Address */
 	u32 csmr0;		/* Chip-select Mask */
@@ -56,6 +106,7 @@ typedef struct fbcs {
 	u32 csmr7;
 	u32 cscr7;
 } fbcs_t;
+#endif
 
 #define FBCS_CSAR_BA(x)			((x) & 0xFFFF0000)
 
@@ -94,6 +145,22 @@ typedef struct fbcs {
 #endif
 #define FBCS_CSMR_V			(0x00000001)	/* Valid bit */
 
+#ifdef CONFIG_M5235
+#define FBCS_CSCR_SRWS(x)       (((x) & 0x3) << 14)
+#define FBCS_CSCR_IWS(x)        (((x) & 0xF) << 10)
+#define FBCS_CSCR_AA_ON         (1 << 8)
+#define FBCS_CSCR_AA_OFF        (0 << 8)
+#define FBCS_CSCR_PS_32         (0 << 6)
+#define FBCS_CSCR_PS_16         (2 << 6)
+#define FBCS_CSCR_PS_8          (1 << 6)
+#define FBCS_CSCR_BEM_ON        (1 << 5)
+#define FBCS_CSCR_BEM_OFF       (0 << 5)
+#define FBCS_CSCR_BSTR_ON       (1 << 4)
+#define FBCS_CSCR_BSTR_OFF      (0 << 4)
+#define FBCS_CSCR_BSTW_ON       (1 << 3)
+#define FBCS_CSCR_BSTW_OFF      (0 << 3)
+#define FBCS_CSCR_SWWS(x)       (((x) & 0x7) << 0)
+#else
 #define FBCS_CSCR_SWS(x)		(((x) & 0x3F) << 26)
 #define FBCS_CSCR_SWS_MASK		(0x03FFFFFF)
 #define FBCS_CSCR_SWSEN			(0x00800000)
@@ -116,5 +183,6 @@ typedef struct fbcs {
 #define FBCS_CSCR_PS_16			(0x00000080)
 #define FBCS_CSCR_PS_8			(0x00000040)
 #define FBCS_CSCR_PS_32			(0x00000000)
+#endif
 
 #endif				/* __FLEXBUS_H */

arch/m68k/include/asm/coldfire/qspi.h

@@ -98,7 +98,7 @@ typedef struct qspi_ctrl {
 #define QSPI_QAR_RECV			(0x0010)
 #define QSPI_QAR_CMD			(0x0020)
 
-/* DR */
+/* DR with RAM command word definitions */
 #define QSPI_QDR_CONT			(0x8000)
 #define QSPI_QDR_BITSE			(0x4000)
 #define QSPI_QDR_DT			(0x2000)

arch/m68k/include/asm/io.h

@@ -1,7 +1,7 @@
 /*
  * IO header file
  *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -225,6 +225,42 @@ extern inline void out_be32(volatile unsigned *addr, int val)
 	*addr = val;
 }
 
+/* Clear and set bits in one shot. These macros can be used to clear and
+ * set multiple bits in a register using a single call. These macros can
+ * also be used to set a multiple-bit bit pattern using a mask, by
+ * specifying the mask in the 'clear' parameter and the new bit pattern
+ * in the 'set' parameter.
+ */
+
+#define clrbits(type, addr, clear) \
+	out_##type((addr), in_##type(addr) & ~(clear))
+
+#define setbits(type, addr, set) \
+	out_##type((addr), in_##type(addr) | (set))
+
+#define clrsetbits(type, addr, clear, set) \
+	out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
+
+#define clrbits_be32(addr, clear) clrbits(be32, addr, clear)
+#define setbits_be32(addr, set) setbits(be32, addr, set)
+#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
+
+#define clrbits_le32(addr, clear) clrbits(le32, addr, clear)
+#define setbits_le32(addr, set) setbits(le32, addr, set)
+#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
+
+#define clrbits_be16(addr, clear) clrbits(be16, addr, clear)
+#define setbits_be16(addr, set) setbits(be16, addr, set)
+#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
+
+#define clrbits_le16(addr, clear) clrbits(le16, addr, clear)
+#define setbits_le16(addr, set) setbits(le16, addr, set)
+#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
+
+#define clrbits_8(addr, clear) clrbits(8, addr, clear)
+#define setbits_8(addr, set) setbits(8, addr, set)
+#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
+
 static inline void sync(void)
 {
 	/* This sync function is for PowerPC or other architecture instruction

arch/m68k/include/asm/m5271.h

@@ -171,6 +171,32 @@
 #define MCF_GPIO_PAR_UART_U1RXD_UART1		0x0C00
 #define MCF_GPIO_PAR_UART_U1TXD_UART1		0x0300
 
+/* Bit definitions and macros for PAR_QSPI */
+#define MCF_GPIO_PAR_QSPI_PCS1_UNMASK		0x3F
+#define MCF_GPIO_PAR_QSPI_PCS1_PCS1		0xC0
+#define MCF_GPIO_PAR_QSPI_PCS1_SDRAM_SCKE	0x80
+#define MCF_GPIO_PAR_QSPI_PCS1_GPIO		0x00
+#define MCF_GPIO_PAR_QSPI_PCS0_UNMASK		0xDF
+#define MCF_GPIO_PAR_QSPI_PCS0_PCS0		0x20
+#define MCF_GPIO_PAR_QSPI_PCS0_GPIO		0x00
+#define MCF_GPIO_PAR_QSPI_SIN_UNMASK		0xE7
+#define MCF_GPIO_PAR_QSPI_SIN_SIN		0x18
+#define MCF_GPIO_PAR_QSPI_SIN_I2C_SDA		0x10
+#define MCF_GPIO_PAR_QSPI_SIN_GPIO		0x00
+#define MCF_GPIO_PAR_QSPI_SOUT_UNMASK		0xFB
+#define MCF_GPIO_PAR_QSPI_SOUT_SOUT		0x04
+#define MCF_GPIO_PAR_QSPI_SOUT_GPIO		0x00
+#define MCF_GPIO_PAR_QSPI_SCK_UNMASK		0xFC
+#define MCF_GPIO_PAR_QSPI_SCK_SCK		0x03
+#define MCF_GPIO_PAR_QSPI_SCK_I2C_SCL		0x02
+#define MCF_GPIO_PAR_QSPI_SCK_GPIO		0x00
+
+/* Bit definitions and macros for PAR_TIMER for QSPI */
+#define MCF_GPIO_PAR_TIMER_T3IN_UNMASK		0x3FFF
+#define MCF_GPIO_PAR_TIMER_T3IN_QSPI_PCS2	0x4000
+#define MCF_GPIO_PAR_TIMER_T3OUT_UNMASK		0xFF3F
+#define MCF_GPIO_PAR_TIMER_T3OUT_QSPI_PCS3	0x0040
+
 #define MCF_GPIO_PAR_SDRAM_PAR_CSSDCS(x)	(((x)&0x03)<<6)
 
 #define MCF_SDRAMC_DCR				0x000040

arch/m68k/lib/board.c

@@ -389,7 +389,6 @@ void board_init_r (gd_t *id, ulong dest_addr)
 {
 	char *s;
 	bd_t *bd;
-	extern void malloc_bin_reloc (void);
 
 #ifndef CONFIG_ENV_IS_NOWHERE
 	extern char * env_name_spec;

arch/microblaze/config.mk

@@ -31,3 +31,5 @@ CONFIG_STANDALONE_LOAD_ADDR ?= 0x80F00000
 PLATFORM_CPPFLAGS += -ffixed-r31 -D__microblaze__
 
 LDSCRIPT ?= $(SRCTREE)/$(CPUDIR)/u-boot.lds
+
+CONFIG_ARCH_DEVICE_TREE := microblaze

arch/microblaze/cpu/interrupts.c

@@ -32,15 +32,12 @@
 
 #undef DEBUG_INT
 
-extern void microblaze_disable_interrupts (void);
-extern void microblaze_enable_interrupts (void);
-
-void enable_interrupts (void)
+void enable_interrupts(void)
 {
 	MSRSET(0x2);
 }
 
-int disable_interrupts (void)
+int disable_interrupts(void)
 {
 	unsigned int msr;
 
@@ -58,20 +55,21 @@ microblaze_intc_t *intc;
 /* default handler */
 static void def_hdlr(void)
 {
-	puts ("def_hdlr\n");
+	puts("def_hdlr\n");
 }
 
 static void enable_one_interrupt(int irq)
 {
 	int mask;
 	int offset = 1;
+
 	offset <<= irq;
 	mask = intc->ier;
 	intc->ier = (mask | offset);
 #ifdef DEBUG_INT
-	printf ("Enable one interrupt irq %x - mask %x,ier %x\n", offset, mask,
+	printf("Enable one interrupt irq %x - mask %x,ier %x\n", offset, mask,
 		intc->ier);
-	printf ("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier,
+	printf("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier,
 		intc->iar, intc->mer);
 #endif
 }
@@ -80,25 +78,26 @@ static void disable_one_interrupt(int irq)
 {
 	int mask;
 	int offset = 1;
+
 	offset <<= irq;
 	mask = intc->ier;
 	intc->ier = (mask & ~offset);
 #ifdef DEBUG_INT
-	printf ("Disable one interrupt irq %x - mask %x,ier %x\n", irq, mask,
+	printf("Disable one interrupt irq %x - mask %x,ier %x\n", irq, mask,
 		intc->ier);
-	printf ("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier,
+	printf("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier,
 		intc->iar, intc->mer);
 #endif
 }
 
-/* adding new handler for interrupt */
-void install_interrupt_handler (int irq, interrupt_handler_t * hdlr, void *arg)
+int install_interrupt_handler(int irq, interrupt_handler_t *hdlr, void *arg)
 {
 	struct irq_action *act;
+
 	/* irq out of range */
 	if ((irq < 0) || (irq > irq_no)) {
-		puts ("IRQ out of range\n");
-		return;
+		puts("IRQ out of range\n");
+		return -1;
 	}
 	act = &vecs[irq];
 	if (hdlr) {		/* enable */
@@ -106,11 +105,14 @@ void install_interrupt_handler (int irq, interrupt_handler_t * hdlr, void *arg)
 		act->arg = arg;
 		act->count = 0;
 		enable_one_interrupt (irq);
-	} else {		/* disable */
-		act->handler = (interrupt_handler_t *) def_hdlr;
-		act->arg = (void *)irq;
-		disable_one_interrupt (irq);
+		return 0;
 	}
+
+	/* Disable */
+	act->handler = (interrupt_handler_t *) def_hdlr;
+	act->arg = (void *)irq;
+	disable_one_interrupt(irq);
+	return 1;
 }
 
 /* initialization interrupt controller - hardware */
@@ -122,7 +124,7 @@ static void intc_init(void)
 	/* XIntc_Start - hw_interrupt enable and all interrupt enable */
 	intc->mer = 0x3;
 #ifdef DEBUG_INT
-	printf ("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier,
+	printf("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier,
 		intc->iar, intc->mer);
 #endif
 }
@@ -157,7 +159,7 @@ int interrupts_init(void)
 	return 0;
 }
 
-void interrupt_handler (void)
+void interrupt_handler(void)
 {
 	int irqs = intc->ivr;	/* find active interrupt */
 	int mask = 1;

arch/microblaze/cpu/start.S

@@ -149,7 +149,7 @@ clear_bss:
 	cmp     r6, r5, r4 /* check if we have reach the end */
 	bnei    r6, 2b
 3:	/* jumping to board_init */
-	brai	board_init
+	brai	board_init_f
 1:	bri	1b
 
 /*

arch/microblaze/cpu/timer.c

@@ -27,42 +27,30 @@
 #include <asm/microblaze_intc.h>
 
 volatile int timestamp = 0;
+microblaze_timer_t *tmr;
 
-#ifdef CONFIG_SYS_TIMER_0
 ulong get_timer (ulong base)
 {
-	return (timestamp - base);
+	if (tmr)
+		return timestamp - base;
+	return timestamp++ - base;
 }
-#else
-ulong get_timer (ulong base)
-{
-	return (timestamp++ - base);
-}
-#endif
 
-#ifdef CONFIG_SYS_TIMER_0
 void __udelay(unsigned long usec)
 {
-	int i;
+	u32 i;
 
-	i = get_timer(0);
-	while ((get_timer(0) - i) < (usec / 1000))
-		;
+	if (tmr) {
+		i = get_timer(0);
+		while ((get_timer(0) - i) < (usec / 1000))
+			;
+	} else {
+		for (i = 0; i < (usec * XILINX_CLOCK_FREQ / 10000000); i++)
+			;
+	}
 }
-#else
-void __udelay(unsigned long usec)
-{
-	unsigned int i;
 
-	for (i = 0; i < (usec * CONFIG_XILINX_CLOCK_FREQ / 10000000); i++)
-		;
-}
-#endif
-
-#ifdef CONFIG_SYS_TIMER_0
-microblaze_timer_t *tmr = (microblaze_timer_t *) (CONFIG_SYS_TIMER_0_ADDR);
-
-void timer_isr (void *arg)
+static void timer_isr(void *arg)
 {
 	timestamp++;
 	tmr->control = tmr->control | TIMER_INTERRUPT;
@@ -70,15 +58,30 @@ void timer_isr (void *arg)
 
 int timer_init (void)
 {
-	tmr->loadreg = CONFIG_SYS_TIMER_0_PRELOAD;
-	tmr->control = TIMER_INTERRUPT | TIMER_RESET;
-	tmr->control =
-	    TIMER_ENABLE | TIMER_ENABLE_INTR | TIMER_RELOAD | TIMER_DOWN_COUNT;
-	timestamp = 0;
-	install_interrupt_handler (CONFIG_SYS_TIMER_0_IRQ, timer_isr, (void *)tmr);
+	int irq = -1;
+	u32 preload = 0;
+	u32 ret = 0;
+
+#if defined(CONFIG_SYS_TIMER_0_ADDR) && defined(CONFIG_SYS_INTC_0_NUM)
+	preload = XILINX_CLOCK_FREQ / CONFIG_SYS_HZ;
+	irq = CONFIG_SYS_TIMER_0_IRQ;
+	tmr = (microblaze_timer_t *) (CONFIG_SYS_TIMER_0_ADDR);
+#endif
+
+	if (tmr && preload && irq >= 0) {
+		tmr->loadreg = preload;
+		tmr->control = TIMER_INTERRUPT | TIMER_RESET;
+		tmr->control = TIMER_ENABLE | TIMER_ENABLE_INTR |\
+					TIMER_RELOAD | TIMER_DOWN_COUNT;
+		timestamp = 0;
+		ret = install_interrupt_handler (irq, timer_isr, (void *)tmr);
+		if (ret)
+			tmr = NULL;
+	}
+
+	/* No problem if timer is not found/initialized */
 	return 0;
 }
-#endif
 
 /*
  * This function is derived from PowerPC code (read timebase as long long).

arch/microblaze/cpu/u-boot.lds

@@ -45,6 +45,7 @@ SECTIONS
 	.data ALIGN(0x4):
 	{
 		__data_start = .;
+		dts/libdts.o (.data)
 		*(.data)
 		__data_end = .;
 	}

arch/microblaze/include/asm/global_data.h

@@ -41,6 +41,7 @@ typedef	struct	global_data {
 	unsigned long	precon_buf_idx;	/* Pre-Console buffer index */
 #endif
 	unsigned long	env_addr;	/* Address  of Environment struct */
+	const void	*fdt_blob;	/* Our device tree, NULL if none */
 	unsigned long	env_valid;	/* Checksum of Environment valid? */
 	unsigned long	fb_base;	/* base address of frame buffer */
 	void		**jt;		/* jump table */

arch/microblaze/include/asm/microblaze_intc.h

@@ -39,7 +39,16 @@ struct irq_action {
 	int count; /* number of interrupt */
 };
 
-void install_interrupt_handler (int irq, interrupt_handler_t * hdlr,
+/**
+ * Register and unregister interrupt handler rutines
+ *
+ * @param irq	IRQ number
+ * @param hdlr	Interrupt handler rutine
+ * @param arg	Pointer to argument which is passed to int. handler rutine
+ * @return	0 if registration pass, 1 if unregistration pass,
+ *		or an error code < 0 otherwise
+ */
+int install_interrupt_handler(int irq, interrupt_handler_t *hdlr,
 				       void *arg);
 
 int interrupts_init(void);

arch/microblaze/include/asm/microblaze_timer.h

@@ -39,3 +39,6 @@ typedef volatile struct microblaze_timer_t {
 	int loadreg; /* load register TLR */
 	int counter; /* timer/counter register */
 } microblaze_timer_t;
+
+int timer_init(void);
+

arch/microblaze/include/asm/processor.h

@@ -28,4 +28,7 @@
 extern char __end[];
 extern char __text_start[];
 
+/* Microblaze board initialization function */
+void board_init(void);
+
 #endif /* __ASM_MICROBLAZE_PROCESSOR_H */

arch/microblaze/lib/board.c

@@ -32,21 +32,13 @@
 #include <stdio_dev.h>
 #include <serial.h>
 #include <net.h>
+#include <linux/compiler.h>
 #include <asm/processor.h>
 #include <asm/microblaze_intc.h>
+#include <fdtdec.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#ifdef CONFIG_SYS_GPIO_0
-extern int gpio_init (void);
-#endif
-#ifdef CONFIG_SYS_TIMER_0
-extern int timer_init (void);
-#endif
-#ifdef CONFIG_SYS_FSL_2
-extern void fsl_init2 (void);
-#endif
-
 /*
  * All attempts to come up with a "common" initialization sequence
  * that works for all boards and architectures failed: some of the
@@ -63,31 +55,26 @@ typedef int (init_fnc_t) (void);
 
 init_fnc_t *init_sequence[] = {
 	env_init,
+#ifdef CONFIG_OF_CONTROL
+	fdtdec_check_fdt,
+#endif
 	serial_init,
 	console_init_f,
-#ifdef CONFIG_SYS_GPIO_0
-	gpio_init,
-#endif
 	interrupts_init,
-#ifdef CONFIG_SYS_TIMER_0
 	timer_init,
-#endif
-#ifdef CONFIG_SYS_FSL_2
-	fsl_init2,
-#endif
 	NULL,
 };
 
 unsigned long monitor_flash_len;
 
-void board_init (void)
+void board_init_f(ulong not_used)
 {
 	bd_t *bd;
 	init_fnc_t **init_fnc_ptr;
 	gd = (gd_t *) (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_GBL_DATA_OFFSET);
 	bd = (bd_t *) (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_GBL_DATA_OFFSET \
 						- GENERATED_BD_INFO_SIZE);
-	char *s;
+	__maybe_unused char *s;
 #if defined(CONFIG_CMD_FLASH)
 	ulong flash_size = 0;
 #endif
@@ -103,6 +90,17 @@ void board_init (void)
 
 	monitor_flash_len = __end - __text_start;
 
+#ifdef CONFIG_OF_EMBED
+	/* Get a pointer to the FDT */
+	gd->fdt_blob = _binary_dt_dtb_start;
+#elif defined CONFIG_OF_SEPARATE
+	/* FDT is at end of image */
+	gd->fdt_blob = (void *)__end;
+#endif
+	/* Allow the early environment to override the fdt address */
+	gd->fdt_blob = (void *)getenv_ulong("fdtcontroladdr", 16,
+						(uintptr_t)gd->fdt_blob);
+
 	/*
 	 * The Malloc area is immediately below the monitor copy in DRAM
 	 * aka CONFIG_SYS_MONITOR_BASE - Note there is no need for reloc_off
@@ -121,6 +119,15 @@ void board_init (void)
 		}
 	}
 
+#ifdef CONFIG_OF_CONTROL
+	/* For now, put this check after the console is ready */
+	if (fdtdec_prepare_fdt()) {
+		panic("** CONFIG_OF_CONTROL defined but no FDT - please see "
+			"doc/README.fdt-control");
+	} else
+		printf("DTB: 0x%x\n", (u32)gd->fdt_blob);
+#endif
+
 	puts ("SDRAM :\n");
 	printf ("\t\tIcache:%s\n", icache_status() ? "ON" : "OFF");
 	printf ("\t\tDcache:%s\n", dcache_status() ? "ON" : "OFF");
@@ -129,9 +136,8 @@ void board_init (void)
 #if defined(CONFIG_CMD_FLASH)
 	puts ("Flash: ");
 	bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
-	if (0 < (flash_size = flash_init ())) {
-		bd->bi_flashsize = flash_size;
-		bd->bi_flashoffset = CONFIG_SYS_FLASH_BASE + flash_size;
+	flash_size = flash_init();
+	if (bd->bi_flashstart && flash_size > 0) {
 # ifdef CONFIG_SYS_FLASH_CHECKSUM
 		print_size (flash_size, "");
 		/*
@@ -142,13 +148,16 @@ void board_init (void)
 		s = getenv ("flashchecksum");
 		if (s && (*s == 'y')) {
 			printf ("  CRC: %08X",
-				crc32 (0, (const unsigned char *) CONFIG_SYS_FLASH_BASE, flash_size)
+				crc32(0, (const u8 *)bd->bi_flashstart,
+							flash_size)
 			);
 		}
 		putc ('\n');
 # else	/* !CONFIG_SYS_FLASH_CHECKSUM */
 		print_size (flash_size, "\n");
 # endif /* CONFIG_SYS_FLASH_CHECKSUM */
+		bd->bi_flashsize = flash_size;
+		bd->bi_flashoffset = bd->bi_flashstart + flash_size;
 	} else {
 		puts ("Flash init FAILED");
 		bd->bi_flashstart = 0;
@@ -169,6 +178,8 @@ void board_init (void)
 	/* Initialize the console (after the relocation and devices init) */
 	console_init_r();
 
+	board_init();
+
 	/* Initialize from environment */
 	load_addr = getenv_ulong("loadaddr", 16, load_addr);
 

arch/mips/config.mk

@@ -23,7 +23,21 @@
 
 CROSS_COMPILE ?= mips_4KC-
 
-CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 -T mips.lds
+# Handle special prefix in ELDK 4.0 toolchain
+ifneq (,$(findstring 4KCle,$(CROSS_COMPILE)))
+ENDIANNESS := -EL
+endif
+
+ifdef CONFIG_SYS_LITTLE_ENDIAN
+ENDIANNESS := -EL
+endif
+
+ifdef CONFIG_SYS_BIG_ENDIAN
+ENDIANNESS := -EB
+endif
+
+# Default to EB if no endianess is configured
+ENDIANNESS ?= -EB
 
 PLATFORM_CPPFLAGS += -DCONFIG_MIPS -D__MIPS__
 
@@ -47,8 +61,8 @@ PLATFORM_CPPFLAGS += -DCONFIG_MIPS -D__MIPS__
 # On the other hand, we want PIC in the U-Boot code to relocate it from ROM
 # to RAM. $28 is always used as gp.
 #
-PLATFORM_CPPFLAGS		+= -G 0 -mabicalls -fpic
+PLATFORM_CPPFLAGS		+= -G 0 -mabicalls -fpic $(ENDIANNESS)
 PLATFORM_CPPFLAGS		+= -msoft-float
-PLATFORM_LDFLAGS		+= -G 0 -static -n -nostdlib
+PLATFORM_LDFLAGS		+= -G 0 -static -n -nostdlib $(ENDIANNESS)
 PLATFORM_RELFLAGS		+= -ffunction-sections -fdata-sections
 LDFLAGS_FINAL			+= --gc-sections

arch/mips/cpu/mips32/config.mk

@@ -29,21 +29,6 @@
 #
 MIPSFLAGS := -march=mips32r2
 
-# Handle special prefix in ELDK 4.0 toolchain
-ifneq (,$(findstring 4KCle,$(CROSS_COMPILE)))
-ENDIANNESS := -EL
-endif
+PLATFORM_CPPFLAGS += $(MIPSFLAGS)
 
-ifdef CONFIG_SYS_LITTLE_ENDIAN
-ENDIANNESS := -EL
-endif
-
-ifdef CONFIG_SYS_BIG_ENDIAN
-ENDIANNESS := -EB
-endif
-
-# Default to EB if no endianess is configured
-ENDIANNESS ?= -EB
-
-PLATFORM_CPPFLAGS += $(MIPSFLAGS) $(ENDIANNESS)
-PLATFORM_LDFLAGS += $(ENDIANNESS)
+CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 -T mips.lds

arch/mips/cpu/xburst/config.mk

@@ -20,5 +20,6 @@
 # MA 02111-1307 USA
 #
 
-PLATFORM_CPPFLAGS += -march=mips32 -EL
-PLATFORM_LDFLAGS += -EL
+PLATFORM_CPPFLAGS += -march=mips32
+
+CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 -T mips.lds

arch/mips/cpu/xburst/cpu.c

@@ -62,7 +62,7 @@ void __attribute__((weak)) _machine_restart(void)
 
 	writew(100, &wdt->tdr); /* wdt_set_data(100) */
 	writew(0, &wdt->tcnt); /* wdt_set_count(0); */
-	writew(TCU_TSSR_WDTSC, &tcu->tscr); /* tcu_start_wdt_clock */
+	writel(TCU_TSSR_WDTSC, &tcu->tscr); /* tcu_start_wdt_clock */
 	writeb(readb(&wdt->tcer) | WDT_TCER_TCEN, &wdt->tcer); /* wdt start */
 
 	while (1)

arch/mips/cpu/xburst/timer.c

@@ -34,13 +34,13 @@ static struct jz4740_tcu *tcu = (struct jz4740_tcu *)JZ4740_TCU_BASE;
 void reset_timer_masked(void)
 {
 	/* reset time */
-	gd->lastinc = readw(&tcu->tcnt0);
+	gd->lastinc = readl(&tcu->tcnt0);
 	gd->tbl = 0;
 }
 
 ulong get_timer_masked(void)
 {
-	ulong now = readw(&tcu->tcnt0);
+	ulong now = readl(&tcu->tcnt0);
 
 	if (gd->lastinc <= now)
 		gd->tbl += now - gd->lastinc; /* normal mode */
@@ -83,11 +83,11 @@ void udelay_masked(unsigned long usec)
 
 int timer_init(void)
 {
-	writew(TCU_TCSR_PRESCALE256 | TCU_TCSR_EXT_EN, &tcu->tcsr0);
+	writel(TCU_TCSR_PRESCALE256 | TCU_TCSR_EXT_EN, &tcu->tcsr0);
 
-	writew(0, &tcu->tcnt0);
-	writew(0, &tcu->tdhr0);
-	writew(TIMER_FDATA, &tcu->tdfr0);
+	writel(0, &tcu->tcnt0);
+	writel(0, &tcu->tdhr0);
+	writel(TIMER_FDATA, &tcu->tdfr0);
 
 	/* mask irqs */
 	writel((1 << TIMER_CHAN) | (1 << (TIMER_CHAN + 16)), &tcu->tmsr);

arch/mips/lib/Makefile

@@ -25,6 +25,13 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(ARCH).o
 
+## Build a couple of necessary functions into a private libgcc
+LIBGCC	= $(obj)libgcc.o
+GLSOBJS	+= ashldi3.o
+GLSOBJS	+= ashrdi3.o
+GLSOBJS	+= lshrdi3.o
+LGOBJS	:= $(addprefix $(obj),$(GLSOBJS))
+
 SOBJS-y	+=
 
 COBJS-y	+= board.o
@@ -37,9 +44,22 @@ endif
 SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
 
+# Always build libmips.o
+TARGETS	:= $(LIB)
+
+# Build private libgcc only when asked for
+ifdef USE_PRIVATE_LIBGCC
+TARGETS	+= $(LIBGCC)
+endif
+
+all:	$(TARGETS)
+
 $(LIB):	$(obj).depend $(OBJS)
 	$(call cmd_link_o_target, $(OBJS))
 
+$(LIBGCC): $(obj).depend $(LGOBJS)
+	$(call cmd_link_o_target, $(LGOBJS))
+
 #########################################################################
 
 # defines $(obj).depend target

arch/mips/lib/ashldi3.c

@@ -0,0 +1,25 @@
+#include "libgcc.h"
+
+long long __ashldi3(long long u, word_type b)
+{
+	DWunion uu, w;
+	word_type bm;
+
+	if (b == 0)
+		return u;
+
+	uu.ll = u;
+	bm = 32 - b;
+
+	if (bm <= 0) {
+		w.s.low = 0;
+		w.s.high = (unsigned int) uu.s.low << -bm;
+	} else {
+		const unsigned int carries = (unsigned int) uu.s.low >> bm;
+
+		w.s.low = (unsigned int) uu.s.low << b;
+		w.s.high = ((unsigned int) uu.s.high << b) | carries;
+	}
+
+	return w.ll;
+}

arch/mips/lib/ashrdi3.c

@@ -0,0 +1,27 @@
+#include "libgcc.h"
+
+long long __ashrdi3(long long u, word_type b)
+{
+	DWunion uu, w;
+	word_type bm;
+
+	if (b == 0)
+		return u;
+
+	uu.ll = u;
+	bm = 32 - b;
+
+	if (bm <= 0) {
+		/* w.s.high = 1..1 or 0..0 */
+		w.s.high =
+		    uu.s.high >> 31;
+		w.s.low = uu.s.high >> -bm;
+	} else {
+		const unsigned int carries = (unsigned int) uu.s.high << bm;
+
+		w.s.high = uu.s.high >> b;
+		w.s.low = ((unsigned int) uu.s.low >> b) | carries;
+	}
+
+	return w.ll;
+}

arch/mips/lib/board.c

@@ -248,7 +248,6 @@ void board_init_r(gd_t *id, ulong dest_addr)
 #ifndef CONFIG_SYS_NO_FLASH
 	ulong size;
 #endif
-	extern void malloc_bin_reloc(void);
 #ifndef CONFIG_ENV_IS_NOWHERE
 	extern char *env_name_spec;
 #endif

arch/mips/lib/libgcc.h

@@ -0,0 +1,25 @@
+#ifndef __ASM_LIBGCC_H
+#define __ASM_LIBGCC_H
+
+#include <asm/byteorder.h>
+
+typedef int word_type __attribute__ ((mode (__word__)));
+
+#ifdef __BIG_ENDIAN
+struct DWstruct {
+	int high, low;
+};
+#elif defined(__LITTLE_ENDIAN)
+struct DWstruct {
+	int low, high;
+};
+#else
+#error I feel sick.
+#endif
+
+typedef union {
+	struct DWstruct s;
+	long long ll;
+} DWunion;
+
+#endif /* __ASM_LIBGCC_H */

arch/mips/lib/lshrdi3.c

@@ -0,0 +1,25 @@
+#include "libgcc.h"
+
+long long __lshrdi3(long long u, word_type b)
+{
+	DWunion uu, w;
+	word_type bm;
+
+	if (b == 0)
+		return u;
+
+	uu.ll = u;
+	bm = 32 - b;
+
+	if (bm <= 0) {
+		w.s.high = 0;
+		w.s.low = (unsigned int) uu.s.high >> -bm;
+	} else {
+		const unsigned int carries = (unsigned int) uu.s.high << bm;
+
+		w.s.high = (unsigned int) uu.s.high >> b;
+		w.s.low = ((unsigned int) uu.s.low >> b) | carries;
+	}
+
+	return w.ll;
+}

arch/nds32/lib/board.c

@@ -306,8 +306,6 @@ void board_init_r(gd_t *id, ulong dest_addr)
 	bd_t *bd;
 	ulong malloc_start;
 
-	extern void malloc_bin_reloc(void);
-
 	gd = id;
 	bd = gd->bd;
 

arch/powerpc/cpu/mpc85xx/Makefile

@@ -55,8 +55,6 @@ COBJS-$(CONFIG_P1011)	+= ddr-gen3.o
 COBJS-$(CONFIG_P1012)	+= ddr-gen3.o
 COBJS-$(CONFIG_P1013)	+= ddr-gen3.o
 COBJS-$(CONFIG_P1014)	+= ddr-gen3.o
-COBJS-$(CONFIG_P1015)	+= ddr-gen3.o
-COBJS-$(CONFIG_P1016)	+= ddr-gen3.o
 COBJS-$(CONFIG_P1020)	+= ddr-gen3.o
 COBJS-$(CONFIG_P1021)	+= ddr-gen3.o
 COBJS-$(CONFIG_P1022)	+= ddr-gen3.o
@@ -64,10 +62,8 @@ COBJS-$(CONFIG_P1024)	+= ddr-gen3.o
 COBJS-$(CONFIG_P1025)	+= ddr-gen3.o
 COBJS-$(CONFIG_P2010)	+= ddr-gen3.o
 COBJS-$(CONFIG_P2020)	+= ddr-gen3.o
-COBJS-$(CONFIG_PPC_P2040)	+= ddr-gen3.o
 COBJS-$(CONFIG_PPC_P2041)	+= ddr-gen3.o
 COBJS-$(CONFIG_PPC_P3041)	+= ddr-gen3.o
-COBJS-$(CONFIG_PPC_P3060)	+= ddr-gen3.o
 COBJS-$(CONFIG_PPC_P4080)	+= ddr-gen3.o
 COBJS-$(CONFIG_PPC_P5020)	+= ddr-gen3.o
 COBJS-$(CONFIG_BSC9131)		+= ddr-gen3.o
@@ -80,10 +76,8 @@ COBJS-$(CONFIG_PCI)	+= pci.o
 COBJS-$(CONFIG_SYS_DPAA_QBMAN) += portals.o
 
 # various SoC specific assignments
-COBJS-$(CONFIG_PPC_P2040) += p2041_ids.o
 COBJS-$(CONFIG_PPC_P2041) += p2041_ids.o
 COBJS-$(CONFIG_PPC_P3041) += p3041_ids.o
-COBJS-$(CONFIG_PPC_P3060) += p3060_ids.o
 COBJS-$(CONFIG_PPC_P4080) += p4080_ids.o
 COBJS-$(CONFIG_PPC_P5020) += p5020_ids.o
 
@@ -103,8 +97,6 @@ COBJS-$(CONFIG_P1011)	+= p1021_serdes.o
 COBJS-$(CONFIG_P1012)	+= p1021_serdes.o
 COBJS-$(CONFIG_P1013)	+= p1022_serdes.o
 COBJS-$(CONFIG_P1014)	+= p1010_serdes.o
-COBJS-$(CONFIG_P1015)	+= p1021_serdes.o
-COBJS-$(CONFIG_P1016)	+= p1021_serdes.o
 COBJS-$(CONFIG_P1017)	+= p1023_serdes.o
 COBJS-$(CONFIG_P1020)	+= p1021_serdes.o
 COBJS-$(CONFIG_P1021)	+= p1021_serdes.o
@@ -114,10 +106,8 @@ COBJS-$(CONFIG_P1024)	+= p1021_serdes.o
 COBJS-$(CONFIG_P1025)	+= p1021_serdes.o
 COBJS-$(CONFIG_P2010)	+= p2020_serdes.o
 COBJS-$(CONFIG_P2020)	+= p2020_serdes.o
-COBJS-$(CONFIG_PPC_P2040) += p2041_serdes.o
 COBJS-$(CONFIG_PPC_P2041) += p2041_serdes.o
 COBJS-$(CONFIG_PPC_P3041) += p3041_serdes.o
-COBJS-$(CONFIG_PPC_P3060) += p3060_serdes.o
 COBJS-$(CONFIG_PPC_P4080) += p4080_serdes.o
 COBJS-$(CONFIG_PPC_P5020) += p5020_serdes.o
 

arch/powerpc/cpu/mpc85xx/cmd_errata.c

@@ -27,6 +27,9 @@
 
 static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
+#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
+	extern int enable_cpu_a011_workaround;
+#endif
 	__maybe_unused u32 svr = get_svr();
 
 #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001)
@@ -56,8 +59,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	/*
 	 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
 	 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1
+	 * The SVR has been checked by cpu_init_r().
 	 */
-	if (SVR_SOC_VER(svr) != SVR_P4080 || SVR_MAJ(svr) < 3)
+	if (enable_cpu_a011_workaround)
 		puts("Work-around for Erratum CPU-A011 enabled\n");
 #endif
 #if defined(CONFIG_SYS_FSL_ERRATUM_CPU_A003999)
@@ -119,6 +123,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
 	if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
 		puts("Work-around for Erratum NMG ETSEC129 enabled\n");
+#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A004510
+	puts("Work-around for Erratum A004510 enabled\n");
 #endif
 	return 0;
 }

arch/powerpc/cpu/mpc85xx/cpu.c

@@ -117,6 +117,9 @@ int checkcpu (void)
 	case PVR_VER_E5500:
 		puts("E5500");
 		break;
+	case PVR_VER_E6500:
+		puts("E6500");
+		break;
 	default:
 		puts("Unknown");
 		break;
@@ -427,10 +430,20 @@ static void dump_spd_ddr_reg(void)
 		case 0:
 			ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR;
 			break;
-#ifdef CONFIG_SYS_MPC85xx_DDR2_ADDR
+#if defined(CONFIG_SYS_MPC85xx_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
 		case 1:
 			ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR2_ADDR;
 			break;
+#endif
+#if defined(CONFIG_SYS_MPC85xx_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
+		case 2:
+			ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR3_ADDR;
+			break;
+#endif
+#if defined(CONFIG_SYS_MPC85xx_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
+		case 3:
+			ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR4_ADDR;
+			break;
 #endif
 		default:
 			printf("%s unexpected controller number = %u\n",

arch/powerpc/cpu/mpc85xx/cpu_init.c

@@ -38,6 +38,7 @@
 #include <asm/fsl_law.h>
 #include <asm/fsl_serdes.h>
 #include <asm/fsl_srio.h>
+#include <hwconfig.h>
 #include <linux/compiler.h>
 #include "mp.h"
 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
@@ -311,11 +312,41 @@ int cpu_init_r(void)
 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
 	defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
 	/*
+	 * CPU22 and NMG_CPU_A011 share the same workaround.
 	 * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
 	 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
-	 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1
+	 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both
+	 * fixed in 2.0. NMG_CPU_A011 is activated by default and can
+	 * be disabled by hwconfig with syntax:
+	 *
+	 * fsl_cpu_a011:disable
 	 */
-	if (SVR_SOC_VER(svr) != SVR_P4080 || SVR_MAJ(svr) < 3) {
+	extern int enable_cpu_a011_workaround;
+#ifdef CONFIG_SYS_P4080_ERRATUM_CPU22
+	enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3);
+#else
+	char buffer[HWCONFIG_BUFFER_SIZE];
+	char *buf = NULL;
+	int n, res;
+
+	n = getenv_f("hwconfig", buffer, sizeof(buffer));
+	if (n > 0)
+		buf = buffer;
+
+	res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf);
+	if (res > 0)
+		enable_cpu_a011_workaround = 0;
+	else {
+		if (n >= HWCONFIG_BUFFER_SIZE) {
+			printf("fsl_cpu_a011 was not found. hwconfig variable "
+				"may be too long\n");
+		}
+		enable_cpu_a011_workaround =
+			(SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) ||
+			(SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2);
+	}
+#endif
+	if (enable_cpu_a011_workaround) {
 		flush_dcache();
 		mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
 		sync();
@@ -447,11 +478,18 @@ skip_l2:
 
 #ifdef CONFIG_SYS_SRIO
 	srio_init();
-#ifdef CONFIG_SRIOBOOT_MASTER
-	srio_boot_master();
-#ifdef CONFIG_SRIOBOOT_SLAVE_HOLDOFF
-	srio_boot_master_release_slave();
-#endif
+#ifdef CONFIG_FSL_CORENET
+	char *s = getenv("bootmaster");
+	if (s) {
+		if (!strcmp(s, "SRIO1")) {
+			srio_boot_master(1);
+			srio_boot_master_release_slave(1);
+		}
+		if (!strcmp(s, "SRIO2")) {
+			srio_boot_master(2);
+			srio_boot_master_release_slave(2);
+		}
+	}
 #endif
 #endif
 

arch/powerpc/cpu/mpc85xx/ddr-gen3.c

@@ -1,5 +1,5 @@
 /*
- * Copyright 2008-2011 Freescale Semiconductor, Inc.
+ * Copyright 2008-2012 Freescale Semiconductor, Inc.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
@@ -32,9 +32,21 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 	case 0:
 		ddr = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR;
 		break;
+#if defined(CONFIG_SYS_MPC85xx_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
 	case 1:
 		ddr = (void *)CONFIG_SYS_MPC85xx_DDR2_ADDR;
 		break;
+#endif
+#if defined(CONFIG_SYS_MPC85xx_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
+	case 2:
+		ddr = (void *)CONFIG_SYS_MPC85xx_DDR3_ADDR;
+		break;
+#endif
+#if defined(CONFIG_SYS_MPC85xx_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
+	case 3:
+		ddr = (void *)CONFIG_SYS_MPC85xx_DDR4_ADDR;
+		break;
+#endif
 	default:
 		printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
 		return;
@@ -43,6 +55,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 	out_be32(&ddr->eor, regs->ddr_eor);
 
 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
+	debug("Workaround for ERRATUM_DDR111_DDR134\n");
 	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 		cs_sa = (regs->cs[i].bnds >> 16) & 0xfff;
 		cs_ea = regs->cs[i].bnds & 0xfff;
@@ -115,8 +128,12 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 	out_be32(&ddr->ddr_cdr2, regs->ddr_cdr2);
 	out_be32(&ddr->err_disable, regs->err_disable);
 	out_be32(&ddr->err_int_en, regs->err_int_en);
-	for (i = 0; i < 32; i++)
-		out_be32(&ddr->debug[i], regs->debug[i]);
+	for (i = 0; i < 32; i++) {
+		if (regs->debug[i]) {
+			debug("Write to debug_%d as %08x\n", i+1, regs->debug[i]);
+			out_be32(&ddr->debug[i], regs->debug[i]);
+		}
+	}
 
 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003474
 	out_be32(&ddr->debug[12], 0x00000015);
@@ -128,6 +145,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 	temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
 	out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003
+	debug("Workaround for ERRATUM_DDR_A003\n");
 	if (regs->ddr_sdram_rcw_2 & 0x00f00000) {
 		out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2 & 0xf07fffff);
 		out_be32(&ddr->debug[2], 0x00000400);
@@ -209,6 +227,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 	 * This erratum does not affect DDR3 mode, only for DDR2 mode.
 	 */
 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_115
+	debug("Workaround for ERRATUM_DDR_115\n");
 	if ((((in_be32(&ddr->sdram_cfg) >> 24) & 0x7) == SDRAM_TYPE_DDR2)
 	    && in_be32(&ddr->sdram_cfg) & 0x80000) {
 		/* set DEBUG_1[31] */
@@ -216,6 +235,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 	}
 #endif
 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
+	debug("Workaround for ERRATUM_DDR111_DDR134\n");
 	/*
 	 * This is the combined workaround for DDR111 and DDR134
 	 * following the published errata for MPC8572

arch/powerpc/cpu/mpc85xx/fdt.c

@@ -57,8 +57,9 @@ void ft_fixup_cpu(void *blob, u64 memory_limit)
 		u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
 
 		if (reg) {
-			u64 val = *reg * SIZE_BOOT_ENTRY + spin_tbl_addr;
-			val = cpu_to_fdt32(val);
+			u32 phys_cpu_id = thread_to_core(*reg);
+			u64 val = phys_cpu_id * SIZE_BOOT_ENTRY + spin_tbl_addr;
+			val = cpu_to_fdt64(val);
 			if (*reg == id) {
 				fdt_setprop_string(blob, off, "status",
 								"okay");
@@ -534,7 +535,7 @@ void fdt_fixup_fman_firmware(void *blob)
 #define fdt_fixup_fman_firmware(x)
 #endif
 
-#if defined(CONFIG_PPC_P4080) || defined(CONFIG_PPC_P3060)
+#if defined(CONFIG_PPC_P4080)
 static void fdt_fixup_usb(void *fdt)
 {
 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);