 Paul Walmsley
|
1c472d8e82
clk: tegra: T114: add DFLL DVCO reset control
|
12 years ago |
|
Paul Walmsley
|
25c9ded6ed
clk: tegra: T114: add FCPU clock shaper programming, needed by the DFLL
|
12 years ago |
 Peter De Schrijver
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7b781c72c9
clk: tegra: Add fields for override bits
|
12 years ago |
|
Peter De Schrijver
|
aa6fefde62
clk: tegra: allow PLL m,n,p init from SoC files
|
12 years ago |
 Prashant Gaikwad
|
061cec925f
clk: tegra: Use common of_clk_init function
|
12 years ago |
|
Peter De Schrijver
|
27aa99dc0e
clk: tegra: devicetree match for nvidia,tegra114-car
|
12 years ago |
|
Peter De Schrijver
|
fdcccbd804
clk: tegra: Workaround for Tegra114 MSENC problem
|
12 years ago |
|
Peter De Schrijver
|
a26a029893
clk: tegra: Add flags to tegra_clk_periph()
|
12 years ago |
|
Peter De Schrijver
|
c1d1939c51
clk: tegra: Add new fields and PLL types for Tegra114
|
12 years ago |
|
Peter De Schrijver
|
3e72771e21
clk: tegra: move from a lock bit idx to a lock mask
|
12 years ago |
|
Peter De Schrijver
|
0b6525acd1
clk: tegra: Add PLL post divider table
|
12 years ago |
|
Peter De Schrijver
|
7ba28813b4
clk: tegra: introduce TEGRA_PLL_HAS_LOCK_ENABLE
|
12 years ago |
|
Peter De Schrijver
|
dd93587be8
clk: tegra: Add TEGRA_PLL_BYPASS flag
|
12 years ago |
|
Peter De Schrijver
|
dba4072a4a
clk: tegra: Refactor PLL programming code
|
12 years ago |
 Stephen Warren
|
441f199a37
clk: tegra: defer application of init table
|
12 years ago |
|
Peter De Schrijver
|
ce4f3313b0
clk: add table lookup to mux
|
12 years ago |
|
Prashant Gaikwad
|
b08e8c0ecc
clk: tegra: add clock support for Tegra30
|
12 years ago |
|
Prashant Gaikwad
|
37c26a9065
clk: tegra: add clock support for Tegra20
|
12 years ago |
|
Prashant Gaikwad
|
8f8f484bf3
clk: tegra: add Tegra specific clocks
|
12 years ago |
