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@@ -116,8 +116,8 @@
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#define PLLDU_MISC_LOCK_ENABLE 22
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#define PLLE_MISC_LOCK_ENABLE 9
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-#define PLL_BASE_LOCK 27
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-#define PLLE_MISC_LOCK 11
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+#define PLL_BASE_LOCK BIT(27)
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+#define PLLE_MISC_LOCK BIT(11)
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#define PLLE_AUX 0x48c
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#define PLLC_OUT 0x84
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@@ -559,7 +559,7 @@ static struct tegra_clk_pll_params pll_c_params = {
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.vco_max = 1400000000,
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.base_reg = PLLC_BASE,
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.misc_reg = PLLC_MISC,
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- .lock_bit_idx = PLL_BASE_LOCK,
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+ .lock_mask = PLL_BASE_LOCK,
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.lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
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.lock_delay = 300,
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};
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@@ -573,7 +573,7 @@ static struct tegra_clk_pll_params pll_m_params = {
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.vco_max = 1200000000,
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.base_reg = PLLM_BASE,
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.misc_reg = PLLM_MISC,
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- .lock_bit_idx = PLL_BASE_LOCK,
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+ .lock_mask = PLL_BASE_LOCK,
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.lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
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.lock_delay = 300,
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};
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@@ -587,7 +587,7 @@ static struct tegra_clk_pll_params pll_p_params = {
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.vco_max = 1400000000,
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.base_reg = PLLP_BASE,
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.misc_reg = PLLP_MISC,
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- .lock_bit_idx = PLL_BASE_LOCK,
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+ .lock_mask = PLL_BASE_LOCK,
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.lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
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.lock_delay = 300,
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};
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@@ -601,7 +601,7 @@ static struct tegra_clk_pll_params pll_a_params = {
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.vco_max = 1400000000,
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.base_reg = PLLA_BASE,
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.misc_reg = PLLA_MISC,
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- .lock_bit_idx = PLL_BASE_LOCK,
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+ .lock_mask = PLL_BASE_LOCK,
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.lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
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.lock_delay = 300,
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};
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@@ -615,7 +615,7 @@ static struct tegra_clk_pll_params pll_d_params = {
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.vco_max = 1000000000,
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.base_reg = PLLD_BASE,
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.misc_reg = PLLD_MISC,
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- .lock_bit_idx = PLL_BASE_LOCK,
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+ .lock_mask = PLL_BASE_LOCK,
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.lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
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.lock_delay = 1000,
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};
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@@ -629,7 +629,7 @@ static struct tegra_clk_pll_params pll_d2_params = {
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.vco_max = 1000000000,
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.base_reg = PLLD2_BASE,
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.misc_reg = PLLD2_MISC,
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- .lock_bit_idx = PLL_BASE_LOCK,
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+ .lock_mask = PLL_BASE_LOCK,
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.lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
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.lock_delay = 1000,
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};
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@@ -643,7 +643,7 @@ static struct tegra_clk_pll_params pll_u_params = {
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.vco_max = 960000000,
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.base_reg = PLLU_BASE,
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.misc_reg = PLLU_MISC,
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- .lock_bit_idx = PLL_BASE_LOCK,
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+ .lock_mask = PLL_BASE_LOCK,
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.lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
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.lock_delay = 1000,
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.pdiv_tohw = pllu_p,
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@@ -658,7 +658,7 @@ static struct tegra_clk_pll_params pll_x_params = {
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.vco_max = 1700000000,
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.base_reg = PLLX_BASE,
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.misc_reg = PLLX_MISC,
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- .lock_bit_idx = PLL_BASE_LOCK,
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+ .lock_mask = PLL_BASE_LOCK,
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.lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
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.lock_delay = 300,
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};
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@@ -672,7 +672,7 @@ static struct tegra_clk_pll_params pll_e_params = {
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.vco_max = 2400000000U,
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.base_reg = PLLE_BASE,
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.misc_reg = PLLE_MISC,
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- .lock_bit_idx = PLLE_MISC_LOCK,
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+ .lock_mask = PLLE_MISC_LOCK,
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.lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
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.lock_delay = 300,
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};
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