 Jacob Shin
|
e259514eef
perf/x86/amd: Enable northbridge performance counters on AMD family 15h
|
12 years ago |
|
Jacob Shin
|
0fbdad078a
perf/x86: Allow for architecture specific RDPMC indexes
|
12 years ago |
|
Jacob Shin
|
4c1fd17a1c
perf/x86: Move MSR address offset calculation to architecture specific files
|
12 years ago |
|
Jacob Shin
|
9f19010af8
perf/x86/amd: Use proper naming scheme for AMD bit field definitions
|
12 years ago |
 Robert Richter
|
4dd4c2ae55
perf/x86/amd: Generalize northbridge constraints code for family 15h
|
12 years ago |
|
Robert Richter
|
2c53c3dd0b
perf/x86/amd: Rework northbridge event constraints handler
|
12 years ago |
 Jiri Olsa
|
0bf79d4413
perf/x86: Add hardware events translations for AMD cpus
|
12 years ago |
 Robert Richter
|
b1dc3c4820
perf/x86/amd: Unify AMD's generic and family 15h pmus
|
13 years ago |
 Linus Torvalds
|
56edab3159
Merge branches 'perf-urgent-for-linus' and 'perf-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
|
13 years ago |
|
Robert Richter
|
5bcdf5e4fe
perf/x86: Update event scheduling constraints for AMD family 15h models
|
13 years ago |
|
Robert Richter
|
450bbd493d
perf/x86-ibs: Precise event sampling with IBS for AMD CPUs
|
13 years ago |
|
Robert Richter
|
5f09fc6889
perf/x86: Fix cmpxchg() usage in amd_put_event_constraints()
|
13 years ago |
|
Jiri Olsa
|
641cc93881
perf: Adding sysfs group format attribute for pmu device
|
13 years ago |
 Stephane Eranian
|
2481c5fa6d
perf: Disable PERF_SAMPLE_BRANCH_* when not supported
|
13 years ago |
 Joerg Roedel
|
1018faa6cf
perf/x86/kvm: Fix Host-Only/Guest-Only counting with SVM disabled
|
13 years ago |
|
Robert Richter
|
bc1738f6ee
perf, x86: Fix event scheduler for constraints with overlapping counters
|
13 years ago |
|
Robert Richter
|
ee5789dbcc
perf, x86: Share IBS macros between perf and oprofile
|
13 years ago |
|
Joerg Roedel
|
011af85784
perf, amd: Use GO/HO bits in perf-ctr
|
13 years ago |
 Randy Dunlap
|
d6eed550a9
x86: Perf_event_amd.c needs <asm/apicdef.h>
|
13 years ago |
 Kevin Winchester
|
de0428a7ad
x86, perf: Clean up perf_event cpu code
|
14 years ago |
 Peter Zijlstra
|
7fdba1ca10
perf, x86: Avoid kfree() in CPU_STARTING
|
14 years ago |
 Peter Zijlstra
|
89d6c0b5bd
perf, arch: Add generic NODE cache events
|
14 years ago |
 Ingo Molnar
|
91fc4cc000
perf, x86: Add new stalled cycles events for Intel and AMD CPUs
|
14 years ago |
|
Robert Richter
|
855357a217
perf, x86: Fix AMD family 15h FPU event constraints
|
14 years ago |
 Andre Przywara
|
83112e688f
perf, x86: Fix pre-defined cache-misses event for AMD family 15h cpus
|
14 years ago |
|
Robert Richter
|
4979d2729a
perf, x86: Add support for AMD family 15h core counters
|
14 years ago |
|
Peter Zijlstra
|
c079c791c5
perf, amd: Remove the nb lock
|
14 years ago |
|
Peter Zijlstra
|
034c6efa46
perf, amd: Use kmalloc_node(,__GFP_ZERO) for northbridge structure allocation
|
14 years ago |
|
Stephane Eranian
|
ba0cef3d14
perf_events: Fix bogus AMD64 generic TLB events
|
14 years ago |
 Vince Weaver
|
f287d332ce
perf, x86: Fix incorrect branches event on AMD CPUs
|
15 years ago |
