|
@@ -226,6 +226,21 @@ static __initconst const u64 snb_hw_cache_event_ids
|
|
|
[ C(RESULT_MISS) ] = -1,
|
|
|
},
|
|
|
},
|
|
|
+ [ C(NODE) ] = {
|
|
|
+ [ C(OP_READ) ] = {
|
|
|
+ [ C(RESULT_ACCESS) ] = -1,
|
|
|
+ [ C(RESULT_MISS) ] = -1,
|
|
|
+ },
|
|
|
+ [ C(OP_WRITE) ] = {
|
|
|
+ [ C(RESULT_ACCESS) ] = -1,
|
|
|
+ [ C(RESULT_MISS) ] = -1,
|
|
|
+ },
|
|
|
+ [ C(OP_PREFETCH) ] = {
|
|
|
+ [ C(RESULT_ACCESS) ] = -1,
|
|
|
+ [ C(RESULT_MISS) ] = -1,
|
|
|
+ },
|
|
|
+ },
|
|
|
+
|
|
|
};
|
|
|
|
|
|
static __initconst const u64 westmere_hw_cache_event_ids
|
|
@@ -327,6 +342,20 @@ static __initconst const u64 westmere_hw_cache_event_ids
|
|
|
[ C(RESULT_MISS) ] = -1,
|
|
|
},
|
|
|
},
|
|
|
+ [ C(NODE) ] = {
|
|
|
+ [ C(OP_READ) ] = {
|
|
|
+ [ C(RESULT_ACCESS) ] = 0x01b7,
|
|
|
+ [ C(RESULT_MISS) ] = 0x01b7,
|
|
|
+ },
|
|
|
+ [ C(OP_WRITE) ] = {
|
|
|
+ [ C(RESULT_ACCESS) ] = 0x01b7,
|
|
|
+ [ C(RESULT_MISS) ] = 0x01b7,
|
|
|
+ },
|
|
|
+ [ C(OP_PREFETCH) ] = {
|
|
|
+ [ C(RESULT_ACCESS) ] = 0x01b7,
|
|
|
+ [ C(RESULT_MISS) ] = 0x01b7,
|
|
|
+ },
|
|
|
+ },
|
|
|
};
|
|
|
|
|
|
/*
|
|
@@ -379,7 +408,21 @@ static __initconst const u64 nehalem_hw_cache_extra_regs
|
|
|
[ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS,
|
|
|
[ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS,
|
|
|
},
|
|
|
- }
|
|
|
+ },
|
|
|
+ [ C(NODE) ] = {
|
|
|
+ [ C(OP_READ) ] = {
|
|
|
+ [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_ALL_DRAM,
|
|
|
+ [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE_DRAM,
|
|
|
+ },
|
|
|
+ [ C(OP_WRITE) ] = {
|
|
|
+ [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_ALL_DRAM,
|
|
|
+ [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE_DRAM,
|
|
|
+ },
|
|
|
+ [ C(OP_PREFETCH) ] = {
|
|
|
+ [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_ALL_DRAM,
|
|
|
+ [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE_DRAM,
|
|
|
+ },
|
|
|
+ },
|
|
|
};
|
|
|
|
|
|
static __initconst const u64 nehalem_hw_cache_event_ids
|
|
@@ -481,6 +524,20 @@ static __initconst const u64 nehalem_hw_cache_event_ids
|
|
|
[ C(RESULT_MISS) ] = -1,
|
|
|
},
|
|
|
},
|
|
|
+ [ C(NODE) ] = {
|
|
|
+ [ C(OP_READ) ] = {
|
|
|
+ [ C(RESULT_ACCESS) ] = 0x01b7,
|
|
|
+ [ C(RESULT_MISS) ] = 0x01b7,
|
|
|
+ },
|
|
|
+ [ C(OP_WRITE) ] = {
|
|
|
+ [ C(RESULT_ACCESS) ] = 0x01b7,
|
|
|
+ [ C(RESULT_MISS) ] = 0x01b7,
|
|
|
+ },
|
|
|
+ [ C(OP_PREFETCH) ] = {
|
|
|
+ [ C(RESULT_ACCESS) ] = 0x01b7,
|
|
|
+ [ C(RESULT_MISS) ] = 0x01b7,
|
|
|
+ },
|
|
|
+ },
|
|
|
};
|
|
|
|
|
|
static __initconst const u64 core2_hw_cache_event_ids
|