 Paul Walmsley
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657ebfadc1
OMAP3/4 clock: split into per-chip family files
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15 years ago |
 Mike Turquette
|
a7e069fc5a
OMAP3630: Clock: Workaround for DPLL HS divider limitation
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15 years ago |
 Ranjith Lohithakshan
|
3cc4a2fc2e
AM35xx: Add clock support for new modules on AM35xx
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15 years ago |
 Tony Lindgren
|
4751227df9
omap3/4: Fix compile for multi-omap for clkops_noncore_dpll_ops
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15 years ago |
|
Paul Walmsley
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e80a9729b1
OMAP2/3/4 clock: rename and clean the omap2_clk_init() functions
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15 years ago |
 Rajendra Nayak
|
a1391d2768
ARM: OMAP4: PM: Move DPLL control apis to dpll.c
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15 years ago |
|
Paul Walmsley
|
82e9bd5885
OMAP3 clock: convert clock34xx.h to clock34xx_data.c
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15 years ago |
|
Tony Lindgren
|
a76df42a67
Merge 7xx-iosplit-plat-merge with omap-fixes
|
15 years ago |
 Tero Kristo
|
72f962fc7b
omap3: clock: Fixed dpll3_m2x2 rate calculation
|
15 years ago |
|
Tony Lindgren
|
ce491cf854
omap: headers: Move remaining headers from include/mach to include/plat
|
15 years ago |
|
Paul Walmsley
|
08e3d5f28d
OMAP3 clock: remove superfluous calls to omap2_init_clk_clkdm
|
15 years ago |
|
Paul Walmsley
|
19f4d3a90b
OMAP clock: associate MPU clocks with the mpu_clkdm
|
15 years ago |
|
Paul Walmsley
|
3c82e229f0
OMAP3 clock: correct module IDLEST bits: SSI; DSS; USBHOST; HSOTGUSB
|
16 years ago |
 Kevin Hilman
|
8111b221a2
OMAP3: PM: Add D2D clocks and auto-idle setup to PRCM init
|
16 years ago |
|
Tony Lindgren
|
ef6685a6de
ARM: OMAP2/3: Remove OMAP_CM_REGADDR
|
16 years ago |
|
Paul Walmsley
|
6f733a349c
ARM: OMAP: GPIO de-bounce clocks don't affect module idle state
|
16 years ago |
|
Paul Walmsley
|
f248076c0d
OMAP2/3 GPTIMER: allow system tick GPTIMER to be changed in board-*.c files
|
16 years ago |
 Sergio Aguirre
|
9e53dd7180
OMAP3: clock: Camera module doesn't have IDLEST bit
|
16 years ago |
 Russell King
|
c0bf31320d
[ARM] omap: add support for bypassing DPLLs
|
16 years ago |
|
Russell King
|
8b9dbc16d4
[ARM] omap: arrange for clock recalc methods to return the rate
|
16 years ago |
|
Russell King
|
3f0a820c4c
[ARM] omap: create a proper tree of clocks
|
16 years ago |
|
Paul Walmsley
|
0eafd4725c
[ARM] OMAP3 clock: add omap3_core_dpll_m2_set_rate()
|
16 years ago |
|
Paul Walmsley
|
95f538ac37
[ARM] OMAP3 clock: avoid invalid FREQSEL values during DPLL rate rounding
|
16 years ago |
|
Paul Walmsley
|
c1bd7aaf67
[ARM] OMAP3 clock: convert dpll_data.idlest_bit to idlest_mask
|
16 years ago |
|
Paul Walmsley
|
b8168d1e39
[ARM] OMAP3 clock: DPLL{1,2}_FCLK clksel can divide by 4
|
16 years ago |
|
Paul Walmsley
|
46e0ccf8ae
[ARM] OMAP3 PRCM: add DPLL1-5 powerdomains, clockdomains; mark clocks
|
16 years ago |
|
Paul Walmsley
|
15b52bc4cb
[ARM] OMAP3 clock: move sys_clkout2 clk to core_clkdm
|
17 years ago |
|
Paul Walmsley
|
ae8578c019
[ARM] OMAP: Make dpll4_m4_ck programmable with clk_set_rate()
|
16 years ago |
|
Sergio Aguirre
|
6c8fe0b954
[ARM] OMAP: Add CSI2 clock struct for handling it with clock API
|
16 years ago |
 Daniel Stone
|
712d7c8602
[ARM] OMAP2: Fix definition of SGX clock register bits
|
16 years ago |
