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@@ -8,7 +8,8 @@
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* Jouni Högander
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*
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* Parts of this code are based on code written by
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- * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
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+ * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu,
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+ * Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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@@ -17,42 +18,16 @@
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#undef DEBUG
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#include <linux/kernel.h>
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-#include <linux/errno.h>
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-#include <linux/delay.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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-#include <linux/err.h>
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-#include <plat/cpu.h>
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#include <plat/clock.h>
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#include "clock.h"
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#include "clock34xx.h"
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-#include "prm.h"
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-#include "prm-regbits-34xx.h"
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#include "cm.h"
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#include "cm-regbits-34xx.h"
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-/*
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- * DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks
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- * that are sourced by DPLL5, and both of these require this clock
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- * to be at 120 MHz for proper operation.
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- */
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-#define DPLL5_FREQ_FOR_USBHOST 120000000
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-
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-/*
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- * In AM35xx IPSS, the {ICK,FCK} enable bits for modules are exported
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- * in the same register at a bit offset of 0x8. The EN_ACK for ICK is
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- * at an offset of 4 from ICK enable bit.
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- */
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-#define AM35XX_IPSS_ICK_MASK 0xF
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-#define AM35XX_IPSS_ICK_EN_ACK_OFFSET 0x4
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-#define AM35XX_IPSS_ICK_FCK_OFFSET 0x8
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-#define AM35XX_IPSS_CLK_IDLEST_VAL 0
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-
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-/* needed by omap3_core_dpll_m2_set_rate() */
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-struct clk *sdrc_ick_p, *arm_fck_p;
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-
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/**
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* omap3430es2_clk_ssi_find_idlest - return CM_IDLEST info for SSI
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* @clk: struct clk * being enabled
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@@ -149,234 +124,3 @@ const struct clkops clkops_omap3430es2_hsotgusb_wait = {
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.find_idlest = omap3430es2_clk_hsotgusb_find_idlest,
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.find_companion = omap2_clk_dflt_find_companion,
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};
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-
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-/**
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- * omap36xx_pwrdn_clk_enable_with_hsdiv_restore - enable clocks suffering
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- * from HSDivider PWRDN problem Implements Errata ID: i556.
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- * @clk: DPLL output struct clk
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- *
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- * 3630 only: dpll3_m3_ck, dpll4_m2_ck, dpll4_m3_ck, dpll4_m4_ck,
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- * dpll4_m5_ck & dpll4_m6_ck dividers gets loaded with reset
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- * valueafter their respective PWRDN bits are set. Any dummy write
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- * (Any other value different from the Read value) to the
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- * corresponding CM_CLKSEL register will refresh the dividers.
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- */
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-static int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk *clk)
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-{
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- u32 dummy_v, orig_v, clksel_shift;
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- int ret;
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-
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- /* Clear PWRDN bit of HSDIVIDER */
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- ret = omap2_dflt_clk_enable(clk);
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-
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- /* Restore the dividers */
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- if (!ret) {
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- clksel_shift = __ffs(clk->parent->clksel_mask);
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- orig_v = __raw_readl(clk->parent->clksel_reg);
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- dummy_v = orig_v;
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-
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- /* Write any other value different from the Read value */
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- dummy_v ^= (1 << clksel_shift);
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- __raw_writel(dummy_v, clk->parent->clksel_reg);
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-
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- /* Write the original divider */
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- __raw_writel(orig_v, clk->parent->clksel_reg);
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- }
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-
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- return ret;
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-}
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-
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-const struct clkops clkops_omap36xx_pwrdn_with_hsdiv_wait_restore = {
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- .enable = omap36xx_pwrdn_clk_enable_with_hsdiv_restore,
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- .disable = omap2_dflt_clk_disable,
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- .find_companion = omap2_clk_dflt_find_companion,
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- .find_idlest = omap2_clk_dflt_find_idlest,
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-};
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-
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-const struct clkops omap3_clkops_noncore_dpll_ops = {
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- .enable = omap3_noncore_dpll_enable,
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- .disable = omap3_noncore_dpll_disable,
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-};
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-
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-/**
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- * am35xx_clk_find_idlest - return clock ACK info for AM35XX IPSS
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- * @clk: struct clk * being enabled
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- * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
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- * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
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- * @idlest_val: pointer to a u8 to store the CM_IDLEST indicator
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- *
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- * The interface clocks on AM35xx IPSS reflects the clock idle status
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- * in the enable register itsel at a bit offset of 4 from the enable
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- * bit. A value of 1 indicates that clock is enabled.
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- */
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-static void am35xx_clk_find_idlest(struct clk *clk,
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- void __iomem **idlest_reg,
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- u8 *idlest_bit,
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- u8 *idlest_val)
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-{
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- *idlest_reg = (__force void __iomem *)(clk->enable_reg);
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- *idlest_bit = clk->enable_bit + AM35XX_IPSS_ICK_EN_ACK_OFFSET;
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- *idlest_val = AM35XX_IPSS_CLK_IDLEST_VAL;
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-}
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-
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-/**
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- * am35xx_clk_find_companion - find companion clock to @clk
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- * @clk: struct clk * to find the companion clock of
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- * @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in
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- * @other_bit: u8 ** to return the companion clock bit shift in
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- *
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- * Some clocks don't have companion clocks. For example, modules with
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- * only an interface clock (such as HECC) don't have a companion
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- * clock. Right now, this code relies on the hardware exporting a bit
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- * in the correct companion register that indicates that the
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- * nonexistent 'companion clock' is active. Future patches will
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- * associate this type of code with per-module data structures to
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- * avoid this issue, and remove the casts. No return value.
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- */
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-static void am35xx_clk_find_companion(struct clk *clk, void __iomem **other_reg,
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- u8 *other_bit)
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-{
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- *other_reg = (__force void __iomem *)(clk->enable_reg);
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- if (clk->enable_bit & AM35XX_IPSS_ICK_MASK)
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- *other_bit = clk->enable_bit + AM35XX_IPSS_ICK_FCK_OFFSET;
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- else
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- *other_bit = clk->enable_bit - AM35XX_IPSS_ICK_FCK_OFFSET;
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-}
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-
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-const struct clkops clkops_am35xx_ipss_module_wait = {
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- .enable = omap2_dflt_clk_enable,
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- .disable = omap2_dflt_clk_disable,
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- .find_idlest = am35xx_clk_find_idlest,
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- .find_companion = am35xx_clk_find_companion,
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-};
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-
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-/**
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- * am35xx_clk_ipss_find_idlest - return CM_IDLEST info for IPSS
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- * @clk: struct clk * being enabled
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- * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
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- * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
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- * @idlest_val: pointer to a u8 to store the CM_IDLEST indicator
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- *
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- * The IPSS target CM_IDLEST bit is at a different shift from the
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- * CM_{I,F}CLKEN bit. Pass back the correct info via @idlest_reg
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- * and @idlest_bit. No return value.
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- */
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-static void am35xx_clk_ipss_find_idlest(struct clk *clk,
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- void __iomem **idlest_reg,
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- u8 *idlest_bit,
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- u8 *idlest_val)
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-{
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- u32 r;
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-
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- r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
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- *idlest_reg = (__force void __iomem *)r;
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- *idlest_bit = AM35XX_ST_IPSS_SHIFT;
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- *idlest_val = OMAP34XX_CM_IDLEST_VAL;
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-}
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-
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-const struct clkops clkops_am35xx_ipss_wait = {
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- .enable = omap2_dflt_clk_enable,
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- .disable = omap2_dflt_clk_disable,
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- .find_idlest = am35xx_clk_ipss_find_idlest,
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- .find_companion = omap2_clk_dflt_find_companion,
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-};
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-
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-int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate)
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-{
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- /*
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- * According to the 12-5 CDP code from TI, "Limitation 2.5"
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- * on 3430ES1 prevents us from changing DPLL multipliers or dividers
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- * on DPLL4.
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- */
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- if (omap_rev() == OMAP3430_REV_ES1_0) {
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- printk(KERN_ERR "clock: DPLL4 cannot change rate due to "
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- "silicon 'Limitation 2.5' on 3430ES1.\n");
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- return -EINVAL;
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- }
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- return omap3_noncore_dpll_set_rate(clk, rate);
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-}
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-
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-void __init omap3_clk_lock_dpll5(void)
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-{
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- struct clk *dpll5_clk;
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- struct clk *dpll5_m2_clk;
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-
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- dpll5_clk = clk_get(NULL, "dpll5_ck");
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- clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST);
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- clk_enable(dpll5_clk);
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-
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- /* Enable autoidle to allow it to enter low power bypass */
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- omap3_dpll_allow_idle(dpll5_clk);
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-
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- /* Program dpll5_m2_clk divider for no division */
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- dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck");
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- clk_enable(dpll5_m2_clk);
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- clk_set_rate(dpll5_m2_clk, DPLL5_FREQ_FOR_USBHOST);
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-
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- clk_disable(dpll5_m2_clk);
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- clk_disable(dpll5_clk);
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- return;
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-}
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-
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-/* Common clock code */
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-
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-/* REVISIT: Move this init stuff out into clock.c */
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-
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-/*
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- * Switch the MPU rate if specified on cmdline.
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- * We cannot do this early until cmdline is parsed.
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- */
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-static int __init omap3xxx_clk_arch_init(void)
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-{
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- struct clk *osc_sys_ck, *dpll1_ck, *arm_fck, *core_ck;
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- unsigned long osc_sys_rate;
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- bool err = 0;
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-
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- if (!cpu_is_omap34xx())
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- return 0;
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-
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- if (!mpurate)
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- return -EINVAL;
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-
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- /* XXX test these for success */
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- dpll1_ck = clk_get(NULL, "dpll1_ck");
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- if (WARN(IS_ERR(dpll1_ck), "Failed to get dpll1_ck.\n"))
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- err = 1;
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-
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- arm_fck = clk_get(NULL, "arm_fck");
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- if (WARN(IS_ERR(arm_fck), "Failed to get arm_fck.\n"))
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- err = 1;
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-
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- core_ck = clk_get(NULL, "core_ck");
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- if (WARN(IS_ERR(core_ck), "Failed to get core_ck.\n"))
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- err = 1;
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-
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- osc_sys_ck = clk_get(NULL, "osc_sys_ck");
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- if (WARN(IS_ERR(osc_sys_ck), "Failed to get osc_sys_ck.\n"))
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- err = 1;
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-
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- if (err)
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- return -ENOENT;
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-
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- /* REVISIT: not yet ready for 343x */
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- if (clk_set_rate(dpll1_ck, mpurate))
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- printk(KERN_ERR "*** Unable to set MPU rate\n");
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-
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- recalculate_root_clocks();
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-
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- osc_sys_rate = clk_get_rate(osc_sys_ck);
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-
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- pr_info("Switched to new clocking rate (Crystal/Core/MPU): "
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- "%ld.%01ld/%ld/%ld MHz\n",
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- (osc_sys_rate / 1000000),
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- ((osc_sys_rate / 100000) % 10),
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- (clk_get_rate(core_ck) / 1000000),
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- (clk_get_rate(arm_fck) / 1000000));
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-
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- calibrate_delay();
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-
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- return 0;
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-}
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-arch_initcall(omap3xxx_clk_arch_init);
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-
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-
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Paul Walmsley