 Will Deacon
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38a8914f9a
ARM: 6987/1: l2x0: fix disabling function to avoid deadlock
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14 years ago |
 Russell King
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1f0090a1ea
Merge branch 'misc' into devel
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14 years ago |
 Santosh Shilimkar
|
2839e06c95
ARM: 6795/1: l2x0: Errata fix for flush by Way operation can cause data corrupti
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14 years ago |
 Srinidhi Kasagar
|
885028e4ba
ARM: 6741/1: errata: pl310 cache sync operation may be faulty
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14 years ago |
|
Santosh Shilimkar
|
444457c1f5
ARM: l2x0: Optimise the range based operations
|
15 years ago |
|
Santosh Shilimkar
|
5ba7037228
ARM: l2x0: Determine the cache size
|
15 years ago |
 Thomas Gleixner
|
2fd8658931
arm: Implement l2x0 cache disable functions
|
15 years ago |
 Catalin Marinas
|
9a6655e49f
ARM: Improve the L2 cache performance when PL310 is used
|
14 years ago |
|
Catalin Marinas
|
6775a558fe
ARM: 6272/1: Convert L2x0 to use the IO relaxed operations
|
15 years ago |
 Sascha Hauer
|
4082cfa776
ARM: 6210/1: Do not rely on reset defaults of L2X0_AUX_CTRL
|
15 years ago |
|
Russell King
|
ac1d426e82
Merge branch 'devel-stable' into devel
|
15 years ago |
 Jason McMullan
|
64039be822
ARM: 6094/1: Extend cache-l2x0 to support the 16-way PL310
|
15 years ago |
|
Catalin Marinas
|
23107c5420
ARM: 5995/1: ARM: Add L2x0 outer_sync() support (3/4)
|
15 years ago |
|
Santosh Shilimkar
|
9e65582a8e
ARM: 5919/1: ARM: L2 : Errata 588369: Clean & Invalidate do not invalidate clean lines
|
15 years ago |
|
Santosh Shilimkar
|
424d6b145f
ARM: 5916/1: ARM: L2 : Add maintainace by line helper functions
|
15 years ago |
|
Russell King
|
bf32eb8549
Merge branch 'pending-l2x0' into cache
|
15 years ago |
|
Russell King
|
3d1074349b
ARM: cache-l2x0: make better use of background cache handling
|
15 years ago |
|
Russell King
|
0eb948dd7f
ARM: cache-l2x0: avoid taking spinlock for every iteration
|
15 years ago |
|
Srinidhi Kasagar
|
48371cd3f4
ARM: 5845/1: l2x0: check whether l2x0 already enabled
|
15 years ago |
 Russell King
|
fced80c735
[ARM] Convert asm/io.h to linux/io.h
|
16 years ago |
 Rui Sousa
|
4f6627ac3b
[ARM] 4568/1: fix l2x0 cache invalidate handling of unaligned addresses
|
17 years ago |
|
Catalin Marinas
|
0762097625
[ARM] 4500/1: Add locking around the background L2x0 cache operations
|
18 years ago |
|
Catalin Marinas
|
382266ad5a
[ARM] 4135/1: Add support for the L210/L220 cache controllers
|
18 years ago |
