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@@ -112,12 +112,26 @@ static void l2x0_cache_sync(void)
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spin_unlock_irqrestore(&l2x0_lock, flags);
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}
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-static inline void l2x0_inv_all(void)
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+static void l2x0_flush_all(void)
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+{
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+ unsigned long flags;
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+
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+ /* clean all ways */
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+ spin_lock_irqsave(&l2x0_lock, flags);
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+ writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_INV_WAY);
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+ cache_wait_way(l2x0_base + L2X0_CLEAN_INV_WAY, l2x0_way_mask);
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+ cache_sync();
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+ spin_unlock_irqrestore(&l2x0_lock, flags);
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+}
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+
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+static void l2x0_inv_all(void)
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{
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unsigned long flags;
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/* invalidate all ways */
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spin_lock_irqsave(&l2x0_lock, flags);
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+ /* Invalidating when L2 is enabled is a nono */
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+ BUG_ON(readl(l2x0_base + L2X0_CTRL) & 1);
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writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_INV_WAY);
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cache_wait_way(l2x0_base + L2X0_INV_WAY, l2x0_way_mask);
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cache_sync();
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@@ -215,6 +229,15 @@ static void l2x0_flush_range(unsigned long start, unsigned long end)
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spin_unlock_irqrestore(&l2x0_lock, flags);
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}
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+static void l2x0_disable(void)
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+{
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+ unsigned long flags;
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+
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+ spin_lock_irqsave(&l2x0_lock, flags);
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+ writel(0, l2x0_base + L2X0_CTRL);
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+ spin_unlock_irqrestore(&l2x0_lock, flags);
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+}
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+
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void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
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{
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__u32 aux;
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@@ -272,6 +295,9 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
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outer_cache.clean_range = l2x0_clean_range;
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outer_cache.flush_range = l2x0_flush_range;
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outer_cache.sync = l2x0_cache_sync;
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+ outer_cache.flush_all = l2x0_flush_all;
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+ outer_cache.inv_all = l2x0_inv_all;
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+ outer_cache.disable = l2x0_disable;
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printk(KERN_INFO "%s cache controller enabled\n", type);
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printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x\n",
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