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@@ -84,6 +84,9 @@ module_param(vmm_exclusive, bool, S_IRUGO);
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static bool __read_mostly fasteoi = 1;
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module_param(fasteoi, bool, S_IRUGO);
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+static bool __read_mostly enable_apicv_reg_vid = 1;
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+module_param(enable_apicv_reg_vid, bool, S_IRUGO);
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+
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/*
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* If nested=1, nested virtualization is supported, i.e., guests may use
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* VMX and be a hypervisor for its own guests. If nested=0, guests may not
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@@ -640,6 +643,8 @@ static unsigned long *vmx_io_bitmap_a;
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static unsigned long *vmx_io_bitmap_b;
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static unsigned long *vmx_msr_bitmap_legacy;
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static unsigned long *vmx_msr_bitmap_longmode;
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+static unsigned long *vmx_msr_bitmap_legacy_x2apic;
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+static unsigned long *vmx_msr_bitmap_longmode_x2apic;
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static bool cpu_has_load_ia32_efer;
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static bool cpu_has_load_perf_global_ctrl;
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@@ -764,6 +769,24 @@ static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
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SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
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}
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+static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
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+{
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+ return vmcs_config.cpu_based_2nd_exec_ctrl &
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+ SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
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+}
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+
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+static inline bool cpu_has_vmx_apic_register_virt(void)
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+{
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+ return vmcs_config.cpu_based_2nd_exec_ctrl &
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+ SECONDARY_EXEC_APIC_REGISTER_VIRT;
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+}
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+
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+static inline bool cpu_has_vmx_virtual_intr_delivery(void)
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+{
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+ return vmcs_config.cpu_based_2nd_exec_ctrl &
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+ SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
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+}
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+
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static inline bool cpu_has_vmx_flexpriority(void)
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{
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return cpu_has_vmx_tpr_shadow() &&
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@@ -1821,6 +1844,25 @@ static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
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vmx->guest_msrs[from] = tmp;
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}
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+static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
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+{
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+ unsigned long *msr_bitmap;
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+
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+ if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
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+ if (is_long_mode(vcpu))
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+ msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
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+ else
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+ msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
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+ } else {
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+ if (is_long_mode(vcpu))
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+ msr_bitmap = vmx_msr_bitmap_longmode;
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+ else
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+ msr_bitmap = vmx_msr_bitmap_legacy;
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+ }
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+
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+ vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
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+}
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+
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/*
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* Set up the vmcs to automatically save and restore system
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* msrs. Don't touch the 64-bit msrs if the guest is in legacy
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@@ -1829,7 +1871,6 @@ static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
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static void setup_msrs(struct vcpu_vmx *vmx)
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{
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int save_nmsrs, index;
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- unsigned long *msr_bitmap;
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save_nmsrs = 0;
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#ifdef CONFIG_X86_64
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@@ -1861,14 +1902,8 @@ static void setup_msrs(struct vcpu_vmx *vmx)
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vmx->save_nmsrs = save_nmsrs;
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- if (cpu_has_vmx_msr_bitmap()) {
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- if (is_long_mode(&vmx->vcpu))
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- msr_bitmap = vmx_msr_bitmap_longmode;
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- else
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- msr_bitmap = vmx_msr_bitmap_legacy;
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-
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- vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
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- }
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+ if (cpu_has_vmx_msr_bitmap())
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+ vmx_set_msr_bitmap(&vmx->vcpu);
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}
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/*
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@@ -2534,13 +2569,16 @@ static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
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if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
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min2 = 0;
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opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
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+ SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
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SECONDARY_EXEC_WBINVD_EXITING |
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SECONDARY_EXEC_ENABLE_VPID |
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SECONDARY_EXEC_ENABLE_EPT |
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SECONDARY_EXEC_UNRESTRICTED_GUEST |
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SECONDARY_EXEC_PAUSE_LOOP_EXITING |
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SECONDARY_EXEC_RDTSCP |
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- SECONDARY_EXEC_ENABLE_INVPCID;
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+ SECONDARY_EXEC_ENABLE_INVPCID |
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+ SECONDARY_EXEC_APIC_REGISTER_VIRT |
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+ SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
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if (adjust_vmx_controls(min2, opt2,
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MSR_IA32_VMX_PROCBASED_CTLS2,
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&_cpu_based_2nd_exec_control) < 0)
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@@ -2551,6 +2589,13 @@ static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
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SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
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_cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
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#endif
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+
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+ if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
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+ _cpu_based_2nd_exec_control &= ~(
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+ SECONDARY_EXEC_APIC_REGISTER_VIRT |
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+ SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
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+ SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
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+
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if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
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/* CR3 accesses and invlpg don't need to cause VM Exits when EPT
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enabled */
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@@ -2748,6 +2793,15 @@ static __init int hardware_setup(void)
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if (!cpu_has_vmx_ple())
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ple_gap = 0;
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+ if (!cpu_has_vmx_apic_register_virt() ||
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+ !cpu_has_vmx_virtual_intr_delivery())
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+ enable_apicv_reg_vid = 0;
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+
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+ if (enable_apicv_reg_vid)
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+ kvm_x86_ops->update_cr8_intercept = NULL;
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+ else
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+ kvm_x86_ops->hwapic_irr_update = NULL;
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+
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if (nested)
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nested_vmx_setup_ctls_msrs();
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@@ -3173,6 +3227,14 @@ static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
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if (!is_paging(vcpu)) {
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hw_cr4 &= ~X86_CR4_PAE;
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hw_cr4 |= X86_CR4_PSE;
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+ /*
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+ * SMEP is disabled if CPU is in non-paging mode in
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+ * hardware. However KVM always uses paging mode to
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+ * emulate guest non-paging mode with TDP.
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+ * To emulate this behavior, SMEP needs to be manually
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+ * disabled when guest switches to non-paging mode.
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+ */
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+ hw_cr4 &= ~X86_CR4_SMEP;
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} else if (!(cr4 & X86_CR4_PAE)) {
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hw_cr4 &= ~X86_CR4_PAE;
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}
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@@ -3707,7 +3769,10 @@ static void free_vpid(struct vcpu_vmx *vmx)
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spin_unlock(&vmx_vpid_lock);
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}
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-static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
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+#define MSR_TYPE_R 1
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+#define MSR_TYPE_W 2
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+static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
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+ u32 msr, int type)
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{
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int f = sizeof(unsigned long);
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@@ -3720,20 +3785,93 @@ static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
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* We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
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*/
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if (msr <= 0x1fff) {
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- __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
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- __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
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+ if (type & MSR_TYPE_R)
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+ /* read-low */
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+ __clear_bit(msr, msr_bitmap + 0x000 / f);
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+
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+ if (type & MSR_TYPE_W)
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+ /* write-low */
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+ __clear_bit(msr, msr_bitmap + 0x800 / f);
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+
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} else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
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msr &= 0x1fff;
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- __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
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- __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
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+ if (type & MSR_TYPE_R)
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+ /* read-high */
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+ __clear_bit(msr, msr_bitmap + 0x400 / f);
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+
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+ if (type & MSR_TYPE_W)
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+ /* write-high */
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+ __clear_bit(msr, msr_bitmap + 0xc00 / f);
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+
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+ }
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+}
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+
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+static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
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+ u32 msr, int type)
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+{
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+ int f = sizeof(unsigned long);
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+
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+ if (!cpu_has_vmx_msr_bitmap())
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+ return;
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+
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+ /*
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+ * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
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+ * have the write-low and read-high bitmap offsets the wrong way round.
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+ * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
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+ */
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+ if (msr <= 0x1fff) {
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+ if (type & MSR_TYPE_R)
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+ /* read-low */
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+ __set_bit(msr, msr_bitmap + 0x000 / f);
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+
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+ if (type & MSR_TYPE_W)
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+ /* write-low */
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+ __set_bit(msr, msr_bitmap + 0x800 / f);
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+
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+ } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
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+ msr &= 0x1fff;
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+ if (type & MSR_TYPE_R)
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+ /* read-high */
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+ __set_bit(msr, msr_bitmap + 0x400 / f);
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+
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+ if (type & MSR_TYPE_W)
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+ /* write-high */
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+ __set_bit(msr, msr_bitmap + 0xc00 / f);
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+
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}
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}
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static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
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{
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if (!longmode_only)
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- __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
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- __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
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+ __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
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+ msr, MSR_TYPE_R | MSR_TYPE_W);
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+ __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
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+ msr, MSR_TYPE_R | MSR_TYPE_W);
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+}
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+
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+static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
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+{
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+ __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
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+ msr, MSR_TYPE_R);
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+ __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
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+ msr, MSR_TYPE_R);
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+}
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+
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+static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
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+{
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+ __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
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+ msr, MSR_TYPE_R);
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+ __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
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+ msr, MSR_TYPE_R);
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+}
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+
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+static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
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+{
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+ __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
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+ msr, MSR_TYPE_W);
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+ __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
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+ msr, MSR_TYPE_W);
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}
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/*
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@@ -3812,6 +3950,11 @@ static u32 vmx_exec_control(struct vcpu_vmx *vmx)
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return exec_control;
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}
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+static int vmx_vm_has_apicv(struct kvm *kvm)
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+{
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+ return enable_apicv_reg_vid && irqchip_in_kernel(kvm);
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+}
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+
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static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
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{
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u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
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@@ -3829,6 +3972,10 @@ static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
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exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
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if (!ple_gap)
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exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
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+ if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
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+ exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
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+ SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
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+ exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
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return exec_control;
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}
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@@ -3873,6 +4020,15 @@ static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
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vmx_secondary_exec_control(vmx));
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}
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+ if (enable_apicv_reg_vid) {
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+ vmcs_write64(EOI_EXIT_BITMAP0, 0);
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+ vmcs_write64(EOI_EXIT_BITMAP1, 0);
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+ vmcs_write64(EOI_EXIT_BITMAP2, 0);
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+ vmcs_write64(EOI_EXIT_BITMAP3, 0);
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+
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+ vmcs_write16(GUEST_INTR_STATUS, 0);
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+ }
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+
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if (ple_gap) {
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vmcs_write32(PLE_GAP, ple_gap);
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vmcs_write32(PLE_WINDOW, ple_window);
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@@ -4787,6 +4943,26 @@ static int handle_apic_access(struct kvm_vcpu *vcpu)
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return emulate_instruction(vcpu, 0) == EMULATE_DONE;
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}
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+static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
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+{
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+ unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
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+ int vector = exit_qualification & 0xff;
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+
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+ /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
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+ kvm_apic_set_eoi_accelerated(vcpu, vector);
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+ return 1;
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+}
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+
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+static int handle_apic_write(struct kvm_vcpu *vcpu)
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+{
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+ unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
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+ u32 offset = exit_qualification & 0xfff;
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+
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+ /* APIC-write VM exit is trap-like and thus no need to adjust IP */
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+ kvm_apic_write_nodecode(vcpu, offset);
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+ return 1;
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+}
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+
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static int handle_task_switch(struct kvm_vcpu *vcpu)
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{
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struct vcpu_vmx *vmx = to_vmx(vcpu);
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@@ -5721,6 +5897,8 @@ static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
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[EXIT_REASON_VMON] = handle_vmon,
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[EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
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[EXIT_REASON_APIC_ACCESS] = handle_apic_access,
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+ [EXIT_REASON_APIC_WRITE] = handle_apic_write,
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+ [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
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[EXIT_REASON_WBINVD] = handle_wbinvd,
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[EXIT_REASON_XSETBV] = handle_xsetbv,
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[EXIT_REASON_TASK_SWITCH] = handle_task_switch,
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@@ -6070,6 +6248,85 @@ static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
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vmcs_write32(TPR_THRESHOLD, irr);
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}
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+static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
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+{
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+ u32 sec_exec_control;
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+
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+ /*
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+ * There is not point to enable virtualize x2apic without enable
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+ * apicv
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+ */
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+ if (!cpu_has_vmx_virtualize_x2apic_mode() ||
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+ !vmx_vm_has_apicv(vcpu->kvm))
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+ return;
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+
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+ if (!vm_need_tpr_shadow(vcpu->kvm))
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+ return;
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+
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+ sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
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+
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+ if (set) {
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+ sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
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+ sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
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+ } else {
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+ sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
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+ sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
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+ }
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+ vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
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+
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+ vmx_set_msr_bitmap(vcpu);
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+}
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+
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+static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
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+{
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+ u16 status;
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+ u8 old;
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+
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+ if (!vmx_vm_has_apicv(kvm))
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+ return;
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+
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+ if (isr == -1)
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+ isr = 0;
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+
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+ status = vmcs_read16(GUEST_INTR_STATUS);
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+ old = status >> 8;
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+ if (isr != old) {
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+ status &= 0xff;
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+ status |= isr << 8;
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+ vmcs_write16(GUEST_INTR_STATUS, status);
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+ }
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+}
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+
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+static void vmx_set_rvi(int vector)
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+{
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+ u16 status;
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+ u8 old;
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+
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+ status = vmcs_read16(GUEST_INTR_STATUS);
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+ old = (u8)status & 0xff;
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+ if ((u8)vector != old) {
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+ status &= ~0xff;
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+ status |= (u8)vector;
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+ vmcs_write16(GUEST_INTR_STATUS, status);
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+ }
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+}
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+
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+static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
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+{
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+ if (max_irr == -1)
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+ return;
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+
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+ vmx_set_rvi(max_irr);
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+}
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+
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+static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
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+{
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+ vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
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+ vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
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+ vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
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+ vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
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+}
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+
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static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
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{
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u32 exit_intr_info;
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@@ -7333,6 +7590,11 @@ static struct kvm_x86_ops vmx_x86_ops = {
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.enable_nmi_window = enable_nmi_window,
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.enable_irq_window = enable_irq_window,
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.update_cr8_intercept = update_cr8_intercept,
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+ .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
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+ .vm_has_apicv = vmx_vm_has_apicv,
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+ .load_eoi_exitmap = vmx_load_eoi_exitmap,
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+ .hwapic_irr_update = vmx_hwapic_irr_update,
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+ .hwapic_isr_update = vmx_hwapic_isr_update,
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.set_tss_addr = vmx_set_tss_addr,
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.get_tdp_level = get_ept_level,
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@@ -7365,7 +7627,7 @@ static struct kvm_x86_ops vmx_x86_ops = {
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static int __init vmx_init(void)
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{
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- int r, i;
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+ int r, i, msr;
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rdmsrl_safe(MSR_EFER, &host_efer);
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@@ -7386,11 +7648,19 @@ static int __init vmx_init(void)
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if (!vmx_msr_bitmap_legacy)
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goto out1;
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+ vmx_msr_bitmap_legacy_x2apic =
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+ (unsigned long *)__get_free_page(GFP_KERNEL);
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+ if (!vmx_msr_bitmap_legacy_x2apic)
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+ goto out2;
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vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
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if (!vmx_msr_bitmap_longmode)
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- goto out2;
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+ goto out3;
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+ vmx_msr_bitmap_longmode_x2apic =
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+ (unsigned long *)__get_free_page(GFP_KERNEL);
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+ if (!vmx_msr_bitmap_longmode_x2apic)
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+ goto out4;
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/*
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* Allow direct access to the PC debug port (it is often used for I/O
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@@ -7422,6 +7692,28 @@ static int __init vmx_init(void)
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vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
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vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
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vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
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+ memcpy(vmx_msr_bitmap_legacy_x2apic,
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+ vmx_msr_bitmap_legacy, PAGE_SIZE);
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+ memcpy(vmx_msr_bitmap_longmode_x2apic,
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+ vmx_msr_bitmap_longmode, PAGE_SIZE);
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+
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+ if (enable_apicv_reg_vid) {
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+ for (msr = 0x800; msr <= 0x8ff; msr++)
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+ vmx_disable_intercept_msr_read_x2apic(msr);
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+
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+ /* According SDM, in x2apic mode, the whole id reg is used.
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+ * But in KVM, it only use the highest eight bits. Need to
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+ * intercept it */
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+ vmx_enable_intercept_msr_read_x2apic(0x802);
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+ /* TMCCT */
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+ vmx_enable_intercept_msr_read_x2apic(0x839);
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+ /* TPR */
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+ vmx_disable_intercept_msr_write_x2apic(0x808);
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+ /* EOI */
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+ vmx_disable_intercept_msr_write_x2apic(0x80b);
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+ /* SELF-IPI */
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+ vmx_disable_intercept_msr_write_x2apic(0x83f);
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+ }
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if (enable_ept) {
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kvm_mmu_set_mask_ptes(0ull,
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@@ -7435,8 +7727,10 @@ static int __init vmx_init(void)
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return 0;
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-out3:
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+out4:
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free_page((unsigned long)vmx_msr_bitmap_longmode);
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+out3:
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+ free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
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out2:
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free_page((unsigned long)vmx_msr_bitmap_legacy);
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out1:
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@@ -7448,6 +7742,8 @@ out:
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static void __exit vmx_exit(void)
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{
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+ free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
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+ free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
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free_page((unsigned long)vmx_msr_bitmap_legacy);
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free_page((unsigned long)vmx_msr_bitmap_longmode);
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free_page((unsigned long)vmx_io_bitmap_b);
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Alexander Graf