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@@ -19,21 +19,25 @@
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/* The base address of the last MMCONFIG device accessed */
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/* The base address of the last MMCONFIG device accessed */
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static u32 mmcfg_last_accessed_device;
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static u32 mmcfg_last_accessed_device;
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+static DECLARE_BITMAP(fallback_slots, 32);
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+
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/*
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/*
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* Functions for accessing PCI configuration space with MMCONFIG accesses
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* Functions for accessing PCI configuration space with MMCONFIG accesses
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*/
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*/
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-static u32 get_base_addr(unsigned int seg, int bus)
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+static u32 get_base_addr(unsigned int seg, int bus, unsigned devfn)
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{
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{
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int cfg_num = -1;
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int cfg_num = -1;
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struct acpi_table_mcfg_config *cfg;
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struct acpi_table_mcfg_config *cfg;
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+ if (seg == 0 && bus == 0 &&
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+ test_bit(PCI_SLOT(devfn), fallback_slots))
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+ return 0;
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+
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while (1) {
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while (1) {
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++cfg_num;
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++cfg_num;
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if (cfg_num >= pci_mmcfg_config_num) {
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if (cfg_num >= pci_mmcfg_config_num) {
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- /* something bad is going on, no cfg table is found. */
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- /* so we fall back to the old way we used to do this */
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- /* and just rely on the first entry to be correct. */
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- return pci_mmcfg_config[0].base_address;
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+ /* Not found - fallback to type 1 */
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+ return 0;
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}
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}
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cfg = &pci_mmcfg_config[cfg_num];
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cfg = &pci_mmcfg_config[cfg_num];
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if (cfg->pci_segment_group_number != seg)
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if (cfg->pci_segment_group_number != seg)
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@@ -44,9 +48,9 @@ static u32 get_base_addr(unsigned int seg, int bus)
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}
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}
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}
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}
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-static inline void pci_exp_set_dev_base(unsigned int seg, int bus, int devfn)
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+static inline void pci_exp_set_dev_base(unsigned int base, int bus, int devfn)
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{
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{
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- u32 dev_base = get_base_addr(seg, bus) | (bus << 20) | (devfn << 12);
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+ u32 dev_base = base | (bus << 20) | (devfn << 12);
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if (dev_base != mmcfg_last_accessed_device) {
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if (dev_base != mmcfg_last_accessed_device) {
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mmcfg_last_accessed_device = dev_base;
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mmcfg_last_accessed_device = dev_base;
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set_fixmap_nocache(FIX_PCIE_MCFG, dev_base);
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set_fixmap_nocache(FIX_PCIE_MCFG, dev_base);
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@@ -57,13 +61,18 @@ static int pci_mmcfg_read(unsigned int seg, unsigned int bus,
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unsigned int devfn, int reg, int len, u32 *value)
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unsigned int devfn, int reg, int len, u32 *value)
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{
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{
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unsigned long flags;
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unsigned long flags;
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+ u32 base;
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if (!value || (bus > 255) || (devfn > 255) || (reg > 4095))
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if (!value || (bus > 255) || (devfn > 255) || (reg > 4095))
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return -EINVAL;
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return -EINVAL;
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+ base = get_base_addr(seg, bus, devfn);
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+ if (!base)
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+ return pci_conf1_read(seg,bus,devfn,reg,len,value);
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+
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spin_lock_irqsave(&pci_config_lock, flags);
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spin_lock_irqsave(&pci_config_lock, flags);
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- pci_exp_set_dev_base(seg, bus, devfn);
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+ pci_exp_set_dev_base(base, bus, devfn);
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switch (len) {
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switch (len) {
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case 1:
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case 1:
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@@ -86,13 +95,18 @@ static int pci_mmcfg_write(unsigned int seg, unsigned int bus,
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unsigned int devfn, int reg, int len, u32 value)
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unsigned int devfn, int reg, int len, u32 value)
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{
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{
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unsigned long flags;
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unsigned long flags;
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+ u32 base;
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if ((bus > 255) || (devfn > 255) || (reg > 4095))
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if ((bus > 255) || (devfn > 255) || (reg > 4095))
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return -EINVAL;
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return -EINVAL;
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+ base = get_base_addr(seg, bus, devfn);
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+ if (!base)
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+ return pci_conf1_write(seg,bus,devfn,reg,len,value);
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+
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spin_lock_irqsave(&pci_config_lock, flags);
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spin_lock_irqsave(&pci_config_lock, flags);
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- pci_exp_set_dev_base(seg, bus, devfn);
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+ pci_exp_set_dev_base(base, bus, devfn);
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switch (len) {
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switch (len) {
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case 1:
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case 1:
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@@ -116,6 +130,37 @@ static struct pci_raw_ops pci_mmcfg = {
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.write = pci_mmcfg_write,
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.write = pci_mmcfg_write,
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};
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};
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+/* K8 systems have some devices (typically in the builtin northbridge)
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+ that are only accessible using type1
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+ Normally this can be expressed in the MCFG by not listing them
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+ and assigning suitable _SEGs, but this isn't implemented in some BIOS.
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+ Instead try to discover all devices on bus 0 that are unreachable using MM
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+ and fallback for them.
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+ We only do this for bus 0/seg 0 */
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+static __init void unreachable_devices(void)
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+{
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+ int i;
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+ unsigned long flags;
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+
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+ for (i = 0; i < 32; i++) {
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+ u32 val1;
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+ u32 addr;
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+
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+ pci_conf1_read(0, 0, PCI_DEVFN(i, 0), 0, 4, &val1);
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+ if (val1 == 0xffffffff)
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+ continue;
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+
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+ /* Locking probably not needed, but safer */
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+ spin_lock_irqsave(&pci_config_lock, flags);
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+ addr = get_base_addr(0, 0, PCI_DEVFN(i, 0));
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+ if (addr != 0)
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+ pci_exp_set_dev_base(addr, 0, PCI_DEVFN(i, 0));
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+ if (addr == 0 || readl((u32 *)addr) != val1)
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+ set_bit(i, fallback_slots);
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+ spin_unlock_irqrestore(&pci_config_lock, flags);
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+ }
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+}
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+
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static int __init pci_mmcfg_init(void)
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static int __init pci_mmcfg_init(void)
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{
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{
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if ((pci_probe & PCI_PROBE_MMCONF) == 0)
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if ((pci_probe & PCI_PROBE_MMCONF) == 0)
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@@ -131,6 +176,8 @@ static int __init pci_mmcfg_init(void)
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raw_pci_ops = &pci_mmcfg;
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raw_pci_ops = &pci_mmcfg;
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pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF;
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pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF;
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+ unreachable_devices();
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+
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out:
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out:
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return 0;
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return 0;
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}
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}
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