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@@ -19,7 +19,36 @@
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*/
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#include "bnx2x.h"
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#include "bnx2x_init.h"
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+#include "bnx2x_cmn.h"
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#include "bnx2x_sriov.h"
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+
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+/* General service functions */
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+static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
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+ u16 pf_id)
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+{
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+ REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
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+ pf_id);
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+ REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
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+ pf_id);
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+ REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
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+ pf_id);
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+ REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
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+ pf_id);
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+}
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+
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+static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
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+ u8 enable)
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+{
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+ REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
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+ enable);
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+ REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
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+ enable);
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+ REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
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+ enable);
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+ REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
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+ enable);
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+}
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+
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int bnx2x_vf_idx_by_abs_fid(struct bnx2x *bp, u16 abs_vfid)
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{
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int idx;
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@@ -272,6 +301,376 @@ failed:
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__bnx2x_iov_free_vfdb(bp);
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return err;
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}
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+/* VF enable primitives
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+ * when pretend is required the caller is responsible
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+ * for calling pretend prior to calling these routines
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+ */
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+
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+/* called only on E1H or E2.
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+ * When pretending to be PF, the pretend value is the function number 0...7
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+ * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
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+ * combination
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+ */
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+int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val)
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+{
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+ u32 pretend_reg;
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+
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+ if (CHIP_IS_E1H(bp) && pretend_func_val > E1H_FUNC_MAX)
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+ return -1;
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+
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+ /* get my own pretend register */
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+ pretend_reg = bnx2x_get_pretend_reg(bp);
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+ REG_WR(bp, pretend_reg, pretend_func_val);
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+ REG_RD(bp, pretend_reg);
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+ return 0;
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+}
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+
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+/* internal vf enable - until vf is enabled internally all transactions
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+ * are blocked. this routine should always be called last with pretend.
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+ */
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+static void bnx2x_vf_enable_internal(struct bnx2x *bp, u8 enable)
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+{
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+ REG_WR(bp, PGLUE_B_REG_INTERNAL_VFID_ENABLE, enable ? 1 : 0);
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+}
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+
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+/* clears vf error in all semi blocks */
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+static void bnx2x_vf_semi_clear_err(struct bnx2x *bp, u8 abs_vfid)
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+{
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+ REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, abs_vfid);
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+ REG_WR(bp, USEM_REG_VFPF_ERR_NUM, abs_vfid);
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+ REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, abs_vfid);
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+ REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, abs_vfid);
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+}
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+
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+static void bnx2x_vf_pglue_clear_err(struct bnx2x *bp, u8 abs_vfid)
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+{
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+ u32 was_err_group = (2 * BP_PATH(bp) + abs_vfid) >> 5;
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+ u32 was_err_reg = 0;
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+
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+ switch (was_err_group) {
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+ case 0:
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+ was_err_reg = PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR;
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+ break;
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+ case 1:
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+ was_err_reg = PGLUE_B_REG_WAS_ERROR_VF_63_32_CLR;
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+ break;
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+ case 2:
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+ was_err_reg = PGLUE_B_REG_WAS_ERROR_VF_95_64_CLR;
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+ break;
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+ case 3:
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+ was_err_reg = PGLUE_B_REG_WAS_ERROR_VF_127_96_CLR;
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+ break;
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+ }
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+ REG_WR(bp, was_err_reg, 1 << (abs_vfid & 0x1f));
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+}
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+
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+void bnx2x_vf_enable_access(struct bnx2x *bp, u8 abs_vfid)
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+{
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+ /* set the VF-PF association in the FW */
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+ storm_memset_vf_to_pf(bp, FW_VF_HANDLE(abs_vfid), BP_FUNC(bp));
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+ storm_memset_func_en(bp, FW_VF_HANDLE(abs_vfid), 1);
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+
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+ /* clear vf errors*/
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+ bnx2x_vf_semi_clear_err(bp, abs_vfid);
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+ bnx2x_vf_pglue_clear_err(bp, abs_vfid);
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+
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+ /* internal vf-enable - pretend */
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+ bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, abs_vfid));
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+ DP(BNX2X_MSG_IOV, "enabling internal access for vf %x\n", abs_vfid);
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+ bnx2x_vf_enable_internal(bp, true);
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+ bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
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+}
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+
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+static u8 bnx2x_vf_is_pcie_pending(struct bnx2x *bp, u8 abs_vfid)
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+{
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+ struct pci_dev *dev;
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+ struct bnx2x_virtf *vf = bnx2x_vf_by_abs_fid(bp, abs_vfid);
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+
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+ if (!vf)
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+ goto unknown_dev;
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+
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+ dev = pci_get_bus_and_slot(vf->bus, vf->devfn);
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+ if (dev)
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+ return bnx2x_is_pcie_pending(dev);
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+
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+unknown_dev:
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+ BNX2X_ERR("Unknown device\n");
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+ return false;
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+}
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+
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+int bnx2x_vf_flr_clnup_epilog(struct bnx2x *bp, u8 abs_vfid)
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+{
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+ /* Wait 100ms */
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+ msleep(100);
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+
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+ /* Verify no pending pci transactions */
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+ if (bnx2x_vf_is_pcie_pending(bp, abs_vfid))
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+ BNX2X_ERR("PCIE Transactions still pending\n");
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+
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+ return 0;
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+}
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+
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+/* must be called after the number of PF queues and the number of VFs are
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+ * both known
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+ */
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+static void
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+bnx2x_iov_static_resc(struct bnx2x *bp, struct vf_pf_resc_request *resc)
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+{
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+ u16 vlan_count = 0;
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+
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+ /* will be set only during VF-ACQUIRE */
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+ resc->num_rxqs = 0;
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+ resc->num_txqs = 0;
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+
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+ /* no credit calculcis for macs (just yet) */
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+ resc->num_mac_filters = 1;
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+
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+ /* divvy up vlan rules */
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+ vlan_count = bp->vlans_pool.check(&bp->vlans_pool);
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+ vlan_count = 1 << ilog2(vlan_count);
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+ resc->num_vlan_filters = vlan_count / BNX2X_NR_VIRTFN(bp);
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+
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+ /* no real limitation */
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+ resc->num_mc_filters = 0;
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+
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+ /* num_sbs already set */
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+}
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+
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+/* IOV global initialization routines */
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+void bnx2x_iov_init_dq(struct bnx2x *bp)
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+{
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+ if (!IS_SRIOV(bp))
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+ return;
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+
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+ /* Set the DQ such that the CID reflect the abs_vfid */
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+ REG_WR(bp, DORQ_REG_VF_NORM_VF_BASE, 0);
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+ REG_WR(bp, DORQ_REG_MAX_RVFID_SIZE, ilog2(BNX2X_MAX_NUM_OF_VFS));
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+
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+ /* Set VFs starting CID. If its > 0 the preceding CIDs are belong to
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+ * the PF L2 queues
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+ */
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+ REG_WR(bp, DORQ_REG_VF_NORM_CID_BASE, BNX2X_FIRST_VF_CID);
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+
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+ /* The VF window size is the log2 of the max number of CIDs per VF */
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+ REG_WR(bp, DORQ_REG_VF_NORM_CID_WND_SIZE, BNX2X_VF_CID_WND);
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+
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+ /* The VF doorbell size 0 - *B, 4 - 128B. We set it here to match
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+ * the Pf doorbell size although the 2 are independent.
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+ */
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+ REG_WR(bp, DORQ_REG_VF_NORM_CID_OFST,
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+ BNX2X_DB_SHIFT - BNX2X_DB_MIN_SHIFT);
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+
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+ /* No security checks for now -
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+ * configure single rule (out of 16) mask = 0x1, value = 0x0,
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+ * CID range 0 - 0x1ffff
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+ */
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+ REG_WR(bp, DORQ_REG_VF_TYPE_MASK_0, 1);
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+ REG_WR(bp, DORQ_REG_VF_TYPE_VALUE_0, 0);
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+ REG_WR(bp, DORQ_REG_VF_TYPE_MIN_MCID_0, 0);
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+ REG_WR(bp, DORQ_REG_VF_TYPE_MAX_MCID_0, 0x1ffff);
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+
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+ /* set the number of VF alllowed doorbells to the full DQ range */
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+ REG_WR(bp, DORQ_REG_VF_NORM_MAX_CID_COUNT, 0x20000);
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+
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+ /* set the VF doorbell threshold */
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+ REG_WR(bp, DORQ_REG_VF_USAGE_CT_LIMIT, 4);
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+}
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+
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+void bnx2x_iov_init_dmae(struct bnx2x *bp)
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+{
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+ DP(BNX2X_MSG_IOV, "SRIOV is %s\n", IS_SRIOV(bp) ? "ON" : "OFF");
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+ if (!IS_SRIOV(bp))
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+ return;
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+
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+ REG_WR(bp, DMAE_REG_BACKWARD_COMP_EN, 0);
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+}
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+
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+static int bnx2x_vf_bus(struct bnx2x *bp, int vfid)
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+{
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+ struct pci_dev *dev = bp->pdev;
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+ struct bnx2x_sriov *iov = &bp->vfdb->sriov;
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+
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+ return dev->bus->number + ((dev->devfn + iov->offset +
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+ iov->stride * vfid) >> 8);
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+}
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+
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+static int bnx2x_vf_devfn(struct bnx2x *bp, int vfid)
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+{
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+ struct pci_dev *dev = bp->pdev;
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+ struct bnx2x_sriov *iov = &bp->vfdb->sriov;
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+
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+ return (dev->devfn + iov->offset + iov->stride * vfid) & 0xff;
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+}
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+
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+static void bnx2x_vf_set_bars(struct bnx2x *bp, struct bnx2x_virtf *vf)
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+{
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+ int i, n;
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+ struct pci_dev *dev = bp->pdev;
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+ struct bnx2x_sriov *iov = &bp->vfdb->sriov;
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+
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+ for (i = 0, n = 0; i < PCI_SRIOV_NUM_BARS; i += 2, n++) {
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+ u64 start = pci_resource_start(dev, PCI_IOV_RESOURCES + i);
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+ u32 size = pci_resource_len(dev, PCI_IOV_RESOURCES + i);
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+
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+ do_div(size, iov->total);
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+ vf->bars[n].bar = start + size * vf->abs_vfid;
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+ vf->bars[n].size = size;
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+ }
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+}
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+
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+void bnx2x_iov_free_mem(struct bnx2x *bp)
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+{
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+ int i;
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+
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+ if (!IS_SRIOV(bp))
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+ return;
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+
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+ /* free vfs hw contexts */
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+ for (i = 0; i < BNX2X_VF_CIDS/ILT_PAGE_CIDS; i++) {
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+ struct hw_dma *cxt = &bp->vfdb->context[i];
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+ BNX2X_PCI_FREE(cxt->addr, cxt->mapping, cxt->size);
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+ }
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+
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+ BNX2X_PCI_FREE(BP_VFDB(bp)->sp_dma.addr,
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+ BP_VFDB(bp)->sp_dma.mapping,
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+ BP_VFDB(bp)->sp_dma.size);
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+
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+ BNX2X_PCI_FREE(BP_VF_MBX_DMA(bp)->addr,
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+ BP_VF_MBX_DMA(bp)->mapping,
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+ BP_VF_MBX_DMA(bp)->size);
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+}
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+
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+int bnx2x_iov_alloc_mem(struct bnx2x *bp)
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+{
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+ size_t tot_size;
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+ int i, rc = 0;
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+
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+ if (!IS_SRIOV(bp))
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+ return rc;
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+
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+ /* allocate vfs hw contexts */
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+ tot_size = (BP_VFDB(bp)->sriov.first_vf_in_pf + BNX2X_NR_VIRTFN(bp)) *
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+ BNX2X_CIDS_PER_VF * sizeof(union cdu_context);
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+
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+ for (i = 0; i < BNX2X_VF_CIDS/ILT_PAGE_CIDS; i++) {
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+ struct hw_dma *cxt = BP_VF_CXT_PAGE(bp, i);
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+ cxt->size = min_t(size_t, tot_size, CDU_ILT_PAGE_SZ);
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+
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+ if (cxt->size) {
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+ BNX2X_PCI_ALLOC(cxt->addr, &cxt->mapping, cxt->size);
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+ } else {
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+ cxt->addr = NULL;
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+ cxt->mapping = 0;
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+ }
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+ tot_size -= cxt->size;
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+ }
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+
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+ /* allocate vfs ramrods dma memory - client_init and set_mac */
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+ tot_size = BNX2X_NR_VIRTFN(bp) * sizeof(struct bnx2x_vf_sp);
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+ BNX2X_PCI_ALLOC(BP_VFDB(bp)->sp_dma.addr, &BP_VFDB(bp)->sp_dma.mapping,
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+ tot_size);
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+ BP_VFDB(bp)->sp_dma.size = tot_size;
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+
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+ /* allocate mailboxes */
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+ tot_size = BNX2X_NR_VIRTFN(bp) * MBX_MSG_ALIGNED_SIZE;
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+ BNX2X_PCI_ALLOC(BP_VF_MBX_DMA(bp)->addr, &BP_VF_MBX_DMA(bp)->mapping,
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+ tot_size);
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+ BP_VF_MBX_DMA(bp)->size = tot_size;
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+
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+ return 0;
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+
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+alloc_mem_err:
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+ return -ENOMEM;
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+}
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+
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+/* called by bnx2x_nic_load */
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+int bnx2x_iov_nic_init(struct bnx2x *bp)
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+{
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+ int vfid, qcount, i;
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+
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+ if (!IS_SRIOV(bp)) {
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+ DP(BNX2X_MSG_IOV, "vfdb was not allocated\n");
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+ return 0;
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+ }
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+
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+ DP(BNX2X_MSG_IOV, "num of vfs: %d\n", (bp)->vfdb->sriov.nr_virtfn);
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+
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+ /* initialize vf database */
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+ for_each_vf(bp, vfid) {
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+ struct bnx2x_virtf *vf = BP_VF(bp, vfid);
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+
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+ int base_vf_cid = (BP_VFDB(bp)->sriov.first_vf_in_pf + vfid) *
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+ BNX2X_CIDS_PER_VF;
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+
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+ union cdu_context *base_cxt = (union cdu_context *)
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+ BP_VF_CXT_PAGE(bp, base_vf_cid/ILT_PAGE_CIDS)->addr +
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+ (base_vf_cid & (ILT_PAGE_CIDS-1));
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+
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+ DP(BNX2X_MSG_IOV,
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+ "VF[%d] Max IGU SBs: %d, base vf cid 0x%x, base cid 0x%x, base cxt %p\n",
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+ vf->abs_vfid, vf_sb_count(vf), base_vf_cid,
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+ BNX2X_FIRST_VF_CID + base_vf_cid, base_cxt);
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+
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+ /* init statically provisioned resources */
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+ bnx2x_iov_static_resc(bp, &vf->alloc_resc);
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+
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+ /* queues are initialized during VF-ACQUIRE */
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+
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+ /* reserve the vf vlan credit */
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+ bp->vlans_pool.get(&bp->vlans_pool, vf_vlan_rules_cnt(vf));
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+
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+ vf->filter_state = 0;
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+ vf->sp_cl_id = bnx2x_fp(bp, 0, cl_id);
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+
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+ /* init mcast object - This object will be re-initialized
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+ * during VF-ACQUIRE with the proper cl_id and cid.
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+ * It needs to be initialized here so that it can be safely
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+ * handled by a subsequent FLR flow.
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+ */
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+ bnx2x_init_mcast_obj(bp, &vf->mcast_obj, 0xFF,
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+ 0xFF, 0xFF, 0xFF,
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+ bnx2x_vf_sp(bp, vf, mcast_rdata),
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+ bnx2x_vf_sp_map(bp, vf, mcast_rdata),
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+ BNX2X_FILTER_MCAST_PENDING,
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+ &vf->filter_state,
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+ BNX2X_OBJ_TYPE_RX_TX);
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|
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+
|
|
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+ /* set the mailbox message addresses */
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|
|
+ BP_VF_MBX(bp, vfid)->msg = (struct bnx2x_vf_mbx_msg *)
|
|
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+ (((u8 *)BP_VF_MBX_DMA(bp)->addr) + vfid *
|
|
|
+ MBX_MSG_ALIGNED_SIZE);
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+
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+ BP_VF_MBX(bp, vfid)->msg_mapping = BP_VF_MBX_DMA(bp)->mapping +
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|
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+ vfid * MBX_MSG_ALIGNED_SIZE;
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|
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+
|
|
|
+ /* Enable vf mailbox */
|
|
|
+ bnx2x_vf_enable_mbx(bp, vf->abs_vfid);
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Final VF init */
|
|
|
+ qcount = 0;
|
|
|
+ for_each_vf(bp, i) {
|
|
|
+ struct bnx2x_virtf *vf = BP_VF(bp, i);
|
|
|
+
|
|
|
+ /* fill in the BDF and bars */
|
|
|
+ vf->bus = bnx2x_vf_bus(bp, i);
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|
|
+ vf->devfn = bnx2x_vf_devfn(bp, i);
|
|
|
+ bnx2x_vf_set_bars(bp, vf);
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|
|
+
|
|
|
+ DP(BNX2X_MSG_IOV,
|
|
|
+ "VF info[%d]: bus 0x%x, devfn 0x%x, bar0 [0x%x, %d], bar1 [0x%x, %d], bar2 [0x%x, %d]\n",
|
|
|
+ vf->abs_vfid, vf->bus, vf->devfn,
|
|
|
+ (unsigned)vf->bars[0].bar, vf->bars[0].size,
|
|
|
+ (unsigned)vf->bars[1].bar, vf->bars[1].size,
|
|
|
+ (unsigned)vf->bars[2].bar, vf->bars[2].size);
|
|
|
+
|
|
|
+ /* set local queue arrays */
|
|
|
+ vf->vfqs = &bp->vfdb->vfqs[qcount];
|
|
|
+ qcount += bnx2x_vf(bp, i, alloc_resc.num_sbs);
|
|
|
+ }
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
|
|
|
/* called by bnx2x_init_hw_func, returns the next ilt line */
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int bnx2x_iov_init_ilt(struct bnx2x *bp, u16 line)
|
Ariel Elior