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@@ -142,6 +142,7 @@
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/* Source 2 operand type */
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#define Src2Shift (31)
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#define Src2None (OpNone << Src2Shift)
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+#define Src2Mem (OpMem << Src2Shift)
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#define Src2CL (OpCL << Src2Shift)
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#define Src2ImmByte (OpImmByte << Src2Shift)
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#define Src2One (OpOne << Src2Shift)
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@@ -548,8 +549,8 @@ FOP_END;
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#define __emulate_1op_rax_rdx(ctxt, _op, _suffix, _ex) \
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do { \
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unsigned long _tmp; \
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- ulong *rax = reg_rmw((ctxt), VCPU_REGS_RAX); \
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- ulong *rdx = reg_rmw((ctxt), VCPU_REGS_RDX); \
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+ ulong *rax = &ctxt->dst.val; \
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+ ulong *rdx = &ctxt->src.val; \
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\
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__asm__ __volatile__ ( \
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_PRE_EFLAGS("0", "5", "1") \
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@@ -564,7 +565,7 @@ FOP_END;
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_ASM_EXTABLE(1b, 3b) \
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: "=m" ((ctxt)->eflags), "=&r" (_tmp), \
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"+a" (*rax), "+d" (*rdx), "+qm"(_ex) \
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- : "i" (EFLAGS_MASK), "m" ((ctxt)->src.val)); \
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+ : "i" (EFLAGS_MASK), "m" ((ctxt)->src2.val)); \
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} while (0)
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/* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
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@@ -3735,10 +3736,10 @@ static const struct opcode group3[] = {
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F(DstMem | SrcImm | NoWrite, em_test),
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F(DstMem | SrcNone | Lock, em_not),
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F(DstMem | SrcNone | Lock, em_neg),
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- I(SrcMem, em_mul_ex),
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- I(SrcMem, em_imul_ex),
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- I(SrcMem, em_div_ex),
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- I(SrcMem, em_idiv_ex),
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+ I(DstXacc | Src2Mem, em_mul_ex),
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+ I(DstXacc | Src2Mem, em_imul_ex),
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+ I(DstXacc | Src2Mem, em_div_ex),
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+ I(DstXacc | Src2Mem, em_idiv_ex),
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};
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static const struct opcode group4[] = {
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Avi Kivity