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@@ -413,8 +413,6 @@ ixgb_init_rx_addrs(struct ixgb_hw *hw)
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IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
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IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
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IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
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IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
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}
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}
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-
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- return;
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}
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}
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/******************************************************************************
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/******************************************************************************
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@@ -483,7 +481,6 @@ ixgb_mc_addr_list_update(struct ixgb_hw *hw,
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}
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}
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pr_debug("MC Update Complete\n");
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pr_debug("MC Update Complete\n");
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- return;
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}
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}
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/******************************************************************************
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/******************************************************************************
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@@ -566,8 +563,6 @@ ixgb_mta_set(struct ixgb_hw *hw,
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mta_reg |= (1 << hash_bit);
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mta_reg |= (1 << hash_bit);
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IXGB_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta_reg);
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IXGB_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta_reg);
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-
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- return;
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}
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}
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/******************************************************************************
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/******************************************************************************
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@@ -600,7 +595,6 @@ ixgb_rar_set(struct ixgb_hw *hw,
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IXGB_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
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IXGB_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
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IXGB_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
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IXGB_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
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- return;
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}
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}
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/******************************************************************************
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/******************************************************************************
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@@ -616,7 +610,6 @@ ixgb_write_vfta(struct ixgb_hw *hw,
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u32 value)
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u32 value)
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{
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{
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IXGB_WRITE_REG_ARRAY(hw, VFTA, offset, value);
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IXGB_WRITE_REG_ARRAY(hw, VFTA, offset, value);
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- return;
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}
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}
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/******************************************************************************
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/******************************************************************************
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@@ -631,7 +624,6 @@ ixgb_clear_vfta(struct ixgb_hw *hw)
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for (offset = 0; offset < IXGB_VLAN_FILTER_TBL_SIZE; offset++)
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for (offset = 0; offset < IXGB_VLAN_FILTER_TBL_SIZE; offset++)
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IXGB_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
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IXGB_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
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- return;
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}
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}
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/******************************************************************************
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/******************************************************************************
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@@ -1050,7 +1042,6 @@ ixgb_clear_hw_cntrs(struct ixgb_hw *hw)
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temp_reg = IXGB_READ_REG(hw, XOFFRXC);
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temp_reg = IXGB_READ_REG(hw, XOFFRXC);
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temp_reg = IXGB_READ_REG(hw, XOFFTXC);
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temp_reg = IXGB_READ_REG(hw, XOFFTXC);
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temp_reg = IXGB_READ_REG(hw, RJC);
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temp_reg = IXGB_READ_REG(hw, RJC);
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- return;
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}
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}
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/******************************************************************************
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/******************************************************************************
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@@ -1066,7 +1057,6 @@ ixgb_led_on(struct ixgb_hw *hw)
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/* To turn on the LED, clear software-definable pin 0 (SDP0). */
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/* To turn on the LED, clear software-definable pin 0 (SDP0). */
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ctrl0_reg &= ~IXGB_CTRL0_SDP0;
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ctrl0_reg &= ~IXGB_CTRL0_SDP0;
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IXGB_WRITE_REG(hw, CTRL0, ctrl0_reg);
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IXGB_WRITE_REG(hw, CTRL0, ctrl0_reg);
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- return;
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}
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}
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/******************************************************************************
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/******************************************************************************
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@@ -1082,7 +1072,6 @@ ixgb_led_off(struct ixgb_hw *hw)
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/* To turn off the LED, set software-definable pin 0 (SDP0). */
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/* To turn off the LED, set software-definable pin 0 (SDP0). */
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ctrl0_reg |= IXGB_CTRL0_SDP0;
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ctrl0_reg |= IXGB_CTRL0_SDP0;
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IXGB_WRITE_REG(hw, CTRL0, ctrl0_reg);
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IXGB_WRITE_REG(hw, CTRL0, ctrl0_reg);
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- return;
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}
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}
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/******************************************************************************
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/******************************************************************************
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@@ -1122,8 +1111,6 @@ ixgb_get_bus_info(struct ixgb_hw *hw)
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hw->bus.width = (status_reg & IXGB_STATUS_BUS64) ?
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hw->bus.width = (status_reg & IXGB_STATUS_BUS64) ?
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ixgb_bus_width_64 : ixgb_bus_width_32;
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ixgb_bus_width_64 : ixgb_bus_width_32;
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-
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- return;
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}
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}
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/******************************************************************************
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/******************************************************************************
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@@ -1210,8 +1197,6 @@ ixgb_optics_reset(struct ixgb_hw *hw)
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IXGB_PHY_ADDRESS,
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IXGB_PHY_ADDRESS,
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MDIO_MMD_PMAPMD);
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MDIO_MMD_PMAPMD);
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}
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}
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-
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- return;
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}
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}
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/******************************************************************************
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/******************************************************************************
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@@ -1272,6 +1257,4 @@ ixgb_optics_reset_bcm(struct ixgb_hw *hw)
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/* SerDes needs extra delay */
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/* SerDes needs extra delay */
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msleep(IXGB_SUN_PHY_RESET_DELAY);
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msleep(IXGB_SUN_PHY_RESET_DELAY);
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-
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- return;
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}
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}
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