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@@ -34,7 +34,6 @@
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#include "ixgbe_common.h"
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#include "ixgbe_phy.h"
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-static s32 ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw);
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static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
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static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
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static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
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@@ -595,14 +594,14 @@ out:
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}
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/**
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- * ixgbe_read_eeprom_generic - Read EEPROM word using EERD
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+ * ixgbe_read_eerd_generic - Read EEPROM word using EERD
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* @hw: pointer to hardware structure
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* @offset: offset of word in the EEPROM to read
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* @data: word read from the EEPROM
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*
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* Reads a 16 bit word from the EEPROM using the EERD register.
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**/
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-s32 ixgbe_read_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
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+s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
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{
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u32 eerd;
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s32 status;
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@@ -614,15 +613,15 @@ s32 ixgbe_read_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
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goto out;
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}
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- eerd = (offset << IXGBE_EEPROM_READ_ADDR_SHIFT) +
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- IXGBE_EEPROM_READ_REG_START;
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+ eerd = (offset << IXGBE_EEPROM_RW_ADDR_SHIFT) +
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+ IXGBE_EEPROM_RW_REG_START;
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IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
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- status = ixgbe_poll_eeprom_eerd_done(hw);
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+ status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
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if (status == 0)
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*data = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
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- IXGBE_EEPROM_READ_REG_DATA);
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+ IXGBE_EEPROM_RW_REG_DATA);
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else
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hw_dbg(hw, "Eeprom read timed out\n");
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@@ -631,20 +630,26 @@ out:
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}
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/**
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- * ixgbe_poll_eeprom_eerd_done - Poll EERD status
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+ * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
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* @hw: pointer to hardware structure
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+ * @ee_reg: EEPROM flag for polling
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*
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- * Polls the status bit (bit 1) of the EERD to determine when the read is done.
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+ * Polls the status bit (bit 1) of the EERD or EEWR to determine when the
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+ * read or write is done respectively.
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**/
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-static s32 ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw)
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+s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
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{
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u32 i;
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u32 reg;
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s32 status = IXGBE_ERR_EEPROM;
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- for (i = 0; i < IXGBE_EERD_ATTEMPTS; i++) {
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- reg = IXGBE_READ_REG(hw, IXGBE_EERD);
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- if (reg & IXGBE_EEPROM_READ_REG_DONE) {
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+ for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) {
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+ if (ee_reg == IXGBE_NVM_POLL_READ)
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+ reg = IXGBE_READ_REG(hw, IXGBE_EERD);
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+ else
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+ reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
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+
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+ if (reg & IXGBE_EEPROM_RW_REG_DONE) {
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status = 0;
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break;
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}
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@@ -2255,3 +2260,490 @@ s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
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return 0;
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}
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+
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+/**
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+ * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
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+ * @hw: pointer to hardware structure
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+ * @san_mac_offset: SAN MAC address offset
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+ *
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+ * This function will read the EEPROM location for the SAN MAC address
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+ * pointer, and returns the value at that location. This is used in both
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+ * get and set mac_addr routines.
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+ **/
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+static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
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+ u16 *san_mac_offset)
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+{
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+ /*
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+ * First read the EEPROM pointer to see if the MAC addresses are
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+ * available.
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+ */
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+ hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, san_mac_offset);
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+
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+ return 0;
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+}
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+
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+/**
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+ * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
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+ * @hw: pointer to hardware structure
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+ * @san_mac_addr: SAN MAC address
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+ *
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+ * Reads the SAN MAC address from the EEPROM, if it's available. This is
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+ * per-port, so set_lan_id() must be called before reading the addresses.
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+ * set_lan_id() is called by identify_sfp(), but this cannot be relied
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+ * upon for non-SFP connections, so we must call it here.
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+ **/
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+s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
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+{
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+ u16 san_mac_data, san_mac_offset;
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+ u8 i;
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+
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+ /*
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+ * First read the EEPROM pointer to see if the MAC addresses are
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+ * available. If they're not, no point in calling set_lan_id() here.
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+ */
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+ ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
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+
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+ if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) {
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+ /*
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+ * No addresses available in this EEPROM. It's not an
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+ * error though, so just wipe the local address and return.
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+ */
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+ for (i = 0; i < 6; i++)
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+ san_mac_addr[i] = 0xFF;
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+
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+ goto san_mac_addr_out;
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+ }
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+
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+ /* make sure we know which port we need to program */
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+ hw->mac.ops.set_lan_id(hw);
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+ /* apply the port offset to the address offset */
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+ (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
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+ (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
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+ for (i = 0; i < 3; i++) {
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+ hw->eeprom.ops.read(hw, san_mac_offset, &san_mac_data);
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+ san_mac_addr[i * 2] = (u8)(san_mac_data);
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+ san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
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+ san_mac_offset++;
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+ }
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+
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+san_mac_addr_out:
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+ return 0;
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+}
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+
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+/**
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+ * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
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+ * @hw: pointer to hardware structure
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+ *
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+ * Read PCIe configuration space, and get the MSI-X vector count from
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+ * the capabilities table.
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+ **/
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+u32 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
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+{
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+ struct ixgbe_adapter *adapter = hw->back;
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+ u16 msix_count;
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+ pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82599_CAPS,
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+ &msix_count);
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+ msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
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+
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+ /* MSI-X count is zero-based in HW, so increment to give proper value */
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+ msix_count++;
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+
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+ return msix_count;
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+}
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+
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+/**
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+ * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
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+ * @hw: pointer to hardware struct
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+ * @rar: receive address register index to disassociate
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+ * @vmdq: VMDq pool index to remove from the rar
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+ **/
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+s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
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+{
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+ u32 mpsar_lo, mpsar_hi;
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+ u32 rar_entries = hw->mac.num_rar_entries;
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+
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+ if (rar < rar_entries) {
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+ mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
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+ mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
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+
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+ if (!mpsar_lo && !mpsar_hi)
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+ goto done;
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+
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+ if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
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+ if (mpsar_lo) {
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+ IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
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+ mpsar_lo = 0;
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+ }
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+ if (mpsar_hi) {
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+ IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
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+ mpsar_hi = 0;
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+ }
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+ } else if (vmdq < 32) {
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+ mpsar_lo &= ~(1 << vmdq);
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+ IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
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+ } else {
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+ mpsar_hi &= ~(1 << (vmdq - 32));
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+ IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
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+ }
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+
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+ /* was that the last pool using this rar? */
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+ if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
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+ hw->mac.ops.clear_rar(hw, rar);
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+ } else {
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+ hw_dbg(hw, "RAR index %d is out of range.\n", rar);
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+ }
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+
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+done:
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+ return 0;
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+}
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+
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+/**
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+ * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
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+ * @hw: pointer to hardware struct
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+ * @rar: receive address register index to associate with a VMDq index
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+ * @vmdq: VMDq pool index
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+ **/
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+s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
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+{
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+ u32 mpsar;
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+ u32 rar_entries = hw->mac.num_rar_entries;
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+
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+ if (rar < rar_entries) {
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+ if (vmdq < 32) {
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+ mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
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+ mpsar |= 1 << vmdq;
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+ IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
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+ } else {
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+ mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
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+ mpsar |= 1 << (vmdq - 32);
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+ IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
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+ }
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+ } else {
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+ hw_dbg(hw, "RAR index %d is out of range.\n", rar);
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+ }
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+ return 0;
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+}
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+
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+/**
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+ * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
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+ * @hw: pointer to hardware structure
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+ **/
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+s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
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+{
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+ int i;
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+
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+
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+ for (i = 0; i < 128; i++)
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+ IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
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+
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+ return 0;
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+}
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+
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+/**
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+ * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
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+ * @hw: pointer to hardware structure
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+ * @vlan: VLAN id to write to VLAN filter
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+ *
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+ * return the VLVF index where this VLAN id should be placed
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+ *
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+ **/
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+s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan)
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+{
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+ u32 bits = 0;
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+ u32 first_empty_slot = 0;
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+ s32 regindex;
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+
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+ /* short cut the special case */
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+ if (vlan == 0)
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+ return 0;
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+
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+ /*
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+ * Search for the vlan id in the VLVF entries. Save off the first empty
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+ * slot found along the way
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+ */
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+ for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {
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+ bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
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+ if (!bits && !(first_empty_slot))
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+ first_empty_slot = regindex;
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+ else if ((bits & 0x0FFF) == vlan)
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+ break;
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+ }
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+
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+ /*
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+ * If regindex is less than IXGBE_VLVF_ENTRIES, then we found the vlan
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+ * in the VLVF. Else use the first empty VLVF register for this
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+ * vlan id.
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+ */
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+ if (regindex >= IXGBE_VLVF_ENTRIES) {
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+ if (first_empty_slot)
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+ regindex = first_empty_slot;
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+ else {
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+ hw_dbg(hw, "No space in VLVF.\n");
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+ regindex = IXGBE_ERR_NO_SPACE;
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+ }
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+ }
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+
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+ return regindex;
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+}
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+
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+/**
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+ * ixgbe_set_vfta_generic - Set VLAN filter table
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+ * @hw: pointer to hardware structure
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+ * @vlan: VLAN id to write to VLAN filter
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+ * @vind: VMDq output index that maps queue to VLAN id in VFVFB
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+ * @vlan_on: boolean flag to turn on/off VLAN in VFVF
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+ *
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+ * Turn on/off specified VLAN in the VLAN filter table.
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+ **/
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+s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
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+ bool vlan_on)
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+{
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+ s32 regindex;
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+ u32 bitindex;
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+ u32 vfta;
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+ u32 bits;
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+ u32 vt;
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+ u32 targetbit;
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+ bool vfta_changed = false;
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+
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+ if (vlan > 4095)
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+ return IXGBE_ERR_PARAM;
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+
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+ /*
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+ * this is a 2 part operation - first the VFTA, then the
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+ * VLVF and VLVFB if VT Mode is set
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+ * We don't write the VFTA until we know the VLVF part succeeded.
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+ */
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+
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+ /* Part 1
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+ * The VFTA is a bitstring made up of 128 32-bit registers
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+ * that enable the particular VLAN id, much like the MTA:
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+ * bits[11-5]: which register
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+ * bits[4-0]: which bit in the register
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+ */
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+ regindex = (vlan >> 5) & 0x7F;
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+ bitindex = vlan & 0x1F;
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+ targetbit = (1 << bitindex);
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+ vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
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+
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+ if (vlan_on) {
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+ if (!(vfta & targetbit)) {
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+ vfta |= targetbit;
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+ vfta_changed = true;
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+ }
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+ } else {
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+ if ((vfta & targetbit)) {
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+ vfta &= ~targetbit;
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+ vfta_changed = true;
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+ }
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+ }
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+
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+ /* Part 2
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+ * If VT Mode is set
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+ * Either vlan_on
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+ * make sure the vlan is in VLVF
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+ * set the vind bit in the matching VLVFB
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+ * Or !vlan_on
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+ * clear the pool bit and possibly the vind
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+ */
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+ vt = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
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+ if (vt & IXGBE_VT_CTL_VT_ENABLE) {
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+ s32 vlvf_index;
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+
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+ vlvf_index = ixgbe_find_vlvf_slot(hw, vlan);
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+ if (vlvf_index < 0)
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+ return vlvf_index;
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+
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+ if (vlan_on) {
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+ /* set the pool bit */
|
|
|
+ if (vind < 32) {
|
|
|
+ bits = IXGBE_READ_REG(hw,
|
|
|
+ IXGBE_VLVFB(vlvf_index*2));
|
|
|
+ bits |= (1 << vind);
|
|
|
+ IXGBE_WRITE_REG(hw,
|
|
|
+ IXGBE_VLVFB(vlvf_index*2),
|
|
|
+ bits);
|
|
|
+ } else {
|
|
|
+ bits = IXGBE_READ_REG(hw,
|
|
|
+ IXGBE_VLVFB((vlvf_index*2)+1));
|
|
|
+ bits |= (1 << (vind-32));
|
|
|
+ IXGBE_WRITE_REG(hw,
|
|
|
+ IXGBE_VLVFB((vlvf_index*2)+1),
|
|
|
+ bits);
|
|
|
+ }
|
|
|
+ } else {
|
|
|
+ /* clear the pool bit */
|
|
|
+ if (vind < 32) {
|
|
|
+ bits = IXGBE_READ_REG(hw,
|
|
|
+ IXGBE_VLVFB(vlvf_index*2));
|
|
|
+ bits &= ~(1 << vind);
|
|
|
+ IXGBE_WRITE_REG(hw,
|
|
|
+ IXGBE_VLVFB(vlvf_index*2),
|
|
|
+ bits);
|
|
|
+ bits |= IXGBE_READ_REG(hw,
|
|
|
+ IXGBE_VLVFB((vlvf_index*2)+1));
|
|
|
+ } else {
|
|
|
+ bits = IXGBE_READ_REG(hw,
|
|
|
+ IXGBE_VLVFB((vlvf_index*2)+1));
|
|
|
+ bits &= ~(1 << (vind-32));
|
|
|
+ IXGBE_WRITE_REG(hw,
|
|
|
+ IXGBE_VLVFB((vlvf_index*2)+1),
|
|
|
+ bits);
|
|
|
+ bits |= IXGBE_READ_REG(hw,
|
|
|
+ IXGBE_VLVFB(vlvf_index*2));
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ /*
|
|
|
+ * If there are still bits set in the VLVFB registers
|
|
|
+ * for the VLAN ID indicated we need to see if the
|
|
|
+ * caller is requesting that we clear the VFTA entry bit.
|
|
|
+ * If the caller has requested that we clear the VFTA
|
|
|
+ * entry bit but there are still pools/VFs using this VLAN
|
|
|
+ * ID entry then ignore the request. We're not worried
|
|
|
+ * about the case where we're turning the VFTA VLAN ID
|
|
|
+ * entry bit on, only when requested to turn it off as
|
|
|
+ * there may be multiple pools and/or VFs using the
|
|
|
+ * VLAN ID entry. In that case we cannot clear the
|
|
|
+ * VFTA bit until all pools/VFs using that VLAN ID have also
|
|
|
+ * been cleared. This will be indicated by "bits" being
|
|
|
+ * zero.
|
|
|
+ */
|
|
|
+ if (bits) {
|
|
|
+ IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index),
|
|
|
+ (IXGBE_VLVF_VIEN | vlan));
|
|
|
+ if (!vlan_on) {
|
|
|
+ /* someone wants to clear the vfta entry
|
|
|
+ * but some pools/VFs are still using it.
|
|
|
+ * Ignore it. */
|
|
|
+ vfta_changed = false;
|
|
|
+ }
|
|
|
+ }
|
|
|
+ else
|
|
|
+ IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
|
|
|
+ }
|
|
|
+
|
|
|
+ if (vfta_changed)
|
|
|
+ IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), vfta);
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+/**
|
|
|
+ * ixgbe_clear_vfta_generic - Clear VLAN filter table
|
|
|
+ * @hw: pointer to hardware structure
|
|
|
+ *
|
|
|
+ * Clears the VLAN filer table, and the VMDq index associated with the filter
|
|
|
+ **/
|
|
|
+s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
|
|
|
+{
|
|
|
+ u32 offset;
|
|
|
+
|
|
|
+ for (offset = 0; offset < hw->mac.vft_size; offset++)
|
|
|
+ IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
|
|
|
+
|
|
|
+ for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
|
|
|
+ IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
|
|
|
+ IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset*2), 0);
|
|
|
+ IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset*2)+1), 0);
|
|
|
+ }
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+/**
|
|
|
+ * ixgbe_check_mac_link_generic - Determine link and speed status
|
|
|
+ * @hw: pointer to hardware structure
|
|
|
+ * @speed: pointer to link speed
|
|
|
+ * @link_up: true when link is up
|
|
|
+ * @link_up_wait_to_complete: bool used to wait for link up or not
|
|
|
+ *
|
|
|
+ * Reads the links register to determine if link is up and the current speed
|
|
|
+ **/
|
|
|
+s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
|
|
|
+ bool *link_up, bool link_up_wait_to_complete)
|
|
|
+{
|
|
|
+ u32 links_reg;
|
|
|
+ u32 i;
|
|
|
+
|
|
|
+ links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
|
|
|
+ if (link_up_wait_to_complete) {
|
|
|
+ for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
|
|
|
+ if (links_reg & IXGBE_LINKS_UP) {
|
|
|
+ *link_up = true;
|
|
|
+ break;
|
|
|
+ } else {
|
|
|
+ *link_up = false;
|
|
|
+ }
|
|
|
+ msleep(100);
|
|
|
+ links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
|
|
|
+ }
|
|
|
+ } else {
|
|
|
+ if (links_reg & IXGBE_LINKS_UP)
|
|
|
+ *link_up = true;
|
|
|
+ else
|
|
|
+ *link_up = false;
|
|
|
+ }
|
|
|
+
|
|
|
+ if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
|
|
|
+ IXGBE_LINKS_SPEED_10G_82599)
|
|
|
+ *speed = IXGBE_LINK_SPEED_10GB_FULL;
|
|
|
+ else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
|
|
|
+ IXGBE_LINKS_SPEED_1G_82599)
|
|
|
+ *speed = IXGBE_LINK_SPEED_1GB_FULL;
|
|
|
+ else
|
|
|
+ *speed = IXGBE_LINK_SPEED_100_FULL;
|
|
|
+
|
|
|
+ /* if link is down, zero out the current_mode */
|
|
|
+ if (*link_up == false) {
|
|
|
+ hw->fc.current_mode = ixgbe_fc_none;
|
|
|
+ hw->fc.fc_was_autonegged = false;
|
|
|
+ }
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+/**
|
|
|
+ * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from
|
|
|
+ * the EEPROM
|
|
|
+ * @hw: pointer to hardware structure
|
|
|
+ * @wwnn_prefix: the alternative WWNN prefix
|
|
|
+ * @wwpn_prefix: the alternative WWPN prefix
|
|
|
+ *
|
|
|
+ * This function will read the EEPROM from the alternative SAN MAC address
|
|
|
+ * block to check the support for the alternative WWNN/WWPN prefix support.
|
|
|
+ **/
|
|
|
+s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
|
|
|
+ u16 *wwpn_prefix)
|
|
|
+{
|
|
|
+ u16 offset, caps;
|
|
|
+ u16 alt_san_mac_blk_offset;
|
|
|
+
|
|
|
+ /* clear output first */
|
|
|
+ *wwnn_prefix = 0xFFFF;
|
|
|
+ *wwpn_prefix = 0xFFFF;
|
|
|
+
|
|
|
+ /* check if alternative SAN MAC is supported */
|
|
|
+ hw->eeprom.ops.read(hw, IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR,
|
|
|
+ &alt_san_mac_blk_offset);
|
|
|
+
|
|
|
+ if ((alt_san_mac_blk_offset == 0) ||
|
|
|
+ (alt_san_mac_blk_offset == 0xFFFF))
|
|
|
+ goto wwn_prefix_out;
|
|
|
+
|
|
|
+ /* check capability in alternative san mac address block */
|
|
|
+ offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
|
|
|
+ hw->eeprom.ops.read(hw, offset, &caps);
|
|
|
+ if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
|
|
|
+ goto wwn_prefix_out;
|
|
|
+
|
|
|
+ /* get the corresponding prefix for WWNN/WWPN */
|
|
|
+ offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
|
|
|
+ hw->eeprom.ops.read(hw, offset, wwnn_prefix);
|
|
|
+
|
|
|
+ offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
|
|
|
+ hw->eeprom.ops.read(hw, offset, wwpn_prefix);
|
|
|
+
|
|
|
+wwn_prefix_out:
|
|
|
+ return 0;
|
|
|
+}
|
Mallikarjuna R Chilakala