bfin_mac.c 28 KB

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  1. /*
  2. * Blackfin On-Chip MAC Driver
  3. *
  4. * Copyright 2004-2007 Analog Devices Inc.
  5. *
  6. * Enter bugs at http://blackfin.uclinux.org/
  7. *
  8. * Licensed under the GPL-2 or later.
  9. */
  10. #include <linux/init.h>
  11. #include <linux/module.h>
  12. #include <linux/kernel.h>
  13. #include <linux/sched.h>
  14. #include <linux/slab.h>
  15. #include <linux/delay.h>
  16. #include <linux/timer.h>
  17. #include <linux/errno.h>
  18. #include <linux/irq.h>
  19. #include <linux/io.h>
  20. #include <linux/ioport.h>
  21. #include <linux/crc32.h>
  22. #include <linux/device.h>
  23. #include <linux/spinlock.h>
  24. #include <linux/mii.h>
  25. #include <linux/phy.h>
  26. #include <linux/netdevice.h>
  27. #include <linux/etherdevice.h>
  28. #include <linux/ethtool.h>
  29. #include <linux/skbuff.h>
  30. #include <linux/platform_device.h>
  31. #include <asm/dma.h>
  32. #include <linux/dma-mapping.h>
  33. #include <asm/dpmc.h>
  34. #include <asm/blackfin.h>
  35. #include <asm/cacheflush.h>
  36. #include <asm/portmux.h>
  37. #include "bfin_mac.h"
  38. #define DRV_NAME "bfin_mac"
  39. #define DRV_VERSION "1.1"
  40. #define DRV_AUTHOR "Bryan Wu, Luke Yang"
  41. #define DRV_DESC "Blackfin on-chip Ethernet MAC driver"
  42. MODULE_AUTHOR(DRV_AUTHOR);
  43. MODULE_LICENSE("GPL");
  44. MODULE_DESCRIPTION(DRV_DESC);
  45. MODULE_ALIAS("platform:bfin_mac");
  46. #if defined(CONFIG_BFIN_MAC_USE_L1)
  47. # define bfin_mac_alloc(dma_handle, size) l1_data_sram_zalloc(size)
  48. # define bfin_mac_free(dma_handle, ptr) l1_data_sram_free(ptr)
  49. #else
  50. # define bfin_mac_alloc(dma_handle, size) \
  51. dma_alloc_coherent(NULL, size, dma_handle, GFP_KERNEL)
  52. # define bfin_mac_free(dma_handle, ptr) \
  53. dma_free_coherent(NULL, sizeof(*ptr), ptr, dma_handle)
  54. #endif
  55. #define PKT_BUF_SZ 1580
  56. #define MAX_TIMEOUT_CNT 500
  57. /* pointers to maintain transmit list */
  58. static struct net_dma_desc_tx *tx_list_head;
  59. static struct net_dma_desc_tx *tx_list_tail;
  60. static struct net_dma_desc_rx *rx_list_head;
  61. static struct net_dma_desc_rx *rx_list_tail;
  62. static struct net_dma_desc_rx *current_rx_ptr;
  63. static struct net_dma_desc_tx *current_tx_ptr;
  64. static struct net_dma_desc_tx *tx_desc;
  65. static struct net_dma_desc_rx *rx_desc;
  66. #if defined(CONFIG_BFIN_MAC_RMII)
  67. static u16 pin_req[] = P_RMII0;
  68. #else
  69. static u16 pin_req[] = P_MII0;
  70. #endif
  71. static void bfin_mac_disable(void);
  72. static void bfin_mac_enable(void);
  73. static void desc_list_free(void)
  74. {
  75. struct net_dma_desc_rx *r;
  76. struct net_dma_desc_tx *t;
  77. int i;
  78. #if !defined(CONFIG_BFIN_MAC_USE_L1)
  79. dma_addr_t dma_handle = 0;
  80. #endif
  81. if (tx_desc) {
  82. t = tx_list_head;
  83. for (i = 0; i < CONFIG_BFIN_TX_DESC_NUM; i++) {
  84. if (t) {
  85. if (t->skb) {
  86. dev_kfree_skb(t->skb);
  87. t->skb = NULL;
  88. }
  89. t = t->next;
  90. }
  91. }
  92. bfin_mac_free(dma_handle, tx_desc);
  93. }
  94. if (rx_desc) {
  95. r = rx_list_head;
  96. for (i = 0; i < CONFIG_BFIN_RX_DESC_NUM; i++) {
  97. if (r) {
  98. if (r->skb) {
  99. dev_kfree_skb(r->skb);
  100. r->skb = NULL;
  101. }
  102. r = r->next;
  103. }
  104. }
  105. bfin_mac_free(dma_handle, rx_desc);
  106. }
  107. }
  108. static int desc_list_init(void)
  109. {
  110. int i;
  111. struct sk_buff *new_skb;
  112. #if !defined(CONFIG_BFIN_MAC_USE_L1)
  113. /*
  114. * This dma_handle is useless in Blackfin dma_alloc_coherent().
  115. * The real dma handler is the return value of dma_alloc_coherent().
  116. */
  117. dma_addr_t dma_handle;
  118. #endif
  119. tx_desc = bfin_mac_alloc(&dma_handle,
  120. sizeof(struct net_dma_desc_tx) *
  121. CONFIG_BFIN_TX_DESC_NUM);
  122. if (tx_desc == NULL)
  123. goto init_error;
  124. rx_desc = bfin_mac_alloc(&dma_handle,
  125. sizeof(struct net_dma_desc_rx) *
  126. CONFIG_BFIN_RX_DESC_NUM);
  127. if (rx_desc == NULL)
  128. goto init_error;
  129. /* init tx_list */
  130. tx_list_head = tx_list_tail = tx_desc;
  131. for (i = 0; i < CONFIG_BFIN_TX_DESC_NUM; i++) {
  132. struct net_dma_desc_tx *t = tx_desc + i;
  133. struct dma_descriptor *a = &(t->desc_a);
  134. struct dma_descriptor *b = &(t->desc_b);
  135. /*
  136. * disable DMA
  137. * read from memory WNR = 0
  138. * wordsize is 32 bits
  139. * 6 half words is desc size
  140. * large desc flow
  141. */
  142. a->config = WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE;
  143. a->start_addr = (unsigned long)t->packet;
  144. a->x_count = 0;
  145. a->next_dma_desc = b;
  146. /*
  147. * enabled DMA
  148. * write to memory WNR = 1
  149. * wordsize is 32 bits
  150. * disable interrupt
  151. * 6 half words is desc size
  152. * large desc flow
  153. */
  154. b->config = DMAEN | WNR | WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE;
  155. b->start_addr = (unsigned long)(&(t->status));
  156. b->x_count = 0;
  157. t->skb = NULL;
  158. tx_list_tail->desc_b.next_dma_desc = a;
  159. tx_list_tail->next = t;
  160. tx_list_tail = t;
  161. }
  162. tx_list_tail->next = tx_list_head; /* tx_list is a circle */
  163. tx_list_tail->desc_b.next_dma_desc = &(tx_list_head->desc_a);
  164. current_tx_ptr = tx_list_head;
  165. /* init rx_list */
  166. rx_list_head = rx_list_tail = rx_desc;
  167. for (i = 0; i < CONFIG_BFIN_RX_DESC_NUM; i++) {
  168. struct net_dma_desc_rx *r = rx_desc + i;
  169. struct dma_descriptor *a = &(r->desc_a);
  170. struct dma_descriptor *b = &(r->desc_b);
  171. /* allocate a new skb for next time receive */
  172. new_skb = dev_alloc_skb(PKT_BUF_SZ + NET_IP_ALIGN);
  173. if (!new_skb) {
  174. printk(KERN_NOTICE DRV_NAME
  175. ": init: low on mem - packet dropped\n");
  176. goto init_error;
  177. }
  178. skb_reserve(new_skb, NET_IP_ALIGN);
  179. r->skb = new_skb;
  180. /*
  181. * enabled DMA
  182. * write to memory WNR = 1
  183. * wordsize is 32 bits
  184. * disable interrupt
  185. * 6 half words is desc size
  186. * large desc flow
  187. */
  188. a->config = DMAEN | WNR | WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE;
  189. /* since RXDWA is enabled */
  190. a->start_addr = (unsigned long)new_skb->data - 2;
  191. a->x_count = 0;
  192. a->next_dma_desc = b;
  193. /*
  194. * enabled DMA
  195. * write to memory WNR = 1
  196. * wordsize is 32 bits
  197. * enable interrupt
  198. * 6 half words is desc size
  199. * large desc flow
  200. */
  201. b->config = DMAEN | WNR | WDSIZE_32 | DI_EN |
  202. NDSIZE_6 | DMAFLOW_LARGE;
  203. b->start_addr = (unsigned long)(&(r->status));
  204. b->x_count = 0;
  205. rx_list_tail->desc_b.next_dma_desc = a;
  206. rx_list_tail->next = r;
  207. rx_list_tail = r;
  208. }
  209. rx_list_tail->next = rx_list_head; /* rx_list is a circle */
  210. rx_list_tail->desc_b.next_dma_desc = &(rx_list_head->desc_a);
  211. current_rx_ptr = rx_list_head;
  212. return 0;
  213. init_error:
  214. desc_list_free();
  215. printk(KERN_ERR DRV_NAME ": kmalloc failed\n");
  216. return -ENOMEM;
  217. }
  218. /*---PHY CONTROL AND CONFIGURATION-----------------------------------------*/
  219. /*
  220. * MII operations
  221. */
  222. /* Wait until the previous MDC/MDIO transaction has completed */
  223. static void bfin_mdio_poll(void)
  224. {
  225. int timeout_cnt = MAX_TIMEOUT_CNT;
  226. /* poll the STABUSY bit */
  227. while ((bfin_read_EMAC_STAADD()) & STABUSY) {
  228. udelay(1);
  229. if (timeout_cnt-- < 0) {
  230. printk(KERN_ERR DRV_NAME
  231. ": wait MDC/MDIO transaction to complete timeout\n");
  232. break;
  233. }
  234. }
  235. }
  236. /* Read an off-chip register in a PHY through the MDC/MDIO port */
  237. static int bfin_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
  238. {
  239. bfin_mdio_poll();
  240. /* read mode */
  241. bfin_write_EMAC_STAADD(SET_PHYAD((u16) phy_addr) |
  242. SET_REGAD((u16) regnum) |
  243. STABUSY);
  244. bfin_mdio_poll();
  245. return (int) bfin_read_EMAC_STADAT();
  246. }
  247. /* Write an off-chip register in a PHY through the MDC/MDIO port */
  248. static int bfin_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum,
  249. u16 value)
  250. {
  251. bfin_mdio_poll();
  252. bfin_write_EMAC_STADAT((u32) value);
  253. /* write mode */
  254. bfin_write_EMAC_STAADD(SET_PHYAD((u16) phy_addr) |
  255. SET_REGAD((u16) regnum) |
  256. STAOP |
  257. STABUSY);
  258. bfin_mdio_poll();
  259. return 0;
  260. }
  261. static int bfin_mdiobus_reset(struct mii_bus *bus)
  262. {
  263. return 0;
  264. }
  265. static void bfin_mac_adjust_link(struct net_device *dev)
  266. {
  267. struct bfin_mac_local *lp = netdev_priv(dev);
  268. struct phy_device *phydev = lp->phydev;
  269. unsigned long flags;
  270. int new_state = 0;
  271. spin_lock_irqsave(&lp->lock, flags);
  272. if (phydev->link) {
  273. /* Now we make sure that we can be in full duplex mode.
  274. * If not, we operate in half-duplex mode. */
  275. if (phydev->duplex != lp->old_duplex) {
  276. u32 opmode = bfin_read_EMAC_OPMODE();
  277. new_state = 1;
  278. if (phydev->duplex)
  279. opmode |= FDMODE;
  280. else
  281. opmode &= ~(FDMODE);
  282. bfin_write_EMAC_OPMODE(opmode);
  283. lp->old_duplex = phydev->duplex;
  284. }
  285. if (phydev->speed != lp->old_speed) {
  286. #if defined(CONFIG_BFIN_MAC_RMII)
  287. u32 opmode = bfin_read_EMAC_OPMODE();
  288. switch (phydev->speed) {
  289. case 10:
  290. opmode |= RMII_10;
  291. break;
  292. case 100:
  293. opmode &= ~(RMII_10);
  294. break;
  295. default:
  296. printk(KERN_WARNING
  297. "%s: Ack! Speed (%d) is not 10/100!\n",
  298. DRV_NAME, phydev->speed);
  299. break;
  300. }
  301. bfin_write_EMAC_OPMODE(opmode);
  302. #endif
  303. new_state = 1;
  304. lp->old_speed = phydev->speed;
  305. }
  306. if (!lp->old_link) {
  307. new_state = 1;
  308. lp->old_link = 1;
  309. }
  310. } else if (lp->old_link) {
  311. new_state = 1;
  312. lp->old_link = 0;
  313. lp->old_speed = 0;
  314. lp->old_duplex = -1;
  315. }
  316. if (new_state) {
  317. u32 opmode = bfin_read_EMAC_OPMODE();
  318. phy_print_status(phydev);
  319. pr_debug("EMAC_OPMODE = 0x%08x\n", opmode);
  320. }
  321. spin_unlock_irqrestore(&lp->lock, flags);
  322. }
  323. /* MDC = 2.5 MHz */
  324. #define MDC_CLK 2500000
  325. static int mii_probe(struct net_device *dev)
  326. {
  327. struct bfin_mac_local *lp = netdev_priv(dev);
  328. struct phy_device *phydev = NULL;
  329. unsigned short sysctl;
  330. int i;
  331. u32 sclk, mdc_div;
  332. /* Enable PHY output early */
  333. if (!(bfin_read_VR_CTL() & CLKBUFOE))
  334. bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE);
  335. sclk = get_sclk();
  336. mdc_div = ((sclk / MDC_CLK) / 2) - 1;
  337. sysctl = bfin_read_EMAC_SYSCTL();
  338. sysctl = (sysctl & ~MDCDIV) | SET_MDCDIV(mdc_div);
  339. bfin_write_EMAC_SYSCTL(sysctl);
  340. /* search for connect PHY device */
  341. for (i = 0; i < PHY_MAX_ADDR; i++) {
  342. struct phy_device *const tmp_phydev = lp->mii_bus->phy_map[i];
  343. if (!tmp_phydev)
  344. continue; /* no PHY here... */
  345. phydev = tmp_phydev;
  346. break; /* found it */
  347. }
  348. /* now we are supposed to have a proper phydev, to attach to... */
  349. if (!phydev) {
  350. printk(KERN_INFO "%s: Don't found any phy device at all\n",
  351. dev->name);
  352. return -ENODEV;
  353. }
  354. #if defined(CONFIG_BFIN_MAC_RMII)
  355. phydev = phy_connect(dev, dev_name(&phydev->dev), &bfin_mac_adjust_link,
  356. 0, PHY_INTERFACE_MODE_RMII);
  357. #else
  358. phydev = phy_connect(dev, dev_name(&phydev->dev), &bfin_mac_adjust_link,
  359. 0, PHY_INTERFACE_MODE_MII);
  360. #endif
  361. if (IS_ERR(phydev)) {
  362. printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
  363. return PTR_ERR(phydev);
  364. }
  365. /* mask with MAC supported features */
  366. phydev->supported &= (SUPPORTED_10baseT_Half
  367. | SUPPORTED_10baseT_Full
  368. | SUPPORTED_100baseT_Half
  369. | SUPPORTED_100baseT_Full
  370. | SUPPORTED_Autoneg
  371. | SUPPORTED_Pause | SUPPORTED_Asym_Pause
  372. | SUPPORTED_MII
  373. | SUPPORTED_TP);
  374. phydev->advertising = phydev->supported;
  375. lp->old_link = 0;
  376. lp->old_speed = 0;
  377. lp->old_duplex = -1;
  378. lp->phydev = phydev;
  379. printk(KERN_INFO "%s: attached PHY driver [%s] "
  380. "(mii_bus:phy_addr=%s, irq=%d, mdc_clk=%dHz(mdc_div=%d)"
  381. "@sclk=%dMHz)\n",
  382. DRV_NAME, phydev->drv->name, dev_name(&phydev->dev), phydev->irq,
  383. MDC_CLK, mdc_div, sclk/1000000);
  384. return 0;
  385. }
  386. /*
  387. * Ethtool support
  388. */
  389. static int
  390. bfin_mac_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd)
  391. {
  392. struct bfin_mac_local *lp = netdev_priv(dev);
  393. if (lp->phydev)
  394. return phy_ethtool_gset(lp->phydev, cmd);
  395. return -EINVAL;
  396. }
  397. static int
  398. bfin_mac_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd)
  399. {
  400. struct bfin_mac_local *lp = netdev_priv(dev);
  401. if (!capable(CAP_NET_ADMIN))
  402. return -EPERM;
  403. if (lp->phydev)
  404. return phy_ethtool_sset(lp->phydev, cmd);
  405. return -EINVAL;
  406. }
  407. static void bfin_mac_ethtool_getdrvinfo(struct net_device *dev,
  408. struct ethtool_drvinfo *info)
  409. {
  410. strcpy(info->driver, DRV_NAME);
  411. strcpy(info->version, DRV_VERSION);
  412. strcpy(info->fw_version, "N/A");
  413. strcpy(info->bus_info, dev_name(&dev->dev));
  414. }
  415. static const struct ethtool_ops bfin_mac_ethtool_ops = {
  416. .get_settings = bfin_mac_ethtool_getsettings,
  417. .set_settings = bfin_mac_ethtool_setsettings,
  418. .get_link = ethtool_op_get_link,
  419. .get_drvinfo = bfin_mac_ethtool_getdrvinfo,
  420. };
  421. /**************************************************************************/
  422. void setup_system_regs(struct net_device *dev)
  423. {
  424. unsigned short sysctl;
  425. /*
  426. * Odd word alignment for Receive Frame DMA word
  427. * Configure checksum support and rcve frame word alignment
  428. */
  429. sysctl = bfin_read_EMAC_SYSCTL();
  430. #if defined(BFIN_MAC_CSUM_OFFLOAD)
  431. sysctl |= RXDWA | RXCKS;
  432. #else
  433. sysctl |= RXDWA;
  434. #endif
  435. bfin_write_EMAC_SYSCTL(sysctl);
  436. bfin_write_EMAC_MMC_CTL(RSTC | CROLL);
  437. /* Initialize the TX DMA channel registers */
  438. bfin_write_DMA2_X_COUNT(0);
  439. bfin_write_DMA2_X_MODIFY(4);
  440. bfin_write_DMA2_Y_COUNT(0);
  441. bfin_write_DMA2_Y_MODIFY(0);
  442. /* Initialize the RX DMA channel registers */
  443. bfin_write_DMA1_X_COUNT(0);
  444. bfin_write_DMA1_X_MODIFY(4);
  445. bfin_write_DMA1_Y_COUNT(0);
  446. bfin_write_DMA1_Y_MODIFY(0);
  447. }
  448. static void setup_mac_addr(u8 *mac_addr)
  449. {
  450. u32 addr_low = le32_to_cpu(*(__le32 *) & mac_addr[0]);
  451. u16 addr_hi = le16_to_cpu(*(__le16 *) & mac_addr[4]);
  452. /* this depends on a little-endian machine */
  453. bfin_write_EMAC_ADDRLO(addr_low);
  454. bfin_write_EMAC_ADDRHI(addr_hi);
  455. }
  456. static int bfin_mac_set_mac_address(struct net_device *dev, void *p)
  457. {
  458. struct sockaddr *addr = p;
  459. if (netif_running(dev))
  460. return -EBUSY;
  461. memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
  462. setup_mac_addr(dev->dev_addr);
  463. return 0;
  464. }
  465. static void adjust_tx_list(void)
  466. {
  467. int timeout_cnt = MAX_TIMEOUT_CNT;
  468. if (tx_list_head->status.status_word != 0 &&
  469. current_tx_ptr != tx_list_head) {
  470. goto adjust_head; /* released something, just return; */
  471. }
  472. /*
  473. * if nothing released, check wait condition
  474. * current's next can not be the head,
  475. * otherwise the dma will not stop as we want
  476. */
  477. if (current_tx_ptr->next->next == tx_list_head) {
  478. while (tx_list_head->status.status_word == 0) {
  479. udelay(10);
  480. if (tx_list_head->status.status_word != 0 ||
  481. !(bfin_read_DMA2_IRQ_STATUS() & DMA_RUN)) {
  482. goto adjust_head;
  483. }
  484. if (timeout_cnt-- < 0) {
  485. printk(KERN_ERR DRV_NAME
  486. ": wait for adjust tx list head timeout\n");
  487. break;
  488. }
  489. }
  490. if (tx_list_head->status.status_word != 0) {
  491. goto adjust_head;
  492. }
  493. }
  494. return;
  495. adjust_head:
  496. do {
  497. tx_list_head->desc_a.config &= ~DMAEN;
  498. tx_list_head->status.status_word = 0;
  499. if (tx_list_head->skb) {
  500. dev_kfree_skb(tx_list_head->skb);
  501. tx_list_head->skb = NULL;
  502. } else {
  503. printk(KERN_ERR DRV_NAME
  504. ": no sk_buff in a transmitted frame!\n");
  505. }
  506. tx_list_head = tx_list_head->next;
  507. } while (tx_list_head->status.status_word != 0 &&
  508. current_tx_ptr != tx_list_head);
  509. return;
  510. }
  511. static int bfin_mac_hard_start_xmit(struct sk_buff *skb,
  512. struct net_device *dev)
  513. {
  514. u16 *data;
  515. u32 data_align = (unsigned long)(skb->data) & 0x3;
  516. current_tx_ptr->skb = skb;
  517. if (data_align == 0x2) {
  518. /* move skb->data to current_tx_ptr payload */
  519. data = (u16 *)(skb->data) - 1;
  520. *data = (u16)(skb->len);
  521. current_tx_ptr->desc_a.start_addr = (u32)data;
  522. /* this is important! */
  523. blackfin_dcache_flush_range((u32)data,
  524. (u32)((u8 *)data + skb->len + 4));
  525. } else {
  526. *((u16 *)(current_tx_ptr->packet)) = (u16)(skb->len);
  527. memcpy((u8 *)(current_tx_ptr->packet + 2), skb->data,
  528. skb->len);
  529. current_tx_ptr->desc_a.start_addr =
  530. (u32)current_tx_ptr->packet;
  531. if (current_tx_ptr->status.status_word != 0)
  532. current_tx_ptr->status.status_word = 0;
  533. blackfin_dcache_flush_range(
  534. (u32)current_tx_ptr->packet,
  535. (u32)(current_tx_ptr->packet + skb->len + 2));
  536. }
  537. /* make sure the internal data buffers in the core are drained
  538. * so that the DMA descriptors are completely written when the
  539. * DMA engine goes to fetch them below
  540. */
  541. SSYNC();
  542. /* enable this packet's dma */
  543. current_tx_ptr->desc_a.config |= DMAEN;
  544. /* tx dma is running, just return */
  545. if (bfin_read_DMA2_IRQ_STATUS() & DMA_RUN)
  546. goto out;
  547. /* tx dma is not running */
  548. bfin_write_DMA2_NEXT_DESC_PTR(&(current_tx_ptr->desc_a));
  549. /* dma enabled, read from memory, size is 6 */
  550. bfin_write_DMA2_CONFIG(current_tx_ptr->desc_a.config);
  551. /* Turn on the EMAC tx */
  552. bfin_write_EMAC_OPMODE(bfin_read_EMAC_OPMODE() | TE);
  553. out:
  554. adjust_tx_list();
  555. current_tx_ptr = current_tx_ptr->next;
  556. dev->stats.tx_packets++;
  557. dev->stats.tx_bytes += (skb->len);
  558. return NETDEV_TX_OK;
  559. }
  560. static void bfin_mac_rx(struct net_device *dev)
  561. {
  562. struct sk_buff *skb, *new_skb;
  563. unsigned short len;
  564. /* allocate a new skb for next time receive */
  565. skb = current_rx_ptr->skb;
  566. new_skb = dev_alloc_skb(PKT_BUF_SZ + NET_IP_ALIGN);
  567. if (!new_skb) {
  568. printk(KERN_NOTICE DRV_NAME
  569. ": rx: low on mem - packet dropped\n");
  570. dev->stats.rx_dropped++;
  571. goto out;
  572. }
  573. /* reserve 2 bytes for RXDWA padding */
  574. skb_reserve(new_skb, NET_IP_ALIGN);
  575. current_rx_ptr->skb = new_skb;
  576. current_rx_ptr->desc_a.start_addr = (unsigned long)new_skb->data - 2;
  577. /* Invidate the data cache of skb->data range when it is write back
  578. * cache. It will prevent overwritting the new data from DMA
  579. */
  580. blackfin_dcache_invalidate_range((unsigned long)new_skb->head,
  581. (unsigned long)new_skb->end);
  582. len = (unsigned short)((current_rx_ptr->status.status_word) & RX_FRLEN);
  583. skb_put(skb, len);
  584. blackfin_dcache_invalidate_range((unsigned long)skb->head,
  585. (unsigned long)skb->tail);
  586. skb->protocol = eth_type_trans(skb, dev);
  587. #if defined(BFIN_MAC_CSUM_OFFLOAD)
  588. skb->csum = current_rx_ptr->status.ip_payload_csum;
  589. skb->ip_summed = CHECKSUM_COMPLETE;
  590. #endif
  591. netif_rx(skb);
  592. dev->stats.rx_packets++;
  593. dev->stats.rx_bytes += len;
  594. current_rx_ptr->status.status_word = 0x00000000;
  595. current_rx_ptr = current_rx_ptr->next;
  596. out:
  597. return;
  598. }
  599. /* interrupt routine to handle rx and error signal */
  600. static irqreturn_t bfin_mac_interrupt(int irq, void *dev_id)
  601. {
  602. struct net_device *dev = dev_id;
  603. int number = 0;
  604. get_one_packet:
  605. if (current_rx_ptr->status.status_word == 0) {
  606. /* no more new packet received */
  607. if (number == 0) {
  608. if (current_rx_ptr->next->status.status_word != 0) {
  609. current_rx_ptr = current_rx_ptr->next;
  610. goto real_rx;
  611. }
  612. }
  613. bfin_write_DMA1_IRQ_STATUS(bfin_read_DMA1_IRQ_STATUS() |
  614. DMA_DONE | DMA_ERR);
  615. return IRQ_HANDLED;
  616. }
  617. real_rx:
  618. bfin_mac_rx(dev);
  619. number++;
  620. goto get_one_packet;
  621. }
  622. #ifdef CONFIG_NET_POLL_CONTROLLER
  623. static void bfin_mac_poll(struct net_device *dev)
  624. {
  625. disable_irq(IRQ_MAC_RX);
  626. bfin_mac_interrupt(IRQ_MAC_RX, dev);
  627. enable_irq(IRQ_MAC_RX);
  628. }
  629. #endif /* CONFIG_NET_POLL_CONTROLLER */
  630. static void bfin_mac_disable(void)
  631. {
  632. unsigned int opmode;
  633. opmode = bfin_read_EMAC_OPMODE();
  634. opmode &= (~RE);
  635. opmode &= (~TE);
  636. /* Turn off the EMAC */
  637. bfin_write_EMAC_OPMODE(opmode);
  638. }
  639. /*
  640. * Enable Interrupts, Receive, and Transmit
  641. */
  642. static void bfin_mac_enable(void)
  643. {
  644. u32 opmode;
  645. pr_debug("%s: %s\n", DRV_NAME, __func__);
  646. /* Set RX DMA */
  647. bfin_write_DMA1_NEXT_DESC_PTR(&(rx_list_head->desc_a));
  648. bfin_write_DMA1_CONFIG(rx_list_head->desc_a.config);
  649. /* Wait MII done */
  650. bfin_mdio_poll();
  651. /* We enable only RX here */
  652. /* ASTP : Enable Automatic Pad Stripping
  653. PR : Promiscuous Mode for test
  654. PSF : Receive frames with total length less than 64 bytes.
  655. FDMODE : Full Duplex Mode
  656. LB : Internal Loopback for test
  657. RE : Receiver Enable */
  658. opmode = bfin_read_EMAC_OPMODE();
  659. if (opmode & FDMODE)
  660. opmode |= PSF;
  661. else
  662. opmode |= DRO | DC | PSF;
  663. opmode |= RE;
  664. #if defined(CONFIG_BFIN_MAC_RMII)
  665. opmode |= RMII; /* For Now only 100MBit are supported */
  666. #if (defined(CONFIG_BF537) || defined(CONFIG_BF536)) && CONFIG_BF_REV_0_2
  667. opmode |= TE;
  668. #endif
  669. #endif
  670. /* Turn on the EMAC rx */
  671. bfin_write_EMAC_OPMODE(opmode);
  672. }
  673. /* Our watchdog timed out. Called by the networking layer */
  674. static void bfin_mac_timeout(struct net_device *dev)
  675. {
  676. pr_debug("%s: %s\n", dev->name, __func__);
  677. bfin_mac_disable();
  678. /* reset tx queue */
  679. tx_list_tail = tx_list_head->next;
  680. bfin_mac_enable();
  681. /* We can accept TX packets again */
  682. dev->trans_start = jiffies; /* prevent tx timeout */
  683. netif_wake_queue(dev);
  684. }
  685. static void bfin_mac_multicast_hash(struct net_device *dev)
  686. {
  687. u32 emac_hashhi, emac_hashlo;
  688. struct netdev_hw_addr *ha;
  689. char *addrs;
  690. u32 crc;
  691. emac_hashhi = emac_hashlo = 0;
  692. netdev_for_each_mc_addr(ha, dev) {
  693. addrs = ha->addr;
  694. /* skip non-multicast addresses */
  695. if (!(*addrs & 1))
  696. continue;
  697. crc = ether_crc(ETH_ALEN, addrs);
  698. crc >>= 26;
  699. if (crc & 0x20)
  700. emac_hashhi |= 1 << (crc & 0x1f);
  701. else
  702. emac_hashlo |= 1 << (crc & 0x1f);
  703. }
  704. bfin_write_EMAC_HASHHI(emac_hashhi);
  705. bfin_write_EMAC_HASHLO(emac_hashlo);
  706. }
  707. /*
  708. * This routine will, depending on the values passed to it,
  709. * either make it accept multicast packets, go into
  710. * promiscuous mode (for TCPDUMP and cousins) or accept
  711. * a select set of multicast packets
  712. */
  713. static void bfin_mac_set_multicast_list(struct net_device *dev)
  714. {
  715. u32 sysctl;
  716. if (dev->flags & IFF_PROMISC) {
  717. printk(KERN_INFO "%s: set to promisc mode\n", dev->name);
  718. sysctl = bfin_read_EMAC_OPMODE();
  719. sysctl |= RAF;
  720. bfin_write_EMAC_OPMODE(sysctl);
  721. } else if (dev->flags & IFF_ALLMULTI) {
  722. /* accept all multicast */
  723. sysctl = bfin_read_EMAC_OPMODE();
  724. sysctl |= PAM;
  725. bfin_write_EMAC_OPMODE(sysctl);
  726. } else if (!netdev_mc_empty(dev)) {
  727. /* set up multicast hash table */
  728. sysctl = bfin_read_EMAC_OPMODE();
  729. sysctl |= HM;
  730. bfin_write_EMAC_OPMODE(sysctl);
  731. bfin_mac_multicast_hash(dev);
  732. } else {
  733. /* clear promisc or multicast mode */
  734. sysctl = bfin_read_EMAC_OPMODE();
  735. sysctl &= ~(RAF | PAM);
  736. bfin_write_EMAC_OPMODE(sysctl);
  737. }
  738. }
  739. /*
  740. * this puts the device in an inactive state
  741. */
  742. static void bfin_mac_shutdown(struct net_device *dev)
  743. {
  744. /* Turn off the EMAC */
  745. bfin_write_EMAC_OPMODE(0x00000000);
  746. /* Turn off the EMAC RX DMA */
  747. bfin_write_DMA1_CONFIG(0x0000);
  748. bfin_write_DMA2_CONFIG(0x0000);
  749. }
  750. /*
  751. * Open and Initialize the interface
  752. *
  753. * Set up everything, reset the card, etc..
  754. */
  755. static int bfin_mac_open(struct net_device *dev)
  756. {
  757. struct bfin_mac_local *lp = netdev_priv(dev);
  758. int retval;
  759. pr_debug("%s: %s\n", dev->name, __func__);
  760. /*
  761. * Check that the address is valid. If its not, refuse
  762. * to bring the device up. The user must specify an
  763. * address using ifconfig eth0 hw ether xx:xx:xx:xx:xx:xx
  764. */
  765. if (!is_valid_ether_addr(dev->dev_addr)) {
  766. printk(KERN_WARNING DRV_NAME ": no valid ethernet hw addr\n");
  767. return -EINVAL;
  768. }
  769. /* initial rx and tx list */
  770. retval = desc_list_init();
  771. if (retval)
  772. return retval;
  773. phy_start(lp->phydev);
  774. phy_write(lp->phydev, MII_BMCR, BMCR_RESET);
  775. setup_system_regs(dev);
  776. setup_mac_addr(dev->dev_addr);
  777. bfin_mac_disable();
  778. bfin_mac_enable();
  779. pr_debug("hardware init finished\n");
  780. netif_start_queue(dev);
  781. netif_carrier_on(dev);
  782. return 0;
  783. }
  784. /*
  785. * this makes the board clean up everything that it can
  786. * and not talk to the outside world. Caused by
  787. * an 'ifconfig ethX down'
  788. */
  789. static int bfin_mac_close(struct net_device *dev)
  790. {
  791. struct bfin_mac_local *lp = netdev_priv(dev);
  792. pr_debug("%s: %s\n", dev->name, __func__);
  793. netif_stop_queue(dev);
  794. netif_carrier_off(dev);
  795. phy_stop(lp->phydev);
  796. phy_write(lp->phydev, MII_BMCR, BMCR_PDOWN);
  797. /* clear everything */
  798. bfin_mac_shutdown(dev);
  799. /* free the rx/tx buffers */
  800. desc_list_free();
  801. return 0;
  802. }
  803. static const struct net_device_ops bfin_mac_netdev_ops = {
  804. .ndo_open = bfin_mac_open,
  805. .ndo_stop = bfin_mac_close,
  806. .ndo_start_xmit = bfin_mac_hard_start_xmit,
  807. .ndo_set_mac_address = bfin_mac_set_mac_address,
  808. .ndo_tx_timeout = bfin_mac_timeout,
  809. .ndo_set_multicast_list = bfin_mac_set_multicast_list,
  810. .ndo_validate_addr = eth_validate_addr,
  811. .ndo_change_mtu = eth_change_mtu,
  812. #ifdef CONFIG_NET_POLL_CONTROLLER
  813. .ndo_poll_controller = bfin_mac_poll,
  814. #endif
  815. };
  816. static int __devinit bfin_mac_probe(struct platform_device *pdev)
  817. {
  818. struct net_device *ndev;
  819. struct bfin_mac_local *lp;
  820. struct platform_device *pd;
  821. int rc;
  822. ndev = alloc_etherdev(sizeof(struct bfin_mac_local));
  823. if (!ndev) {
  824. dev_err(&pdev->dev, "Cannot allocate net device!\n");
  825. return -ENOMEM;
  826. }
  827. SET_NETDEV_DEV(ndev, &pdev->dev);
  828. platform_set_drvdata(pdev, ndev);
  829. lp = netdev_priv(ndev);
  830. /* Grab the MAC address in the MAC */
  831. *(__le32 *) (&(ndev->dev_addr[0])) = cpu_to_le32(bfin_read_EMAC_ADDRLO());
  832. *(__le16 *) (&(ndev->dev_addr[4])) = cpu_to_le16((u16) bfin_read_EMAC_ADDRHI());
  833. /* probe mac */
  834. /*todo: how to proble? which is revision_register */
  835. bfin_write_EMAC_ADDRLO(0x12345678);
  836. if (bfin_read_EMAC_ADDRLO() != 0x12345678) {
  837. dev_err(&pdev->dev, "Cannot detect Blackfin on-chip ethernet MAC controller!\n");
  838. rc = -ENODEV;
  839. goto out_err_probe_mac;
  840. }
  841. /*
  842. * Is it valid? (Did bootloader initialize it?)
  843. * Grab the MAC from the board somehow
  844. * this is done in the arch/blackfin/mach-bfxxx/boards/eth_mac.c
  845. */
  846. if (!is_valid_ether_addr(ndev->dev_addr))
  847. bfin_get_ether_addr(ndev->dev_addr);
  848. /* If still not valid, get a random one */
  849. if (!is_valid_ether_addr(ndev->dev_addr))
  850. random_ether_addr(ndev->dev_addr);
  851. setup_mac_addr(ndev->dev_addr);
  852. if (!pdev->dev.platform_data) {
  853. dev_err(&pdev->dev, "Cannot get platform device bfin_mii_bus!\n");
  854. rc = -ENODEV;
  855. goto out_err_probe_mac;
  856. }
  857. pd = pdev->dev.platform_data;
  858. lp->mii_bus = platform_get_drvdata(pd);
  859. lp->mii_bus->priv = ndev;
  860. rc = mii_probe(ndev);
  861. if (rc) {
  862. dev_err(&pdev->dev, "MII Probe failed!\n");
  863. goto out_err_mii_probe;
  864. }
  865. /* Fill in the fields of the device structure with ethernet values. */
  866. ether_setup(ndev);
  867. ndev->netdev_ops = &bfin_mac_netdev_ops;
  868. ndev->ethtool_ops = &bfin_mac_ethtool_ops;
  869. spin_lock_init(&lp->lock);
  870. /* now, enable interrupts */
  871. /* register irq handler */
  872. rc = request_irq(IRQ_MAC_RX, bfin_mac_interrupt,
  873. IRQF_DISABLED, "EMAC_RX", ndev);
  874. if (rc) {
  875. dev_err(&pdev->dev, "Cannot request Blackfin MAC RX IRQ!\n");
  876. rc = -EBUSY;
  877. goto out_err_request_irq;
  878. }
  879. rc = register_netdev(ndev);
  880. if (rc) {
  881. dev_err(&pdev->dev, "Cannot register net device!\n");
  882. goto out_err_reg_ndev;
  883. }
  884. /* now, print out the card info, in a short format.. */
  885. dev_info(&pdev->dev, "%s, Version %s\n", DRV_DESC, DRV_VERSION);
  886. return 0;
  887. out_err_reg_ndev:
  888. free_irq(IRQ_MAC_RX, ndev);
  889. out_err_request_irq:
  890. out_err_mii_probe:
  891. mdiobus_unregister(lp->mii_bus);
  892. mdiobus_free(lp->mii_bus);
  893. peripheral_free_list(pin_req);
  894. out_err_probe_mac:
  895. platform_set_drvdata(pdev, NULL);
  896. free_netdev(ndev);
  897. return rc;
  898. }
  899. static int __devexit bfin_mac_remove(struct platform_device *pdev)
  900. {
  901. struct net_device *ndev = platform_get_drvdata(pdev);
  902. struct bfin_mac_local *lp = netdev_priv(ndev);
  903. platform_set_drvdata(pdev, NULL);
  904. lp->mii_bus->priv = NULL;
  905. unregister_netdev(ndev);
  906. free_irq(IRQ_MAC_RX, ndev);
  907. free_netdev(ndev);
  908. peripheral_free_list(pin_req);
  909. return 0;
  910. }
  911. #ifdef CONFIG_PM
  912. static int bfin_mac_suspend(struct platform_device *pdev, pm_message_t mesg)
  913. {
  914. struct net_device *net_dev = platform_get_drvdata(pdev);
  915. if (netif_running(net_dev))
  916. bfin_mac_close(net_dev);
  917. return 0;
  918. }
  919. static int bfin_mac_resume(struct platform_device *pdev)
  920. {
  921. struct net_device *net_dev = platform_get_drvdata(pdev);
  922. if (netif_running(net_dev))
  923. bfin_mac_open(net_dev);
  924. return 0;
  925. }
  926. #else
  927. #define bfin_mac_suspend NULL
  928. #define bfin_mac_resume NULL
  929. #endif /* CONFIG_PM */
  930. static int __devinit bfin_mii_bus_probe(struct platform_device *pdev)
  931. {
  932. struct mii_bus *miibus;
  933. int rc, i;
  934. /*
  935. * We are setting up a network card,
  936. * so set the GPIO pins to Ethernet mode
  937. */
  938. rc = peripheral_request_list(pin_req, DRV_NAME);
  939. if (rc) {
  940. dev_err(&pdev->dev, "Requesting peripherals failed!\n");
  941. return rc;
  942. }
  943. rc = -ENOMEM;
  944. miibus = mdiobus_alloc();
  945. if (miibus == NULL)
  946. goto out_err_alloc;
  947. miibus->read = bfin_mdiobus_read;
  948. miibus->write = bfin_mdiobus_write;
  949. miibus->reset = bfin_mdiobus_reset;
  950. miibus->parent = &pdev->dev;
  951. miibus->name = "bfin_mii_bus";
  952. snprintf(miibus->id, MII_BUS_ID_SIZE, "0");
  953. miibus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
  954. if (miibus->irq == NULL)
  955. goto out_err_alloc;
  956. for (i = 0; i < PHY_MAX_ADDR; ++i)
  957. miibus->irq[i] = PHY_POLL;
  958. rc = mdiobus_register(miibus);
  959. if (rc) {
  960. dev_err(&pdev->dev, "Cannot register MDIO bus!\n");
  961. goto out_err_mdiobus_register;
  962. }
  963. platform_set_drvdata(pdev, miibus);
  964. return 0;
  965. out_err_mdiobus_register:
  966. mdiobus_free(miibus);
  967. out_err_alloc:
  968. peripheral_free_list(pin_req);
  969. return rc;
  970. }
  971. static int __devexit bfin_mii_bus_remove(struct platform_device *pdev)
  972. {
  973. struct mii_bus *miibus = platform_get_drvdata(pdev);
  974. platform_set_drvdata(pdev, NULL);
  975. mdiobus_unregister(miibus);
  976. mdiobus_free(miibus);
  977. peripheral_free_list(pin_req);
  978. return 0;
  979. }
  980. static struct platform_driver bfin_mii_bus_driver = {
  981. .probe = bfin_mii_bus_probe,
  982. .remove = __devexit_p(bfin_mii_bus_remove),
  983. .driver = {
  984. .name = "bfin_mii_bus",
  985. .owner = THIS_MODULE,
  986. },
  987. };
  988. static struct platform_driver bfin_mac_driver = {
  989. .probe = bfin_mac_probe,
  990. .remove = __devexit_p(bfin_mac_remove),
  991. .resume = bfin_mac_resume,
  992. .suspend = bfin_mac_suspend,
  993. .driver = {
  994. .name = DRV_NAME,
  995. .owner = THIS_MODULE,
  996. },
  997. };
  998. static int __init bfin_mac_init(void)
  999. {
  1000. int ret;
  1001. ret = platform_driver_register(&bfin_mii_bus_driver);
  1002. if (!ret)
  1003. return platform_driver_register(&bfin_mac_driver);
  1004. return -ENODEV;
  1005. }
  1006. module_init(bfin_mac_init);
  1007. static void __exit bfin_mac_cleanup(void)
  1008. {
  1009. platform_driver_unregister(&bfin_mac_driver);
  1010. platform_driver_unregister(&bfin_mii_bus_driver);
  1011. }
  1012. module_exit(bfin_mac_cleanup);