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@@ -261,7 +261,6 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = {
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* efuse_ctrl_cust
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* efuse_ctrl_std
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* elm
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- * gpu
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* mcasp
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* mpu_c0
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* mpu_c1
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@@ -1167,6 +1166,47 @@ static struct omap_hwmod omap44xx_gpmc_hwmod = {
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},
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};
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+/*
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+ * 'gpu' class
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+ * 2d/3d graphics accelerator
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+ */
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+
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+static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = {
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+ .rev_offs = 0x1fc00,
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+ .sysc_offs = 0x1fc10,
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+ .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
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+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
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+ SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
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+ MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
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+ .sysc_fields = &omap_hwmod_sysc_type2,
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+};
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+
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+static struct omap_hwmod_class omap44xx_gpu_hwmod_class = {
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+ .name = "gpu",
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+ .sysc = &omap44xx_gpu_sysc,
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+};
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+
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+/* gpu */
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+static struct omap_hwmod_irq_info omap44xx_gpu_irqs[] = {
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+ { .irq = 21 + OMAP44XX_IRQ_GIC_START },
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+ { .irq = -1 }
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+};
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+
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+static struct omap_hwmod omap44xx_gpu_hwmod = {
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+ .name = "gpu",
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+ .class = &omap44xx_gpu_hwmod_class,
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+ .clkdm_name = "l3_gfx_clkdm",
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+ .mpu_irqs = omap44xx_gpu_irqs,
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+ .main_clk = "gpu_fck",
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+ .prcm = {
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+ .omap4 = {
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+ .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET,
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+ .context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET,
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+ .modulemode = MODULEMODE_SWCTRL,
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+ },
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+ },
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+};
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+
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/*
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* 'hdq1w' class
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* hdq / 1-wire serial interface controller
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@@ -3179,6 +3219,14 @@ static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = {
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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+/* gpu -> l3_main_2 */
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+static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = {
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+ .master = &omap44xx_gpu_hwmod,
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+ .slave = &omap44xx_l3_main_2_hwmod,
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+ .clk = "l3_div_ck",
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+ .user = OCP_USER_MPU | OCP_USER_SDMA,
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+};
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+
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/* hsi -> l3_main_2 */
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static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
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.master = &omap44xx_hsi_hwmod,
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@@ -3909,6 +3957,24 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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+static struct omap_hwmod_addr_space omap44xx_gpu_addrs[] = {
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+ {
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+ .pa_start = 0x56000000,
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+ .pa_end = 0x5600ffff,
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+ .flags = ADDR_TYPE_RT
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+ },
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+ { }
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+};
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+
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+/* l3_main_2 -> gpu */
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+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = {
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+ .master = &omap44xx_l3_main_2_hwmod,
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+ .slave = &omap44xx_gpu_hwmod,
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+ .clk = "l3_div_ck",
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+ .addr = omap44xx_gpu_addrs,
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+ .user = OCP_USER_MPU | OCP_USER_SDMA,
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+};
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+
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static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs[] = {
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{
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.pa_start = 0x480b2000,
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@@ -4977,6 +5043,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
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&omap44xx_mpu__l3_main_1,
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&omap44xx_dma_system__l3_main_2,
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&omap44xx_fdif__l3_main_2,
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+ &omap44xx_gpu__l3_main_2,
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&omap44xx_hsi__l3_main_2,
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&omap44xx_ipu__l3_main_2,
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&omap44xx_iss__l3_main_2,
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@@ -5028,6 +5095,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
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&omap44xx_l4_per__gpio5,
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&omap44xx_l4_per__gpio6,
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&omap44xx_l3_main_2__gpmc,
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+ &omap44xx_l3_main_2__gpu,
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&omap44xx_l4_per__hdq1w,
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&omap44xx_l4_cfg__hsi,
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&omap44xx_l4_per__i2c1,
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