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@@ -636,82 +636,82 @@ struct rx_buf_desc {
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#define SEG_BASE IPHASE5575_FRAG_CONTROL_REG_BASE
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#define REASS_BASE IPHASE5575_REASS_CONTROL_REG_BASE
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-typedef volatile u_int freg_t;
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+typedef volatile u_int ffreg_t;
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typedef u_int rreg_t;
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typedef struct _ffredn_t {
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- freg_t idlehead_high; /* Idle cell header (high) */
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- freg_t idlehead_low; /* Idle cell header (low) */
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- freg_t maxrate; /* Maximum rate */
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- freg_t stparms; /* Traffic Management Parameters */
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- freg_t abrubr_abr; /* ABRUBR Priority Byte 1, TCR Byte 0 */
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- freg_t rm_type; /* */
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- u_int filler5[0x17 - 0x06];
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- freg_t cmd_reg; /* Command register */
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- u_int filler18[0x20 - 0x18];
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- freg_t cbr_base; /* CBR Pointer Base */
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- freg_t vbr_base; /* VBR Pointer Base */
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- freg_t abr_base; /* ABR Pointer Base */
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- freg_t ubr_base; /* UBR Pointer Base */
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- u_int filler24;
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- freg_t vbrwq_base; /* VBR Wait Queue Base */
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- freg_t abrwq_base; /* ABR Wait Queue Base */
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- freg_t ubrwq_base; /* UBR Wait Queue Base */
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- freg_t vct_base; /* Main VC Table Base */
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- freg_t vcte_base; /* Extended Main VC Table Base */
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- u_int filler2a[0x2C - 0x2A];
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- freg_t cbr_tab_beg; /* CBR Table Begin */
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- freg_t cbr_tab_end; /* CBR Table End */
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- freg_t cbr_pointer; /* CBR Pointer */
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- u_int filler2f[0x30 - 0x2F];
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- freg_t prq_st_adr; /* Packet Ready Queue Start Address */
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- freg_t prq_ed_adr; /* Packet Ready Queue End Address */
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- freg_t prq_rd_ptr; /* Packet Ready Queue read pointer */
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- freg_t prq_wr_ptr; /* Packet Ready Queue write pointer */
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- freg_t tcq_st_adr; /* Transmit Complete Queue Start Address*/
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- freg_t tcq_ed_adr; /* Transmit Complete Queue End Address */
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- freg_t tcq_rd_ptr; /* Transmit Complete Queue read pointer */
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- freg_t tcq_wr_ptr; /* Transmit Complete Queue write pointer*/
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- u_int filler38[0x40 - 0x38];
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- freg_t queue_base; /* Base address for PRQ and TCQ */
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- freg_t desc_base; /* Base address of descriptor table */
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- u_int filler42[0x45 - 0x42];
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- freg_t mode_reg_0; /* Mode register 0 */
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- freg_t mode_reg_1; /* Mode register 1 */
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- freg_t intr_status_reg;/* Interrupt Status register */
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- freg_t mask_reg; /* Mask Register */
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- freg_t cell_ctr_high1; /* Total cell transfer count (high) */
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- freg_t cell_ctr_lo1; /* Total cell transfer count (low) */
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- freg_t state_reg; /* Status register */
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- u_int filler4c[0x58 - 0x4c];
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- freg_t curr_desc_num; /* Contains the current descriptor num */
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- freg_t next_desc; /* Next descriptor */
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- freg_t next_vc; /* Next VC */
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- u_int filler5b[0x5d - 0x5b];
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- freg_t present_slot_cnt;/* Present slot count */
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- u_int filler5e[0x6a - 0x5e];
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- freg_t new_desc_num; /* New descriptor number */
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- freg_t new_vc; /* New VC */
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- freg_t sched_tbl_ptr; /* Schedule table pointer */
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- freg_t vbrwq_wptr; /* VBR wait queue write pointer */
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- freg_t vbrwq_rptr; /* VBR wait queue read pointer */
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- freg_t abrwq_wptr; /* ABR wait queue write pointer */
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- freg_t abrwq_rptr; /* ABR wait queue read pointer */
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- freg_t ubrwq_wptr; /* UBR wait queue write pointer */
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- freg_t ubrwq_rptr; /* UBR wait queue read pointer */
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- freg_t cbr_vc; /* CBR VC */
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- freg_t vbr_sb_vc; /* VBR SB VC */
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- freg_t abr_sb_vc; /* ABR SB VC */
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- freg_t ubr_sb_vc; /* UBR SB VC */
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- freg_t vbr_next_link; /* VBR next link */
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- freg_t abr_next_link; /* ABR next link */
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- freg_t ubr_next_link; /* UBR next link */
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- u_int filler7a[0x7c-0x7a];
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- freg_t out_rate_head; /* Out of rate head */
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- u_int filler7d[0xca-0x7d]; /* pad out to full address space */
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- freg_t cell_ctr_high1_nc;/* Total cell transfer count (high) */
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- freg_t cell_ctr_lo1_nc;/* Total cell transfer count (low) */
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- u_int fillercc[0x100-0xcc]; /* pad out to full address space */
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+ ffreg_t idlehead_high; /* Idle cell header (high) */
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+ ffreg_t idlehead_low; /* Idle cell header (low) */
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+ ffreg_t maxrate; /* Maximum rate */
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+ ffreg_t stparms; /* Traffic Management Parameters */
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+ ffreg_t abrubr_abr; /* ABRUBR Priority Byte 1, TCR Byte 0 */
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+ ffreg_t rm_type; /* */
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+ u_int filler5[0x17 - 0x06];
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+ ffreg_t cmd_reg; /* Command register */
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+ u_int filler18[0x20 - 0x18];
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+ ffreg_t cbr_base; /* CBR Pointer Base */
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+ ffreg_t vbr_base; /* VBR Pointer Base */
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+ ffreg_t abr_base; /* ABR Pointer Base */
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+ ffreg_t ubr_base; /* UBR Pointer Base */
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+ u_int filler24;
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+ ffreg_t vbrwq_base; /* VBR Wait Queue Base */
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+ ffreg_t abrwq_base; /* ABR Wait Queue Base */
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+ ffreg_t ubrwq_base; /* UBR Wait Queue Base */
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+ ffreg_t vct_base; /* Main VC Table Base */
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+ ffreg_t vcte_base; /* Extended Main VC Table Base */
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+ u_int filler2a[0x2C - 0x2A];
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+ ffreg_t cbr_tab_beg; /* CBR Table Begin */
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+ ffreg_t cbr_tab_end; /* CBR Table End */
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+ ffreg_t cbr_pointer; /* CBR Pointer */
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+ u_int filler2f[0x30 - 0x2F];
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+ ffreg_t prq_st_adr; /* Packet Ready Queue Start Address */
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+ ffreg_t prq_ed_adr; /* Packet Ready Queue End Address */
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+ ffreg_t prq_rd_ptr; /* Packet Ready Queue read pointer */
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+ ffreg_t prq_wr_ptr; /* Packet Ready Queue write pointer */
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+ ffreg_t tcq_st_adr; /* Transmit Complete Queue Start Address*/
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+ ffreg_t tcq_ed_adr; /* Transmit Complete Queue End Address */
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+ ffreg_t tcq_rd_ptr; /* Transmit Complete Queue read pointer */
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+ ffreg_t tcq_wr_ptr; /* Transmit Complete Queue write pointer*/
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+ u_int filler38[0x40 - 0x38];
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+ ffreg_t queue_base; /* Base address for PRQ and TCQ */
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+ ffreg_t desc_base; /* Base address of descriptor table */
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+ u_int filler42[0x45 - 0x42];
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+ ffreg_t mode_reg_0; /* Mode register 0 */
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+ ffreg_t mode_reg_1; /* Mode register 1 */
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+ ffreg_t intr_status_reg;/* Interrupt Status register */
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+ ffreg_t mask_reg; /* Mask Register */
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+ ffreg_t cell_ctr_high1; /* Total cell transfer count (high) */
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+ ffreg_t cell_ctr_lo1; /* Total cell transfer count (low) */
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+ ffreg_t state_reg; /* Status register */
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+ u_int filler4c[0x58 - 0x4c];
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+ ffreg_t curr_desc_num; /* Contains the current descriptor num */
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+ ffreg_t next_desc; /* Next descriptor */
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+ ffreg_t next_vc; /* Next VC */
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+ u_int filler5b[0x5d - 0x5b];
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+ ffreg_t present_slot_cnt;/* Present slot count */
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+ u_int filler5e[0x6a - 0x5e];
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+ ffreg_t new_desc_num; /* New descriptor number */
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+ ffreg_t new_vc; /* New VC */
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+ ffreg_t sched_tbl_ptr; /* Schedule table pointer */
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+ ffreg_t vbrwq_wptr; /* VBR wait queue write pointer */
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+ ffreg_t vbrwq_rptr; /* VBR wait queue read pointer */
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+ ffreg_t abrwq_wptr; /* ABR wait queue write pointer */
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+ ffreg_t abrwq_rptr; /* ABR wait queue read pointer */
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+ ffreg_t ubrwq_wptr; /* UBR wait queue write pointer */
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+ ffreg_t ubrwq_rptr; /* UBR wait queue read pointer */
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+ ffreg_t cbr_vc; /* CBR VC */
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+ ffreg_t vbr_sb_vc; /* VBR SB VC */
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+ ffreg_t abr_sb_vc; /* ABR SB VC */
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+ ffreg_t ubr_sb_vc; /* UBR SB VC */
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+ ffreg_t vbr_next_link; /* VBR next link */
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+ ffreg_t abr_next_link; /* ABR next link */
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+ ffreg_t ubr_next_link; /* UBR next link */
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+ u_int filler7a[0x7c-0x7a];
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+ ffreg_t out_rate_head; /* Out of rate head */
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+ u_int filler7d[0xca-0x7d]; /* pad out to full address space */
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+ ffreg_t cell_ctr_high1_nc;/* Total cell transfer count (high) */
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+ ffreg_t cell_ctr_lo1_nc;/* Total cell transfer count (low) */
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+ u_int fillercc[0x100-0xcc]; /* pad out to full address space */
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} ffredn_t;
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typedef struct _rfredn_t {
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