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@@ -417,90 +417,74 @@ void r600_hdmi_update_audio_settings(struct drm_encoder *encoder,
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WREG32_P(offset+R600_HDMI_CNTL, 0x04000000, ~0x04000000);
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}
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-/*
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- * enable/disable the HDMI engine
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- */
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-void r600_hdmi_enable(struct drm_encoder *encoder, int enable)
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+static void r600_hdmi_assign_block(struct drm_encoder *encoder)
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{
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struct drm_device *dev = encoder->dev;
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struct radeon_device *rdev = dev->dev_private;
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struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
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- uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset;
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+ struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
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- if (!offset)
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+ if (!dig) {
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+ dev_err(rdev->dev, "Enabling HDMI on non-dig encoder\n");
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return;
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+ }
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- DRM_DEBUG("%s HDMI interface @ 0x%04X\n", enable ? "Enabling" : "Disabling", offset);
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-
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- /* some version of atombios ignore the enable HDMI flag
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- * so enabling/disabling HDMI was moved here for TMDS1+2 */
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- switch (radeon_encoder->encoder_id) {
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- case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
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- WREG32_P(AVIVO_TMDSA_CNTL, enable ? 0x4 : 0x0, ~0x4);
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- WREG32(offset+R600_HDMI_ENABLE, enable ? 0x101 : 0x0);
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- break;
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-
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- case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
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- WREG32_P(AVIVO_LVTMA_CNTL, enable ? 0x4 : 0x0, ~0x4);
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- WREG32(offset+R600_HDMI_ENABLE, enable ? 0x105 : 0x0);
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- break;
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-
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- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
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- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
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- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
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- case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
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- /* This part is doubtfull in my opinion */
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- WREG32(offset+R600_HDMI_ENABLE, enable ? 0x110 : 0x0);
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- break;
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-
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- default:
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- DRM_ERROR("unknown HDMI output type\n");
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- break;
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+ if (ASIC_IS_DCE4(rdev)) {
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+ /* TODO */
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+ } else if (ASIC_IS_DCE3(rdev)) {
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+ radeon_encoder->hdmi_offset = dig->dig_encoder ?
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+ R600_HDMI_BLOCK3 : R600_HDMI_BLOCK1;
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+ if (ASIC_IS_DCE32(rdev))
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+ radeon_encoder->hdmi_config_offset = dig->dig_encoder ?
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+ R600_HDMI_CONFIG2 : R600_HDMI_CONFIG1;
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}
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}
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/*
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- * determin at which register offset the HDMI encoder is
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+ * enable the HDMI engine
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*/
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-void r600_hdmi_init(struct drm_encoder *encoder)
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+void r600_hdmi_enable(struct drm_encoder *encoder)
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{
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+ struct drm_device *dev = encoder->dev;
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+ struct radeon_device *rdev = dev->dev_private;
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struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
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- switch (radeon_encoder->encoder_id) {
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- case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
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- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
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- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
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- radeon_encoder->hdmi_offset = R600_HDMI_BLOCK1;
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- break;
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-
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- case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
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- switch (r600_audio_tmds_index(encoder)) {
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- case 0:
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- radeon_encoder->hdmi_offset = R600_HDMI_BLOCK1;
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- break;
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- case 1:
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- radeon_encoder->hdmi_offset = R600_HDMI_BLOCK2;
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- break;
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- default:
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- radeon_encoder->hdmi_offset = 0;
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- break;
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+ if (!radeon_encoder->hdmi_offset) {
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+ r600_hdmi_assign_block(encoder);
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+ if (!radeon_encoder->hdmi_offset) {
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+ dev_warn(rdev->dev, "Could not find HDMI block for "
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+ "0x%x encoder\n", radeon_encoder->encoder_id);
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+ return;
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}
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- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
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- radeon_encoder->hdmi_offset = R600_HDMI_BLOCK2;
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- break;
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+ }
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- case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
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- radeon_encoder->hdmi_offset = R600_HDMI_BLOCK3;
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- break;
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+ if (ASIC_IS_DCE32(rdev) && !ASIC_IS_DCE4(rdev))
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+ WREG32_P(radeon_encoder->hdmi_config_offset + 0x4, 0x1, ~0x1);
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+
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+ DRM_DEBUG("Enabling HDMI interface @ 0x%04X for encoder 0x%x\n",
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+ radeon_encoder->hdmi_offset, radeon_encoder->encoder_id);
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+}
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- default:
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- radeon_encoder->hdmi_offset = 0;
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- break;
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+/*
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+ * disable the HDMI engine
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+ */
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+void r600_hdmi_disable(struct drm_encoder *encoder)
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+{
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+ struct drm_device *dev = encoder->dev;
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+ struct radeon_device *rdev = dev->dev_private;
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+ struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
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+
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+ if (!radeon_encoder->hdmi_offset) {
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+ dev_err(rdev->dev, "Disabling not enabled HDMI\n");
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+ return;
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}
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- DRM_DEBUG("using HDMI engine at offset 0x%04X for encoder 0x%x\n",
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- radeon_encoder->hdmi_offset, radeon_encoder->encoder_id);
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+ DRM_DEBUG("Disabling HDMI interface @ 0x%04X for encoder 0x%x\n",
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+ radeon_encoder->hdmi_offset, radeon_encoder->encoder_id);
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+
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+ if (ASIC_IS_DCE32(rdev) && !ASIC_IS_DCE4(rdev))
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+ WREG32_P(radeon_encoder->hdmi_config_offset + 0x4, 0, ~0x1);
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- /* TODO: make this configureable */
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- radeon_encoder->hdmi_audio_workaround = 0;
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+ radeon_encoder->hdmi_offset = 0;
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+ radeon_encoder->hdmi_config_offset = 0;
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}
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