Commit History

Autor SHA1 Mensaxe Data
  Haiying Wang dbbbb3abef Make DDR interleaving mode work correctly %!s(int64=16) %!d(string=hai) anos
  Wolfgang Denk f12e4549b6 Coding style cleanup, update CHANGELOG %!s(int64=16) %!d(string=hai) anos
  Kumar Gala 58e5e9aff1 FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code. %!s(int64=16) %!d(string=hai) anos