 Kumar Gala
|
94e9411b9d
ppc/85xx: Add tracking of TLB CAM usage
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%!s(int64=15) %!d(string=hai) anos |
|
Kumar Gala
|
82fd1f8da9
85xx: Add support for e500mc cache stashing
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%!s(int64=16) %!d(string=hai) anos |
 Dave Liu
|
654ea1f318
ppc/85xx: Make L2 support more robust
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%!s(int64=15) %!d(string=hai) anos |
|
Kumar Gala
|
3c2a67eec8
ppc/p4080: Handle timebase enabling and frequency reporting
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%!s(int64=15) %!d(string=hai) anos |
|
Kumar Gala
|
25bacf7a2b
ppc/85xx: Fix enabling of L2 cache
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%!s(int64=15) %!d(string=hai) anos |
|
Kumar Gala
|
15fba3279b
ppc/85xx: Disable all async interrupt sources when we boot
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%!s(int64=15) %!d(string=hai) anos |
|
Kumar Gala
|
9f00409a9d
ppc/85xx: Split out cpu_init_early into its own file for NAND_SPL
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%!s(int64=15) %!d(string=hai) anos |
|
Kumar Gala
|
0456dbf347
ppc/85xx: Change cpu_init_early_f so we can use with NAND SPL
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%!s(int64=15) %!d(string=hai) anos |
 Mingkai Hu
|
7da53351d8
ppc/85xx: add boot from NAND/eSDHC/eSPI support
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%!s(int64=15) %!d(string=hai) anos |
|
Kumar Gala
|
26f4cdba6b
85xx: Add support for setting IVORs to fixed offset defaults
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%!s(int64=15) %!d(string=hai) anos |
|
Mingkai Hu
|
76b474e2f5
85xx: Add L2SRAM Register's macro definition
|
%!s(int64=15) %!d(string=hai) anos |
 Peter Tyser
|
79f4333ceb
8xxx: Move dma_init() call to common code
|
%!s(int64=16) %!d(string=hai) anos |
|
Kumar Gala
|
1b3e4044a2
85xx: Add support for additional e500mc features
|
%!s(int64=16) %!d(string=hai) anos |
|
Kumar Gala
|
9df59533f7
85xx: init gd as early as possible
|
%!s(int64=16) %!d(string=hai) anos |
|
Kumar Gala
|
aed461af81
85xx: Fix relocation of CCSRBAR
|
%!s(int64=16) %!d(string=hai) anos |
|
Peter Tyser
|
a2cd50ed6e
85xx: Add CPU 2 errata workaround to all 8548 boards
|
%!s(int64=16) %!d(string=hai) anos |
 Jean-Christophe PLAGNIOL-VILLARD
|
6d0f6bcf33
rename CFG_ macros to CONFIG_SYS
|
%!s(int64=16) %!d(string=hai) anos |
|
Kumar Gala
|
ef50d6c06e
mpc85xx: Add support for the MPC8536
|
%!s(int64=16) %!d(string=hai) anos |
|
Kumar Gala
|
73f15a060f
85xx: Cleanup L2 cache size detection
|
%!s(int64=17) %!d(string=hai) anos |
|
Kumar Gala
|
f060054dad
FSL LAW: Keep track of LAW allocations
|
%!s(int64=17) %!d(string=hai) anos |
 Wolfgang Grandegger
|
6beecfbb54
MPC85xx: Beautify boot output of L2 cache configuration
|
%!s(int64=17) %!d(string=hai) anos |
|
Kumar Gala
|
f3e04bdc3f
85xx: Use SVR_SOC_VER instead of SVR_VER
|
%!s(int64=17) %!d(string=hai) anos |
|
Kumar Gala
|
ec2b74ffd3
85xx: Added support for multicore boot mechanism
|
%!s(int64=17) %!d(string=hai) anos |
|
Kumar Gala
|
f69766e4b5
85xx: Add the concept of CFG_CCSRBAR_PHYS
|
%!s(int64=17) %!d(string=hai) anos |
|
Kumar Gala
|
7dc358bb0d
85xx: Get ride of old TLB setup code
|
%!s(int64=17) %!d(string=hai) anos |
|
Kumar Gala
|
8716318057
85xx: Reworked initial processor init
|
%!s(int64=17) %!d(string=hai) anos |
|
Kumar Gala
|
83d40dfd79
85xx: Move LAW init code into C
|
%!s(int64=17) %!d(string=hai) anos |
|
Kumar Gala
|
04db400892
Stop using immap_t on 85xx
|
%!s(int64=17) %!d(string=hai) anos |
|
Kumar Gala
|
aafeefbdb8
Stop using immap_t for cpm offset on 85xx
|
%!s(int64=17) %!d(string=hai) anos |
 Haiying Wang
|
7a1ac419fa
Enable L2 cache for MPC8568MDS board
|
%!s(int64=17) %!d(string=hai) anos |
