|
@@ -37,7 +37,7 @@
|
|
#define MX25_H1_SIC_SHIFT 21
|
|
#define MX25_H1_SIC_SHIFT 21
|
|
#define MX25_H1_SIC_MASK (0x3 << MX25_H1_SIC_SHIFT)
|
|
#define MX25_H1_SIC_MASK (0x3 << MX25_H1_SIC_SHIFT)
|
|
#define MX25_H1_PP_BIT (1 << 18)
|
|
#define MX25_H1_PP_BIT (1 << 18)
|
|
-#define MX25_H1_PM_BIT (1 << 8)
|
|
|
|
|
|
+#define MX25_H1_PM_BIT (1 << 16)
|
|
#define MX25_H1_IPPUE_UP_BIT (1 << 7)
|
|
#define MX25_H1_IPPUE_UP_BIT (1 << 7)
|
|
#define MX25_H1_IPPUE_DOWN_BIT (1 << 6)
|
|
#define MX25_H1_IPPUE_DOWN_BIT (1 << 6)
|
|
#define MX25_H1_TLL_BIT (1 << 5)
|
|
#define MX25_H1_TLL_BIT (1 << 5)
|