Add support for ep8248 board

Patch by Yuli Barcohen, 12 Dec 2004

Minor code cleanup.

CHANGELOG

@@ -2,12 +2,17 @@
 Changes for U-Boot 1.1.3:
 ======================================================================
 
+* Add support for ep8248 board
+  Patch by Yuli Barcohen, 12 Dec 2004
+
+  Minor code cleanup.
+
 * Fix baudrate setting for KGDB on MPC8260
   Patch by HoJin, 11 Dec 2004
 
 * Fix 'mii help' text formatting
   Patch by Cory Tusar, 10 Dec 2004
-  
+
 * Fix return code of NFS command
   Patch by Hiroshi Ito, 11 Dec 2004
 

MAINTAINERS

@@ -32,6 +32,7 @@ Reinhard Arlt <reinhard.arlt@esd-electronics.com>
 Yuli Barcohen <yuli@arabellasw.com>
 
 	Adder			MPC87x/MPC852T
+	ep8248			MPC8248
 	ISPAN			MPC8260
 	MPC8260ADS		MPC826x/MPC827x/MPC8280
 	Rattler			MPC8248

MAKEALL

@@ -99,12 +99,12 @@ LIST_824x="	\
 
 LIST_8260="	\
 	atc		cogent_mpc8260	CPU86		CPU87		\
-	ep8260		gw8260		hymod		IPHASE4539	\
-	ISPAN		MPC8260ADS	MPC8266ADS	MPC8272ADS	\
-	PM826		PM828		ppmc8260	Rattler8248	\
-	RPXsuper	rsdproto	sacsng		sbc8260		\
-	SCM		TQM8260_AC	TQM8260_AD	TQM8260_AE	\
-	ZPC1900								\
+	ep8248		ep8260		gw8260		hymod		\
+	IPHASE4539	ISPAN		MPC8260ADS	MPC8266ADS	\
+	MPC8272ADS	PM826		PM828		ppmc8260	\
+	Rattler8248	RPXsuper	rsdproto	sacsng		\
+	sbc8260		SCM		TQM8260_AC	TQM8260_AD	\
+	TQM8260_AE	ZPC1900						\
 "
 
 #########################################################################

Makefile

@@ -997,6 +997,10 @@ CPU87_ROMBOOT_config: unconfig
 	fi; \
 	echo "export CONFIG_BOOT_ROM" >> config.mk;
 
+ep8248_config	\
+ep8248E_config	:	unconfig
+	@./mkconfig ep8248 ppc mpc8260 ep8248
+
 ep8260_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8260 ep8260
 

board/amcc/bamboo/bamboo.h

@@ -12,7 +12,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -29,107 +29,107 @@
  * TLB initialization makes it correspond to logical address 0x80001FF0.
  * => Done init_chip.s in bootlib
  */
-#define FPGA_BASE_ADDR  0x80002000
+#define FPGA_BASE_ADDR	0x80002000
 
 /*----------------------------------------------------------------------------+
   | Board Jumpers Setting Register
   |   Board Settings provided by jumpers
   +----------------------------------------------------------------------------*/
-#define FPGA_SETTING_REG            (FPGA_BASE_ADDR+0x3)
+#define FPGA_SETTING_REG	    (FPGA_BASE_ADDR+0x3)
 /* Boot from small flash */
-#define     FPGA_SET_REG_BOOT_SMALL_FLASH           0x80
+#define	    FPGA_SET_REG_BOOT_SMALL_FLASH	    0x80
 /* Operational Flash versus SRAM position in Memory Map */
-#define     FPGA_SET_REG_OP_CODE_SRAM_SEL_MASK      0x40
-#define      FPGA_SET_REG_OP_CODE_FLASH_ABOVE        0x40
-#define      FPGA_SET_REG_SRAM_ABOVE                 0x00
+#define	    FPGA_SET_REG_OP_CODE_SRAM_SEL_MASK	    0x40
+#define	     FPGA_SET_REG_OP_CODE_FLASH_ABOVE	     0x40
+#define	     FPGA_SET_REG_SRAM_ABOVE		     0x00
 /* Boot From NAND Flash */
-#define     FPGA_SET_REG_BOOT_NAND_FLASH_MASK       0x40
-#define     FPGA_SET_REG_BOOT_NAND_FLASH_SELECT      0x00
+#define	    FPGA_SET_REG_BOOT_NAND_FLASH_MASK	    0x40
+#define	    FPGA_SET_REG_BOOT_NAND_FLASH_SELECT	     0x00
 /* On Board PCI Arbiter Select */
-#define     FPGA_SET_REG_PCI_EXT_ARBITER_SEL_MASK   0x10
-#define     FPGA_SET_REG_PCI_EXT_ARBITER_SEL        0x00
+#define	    FPGA_SET_REG_PCI_EXT_ARBITER_SEL_MASK   0x10
+#define	    FPGA_SET_REG_PCI_EXT_ARBITER_SEL	    0x00
 
 /*----------------------------------------------------------------------------+
   | Functions Selection Register 1
   +----------------------------------------------------------------------------*/
-#define FPGA_SELECTION_1_REG        (FPGA_BASE_ADDR+0x4)
-#define     FPGA_SEL_1_REG_PHY_MASK         0xE0
-#define     FPGA_SEL_1_REG_MII              0x80
-#define     FPGA_SEL_1_REG_RMII             0x40
-#define     FPGA_SEL_1_REG_SMII             0x20
-#define     FPGA_SEL_1_REG_USB2_DEV_SEL     0x10           /* USB2 Device Selection */
-#define     FPGA_SEL_1_REG_USB2_HOST_SEL    0x08           /* USB2 Host Selection */
-#define     FPGA_SEL_1_REG_NF_SELEC_MASK    0x07           /* NF Selection Mask */
-#define     FPGA_SEL_1_REG_NF0_SEL_BY_NFCS1 0x04           /* NF0 Selected by NF_CS1 */
-#define     FPGA_SEL_1_REG_NF1_SEL_BY_NFCS2 0x02           /* NF1 Selected by NF_CS2 */
-#define     FPGA_SEL_1_REG_NF1_SEL_BY_NFCS3 0x01           /* NF1 Selected by NF_CS3 */
+#define FPGA_SELECTION_1_REG	    (FPGA_BASE_ADDR+0x4)
+#define	    FPGA_SEL_1_REG_PHY_MASK	    0xE0
+#define	    FPGA_SEL_1_REG_MII		    0x80
+#define	    FPGA_SEL_1_REG_RMII		    0x40
+#define	    FPGA_SEL_1_REG_SMII		    0x20
+#define	    FPGA_SEL_1_REG_USB2_DEV_SEL	    0x10	   /* USB2 Device Selection */
+#define	    FPGA_SEL_1_REG_USB2_HOST_SEL    0x08	   /* USB2 Host Selection */
+#define	    FPGA_SEL_1_REG_NF_SELEC_MASK    0x07	   /* NF Selection Mask */
+#define	    FPGA_SEL_1_REG_NF0_SEL_BY_NFCS1 0x04	   /* NF0 Selected by NF_CS1 */
+#define	    FPGA_SEL_1_REG_NF1_SEL_BY_NFCS2 0x02	   /* NF1 Selected by NF_CS2 */
+#define	    FPGA_SEL_1_REG_NF1_SEL_BY_NFCS3 0x01	   /* NF1 Selected by NF_CS3 */
 
 /*----------------------------------------------------------------------------+
   | Functions Selection Register 2
   +----------------------------------------------------------------------------*/
-#define FPGA_SELECTION_2_REG        (FPGA_BASE_ADDR+0x5)
-#define     FPGA_SEL2_REG_IIC1_SCP_SEL_MASK 0x80           /* IIC1 / SCP Selection */
-#define     FPGA_SEL2_REG_SEL_FRAM          0x80           /* FRAM on IIC1 bus selected - SCP Select */
-#define     FPGA_SEL2_REG_SEL_SCP           0x80           /* Identical to SCP Selection */
-#define     FPGA_SEL2_REG_SEL_IIC1          0x00           /* IIC1 Selection - Default Value */
-#define     FPGA_SEL2_REG_SEL_DMA_A_B       0x40           /* DMA A & B channels selected */
-#define     FPGA_SEL2_REG_SEL_DMA_C_D       0x20           /* DMA C & D channels selected */
-#define     FPGA_SEL2_REG_DMA_EOT_TC_3_SEL  0x10           /* 0 = EOT - input to 440EP */
-                                                           /* 1 = TC - output from 440EP */
-#define     FPGA_SEL2_REG_DMA_EOT_TC_2_SEL  0x08           /* 0 = EOT (input to 440EP) */
-                                                           /* 1 = TC (output from 440EP) */
-#define     FPGA_SEL2_REG_SEL_GPIO_1        0x04           /* EBC_GPIO & USB2_GPIO selected */
-#define     FPGA_SEL2_REG_SEL_GPIO_2        0x02           /* Ether._GPIO & UART_GPIO selected */
-#define     FPGA_SEL2_REG_SEL_GPIO_3        0x01           /* DMA_GPIO & Trace_GPIO selected */
+#define FPGA_SELECTION_2_REG	    (FPGA_BASE_ADDR+0x5)
+#define	    FPGA_SEL2_REG_IIC1_SCP_SEL_MASK 0x80	   /* IIC1 / SCP Selection */
+#define	    FPGA_SEL2_REG_SEL_FRAM	    0x80	   /* FRAM on IIC1 bus selected - SCP Select */
+#define	    FPGA_SEL2_REG_SEL_SCP	    0x80	   /* Identical to SCP Selection */
+#define	    FPGA_SEL2_REG_SEL_IIC1	    0x00	   /* IIC1 Selection - Default Value */
+#define	    FPGA_SEL2_REG_SEL_DMA_A_B	    0x40	   /* DMA A & B channels selected */
+#define	    FPGA_SEL2_REG_SEL_DMA_C_D	    0x20	   /* DMA C & D channels selected */
+#define	    FPGA_SEL2_REG_DMA_EOT_TC_3_SEL  0x10	   /* 0 = EOT - input to 440EP */
+							   /* 1 = TC - output from 440EP */
+#define	    FPGA_SEL2_REG_DMA_EOT_TC_2_SEL  0x08	   /* 0 = EOT (input to 440EP) */
+							   /* 1 = TC (output from 440EP) */
+#define	    FPGA_SEL2_REG_SEL_GPIO_1	    0x04	   /* EBC_GPIO & USB2_GPIO selected */
+#define	    FPGA_SEL2_REG_SEL_GPIO_2	    0x02	   /* Ether._GPIO & UART_GPIO selected */
+#define	    FPGA_SEL2_REG_SEL_GPIO_3	    0x01	   /* DMA_GPIO & Trace_GPIO selected */
 
 /*----------------------------------------------------------------------------+
   | Functions Selection Register 3
   +----------------------------------------------------------------------------*/
-#define FPGA_SELECTION_3_REG        (FPGA_BASE_ADDR+0x6)
-#define     FPGA_SEL3_REG_EXP_SLOT_EN               0x80    /* Expansion Slot enabled */
-#define     FPGA_SEL3_REG_SEL_UART_CONFIG_MASK      0x70
-#define     FPGA_SEL3_REG_SEL_UART_CONFIG1          0x40    /* one 8_pin UART */
-#define     FPGA_SEL3_REG_SEL_UART_CONFIG2          0x20    /* two 4_pin UARTs */
-#define     FPGA_SEL3_REG_SEL_UART_CONFIG3          0x10    /* one 4_pin & two 2_pin UARTs */
-#define     FPGA_SEL3_REG_SEL_UART_CONFIG4          0x08    /* four 2_pin UARTs */
-#define     FPGA_SEL3_REG_DTR_DSR_MODE_4_PIN_UART   0x00    /* DTR/DSR mode for 4_pin_UART */
-#define     FPGA_SEL3_REG_RTS_CTS_MODE_4_PIN_UART   0x04    /* RTS/CTS mode for 4_pin_UART */
+#define FPGA_SELECTION_3_REG	    (FPGA_BASE_ADDR+0x6)
+#define	    FPGA_SEL3_REG_EXP_SLOT_EN		    0x80    /* Expansion Slot enabled */
+#define	    FPGA_SEL3_REG_SEL_UART_CONFIG_MASK	    0x70
+#define	    FPGA_SEL3_REG_SEL_UART_CONFIG1	    0x40    /* one 8_pin UART */
+#define	    FPGA_SEL3_REG_SEL_UART_CONFIG2	    0x20    /* two 4_pin UARTs */
+#define	    FPGA_SEL3_REG_SEL_UART_CONFIG3	    0x10    /* one 4_pin & two 2_pin UARTs */
+#define	    FPGA_SEL3_REG_SEL_UART_CONFIG4	    0x08    /* four 2_pin UARTs */
+#define	    FPGA_SEL3_REG_DTR_DSR_MODE_4_PIN_UART   0x00    /* DTR/DSR mode for 4_pin_UART */
+#define	    FPGA_SEL3_REG_RTS_CTS_MODE_4_PIN_UART   0x04    /* RTS/CTS mode for 4_pin_UART */
 
 /*----------------------------------------------------------------------------+
   | Soft Reset Register
   +----------------------------------------------------------------------------*/
-#define FPGA_RESET_REG              (FPGA_BASE_ADDR+0x7)
-#define     FPGA_RESET_REG_RESET_USB20_DEV          0x80    /* Hard Reset of the GT3200 */
-#define     FPGA_RESET_REG_RESET_DISPLAY            0x40    /* Hard Reset on Display Device */
-#define     FPGA_RESET_REG_STATUS_LED_0             0x08    /* 1 = Led On */
-#define     FPGA_RESET_REG_STATUS_LED_1             0x04    /* 1 = Led On */
-#define     FPGA_RESET_REG_STATUS_LED_2             0x02    /* 1 = Led On */
-#define     FPGA_RESET_REG_STATUS_LED_3             0x01    /* 1 = Led On */
+#define FPGA_RESET_REG		    (FPGA_BASE_ADDR+0x7)
+#define	    FPGA_RESET_REG_RESET_USB20_DEV	    0x80    /* Hard Reset of the GT3200 */
+#define	    FPGA_RESET_REG_RESET_DISPLAY	    0x40    /* Hard Reset on Display Device */
+#define	    FPGA_RESET_REG_STATUS_LED_0		    0x08    /* 1 = Led On */
+#define	    FPGA_RESET_REG_STATUS_LED_1		    0x04    /* 1 = Led On */
+#define	    FPGA_RESET_REG_STATUS_LED_2		    0x02    /* 1 = Led On */
+#define	    FPGA_RESET_REG_STATUS_LED_3		    0x01    /* 1 = Led On */
 
 
 /*----------------------------------------------------------------------------+
 | SDR Configuration registers
 +----------------------------------------------------------------------------*/
 /* Serial Device Strap Reg 0 */
-#define SDR0_SDSTP0                  0x0020
+#define SDR0_SDSTP0		     0x0020
 /* Serial Device Strap Reg 1 */
-#define SDR0_SDSTP1                  0x0021
+#define SDR0_SDSTP1		     0x0021
 /* Serial Device Strap Reg 2 */
-#define SDR0_SDSTP2                  SDR0_STRP2
+#define SDR0_SDSTP2		     SDR0_STRP2
 /* Serial Device Strap Reg 3 */
-#define SDR0_SDSTP3                  SDR0_STRP3
+#define SDR0_SDSTP3		     SDR0_STRP3
 
-#define sdr_pstrp0                   0x0040
+#define sdr_pstrp0		     0x0040
 
-#define   SDR0_SDSTP1_EBC_ROM_BS_MASK  0x00006000  /* EBC Boot Size Mask */
-#define   SDR0_SDSTP1_EBC_ROM_BS_32BIT 0x00004000    /* EBC 32 bits */
-#define   SDR0_SDSTP1_EBC_ROM_BS_16BIT 0x00002000    /* EBC 16 Bits */
-#define   SDR0_SDSTP1_EBC_ROM_BS_8BIT  0x00000000    /* EBC  8 Bits */
+#define	  SDR0_SDSTP1_EBC_ROM_BS_MASK  0x00006000  /* EBC Boot Size Mask */
+#define	  SDR0_SDSTP1_EBC_ROM_BS_32BIT 0x00004000    /* EBC 32 bits */
+#define	  SDR0_SDSTP1_EBC_ROM_BS_16BIT 0x00002000    /* EBC 16 Bits */
+#define	  SDR0_SDSTP1_EBC_ROM_BS_8BIT  0x00000000    /* EBC  8 Bits */
 
-#define   SDR0_SDSTP1_BOOT_SEL_MASK    0x00001800   /* Boot device Selection Mask */
-#define   SDR0_SDSTP1_BOOT_SEL_EBC     0x00000000     /* EBC */
-#define   SDR0_SDSTP1_BOOT_SEL_PCI     0x00000800     /* PCI */
-#define   SDR0_SDSTP1_BOOT_SEL_NDFC    0x00001000     /* NDFC */
+#define	  SDR0_SDSTP1_BOOT_SEL_MASK    0x00001800   /* Boot device Selection Mask */
+#define	  SDR0_SDSTP1_BOOT_SEL_EBC     0x00000000     /* EBC */
+#define	  SDR0_SDSTP1_BOOT_SEL_PCI     0x00000800     /* PCI */
+#define	  SDR0_SDSTP1_BOOT_SEL_NDFC    0x00001000     /* NDFC */
 
 /* Serial Device Enabled - Addr = 0xA8 */
 #define SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS5
@@ -137,8 +137,8 @@
 #define SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS7
 
 /* Pin Straps Reg */
-#define SDR0_PSTRP0                  0x0040
-#define SDR0_PSTRP0_BOOTSTRAP_MASK      0xE0000000  /* Strap Bits */
+#define SDR0_PSTRP0		     0x0040
+#define SDR0_PSTRP0_BOOTSTRAP_MASK	0xE0000000  /* Strap Bits */
 
 #define SDR0_PSTRP0_BOOTSTRAP_SETTINGS0 0x00000000  /* Default strap settings 0 */
 #define SDR0_PSTRP0_BOOTSTRAP_SETTINGS1 0x20000000  /* Default strap settings 1 */
@@ -153,182 +153,182 @@
 | EBC Configuration Register - EBC0_CFG
 +----------------------------------------------------------------------------*/
 /* External Bus Three-State Control */
-#define EBC0_CFG_EBTC_DRIVEN        0x80000000
+#define EBC0_CFG_EBTC_DRIVEN	    0x80000000
 /* Device-Paced Time-out Disable */
-#define EBC0_CFG_PTD_ENABLED        0x00000000
+#define EBC0_CFG_PTD_ENABLED	    0x00000000
 /* Ready Timeout Count */
-#define EBC0_CFG_RTC_MASK           0x38000000
-#define EBC0_CFG_RTC_16PERCLK       0x00000000
-#define EBC0_CFG_RTC_32PERCLK       0x08000000
-#define EBC0_CFG_RTC_64PERCLK       0x10000000
-#define EBC0_CFG_RTC_128PERCLK      0x18000000
-#define EBC0_CFG_RTC_256PERCLK      0x20000000
-#define EBC0_CFG_RTC_512PERCLK      0x28000000
-#define EBC0_CFG_RTC_1024PERCLK     0x30000000
-#define EBC0_CFG_RTC_2048PERCLK     0x38000000
+#define EBC0_CFG_RTC_MASK	    0x38000000
+#define EBC0_CFG_RTC_16PERCLK	    0x00000000
+#define EBC0_CFG_RTC_32PERCLK	    0x08000000
+#define EBC0_CFG_RTC_64PERCLK	    0x10000000
+#define EBC0_CFG_RTC_128PERCLK	    0x18000000
+#define EBC0_CFG_RTC_256PERCLK	    0x20000000
+#define EBC0_CFG_RTC_512PERCLK	    0x28000000
+#define EBC0_CFG_RTC_1024PERCLK	    0x30000000
+#define EBC0_CFG_RTC_2048PERCLK	    0x38000000
 /* External Master Priority Low */
-#define EBC0_CFG_EMPL_LOW           0x00000000
+#define EBC0_CFG_EMPL_LOW	    0x00000000
 #define EBC0_CFG_EMPL_MEDIUM_LOW    0x02000000
 #define EBC0_CFG_EMPL_MEDIUM_HIGH   0x04000000
-#define EBC0_CFG_EMPL_HIGH          0x06000000
+#define EBC0_CFG_EMPL_HIGH	    0x06000000
 /* External Master Priority High */
-#define EBC0_CFG_EMPH_LOW           0x00000000
+#define EBC0_CFG_EMPH_LOW	    0x00000000
 #define EBC0_CFG_EMPH_MEDIUM_LOW    0x00800000
 #define EBC0_CFG_EMPH_MEDIUM_HIGH   0x01000000
-#define EBC0_CFG_EMPH_HIGH          0x01800000
+#define EBC0_CFG_EMPH_HIGH	    0x01800000
 /* Chip Select Three-State Control */
-#define EBC0_CFG_CSTC_DRIVEN        0x00400000
+#define EBC0_CFG_CSTC_DRIVEN	    0x00400000
 /* Burst Prefetch */
-#define EBC0_CFG_BPF_ONEDW          0x00000000
-#define EBC0_CFG_BPF_TWODW          0x00100000
-#define EBC0_CFG_BPF_FOURDW         0x00200000
+#define EBC0_CFG_BPF_ONEDW	    0x00000000
+#define EBC0_CFG_BPF_TWODW	    0x00100000
+#define EBC0_CFG_BPF_FOURDW	    0x00200000
 /* External Master Size */
-#define EBC0_CFG_EMS_8BIT           0x00000000
+#define EBC0_CFG_EMS_8BIT	    0x00000000
 /* Power Management Enable */
-#define EBC0_CFG_PME_DISABLED       0x00000000
-#define EBC0_CFG_PME_ENABLED        0x00020000
+#define EBC0_CFG_PME_DISABLED	    0x00000000
+#define EBC0_CFG_PME_ENABLED	    0x00020000
 /* Power Management Timer */
-#define EBC0_CFG_PMT_ENCODE(n)          ((((unsigned long)(n))&0x1F)<<12)
+#define EBC0_CFG_PMT_ENCODE(n)		((((unsigned long)(n))&0x1F)<<12)
 
 /*----------------------------------------------------------------------------+
 | Peripheral Bank Configuration Register - EBC0_BnCR
 +----------------------------------------------------------------------------*/
 /* BAS - Base Address Select */
-#define EBC0_BNCR_BAS_ENCODE(n)         ((((unsigned long)(n))&0xFFF00000)<<0)
+#define EBC0_BNCR_BAS_ENCODE(n)		((((unsigned long)(n))&0xFFF00000)<<0)
 /* BS - Bank Size */
-#define EBC0_BNCR_BS_MASK       0x000E0000
-#define EBC0_BNCR_BS_1MB        0x00000000
-#define EBC0_BNCR_BS_2MB        0x00020000
-#define EBC0_BNCR_BS_4MB        0x00040000
-#define EBC0_BNCR_BS_8MB        0x00060000
-#define EBC0_BNCR_BS_16MB       0x00080000
-#define EBC0_BNCR_BS_32MB       0x000A0000
-#define EBC0_BNCR_BS_64MB       0x000C0000
-#define EBC0_BNCR_BS_128MB      0x000E0000
+#define EBC0_BNCR_BS_MASK	0x000E0000
+#define EBC0_BNCR_BS_1MB	0x00000000
+#define EBC0_BNCR_BS_2MB	0x00020000
+#define EBC0_BNCR_BS_4MB	0x00040000
+#define EBC0_BNCR_BS_8MB	0x00060000
+#define EBC0_BNCR_BS_16MB	0x00080000
+#define EBC0_BNCR_BS_32MB	0x000A0000
+#define EBC0_BNCR_BS_64MB	0x000C0000
+#define EBC0_BNCR_BS_128MB	0x000E0000
 /* BU - Bank Usage */
-#define EBC0_BNCR_BU_MASK       0x00018000
-#define EBC0_BNCR_BU_RO             0x00008000
-#define EBC0_BNCR_BU_WO             0x00010000
-#define EBC0_BNCR_BU_RW         0x00018000
+#define EBC0_BNCR_BU_MASK	0x00018000
+#define EBC0_BNCR_BU_RO		    0x00008000
+#define EBC0_BNCR_BU_WO		    0x00010000
+#define EBC0_BNCR_BU_RW		0x00018000
 /* BW - Bus Width */
-#define EBC0_BNCR_BW_MASK       0x00006000
-#define EBC0_BNCR_BW_8BIT       0x00000000
-#define EBC0_BNCR_BW_16BIT      0x00002000
-#define EBC0_BNCR_BW_32BIT      0x00004000
+#define EBC0_BNCR_BW_MASK	0x00006000
+#define EBC0_BNCR_BW_8BIT	0x00000000
+#define EBC0_BNCR_BW_16BIT	0x00002000
+#define EBC0_BNCR_BW_32BIT	0x00004000
 
 /*----------------------------------------------------------------------------+
 | Peripheral Bank Access Parameters - EBC0_BnAP
 +----------------------------------------------------------------------------*/
 /* Burst Mode Enable */
-#define EBC0_BNAP_BME_ENABLED       0x80000000
-#define EBC0_BNAP_BME_DISABLED      0x00000000
+#define EBC0_BNAP_BME_ENABLED	    0x80000000
+#define EBC0_BNAP_BME_DISABLED	    0x00000000
 /* Transfert Wait */
-#define EBC0_BNAP_TWT_ENCODE(n)     ((((unsigned long)(n))&0xFF)<<23)   /* Bits 1:8 */
+#define EBC0_BNAP_TWT_ENCODE(n)	    ((((unsigned long)(n))&0xFF)<<23)	/* Bits 1:8 */
 /* Chip Select On Timing */
-#define EBC0_BNAP_CSN_ENCODE(n)     ((((unsigned long)(n))&0x3)<<18)    /* Bits 12:13 */
+#define EBC0_BNAP_CSN_ENCODE(n)	    ((((unsigned long)(n))&0x3)<<18)	/* Bits 12:13 */
 /* Output Enable On Timing */
-#define EBC0_BNAP_OEN_ENCODE(n)     ((((unsigned long)(n))&0x3)<<16)    /* Bits 14:15 */
+#define EBC0_BNAP_OEN_ENCODE(n)	    ((((unsigned long)(n))&0x3)<<16)	/* Bits 14:15 */
 /* Write Back Enable On Timing */
-#define EBC0_BNAP_WBN_ENCODE(n)     ((((unsigned long)(n))&0x3)<<14)    /* Bits 16:17 */
+#define EBC0_BNAP_WBN_ENCODE(n)	    ((((unsigned long)(n))&0x3)<<14)	/* Bits 16:17 */
 /* Write Back Enable Off Timing */
-#define EBC0_BNAP_WBF_ENCODE(n)     ((((unsigned long)(n))&0x3)<<12)    /* Bits 18:19 */
+#define EBC0_BNAP_WBF_ENCODE(n)	    ((((unsigned long)(n))&0x3)<<12)	/* Bits 18:19 */
 /* Transfert Hold */
-#define EBC0_BNAP_TH_ENCODE(n)      ((((unsigned long)(n))&0x7)<<9)     /* Bits 20:22 */
+#define EBC0_BNAP_TH_ENCODE(n)	    ((((unsigned long)(n))&0x7)<<9)	/* Bits 20:22 */
 /* PerReady Enable */
-#define EBC0_BNAP_RE_ENABLED        0x00000100
-#define EBC0_BNAP_RE_DISABLED       0x00000000
+#define EBC0_BNAP_RE_ENABLED	    0x00000100
+#define EBC0_BNAP_RE_DISABLED	    0x00000000
 /* Sample On Ready */
-#define EBC0_BNAP_SOR_DELAYED       0x00000000
+#define EBC0_BNAP_SOR_DELAYED	    0x00000000
 #define EBC0_BNAP_SOR_NOT_DELAYED   0x00000080
 /* Byte Enable Mode */
-#define EBC0_BNAP_BEM_WRITEONLY     0x00000000
-#define EBC0_BNAP_BEM_RW            0x00000040
+#define EBC0_BNAP_BEM_WRITEONLY	    0x00000000
+#define EBC0_BNAP_BEM_RW	    0x00000040
 /* Parity Enable */
-#define EBC0_BNAP_PEN_DISABLED      0x00000000
-#define EBC0_BNAP_PEN_ENABLED       0x00000020
+#define EBC0_BNAP_PEN_DISABLED	    0x00000000
+#define EBC0_BNAP_PEN_ENABLED	    0x00000020
 
 /*----------------------------------------------------------------------------+
 | Define Boot devices
 +----------------------------------------------------------------------------*/
 /* */
-#define BOOT_FROM_SMALL_FLASH           0x00
-#define BOOT_FROM_LARGE_FLASH_OR_SRAM   0x01
-#define BOOT_FROM_NAND_FLASH0           0x02
-#define BOOT_FROM_PCI                   0x03
-#define BOOT_DEVICE_UNKNOWN             0x04
+#define BOOT_FROM_SMALL_FLASH		0x00
+#define BOOT_FROM_LARGE_FLASH_OR_SRAM	0x01
+#define BOOT_FROM_NAND_FLASH0		0x02
+#define BOOT_FROM_PCI			0x03
+#define BOOT_DEVICE_UNKNOWN		0x04
 
 
-#define  PVR_POWERPC_440EP_PASS1    0x42221850
-#define  PVR_POWERPC_440EP_PASS2    0x422218D3
+#define	 PVR_POWERPC_440EP_PASS1    0x42221850
+#define	 PVR_POWERPC_440EP_PASS2    0x422218D3
 
 #define TRUE 1
 #define FALSE 0
 
-#define GPIO_GROUP_MAX      2
-#define GPIO_MAX            32
-#define GPIO_ALT1_SEL       0x40000000      /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 0 */
-#define GPIO_ALT2_SEL       0x80000000      /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 1 */
-#define GPIO_ALT3_SEL       0xC0000000      /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 2 */
-#define GPIO_MASK           0xC0000000      /* GPIO_MASK */
-#define GPIO_IN_SEL         0x40000000      /* GPIO_IN value put in GPIO_ISx for the GPIO nb 0 */
-                                            /* For the other GPIO number, you must shift */
+#define GPIO_GROUP_MAX	    2
+#define GPIO_MAX	    32
+#define GPIO_ALT1_SEL	    0x40000000	    /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 0 */
+#define GPIO_ALT2_SEL	    0x80000000	    /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 1 */
+#define GPIO_ALT3_SEL	    0xC0000000	    /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 2 */
+#define GPIO_MASK	    0xC0000000	    /* GPIO_MASK */
+#define GPIO_IN_SEL	    0x40000000	    /* GPIO_IN value put in GPIO_ISx for the GPIO nb 0 */
+					    /* For the other GPIO number, you must shift */
 
-#define GPIO0           0
-#define GPIO1           1
+#define GPIO0		0
+#define GPIO1		1
 
 
-/*#define MAX_SELECTION_NB      CORE_NB */
-#define MAX_CORE_SELECT_NB      22
+/*#define MAX_SELECTION_NB	CORE_NB */
+#define MAX_CORE_SELECT_NB	22
 
 /*----------------------------------------------------------------------------+
   | PPC440EP GPIOs addresses.
   +----------------------------------------------------------------------------*/
-#define GPIO0_BASE       0xEF600B00
-#define GPIO0_REAL       0xEF600B00
+#define GPIO0_BASE	 0xEF600B00
+#define GPIO0_REAL	 0xEF600B00
 
-#define GPIO1_BASE       0xEF600C00
-#define GPIO1_REAL       0xEF600C00
+#define GPIO1_BASE	 0xEF600C00
+#define GPIO1_REAL	 0xEF600C00
 
 /* Offsets */
-#define GPIOx_OR    0x00        /* GPIO Output Register */
-#define GPIOx_TCR   0x04        /* GPIO Three-State Control Register */
-#define GPIOx_OSL   0x08        /* GPIO Output Select Register (Bits 0-31) */
-#define GPIOx_OSH   0x0C        /* GPIO Ouput Select Register (Bits 32-63) */
-#define GPIOx_TSL   0x10        /* GPIO Three-State Select Register (Bits 0-31) */
-#define GPIOx_TSH   0x14        /* GPIO Three-State Select Register  (Bits 32-63) */
-#define GPIOx_ODR   0x18        /* GPIO Open drain Register */
-#define GPIOx_IR    0x1C        /* GPIO Input Register */
-#define GPIOx_RR1   0x20        /* GPIO Receive Register 1 */
-#define GPIOx_RR2   0x24        /* GPIO Receive Register 2 */
-#define GPIOx_RR3   0x28        /* GPIO Receive Register 3 */
-#define GPIOx_IS1L  0x30        /* GPIO Input Select Register 1 (Bits 0-31) */
-#define GPIOx_IS1H  0x34        /* GPIO Input Select Register 1 (Bits 32-63) */
-#define GPIOx_IS2L  0x38        /* GPIO Input Select Register 2 (Bits 0-31) */
-#define GPIOx_IS2H  0x3C        /* GPIO Input Select Register 2 (Bits 32-63) */
-#define GPIOx_IS3L  0x40        /* GPIO Input Select Register 3 (Bits 0-31) */
-#define GPIOx_IS3H  0x44        /* GPIO Input Select Register 3 (Bits 32-63) */
+#define GPIOx_OR    0x00	/* GPIO Output Register */
+#define GPIOx_TCR   0x04	/* GPIO Three-State Control Register */
+#define GPIOx_OSL   0x08	/* GPIO Output Select Register (Bits 0-31) */
+#define GPIOx_OSH   0x0C	/* GPIO Ouput Select Register (Bits 32-63) */
+#define GPIOx_TSL   0x10	/* GPIO Three-State Select Register (Bits 0-31) */
+#define GPIOx_TSH   0x14	/* GPIO Three-State Select Register  (Bits 32-63) */
+#define GPIOx_ODR   0x18	/* GPIO Open drain Register */
+#define GPIOx_IR    0x1C	/* GPIO Input Register */
+#define GPIOx_RR1   0x20	/* GPIO Receive Register 1 */
+#define GPIOx_RR2   0x24	/* GPIO Receive Register 2 */
+#define GPIOx_RR3   0x28	/* GPIO Receive Register 3 */
+#define GPIOx_IS1L  0x30	/* GPIO Input Select Register 1 (Bits 0-31) */
+#define GPIOx_IS1H  0x34	/* GPIO Input Select Register 1 (Bits 32-63) */
+#define GPIOx_IS2L  0x38	/* GPIO Input Select Register 2 (Bits 0-31) */
+#define GPIOx_IS2H  0x3C	/* GPIO Input Select Register 2 (Bits 32-63) */
+#define GPIOx_IS3L  0x40	/* GPIO Input Select Register 3 (Bits 0-31) */
+#define GPIOx_IS3H  0x44	/* GPIO Input Select Register 3 (Bits 32-63) */
 
 /* GPIO0 */
-#define GPIO0_IS1L      (GPIO0_BASE+GPIOx_IS1L)
-#define GPIO0_IS1H      (GPIO0_BASE+GPIOx_IS1H)
-#define GPIO0_IS2L      (GPIO0_BASE+GPIOx_IS2L)
-#define GPIO0_IS2H      (GPIO0_BASE+GPIOx_IS2H)
-#define GPIO0_IS3L      (GPIO0_BASE+GPIOx_IS3L)
-#define GPIO0_IS3H      (GPIO0_BASE+GPIOx_IS3L)
+#define GPIO0_IS1L	(GPIO0_BASE+GPIOx_IS1L)
+#define GPIO0_IS1H	(GPIO0_BASE+GPIOx_IS1H)
+#define GPIO0_IS2L	(GPIO0_BASE+GPIOx_IS2L)
+#define GPIO0_IS2H	(GPIO0_BASE+GPIOx_IS2H)
+#define GPIO0_IS3L	(GPIO0_BASE+GPIOx_IS3L)
+#define GPIO0_IS3H	(GPIO0_BASE+GPIOx_IS3L)
 
 /* GPIO1 */
-#define GPIO1_IS1L      (GPIO1_BASE+GPIOx_IS1L)
-#define GPIO1_IS1H      (GPIO1_BASE+GPIOx_IS1H)
-#define GPIO1_IS2L      (GPIO1_BASE+GPIOx_IS2L)
-#define GPIO1_IS2H      (GPIO1_BASE+GPIOx_IS2H)
-#define GPIO1_IS3L      (GPIO1_BASE+GPIOx_IS3L)
-#define GPIO1_IS3H      (GPIO1_BASE+GPIOx_IS3L)
+#define GPIO1_IS1L	(GPIO1_BASE+GPIOx_IS1L)
+#define GPIO1_IS1H	(GPIO1_BASE+GPIOx_IS1H)
+#define GPIO1_IS2L	(GPIO1_BASE+GPIOx_IS2L)
+#define GPIO1_IS2H	(GPIO1_BASE+GPIOx_IS2H)
+#define GPIO1_IS3L	(GPIO1_BASE+GPIOx_IS3L)
+#define GPIO1_IS3H	(GPIO1_BASE+GPIOx_IS3L)
 
-#define GPIO_OS(x)      (x+GPIOx_OSL)    /* GPIO Output Register High or Low */
-#define GPIO_TS(x)      (x+GPIOx_TSL)    /* GPIO Three-state Control Reg High or Low */
-#define GPIO_IS1(x)     (x+GPIOx_IS1L)   /* GPIO Input register1 High or Low */
-#define GPIO_IS2(x)     (x+GPIOx_IS2L)   /* GPIO Input register2 High or Low */
-#define GPIO_IS3(x)     (x+GPIOx_IS3L)   /* GPIO Input register3 High or Low */
+#define GPIO_OS(x)	(x+GPIOx_OSL)	 /* GPIO Output Register High or Low */
+#define GPIO_TS(x)	(x+GPIOx_TSL)	 /* GPIO Three-state Control Reg High or Low */
+#define GPIO_IS1(x)	(x+GPIOx_IS1L)	 /* GPIO Input register1 High or Low */
+#define GPIO_IS2(x)	(x+GPIOx_IS2L)	 /* GPIO Input register2 High or Low */
+#define GPIO_IS3(x)	(x+GPIOx_IS3L)	 /* GPIO Input register3 High or Low */
 
 
 /*----------------------------------------------------------------------------+
@@ -337,27 +337,27 @@
 typedef enum gpio_select { GPIO_SEL, GPIO_ALT1, GPIO_ALT2, GPIO_ALT3 } gpio_select_t;
 typedef enum gpio_driver { GPIO_DIS, GPIO_IN, GPIO_OUT, GPIO_BI } gpio_driver_t;
 
-typedef struct { unsigned long  add;    /* gpio core base address */
+typedef struct { unsigned long	add;	/* gpio core base address */
 	gpio_driver_t  in_out; /* Driver Setting */
 	gpio_select_t  alt_nb; /* Selected Alternate */
 } gpio_param_s;
 
 /*----------------------------------------------------------------------------+
-  |                     XX     XX
+  |			XX     XX
   |
   | XXXXXX   XXX XX    XXX    XXX
-  |    XX    XX X XX    XX     XX
-  |   XX     XX X XX    XX     XX
-  |  XX      XX   XX    XX     XX
+  |    XX    XX X XX	XX     XX
+  |   XX     XX X XX	XX     XX
+  |  XX	     XX	  XX	XX     XX
   | XXXXXX   XXX  XXX  XXXX   XXXX
   +----------------------------------------------------------------------------*/
 /*----------------------------------------------------------------------------+
   | Defines
   +----------------------------------------------------------------------------*/
 typedef enum zmii_config { ZMII_CONFIGURATION_UNKNOWN,
-                           ZMII_CONFIGURATION_IS_MII,
-                           ZMII_CONFIGURATION_IS_RMII,
-                           ZMII_CONFIGURATION_IS_SMII
+			   ZMII_CONFIGURATION_IS_MII,
+			   ZMII_CONFIGURATION_IS_RMII,
+			   ZMII_CONFIGURATION_IS_SMII
 } zmii_config_t;
 
 /*----------------------------------------------------------------------------+
@@ -366,36 +366,36 @@ typedef enum zmii_config { ZMII_CONFIGURATION_UNKNOWN,
 typedef enum uart_config_nb { L1, L2, L3, L4 } uart_config_nb_t;
 typedef enum core_selection { CORE_NOT_SELECTED, CORE_SELECTED} core_selection_t;
 typedef enum config_list {  IIC_CORE,
-                            SCP_CORE,
-                            DMA_CHANNEL_AB,
-                            UIC_4_9,
-                            USB2_HOST,
-                            DMA_CHANNEL_CD,
-                            USB2_DEVICE,
-                            PACKET_REJ_FUNC_AVAIL,
-                            USB1_DEVICE,
-                            EBC_MASTER,
-                            NAND_FLASH,
-                            UART_CORE0,
-                            UART_CORE1,
-                            UART_CORE2,
-                            UART_CORE3,
-                            MII_SEL,
-                            RMII_SEL,
-                            SMII_SEL,
-                            PACKET_REJ_FUNC_EN,
-                            UIC_0_3,
-                            USB1_HOST,
-                            PCI_PATCH,
-                            CORE_NB
+			    SCP_CORE,
+			    DMA_CHANNEL_AB,
+			    UIC_4_9,
+			    USB2_HOST,
+			    DMA_CHANNEL_CD,
+			    USB2_DEVICE,
+			    PACKET_REJ_FUNC_AVAIL,
+			    USB1_DEVICE,
+			    EBC_MASTER,
+			    NAND_FLASH,
+			    UART_CORE0,
+			    UART_CORE1,
+			    UART_CORE2,
+			    UART_CORE3,
+			    MII_SEL,
+			    RMII_SEL,
+			    SMII_SEL,
+			    PACKET_REJ_FUNC_EN,
+			    UIC_0_3,
+			    USB1_HOST,
+			    PCI_PATCH,
+			    CORE_NB
 } core_list_t;
 
 typedef enum block3_value { B3_V1,  B3_V2,  B3_V3,  B3_V4,  B3_V5,
-                            B3_V6,  B3_V7,  B3_V8,  B3_V9,  B3_V10,
-                            B3_V11, B3_V12, B3_V13, B3_V14, B3_V15,
-                            B3_V16, B3_VALUE_UNKNOWN
+			    B3_V6,  B3_V7,  B3_V8,  B3_V9,  B3_V10,
+			    B3_V11, B3_V12, B3_V13, B3_V14, B3_V15,
+			    B3_V16, B3_VALUE_UNKNOWN
 } block3_value_t;
 
 typedef enum config_validity { CONFIG_IS_VALID,
-                               CONFIG_IS_INVALID
+			       CONFIG_IS_INVALID
 } config_validity_t;

board/ep8248/Makefile

@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################

board/ep8248/config.mk

@@ -0,0 +1,30 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Modified by, Yuli Barcohen, Arabella Software Ltd. <yuli@arabellasw.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# EP82xx series boards by Embedded Planet
+#
+
+TEXT_BASE = 0xFFF00000

board/ep8248/ep8248.c

@@ -0,0 +1,263 @@
+/*
+ * Copyright (C) 2004 Arabella Software Ltd.
+ * Yuli Barcohen <yuli@arabellasw.com>
+ *
+ * Support for Embedded Planet EP8248 boards.
+ * Tested on EP8248E.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8260.h>
+#include <ioports.h>
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+#define CFG_FCC1 (CONFIG_ETHER_INDEX == 1)
+#define CFG_FCC2 (CONFIG_ETHER_INDEX == 2)
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A */
+    {	/*	      conf      ppar psor pdir podr pdat */
+	/* PA31 */ { CFG_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII COL    */
+	/* PA30 */ { CFG_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII CRS    */
+	/* PA29 */ { CFG_FCC1,   1,   1,   1,   0,   0 }, /* FCC1 MII TX_ER  */
+	/* PA28 */ { CFG_FCC1,   1,   1,   1,   0,   0 }, /* FCC1 MII TX_EN  */
+	/* PA27 */ { CFG_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII RX_DV  */
+	/* PA26 */ { CFG_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII RX_ER  */
+	/* PA25 */ { 0,          0,   0,   0,   0,   0 }, /* PA25            */
+	/* PA24 */ { 0,          0,   0,   0,   0,   0 }, /* PA24            */
+	/* PA23 */ { 0,          0,   0,   0,   0,   0 }, /* PA23            */
+	/* PA22 */ { 0,          0,   0,   0,   0,   0 }, /* PA22            */
+	/* PA21 */ { CFG_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[3] */
+	/* PA20 */ { CFG_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[2] */
+	/* PA19 */ { CFG_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[1] */
+	/* PA18 */ { CFG_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[0] */
+	/* PA17 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[0] */
+	/* PA16 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[1] */
+	/* PA15 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[2] */
+	/* PA14 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[3] */
+	/* PA13 */ { 0,          0,   0,   0,   0,   0 }, /* PA13            */
+	/* PA12 */ { 0,          0,   0,   0,   0,   0 }, /* PA12            */
+	/* PA11 */ { 0,          0,   0,   0,   0,   0 }, /* PA11            */
+	/* PA10 */ { 0,          0,   0,   0,   0,   0 }, /* PA10            */
+	/* PA9  */ { 0,          1,   0,   1,   0,   0 }, /* SMC2 TxD        */
+	/* PA8  */ { 0,          1,   0,   0,   0,   0 }, /* SMC2 RxD        */
+	/* PA7  */ { 0,          0,   0,   0,   0,   0 }, /* PA7             */
+	/* PA6  */ { 0,          0,   0,   0,   0,   0 }, /* PA6             */
+	/* PA5  */ { 0,          0,   0,   0,   0,   0 }, /* PA5             */
+	/* PA4  */ { 0,          0,   0,   0,   0,   0 }, /* PA4             */
+	/* PA3  */ { 0,          0,   0,   0,   0,   0 }, /* PA3             */
+	/* PA2  */ { 0,          0,   0,   0,   0,   0 }, /* PA2             */
+	/* PA1  */ { 0,          0,   0,   0,   0,   0 }, /* PA1             */
+	/* PA0  */ { 0,          0,   0,   0,   0,   0 }  /* PA0             */
+    },
+
+    /* Port B */
+    {   /*	      conf      ppar psor pdir podr pdat */
+	/* PB31 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TX_ER  */
+	/* PB30 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RX_DV  */
+	/* PB29 */ { CFG_FCC2,   1,   1,   1,   0,   0 }, /* FCC2 MII TX_EN  */
+	/* PB28 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RX_ER  */
+	/* PB27 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII COL    */
+	/* PB26 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII CRS    */
+	/* PB25 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[3] */
+	/* PB24 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[2] */
+	/* PB23 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[1] */
+	/* PB22 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[0] */
+	/* PB21 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[0] */
+	/* PB20 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[1] */
+	/* PB19 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[2] */
+	/* PB18 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[3] */
+	/* PB17 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB16 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB15 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB14 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB13 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB12 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB11 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB10 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB9  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB8  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB7  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB6  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB5  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB4  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB3  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB2  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB1  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB0  */ { 0,          0,   0,   0,   0,   0 }  /* non-existent    */
+    },
+
+    /* Port C */
+    {   /*	      conf      ppar psor pdir podr pdat */
+	/* PC31 */ { 0,          0,   0,   0,   0,   0 }, /* PC31            */
+	/* PC30 */ { 0,          0,   0,   0,   0,   0 }, /* PC30            */
+	/* PC29 */ { 0,          0,   0,   0,   0,   0 }, /* PC29            */
+	/* PC28 */ { 0,          0,   0,   0,   0,   0 }, /* PC28            */
+	/* PC27 */ { 0,          0,   0,   0,   0,   0 }, /* PC27            */
+	/* PC26 */ { 0,          0,   0,   0,   0,   0 }, /* PC26            */
+	/* PC25 */ { 0,          0,   0,   0,   0,   0 }, /* PC25            */
+	/* PC24 */ { 0,          0,   0,   0,   0,   0 }, /* PC24            */
+	/* PC23 */ { 0,          0,   0,   0,   0,   0 }, /* PC23            */
+	/* PC22 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 RxClk (CLK10) */
+	/* PC21 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 TxClk (CLK11) */
+	/* PC20 */ { 0,          0,   0,   0,   0,   0 }, /* PC20            */
+	/* PC19 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 RxClk (CLK13) */
+	/* PC18 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 TxClk (CLK14) */
+	/* PC17 */ { 0,          0,   0,   0,   0,   0 }, /* PC17            */
+	/* PC16 */ { 0,          0,   0,   0,   0,   0 }, /* PC16            */
+	/* PC15 */ { 0,          0,   0,   0,   0,   0 }, /* PC15            */
+	/* PC14 */ { 0,          0,   0,   0,   0,   0 }, /* PC14            */
+	/* PC13 */ { 0,          0,   0,   0,   0,   0 }, /* PC13            */
+	/* PC12 */ { 0,          0,   0,   0,   0,   0 }, /* PC12            */
+	/* PC11 */ { 0,          0,   0,   0,   0,   0 }, /* PC11            */
+	/* PC10 */ { 0,          0,   0,   0,   0,   0 }, /* PC10            */
+	/* PC9  */ { 1,          0,   0,   1,   0,   1 }, /* MDIO            */
+	/* PC8  */ { 1,          0,   0,   1,   0,   1 }, /* MDC             */
+	/* PC7  */ { 0,          0,   0,   0,   0,   0 }, /* PC7             */
+	/* PC6  */ { 0,          0,   0,   0,   0,   0 }, /* PC6             */
+	/* PC5  */ { 1,          1,   0,   1,   0,   0 }, /* SMC1 TxD        */
+	/* PC4  */ { 1,          1,   0,   0,   0,   0 }, /* SMC1 RxD        */
+	/* PC3  */ { 0,          0,   0,   0,   0,   0 }, /* PC3             */
+	/* PC2  */ { 0,          0,   0,   0,   0,   0 }, /* PC2             */
+	/* PC1  */ { 0,          0,   0,   0,   0,   0 }, /* PC1             */
+	/* PC0  */ { 0,          0,   0,   0,   0,   0 }, /* PC0             */
+    },
+
+    /* Port D */
+    {   /*	      conf      ppar psor pdir podr pdat */
+	/* PD31 */ { 1,          1,   0,   0,   0,   0 }, /* SCC1 RxD        */
+	/* PD30 */ { 1,          1,   1,   1,   0,   0 }, /* SCC1 TxD        */
+	/* PD29 */ { 0,          0,   0,   0,   0,   0 }, /* PD29            */
+	/* PD28 */ { 0,          0,   0,   0,   0,   0 }, /* PD28            */
+	/* PD27 */ { 0,          0,   0,   0,   0,   0 }, /* PD27            */
+	/* PD26 */ { 0,          0,   0,   0,   0,   0 }, /* PD26            */
+	/* PD25 */ { 0,          0,   0,   0,   0,   0 }, /* PD25            */
+	/* PD24 */ { 0,          0,   0,   0,   0,   0 }, /* PD24            */
+	/* PD23 */ { 0,          0,   0,   0,   0,   0 }, /* PD23            */
+	/* PD22 */ { 0,          0,   0,   0,   0,   0 }, /* PD22            */
+	/* PD21 */ { 0,          0,   0,   0,   0,   0 }, /* PD21            */
+	/* PD20 */ { 0,          0,   0,   0,   0,   0 }, /* PD20            */
+	/* PD19 */ { 0,          0,   0,   0,   0,   0 }, /* PD19            */
+	/* PD18 */ { 0,          0,   0,   0,   0,   0 }, /* PD18            */
+	/* PD17 */ { 0,          0,   0,   0,   0,   0 }, /* PD17            */
+	/* PD16 */ { 0,          0,   0,   0,   0,   0 }, /* PD16            */
+	/* PD15 */ { 1,          1,   1,   0,   1,   0 }, /* I2C SDA         */
+	/* PD14 */ { 1,          1,   1,   0,   1,   0 }, /* I2C SCL         */
+	/* PD13 */ { 0,          0,   0,   0,   0,   0 }, /* PD13            */
+	/* PD12 */ { 0,          0,   0,   0,   0,   0 }, /* PD12            */
+	/* PD11 */ { 0,          0,   0,   0,   0,   0 }, /* PD11            */
+	/* PD10 */ { 0,          0,   0,   0,   0,   0 }, /* PD10            */
+	/* PD9  */ { 0,          0,   0,   0,   0,   0 }, /* PD9             */
+	/* PD8  */ { 0,          0,   0,   0,   0,   0 }, /* PD8             */
+	/* PD7  */ { 0,          0,   0,   0,   0,   0 }, /* PD7             */
+	/* PD6  */ { 0,          0,   0,   0,   0,   0 }, /* PD6             */
+	/* PD5  */ { 0,          0,   0,   0,   0,   0 }, /* PD5             */
+	/* PD4  */ { 0,          0,   0,   0,   0,   0 }, /* PD4             */
+	/* PD3  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PD2  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PD1  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PD0  */ { 0,          0,   0,   0,   0,   0 }  /* non-existent    */
+    }
+};
+
+int board_early_init_f (void)
+{
+	vu_char *bcsr = (vu_char *)CFG_BCSR;
+
+	bcsr[4] |= 0x30; /* Turn the LEDs off */
+
+#if defined(CONFIG_CONS_ON_SMC) || defined(CONFIG_KGDB_ON_SMC)
+	bcsr[6] |= 0x10;
+#endif
+#if defined(CONFIG_CONS_ON_SCC) || defined(CONFIG_KGDB_ON_SCC)
+	bcsr[7] |= 0x10;
+#endif
+
+#if CFG_FCC1
+	bcsr[8] |= 0xC0;
+#endif /* CFG_FCC1 */
+#if CFG_FCC2
+	bcsr[8] |= 0x30;
+#endif /* CFG_FCC2 */
+
+	return 0;
+}
+
+long int initdram(int board_type)
+{
+	vu_char *bcsr = (vu_char *)CFG_BCSR;
+	long int msize = 16L << (bcsr[2] & 3);
+
+#ifndef CFG_RAMBOOT
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+	vu_char *ramaddr = (vu_char *)CFG_SDRAM_BASE;
+	uchar c = 0xFF;
+	uint psdmr = CFG_PSDMR;
+	int i;
+
+	immap->im_siu_conf.sc_ppc_acr  = 0x02;
+	immap->im_siu_conf.sc_ppc_alrh = 0x30126745;
+	immap->im_siu_conf.sc_tescr1   = 0x00004000;
+
+	memctl->memc_mptpr = CFG_MPTPR;
+
+	/* Initialise 60x bus SDRAM */
+	memctl->memc_psrt = CFG_PSRT;
+	memctl->memc_or1  = CFG_SDRAM_OR;
+	memctl->memc_br1  = CFG_SDRAM_BR;
+	memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; /* Precharge all banks */
+	*ramaddr = c;
+	memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */
+	for (i = 0; i < 8; i++)
+		*ramaddr = c;
+	memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;  /* Mode Register write */
+	*ramaddr = c;
+	memctl->memc_psdmr = psdmr | PSDMR_RFEN;    /* Refresh enable */
+	*ramaddr = c;
+#endif /* !CFG_RAMBOOT */
+
+	/* Return total 60x bus SDRAM size */
+	return msize * 1024 * 1024;
+}
+
+int checkboard(void)
+{
+	vu_char *bcsr = (vu_char *)CFG_BCSR;
+
+	puts("Board: ");
+	switch (bcsr[0]) {
+	case 0x0C:
+		printf("EP8248E 1.0 CPLD revision %d\n", bcsr[1]);
+		break;
+	default:
+		printf("unknown: ID=%02X\n", bcsr[0]);
+	}
+
+	return 0;
+}

board/ep8248/u-boot.lds

@@ -0,0 +1,122 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Modified by Yuli Barcohen <yuli@arabellasw.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc8260/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
+ENTRY(_start)

cpu/ppc4xx/start.S

@@ -158,8 +158,8 @@ _start_440:
 	/*----------------------------------------------------------------*/
 	/* Clear and set up some registers. */
 	/*----------------------------------------------------------------*/
-	iccci	r0,r0           /* NOTE: operands not used for 440 */
-	dccci	r0,r0           /* NOTE: operands not used for 440 */
+	iccci	r0,r0		/* NOTE: operands not used for 440 */
+	dccci	r0,r0		/* NOTE: operands not used for 440 */
 	sync
 	li	r0,0
 	mtspr	srr0,r0
@@ -167,10 +167,10 @@ _start_440:
 	mtspr	csrr0,r0
 	mtspr	csrr1,r0
 #if defined (CONFIG_440_GX) /* NOTE: 440GX adds machine check status regs */
-	mtspr   mcsrr0,r0
-	mtspr   mcsrr1,r0
-	mfspr   r1, mcsr
-	mtspr   mcsr,r1
+	mtspr	mcsrr0,r0
+	mtspr	mcsrr1,r0
+	mfspr	r1, mcsr
+	mtspr	mcsr,r1
 #endif
 	/*----------------------------------------------------------------*/
 	/* Initialize debug */
@@ -204,13 +204,13 @@ _start_440:
 	/* Setup interrupt vectors */
 	/*----------------------------------------------------------------*/
 	mtspr	ivpr,r0		/* Vectors start at 0x0000_0000 */
-	li      r1,0x0100
+	li	r1,0x0100
 	mtspr	ivor0,r1	/* Critical input */
-	li      r1,0x0200
+	li	r1,0x0200
 	mtspr	ivor1,r1	/* Machine check */
-	li      r1,0x0300
+	li	r1,0x0300
 	mtspr	ivor2,r1	/* Data storage */
-	li      r1,0x0400
+	li	r1,0x0400
 	mtspr	ivor3,r1	/* Instruction storage */
 	li	r1,0x0500
 	mtspr	ivor4,r1	/* External interrupt */
@@ -349,8 +349,8 @@ _start:
 	b	__440gx_msr_continue
 
 __440gx_msr_set:
-	lis 	r1, 0x0002		/* set CE bit (Critical Exceptions) */
-	ori 	r1,r1,0x1000	/* set ME bit (Machine Exceptions) */
+	lis	r1, 0x0002		/* set CE bit (Critical Exceptions) */
+	ori	r1,r1,0x1000	/* set ME bit (Machine Exceptions) */
 	mtspr	srr1,r1
 	mflr	r1
 	mtspr	srr0,r1
@@ -379,23 +379,23 @@ __440gx_msr_continue:
 	li	r0,0
 #if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
 	/* Clear Dcache to use as RAM */
-        addis   r3,r0,CFG_INIT_RAM_ADDR@h
-        ori     r3,r3,CFG_INIT_RAM_ADDR@l
-        addis   r4,r0,CFG_INIT_RAM_END@h
-        ori     r4,r4,CFG_INIT_RAM_END@l
+	addis	r3,r0,CFG_INIT_RAM_ADDR@h
+	ori	r3,r3,CFG_INIT_RAM_ADDR@l
+	addis	r4,r0,CFG_INIT_RAM_END@h
+	ori	r4,r4,CFG_INIT_RAM_END@l
 	rlwinm. r5,r4,0,27,31
-	rlwinm  r5,r4,27,5,31
-	beq     ..d_ran
-	addi    r5,r5,0x0001
+	rlwinm	r5,r4,27,5,31
+	beq	..d_ran
+	addi	r5,r5,0x0001
 ..d_ran:
-	mtctr   r5
+	mtctr	r5
 ..d_ag:
-	dcbz    r0,r3
-	addi    r3,r3,32
-	bdnz    ..d_ag
+	dcbz	r0,r3
+	addi	r3,r3,32
+	bdnz	..d_ag
 #else
 #if defined (CONFIG_440_GX)
-	mtdcr   l2_cache_cfg,r0		/* Ensure L2 Cache is off */
+	mtdcr	l2_cache_cfg,r0		/* Ensure L2 Cache is off */
 #endif
 	mtdcr	isram0_sb1cr,r0		/* Disable bank 1 */
 
@@ -411,16 +411,16 @@ __440gx_msr_continue:
 	lis	r1,0x8000		/* BAS = 8000_0000 */
 #if defined(CONFIG_440_GX)
 	ori	r1,r1,0x0980		/* first 64k */
-	mtdcr   isram0_sb0cr,r1
+	mtdcr	isram0_sb0cr,r1
 	lis	r1,0x8001
 	ori	r1,r1,0x0980		/* second 64k */
-	mtdcr   isram0_sb1cr,r1
+	mtdcr	isram0_sb1cr,r1
 	lis	r1, 0x8002
 	ori	r1,r1, 0x0980		/* third 64k */
-	mtdcr   isram0_sb2cr,r1
+	mtdcr	isram0_sb2cr,r1
 	lis	r1, 0x8003
 	ori	r1,r1, 0x0980		/* fourth 64k */
-	mtdcr   isram0_sb3cr,r1
+	mtdcr	isram0_sb3cr,r1
 #else
 	ori	r1,r1,0x0380		/* 8k rw */
 	mtdcr	isram0_sb0cr,r1
@@ -610,11 +610,11 @@ __440gx_msr_continue:
 	/*----------------------------------------------------------------------- */
 	/* DMA Status, clear to come up clean */
 	/*----------------------------------------------------------------------- */
-	addis   r3,r0, 0xFFFF         /* Clear all existing DMA status */
-	ori     r3,r3, 0xFFFF
-	mtdcr   dmasr, r3
+	addis	r3,r0, 0xFFFF	      /* Clear all existing DMA status */
+	ori	r3,r3, 0xFFFF
+	mtdcr	dmasr, r3
 
-	bl	ppc405ep_init         /* do ppc405ep specific init */
+	bl	ppc405ep_init	      /* do ppc405ep specific init */
 #endif /* CONFIG_405EP */
 
 #if defined(CFG_OCM_DATA_ADDR) && defined(CFG_OCM_DATA_SIZE)
@@ -624,7 +624,7 @@ __440gx_msr_continue:
 	/* Setup OCM */
 	lis	r0, 0x7FFF
 	ori	r0, r0, 0xFFFF
-	mfdcr	r3, ocmiscntl 		/* get instr-side IRAM config */
+	mfdcr	r3, ocmiscntl		/* get instr-side IRAM config */
 	mfdcr	r4, ocmdscntl	/* get data-side IRAM config */
 	and	r3, r3, r0	/* disable data-side IRAM */
 	and	r4, r4, r0	/* disable data-side IRAM */
@@ -666,13 +666,13 @@ __440gx_msr_continue:
 	/* set stack pointer and clear stack to known value */
 
 	lis	r1,CFG_INIT_RAM_ADDR@h
-	ori     r1,r1,CFG_INIT_SP_OFFSET@l
+	ori	r1,r1,CFG_INIT_SP_OFFSET@l
 
 	li	r4,2048			/* we store 2048 words to stack */
 	mtctr	r4
 
 	lis	r2,CFG_INIT_RAM_ADDR@h		/* we also clear data area */
-	ori	r2,r2,CFG_INIT_RAM_END@l 	/* so cant copy value from r1 */
+	ori	r2,r2,CFG_INIT_RAM_END@l	/* so cant copy value from r1 */
 
 	lis	r4,0xdead		/* we store 0xdeaddead in the stack */
 	ori	r4,r4,0xdead
@@ -721,7 +721,7 @@ __440gx_msr_continue:
 #endif /* CFG_INIT_DCACHE_CS */
 
 	/*----------------------------------------------------------------------- */
-	/* Initialize SDRAM Controller  */
+	/* Initialize SDRAM Controller	*/
 	/*----------------------------------------------------------------------- */
 	bl	sdram_init
 
@@ -747,11 +747,11 @@ __440gx_msr_continue:
 	ori	r0, r0, RESET_VECTOR@l
 	stwu	r1, -8(r1)		/* Save back chain and move SP */
 	stw	r0, +12(r1)		/* Save return addr (underflow vect) */
-#endif /* !(CFG_INIT_DCACHE_CS  || !CFG_TEM_STACK_OCM) */
+#endif /* !(CFG_INIT_DCACHE_CS	|| !CFG_TEM_STACK_OCM) */
 
 	GET_GOT			/* initialize GOT access			*/
 
-	bl	cpu_init_f	/* run low-level CPU init code     (from Flash)	*/
+	bl	cpu_init_f	/* run low-level CPU init code	   (from Flash) */
 
 	/* NEVER RETURNS! */
 	bl	board_init_f	/* run first part of init code (from Flash)	*/
@@ -976,8 +976,8 @@ invalidate_dcache:
 	addi	r6,0,0x0000		/* clear GPR 6 */
 	/* Do loop for # of dcache congruence classes. */
 #if defined(CONFIG_440_GX) || defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
-	lis     r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha	/* TBS for large sized cache */
-	ori     r7, r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l
+	lis	r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha	/* TBS for large sized cache */
+	ori	r7, r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l
 #else
 	addi	r7,r0, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)
 #endif
@@ -1002,16 +1002,16 @@ flush_dcache:
 
 	/* do loop for # of congruence classes. */
 #if defined(CONFIG_440_GX) || defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
-	lis     r10,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha	/* TBS: for large cache sizes */
-	ori     r10,r10,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l
-	lis     r11,(CFG_DCACHE_SIZE / 2)@ha /* D cache set size - 2 way sets */
-	ori     r11,r11,(CFG_DCACHE_SIZE / 2)@l /* D cache set size - 2 way sets */
+	lis	r10,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha	/* TBS: for large cache sizes */
+	ori	r10,r10,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l
+	lis	r11,(CFG_DCACHE_SIZE / 2)@ha /* D cache set size - 2 way sets */
+	ori	r11,r11,(CFG_DCACHE_SIZE / 2)@l /* D cache set size - 2 way sets */
 #else
 	addi	r10,r0,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)
 	addi	r11,r0,(CFG_DCACHE_SIZE / 2) /* D cache set size - 2 way sets */
 #endif
 	mtctr	r10
-	addi	r10,r0,(0xE000-0x10000)	/* start at 0xFFFFE000 */
+	addi	r10,r0,(0xE000-0x10000) /* start at 0xFFFFE000 */
 	add	r11,r10,r11		/* add to get to other side of cache line */
 ..flush_dcache_loop:
 	lwz	r3,0(r10)		/* least recently used side */
@@ -1229,12 +1229,12 @@ ppcSync:
 	.globl	relocate_code
 relocate_code:
 #if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
-	dccci	0,0		            /* Invalidate data cache, now no longer our stack */
+	dccci	0,0			    /* Invalidate data cache, now no longer our stack */
 	sync
-	addi    r1,r0,0x0000        /* Tlb entry #0 */
+	addi	r1,r0,0x0000	    /* Tlb entry #0 */
 	tlbre	r0,r1,0x0002		/* Read contents */
-	ori     r0,r0,0x0c00        /* Or in the inhibit, write through bit */
-	tlbwe   r0,r1,0x0002		/* Save it out */
+	ori	r0,r0,0x0c00	    /* Or in the inhibit, write through bit */
+	tlbwe	r0,r1,0x0002		/* Save it out */
 	isync
 #endif
 	mr	r1,  r3		/* Set new stack pointer		*/
@@ -1455,7 +1455,7 @@ trap_reloc:
 
 
 /**************************************************************************/
-/* PPC405EP specific stuff                                                */
+/* PPC405EP specific stuff						  */
 /**************************************************************************/
 #ifdef CONFIG_405EP
 ppc405ep_init:
@@ -1539,7 +1539,7 @@ ppc405ep_init:
 	mtdcr	ebccfgd,r3
 #endif
 
-	addi    r3,0,CPC0_PCI_HOST_CFG_EN
+	addi	r3,0,CPC0_PCI_HOST_CFG_EN
 #ifdef CONFIG_BUBINGA
 	/*
 	!-----------------------------------------------------------------------
@@ -1547,30 +1547,30 @@ ppc405ep_init:
 	!   If board is set to internal arbitration, update cpc0_pci
 	!-----------------------------------------------------------------------
 	*/
-	addis   r5,r0,FPGA_REG1@h      /* set offset for FPGA_REG1 */
-	ori     r5,r5,FPGA_REG1@l
-	lbz     r5,0x0(r5)              /* read to get PCI arb selection */
-	andi.   r6,r5,FPGA_REG1_PCI_INT_ARB  /* using internal arbiter ?*/
-	beq     ..pci_cfg_set             /* if not set, then bypass reg write*/
+	addis	r5,r0,FPGA_REG1@h      /* set offset for FPGA_REG1 */
+	ori	r5,r5,FPGA_REG1@l
+	lbz	r5,0x0(r5)		/* read to get PCI arb selection */
+	andi.	r6,r5,FPGA_REG1_PCI_INT_ARB  /* using internal arbiter ?*/
+	beq	..pci_cfg_set		  /* if not set, then bypass reg write*/
 #endif
-	ori     r3,r3,CPC0_PCI_ARBIT_EN
+	ori	r3,r3,CPC0_PCI_ARBIT_EN
 ..pci_cfg_set:
-	mtdcr   CPC0_PCI, r3             /* Enable internal arbiter*/
+	mtdcr	CPC0_PCI, r3		 /* Enable internal arbiter*/
 
 	/*
 	!-----------------------------------------------------------------------
 	! Check to see if chip is in bypass mode.
 	! If so, write stored CPC0_PLLMR0 and CPC0_PLLMR1 values and perform a
 	! CPU reset   Otherwise, skip this step and keep going.
-	! Note:  Running BIOS in bypass mode is not supported since PLB speed
-	!        will not be fast enough for the SDRAM (min 66MHz)
+	! Note:	 Running BIOS in bypass mode is not supported since PLB speed
+	!	 will not be fast enough for the SDRAM (min 66MHz)
 	!-----------------------------------------------------------------------
 	*/
-	mfdcr   r5, CPC0_PLLMR1
-	rlwinm  r4,r5,1,0x1            /* get system clock source (SSCS) */
-	cmpi    cr0,0,r4,0x1
+	mfdcr	r5, CPC0_PLLMR1
+	rlwinm	r4,r5,1,0x1	       /* get system clock source (SSCS) */
+	cmpi	cr0,0,r4,0x1
 
-	beq    pll_done                   /* if SSCS =b'1' then PLL has */
+	beq    pll_done			  /* if SSCS =b'1' then PLL has */
 					  /* already been set */
 					  /* and CPU has been reset */
 					  /* so skip to next section */
@@ -1584,40 +1584,40 @@ ppc405ep_init:
 	! See CPU_DEFAULT_200 and CPU_DEFAULT_266 above.
 	!
 	! WARNING:  This code assumes the first three words in the nvram_t
-	!           structure in openbios.h.  Changing the beginning of
-	!           the structure will break this code.
+	!	    structure in openbios.h.  Changing the beginning of
+	!	    the structure will break this code.
 	!
 	!-----------------------------------------------------------------------
 	*/
-	addis   r3,0,NVRAM_BASE@h
-	addi    r3,r3,NVRAM_BASE@l
-
-	lwz     r4, 0(r3)
-	addis   r5,0,NVRVFY1@h
-	addi    r5,r5,NVRVFY1@l
-	cmp     cr0,0,r4,r5            /* Compare 1st NVRAM Magic number*/
-	bne     ..no_pllset
-	addi    r3,r3,4
-	lwz     r4, 0(r3)
-	addis   r5,0,NVRVFY2@h
-	addi    r5,r5,NVRVFY2@l
-	cmp     cr0,0,r4,r5            /* Compare 2 NVRAM Magic number */
-	bne     ..no_pllset
-	addi    r3,r3,8                 /* Skip over conf_size */
-	lwz     r4, 4(r3)               /* Load PLLMR1 value from NVRAM */
-	lwz     r3, 0(r3)               /* Load PLLMR0 value from NVRAM */
-	rlwinm  r5,r4,1,0x1             /* get system clock source (SSCS) */
-	cmpi     cr0,0,r5,1             /* See if PLL is locked */
-	beq     pll_write
+	addis	r3,0,NVRAM_BASE@h
+	addi	r3,r3,NVRAM_BASE@l
+
+	lwz	r4, 0(r3)
+	addis	r5,0,NVRVFY1@h
+	addi	r5,r5,NVRVFY1@l
+	cmp	cr0,0,r4,r5	       /* Compare 1st NVRAM Magic number*/
+	bne	..no_pllset
+	addi	r3,r3,4
+	lwz	r4, 0(r3)
+	addis	r5,0,NVRVFY2@h
+	addi	r5,r5,NVRVFY2@l
+	cmp	cr0,0,r4,r5	       /* Compare 2 NVRAM Magic number */
+	bne	..no_pllset
+	addi	r3,r3,8			/* Skip over conf_size */
+	lwz	r4, 4(r3)		/* Load PLLMR1 value from NVRAM */
+	lwz	r3, 0(r3)		/* Load PLLMR0 value from NVRAM */
+	rlwinm	r5,r4,1,0x1		/* get system clock source (SSCS) */
+	cmpi	 cr0,0,r5,1		/* See if PLL is locked */
+	beq	pll_write
 ..no_pllset:
 #endif /* CONFIG_BUBINGA */
 
-	addis   r3,0,PLLMR0_DEFAULT@h       /* PLLMR0 default value */
-	ori     r3,r3,PLLMR0_DEFAULT@l     /* */
-	addis   r4,0,PLLMR1_DEFAULT@h       /* PLLMR1 default value */
-	ori     r4,r4,PLLMR1_DEFAULT@l     /* */
+	addis	r3,0,PLLMR0_DEFAULT@h	    /* PLLMR0 default value */
+	ori	r3,r3,PLLMR0_DEFAULT@l	   /* */
+	addis	r4,0,PLLMR1_DEFAULT@h	    /* PLLMR1 default value */
+	ori	r4,r4,PLLMR1_DEFAULT@l	   /* */
 
-	b       pll_write                 /* Write the CPC0_PLLMR with new value */
+	b	pll_write		  /* Write the CPC0_PLLMR with new value */
 
 pll_done:
 	/*
@@ -1626,27 +1626,27 @@ pll_done:
 	! This is needed to enable PCI if not booting from serial EPROM
 	!-----------------------------------------------------------------------
 		*/
-	addi    r3, 0, 0x0
-	mtdcr   CPC0_SRR, r3
+	addi	r3, 0, 0x0
+	mtdcr	CPC0_SRR, r3
 
-	addis    r3,0,0x0010
-	mtctr   r3
+	addis	 r3,0,0x0010
+	mtctr	r3
 pci_wait:
-	bdnz    pci_wait
+	bdnz	pci_wait
 
 	blr				  /* return to main code */
 
 /*
 !-----------------------------------------------------------------------------
-! Function:     pll_write
-! Description:  Updates the value of the CPC0_PLLMR according to CMOS27E documentation
-!               That is:
-!                         1.  Pll is first disabled (de-activated by putting in bypass mode)
-!                         2.  PLL is reset
-!                         3.  Clock dividers are set while PLL is held in reset and bypassed
-!                         4.  PLL Reset is cleared
-!                         5.  Wait 100us for PLL to lock
-!                         6.  A core reset is performed
+! Function:	pll_write
+! Description:	Updates the value of the CPC0_PLLMR according to CMOS27E documentation
+!		That is:
+!			  1.  Pll is first disabled (de-activated by putting in bypass mode)
+!			  2.  PLL is reset
+!			  3.  Clock dividers are set while PLL is held in reset and bypassed
+!			  4.  PLL Reset is cleared
+!			  5.  Wait 100us for PLL to lock
+!			  6.  A core reset is performed
 ! Input: r3 = Value to write to CPC0_PLLMR0
 ! Input: r4 = Value to write to CPC0_PLLMR1
 ! Output r3 = none
@@ -1655,41 +1655,41 @@ pci_wait:
 pll_write:
 	mfdcr  r5, CPC0_UCR
 	andis. r5,r5,0xFFFF
-	ori    r5,r5,0x0101              /* Stop the UART clocks */
-	mtdcr  CPC0_UCR,r5               /* Before changing PLL */
+	ori    r5,r5,0x0101		 /* Stop the UART clocks */
+	mtdcr  CPC0_UCR,r5		 /* Before changing PLL */
 
 	mfdcr  r5, CPC0_PLLMR1
-	rlwinm r5,r5,0,0x7FFFFFFF        /* Disable PLL */
-	mtdcr   CPC0_PLLMR1,r5
-	oris   r5,r5,0x4000              /* Set PLL Reset */
-	mtdcr   CPC0_PLLMR1,r5
-
-	mtdcr   CPC0_PLLMR0,r3           /* Set clock dividers */
-	rlwinm r5,r4,0,0x3FFFFFFF        /* Reset & Bypass new PLL dividers */
-	oris   r5,r5,0x4000              /* Set PLL Reset */
-	mtdcr   CPC0_PLLMR1,r5           /* Set clock dividers */
-	rlwinm r5,r5,0,0xBFFFFFFF        /* Clear PLL Reset */
-	mtdcr   CPC0_PLLMR1,r5
+	rlwinm r5,r5,0,0x7FFFFFFF	 /* Disable PLL */
+	mtdcr	CPC0_PLLMR1,r5
+	oris   r5,r5,0x4000		 /* Set PLL Reset */
+	mtdcr	CPC0_PLLMR1,r5
+
+	mtdcr	CPC0_PLLMR0,r3		 /* Set clock dividers */
+	rlwinm r5,r4,0,0x3FFFFFFF	 /* Reset & Bypass new PLL dividers */
+	oris   r5,r5,0x4000		 /* Set PLL Reset */
+	mtdcr	CPC0_PLLMR1,r5		 /* Set clock dividers */
+	rlwinm r5,r5,0,0xBFFFFFFF	 /* Clear PLL Reset */
+	mtdcr	CPC0_PLLMR1,r5
 
 		/*
 	! Wait min of 100us for PLL to lock.
 	! See CMOS 27E databook for more info.
 	! At 200MHz, that means waiting 20,000 instructions
 		 */
-	addi    r3,0,20000              /* 2000 = 0x4e20 */
-	mtctr   r3
+	addi	r3,0,20000		/* 2000 = 0x4e20 */
+	mtctr	r3
 pll_wait:
-	bdnz    pll_wait
+	bdnz	pll_wait
 
-	oris   r5,r5,0x8000             /* Enable PLL */
-	mtdcr   CPC0_PLLMR1,r5          /* Engage */
+	oris   r5,r5,0x8000		/* Enable PLL */
+	mtdcr	CPC0_PLLMR1,r5		/* Engage */
 
 	/*
 	 * Reset CPU to guarantee timings are OK
 	 * Not sure if this is needed...
 	 */
 	addis r3,0,0x1000
-	mtspr dbcr0,r3               /* This will cause a CPU core reset, and */
+	mtspr dbcr0,r3		     /* This will cause a CPU core reset, and */
 				     /* execution will continue from the poweron */
 				     /* vector of 0xfffffffc */
 #endif /* CONFIG_405EP */

doc/README.mpc83xxads

@@ -3,9 +3,11 @@ Freescale MPC83xx ADS Boards
 
 0. Toolchain / Building
 
-    % setenv CROSS_COMPILE /usr/powerpc/bin/powerpc-linux-
+    $ PATH=$PATH:/usr/powerpc/bin
+    $ CROSS_COMPILE=powerpc-linux-
+    $ export PATH CROSS_COMPILE
 
-    % /usr/powerpc/bin/powerpc-linux-gcc -v
+    $ powerpc-linux-gcc -v
     Reading specs from /usr/powerpc/lib/gcc/powerpc-linux/3.4.3/specs
     Configured with: ../configure --prefix=/usr/powerpc
     --exec-prefix=/usr/powerpc --target=powerpc-linux --enable-shared
@@ -13,14 +15,14 @@ Freescale MPC83xx ADS Boards
     Thread model: posix
     gcc version 3.4.3 (Debian)
 
-    % /usr/powerpc/bin/powerpc-linux-as -v
+    $ powerpc-linux-as -v
     GNU assembler version 2.15 (powerpc-linux) using BFD version 2.15
 
 
-    % make MPC8349ADS_config
+    $ make MPC8349ADS_config
     Configuring for MPC8349ADS board...
 
-    % make
+    $ make
 
 
 1. Board Switches and Jumpers
@@ -76,7 +78,7 @@ Freescale MPC83xx ADS Boards
 
     Or via tftp:
 
-        tftp 10000 u-boot.bin
+	tftp 10000 u-boot.bin
 
 5.1 Reflash U-boot Image using U-boot
 

include/configs/ep8248.h

@@ -0,0 +1,277 @@
+/*
+ * Copyright (C) 2004 Arabella Software Ltd.
+ * Yuli Barcohen <yuli@arabellasw.com>
+ *
+ * U-Boot configuration for Embedded Planet EP8248 boards.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MPC8248
+#define CPU_ID_STR		"MPC8248"
+
+#define CONFIG_EP8248			/* Embedded Planet EP8248 board */
+
+#undef DEBUG
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/
+
+/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * Select serial console configuration
+ *
+ * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
+ * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
+ * for SCC).
+ */
+#define	CONFIG_CONS_ON_SMC		/* Console is on SMC         */
+#undef  CONFIG_CONS_ON_SCC		/* It's not on SCC           */
+#undef	CONFIG_CONS_NONE		/* It's not on external UART */
+#define CONFIG_CONS_INDEX	1	/* SMC1 is used for console  */
+
+#define CFG_BCSR		0xFA000000
+
+/*
+ * Select ethernet configuration
+ *
+ * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
+ * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
+ * SCC, 1-3 for FCC)
+ *
+ * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
+ * must be defined elsewhere (as for the console), or CFG_CMD_NET must
+ * be removed from CONFIG_COMMANDS to remove support for networking.
+ */
+#undef	CONFIG_ETHER_ON_SCC		/* Ethernet is not on SCC */
+#define CONFIG_ETHER_ON_FCC		/* Ethernet is on FCC     */
+#undef	CONFIG_ETHER_NONE		/* No external Ethernet   */
+
+#ifdef CONFIG_ETHER_ON_FCC
+
+#define CONFIG_ETHER_INDEX	1	/* FCC1 is used for Ethernet */
+
+#if   (CONFIG_ETHER_INDEX == 1)
+
+/* - Rx clock is CLK10
+ * - Tx clock is CLK11
+ * - BDs/buffers on 60x bus
+ * - Full duplex
+ */
+#define CFG_CMXFCR_MASK	(CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
+#define CFG_CMXFCR_VALUE	(CMXFCR_RF1CS_CLK10 | CMXFCR_TF1CS_CLK11)
+#define CFG_CPMFCR_RAMTYPE	0
+#define CFG_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
+
+#elif (CONFIG_ETHER_INDEX == 2)
+
+/* - Rx clock is CLK13
+ * - Tx clock is CLK14
+ * - BDs/buffers on 60x bus
+ * - Full duplex
+ */
+#define CFG_CMXFCR_MASK	(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
+#define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
+#define CFG_CPMFCR_RAMTYPE	0
+#define CFG_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
+
+#endif /* CONFIG_ETHER_INDEX */
+
+#define CONFIG_MII			/* MII PHY management        */
+#define CONFIG_BITBANGMII		/* Bit-banged MDIO interface */
+/*
+ * GPIO pins used for bit-banged MII communications
+ */
+#define MDIO_PORT		0	/* Not used - implemented in BCSR */
+#define MDIO_ACTIVE		(*(vu_char *)(CFG_BCSR + 8) &= 0xFB)
+#define MDIO_TRISTATE		(*(vu_char *)(CFG_BCSR + 8) |= 0x04)
+#define MDIO_READ		(*(vu_char *)(CFG_BCSR + 8) & 1)
+
+#define MDIO(bit)		if(bit) *(vu_char *)(CFG_BCSR + 8) |= 0x01; \
+				else	*(vu_char *)(CFG_BCSR + 8) &= 0xFE
+
+#define MDC(bit)		if(bit) *(vu_char *)(CFG_BCSR + 8) |= 0x02; \
+				else	*(vu_char *)(CFG_BCSR + 8) &= 0xFD
+
+#define MIIDELAY		udelay(1)
+
+#endif /* CONFIG_ETHER_ON_FCC */
+
+#ifndef CONFIG_8260_CLKIN
+#define CONFIG_8260_CLKIN	66000000	/* in Hz */
+#endif
+
+#define CONFIG_BAUDRATE		38400
+
+#define CONFIG_COMMANDS		(CONFIG_CMD_DFL   \
+				| CFG_CMD_DHCP    \
+				| CFG_CMD_ECHO    \
+				| CFG_CMD_I2C     \
+				| CFG_CMD_IMMAP   \
+				| CFG_CMD_MII     \
+				| CFG_CMD_PING    \
+				)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
+#define CONFIG_BOOTCOMMAND	"bootm FF860000"	/* autoboot command */
+#define CONFIG_BOOTARGS		"root=/dev/mtdblock1 rw mtdparts=phys:7M(root),-(root)ro"
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#undef	CONFIG_KGDB_ON_SMC		/* define if kgdb on SMC */
+#define CONFIG_KGDB_ON_SCC		/* define if kgdb on SCC */
+#undef	CONFIG_KGDB_NONE		/* define if kgdb on something else */
+#define CONFIG_KGDB_INDEX	1	/* which serial channel for kgdb */
+#define CONFIG_KGDB_BAUDRATE	115200	/* speed to run kgdb serial port at */
+#endif
+
+#define CONFIG_BZIP2	/* include support for bzip2 compressed images */
+#undef	CONFIG_WATCHDOG			/* disable platform specific watchdog */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2	"> "
+#define CFG_LONGHELP			/* undef to save memory	    */
+#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
+#else
+#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size  */
+#define CFG_MAXARGS		16		/* max number of command args */
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size  */
+
+#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
+#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x100000	/* default load address */
+
+#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+#define CFG_FLASH_BASE		0xFF800000
+#define CFG_FLASH_CFI
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_MAX_FLASH_BANKS	1	/* max num of flash banks	*/
+#define CFG_MAX_FLASH_SECT	256	/* max num of sects on one chip */
+
+#define	CFG_DIRECT_FLASH_TFTP
+
+#if (CONFIG_COMMANDS & CFG_CMD_JFFS2)
+#define CFG_JFFS2_FIRST_BANK	0
+#define CFG_JFFS2_NUM_BANKS	CFG_MAX_FLASH_BANKS
+#define CFG_JFFS2_FIRST_SECTOR  0
+#define CFG_JFFS2_LAST_SECTOR   62
+#define CFG_JFFS2_SORT_FRAGMENTS
+#define CFG_JFFS_CUSTOM_PART
+#endif /* CFG_CMD_JFFS2 */
+
+#if (CONFIG_COMMANDS & CFG_CMD_I2C)
+#define CONFIG_HARD_I2C		1	/* To enable I2C support	*/
+#define CFG_I2C_SPEED		100000	/* I2C speed			*/
+#define CFG_I2C_SLAVE		0x7F	/* I2C slave address		*/
+#endif /* CFG_CMD_I2C */
+
+#define CFG_MONITOR_BASE	TEXT_BASE
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#define CFG_RAMBOOT
+#endif
+
+#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256KB for Monitor */
+
+#define CFG_ENV_IS_IN_FLASH
+
+#ifdef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE	0x20000
+#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#endif /* CFG_ENV_IS_IN_FLASH */
+
+#define CFG_DEFAULT_IMMR	0x00010000
+
+#define CFG_IMMR		0xF0000000
+
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define CFG_INIT_RAM_END	0x2000	/* End of used area in DPRAM	*/
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/* Hard reset configuration word */
+#define CFG_HRCW_MASTER		0x0C40025A /* Not used - provided by FPGA */
+/* No slaves */
+#define CFG_HRCW_SLAVE1 	0
+#define CFG_HRCW_SLAVE2 	0
+#define CFG_HRCW_SLAVE3 	0
+#define CFG_HRCW_SLAVE4 	0
+#define CFG_HRCW_SLAVE5 	0
+#define CFG_HRCW_SLAVE6 	0
+#define CFG_HRCW_SLAVE7 	0
+
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM		0x02	/* Software reboot                  */
+
+#define CFG_MALLOC_LEN		(4096 << 10)	/* Reserve 4 MB for malloc()	*/
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+#define CFG_CACHELINE_SIZE	32	/* For MPC8260 CPUs */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+#define CFG_HID0_INIT		0
+#define CFG_HID0_FINAL		(HID0_ICE | HID0_IFEM | HID0_ABE)
+
+#define CFG_HID2		0
+
+#define CFG_SIUMCR		0x01240200
+#define CFG_SYPCR		0xFFFF0683
+#define CFG_BCR			0x00000000
+#define CFG_SCCR		SCCR_DFBRG01
+
+#define CFG_RMR			RMR_CSRE
+#define CFG_TMCNTSC		(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+#define CFG_PISCR		(PISCR_PS|PISCR_PTF|PISCR_PTE)
+#define CFG_RCCR		0
+
+#define CFG_MPTPR		0x1300
+#define CFG_PSDMR		0x82672522
+#define CFG_PSRT		0x4B
+
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_SDRAM_BR		(CFG_SDRAM_BASE | 0x00001841)
+#define CFG_SDRAM_OR		0xFF0030C0
+
+#define CFG_BR0_PRELIM		(CFG_FLASH_BASE | 0x00001801)
+#define CFG_OR0_PRELIM		0xFF8008C2
+#define CFG_BR2_PRELIM		(CFG_BCSR | 0x00000801)
+#define CFG_OR2_PRELIM		0xFFF00864
+
+#define CFG_RESET_ADDRESS	0xC0000000
+
+#endif /* __CONFIG_H */