* Code cleanup, mostly for GCC-3.3.x

* Cleanup confusing use of CONFIG_ETH*ADDR - ust his only to
  pre-define a MAC address; use CONFIG_HAS_ETH* to enable support for
  additional ethernet addresses.

* Cleanup drivers/i82365.c - avoid duplication of code

* Fix bogus "cannot span across banks" flash error message

* Add support for CompactFlash for the CPC45 Board.

CHANGELOG

@@ -2,6 +2,20 @@
 Changes since U-Boot 1.1.1:
 ======================================================================
 
+* Code cleanup, mostly for GCC-3.3.x
+
+* Cleanup confusing use of CONFIG_ETH*ADDR - ust his only to
+  pre-define a MAC address; use CONFIG_HAS_ETH* to enable support for
+  additional ethernet addresses.
+
+* Cleanup drivers/i82365.c - avoid duplication of code
+
+* Fix bogus "cannot span across banks" flash error message
+
+* Code cleanup
+
+* Add support for CompactFlash for the CPC45 Board.
+
 * Fix problems with CMC_PU2 flash driver.
 
 * Cleanup:

MAKEALL

@@ -99,9 +99,9 @@ LIST_8260="	\
 	atc		cogent_mpc8260	CPU86		ep8260		\
 	gw8260		hymod		IPHASE4539	ISPAN		\
 	MPC8260ADS	MPC8266ADS	MPC8272ADS	PM826		\
-	PM828		ppmc8260	PQ2FADS		RPXsuper	\
-	rsdproto	sacsng		sbc8260		SCM		\
-	TQM8260_AC	TQM8260_AD	TQM8260_AE	ZPC1900		\
+	PM828		ppmc8260	RPXsuper	rsdproto	\
+	sacsng		sbc8260		SCM		TQM8260_AC	\
+	TQM8260_AD	TQM8260_AE	ZPC1900				\
 "
 
 #########################################################################

board/cmc_pu2/flash.c

@@ -264,7 +264,7 @@ int	flash_erase (flash_info_t *info, int s_first, int s_last)
 {
 	vu_short *addr = (vu_short *)(info->start[0]);
 	int flag, prot, sect, ssect, l_sect;
-	ulong start, now, last;
+	ulong now, last;
 
 	debug ("flash_erase: first: %d last: %d\n", s_first, s_last);
 
@@ -336,7 +336,7 @@ int	flash_erase (flash_info_t *info, int s_first, int s_last)
 			goto DONE;
 
 		reset_timer_masked ();
-		last  = start;
+		last  = 0;
 		addr = (vu_short *)(info->start[l_sect]);
 		while ((addr[0] & 0x0080) != 0x0080) {
 			if ((now = get_timer_masked ()) > CFG_FLASH_ERASE_TOUT) {
@@ -432,7 +432,6 @@ printf ("write_buff 1: write_word_amd() rc=%d\n", rc);
  */
 static int write_word_amd (flash_info_t *info, vu_short *dest, ushort data)
 {
-	ulong start;
 	int flag;
 	vu_short *base;		/* first address in flash bank	*/
 

board/cpc45/Makefile

@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= lib$(BOARD).a
 
-OBJS	= $(BOARD).o flash.o plx9030.o
+OBJS	= $(BOARD).o flash.o plx9030.o pd67290.o
 
 $(LIB):	.depend $(OBJS)
 	$(AR) crv $@ $(OBJS)

board/cpc45/cpc45.c

@@ -24,11 +24,13 @@
 #include <common.h>
 #include <mpc824x.h>
 #include <asm/processor.h>
+#include <asm/io.h>
 #include <pci.h>
 #include <i2c.h>
 
 int sysControlDisplay(int digit, uchar ascii_code);
 extern void Plx9030Init(void);
+extern void SPD67290Init(void);
 
 	/* We have to clear the initial data area here. Couldn't have done it
 	 * earlier because DRAM had not been initialized.
@@ -180,6 +182,10 @@ static struct pci_config_table pci_cpc45_config_table[] = {
 	  pci_cfgfunc_config_device, { PCI_PLX9030_IOADDR,
 				       PCI_PLX9030_MEMADDR,
 				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0E, PCI_ANY_ID,
+	  pci_cfgfunc_config_device, { PCMCIA_IO_BASE,
+				       PCMCIA_IO_BASE,
+				       PCI_COMMAND_MEMORY | PCI_COMMAND_IO }},
 #endif /*CONFIG_PCI_PNP*/
 	{ }
 };
@@ -233,3 +239,37 @@ int sysControlDisplay (int digit,	/* number of digit 0..7 */
 
 	return (0);
 }
+
+#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
+
+#ifdef CFG_PCMCIA_MEM_ADDR
+volatile unsigned char *pcmcia_mem = (unsigned char*)CFG_PCMCIA_MEM_ADDR;
+#endif
+
+int pcmcia_init(void)
+{
+	u_int rc;
+
+	debug ("Enable PCMCIA " PCMCIA_SLOT_MSG "\n");
+
+	rc = i82365_init();
+
+	return rc;
+}
+
+#endif	/* CFG_CMD_PCMCIA */
+
+# ifdef CONFIG_IDE_LED
+void ide_led (uchar led, uchar status)
+{
+	u_char  val;
+	/* We have one PCMCIA slot and use LED H4 for the IDE Interface */
+	val = readb(BCSR_BASE + 0x04);
+	if (status) {				/* led on */
+		val |= B_CTRL_LED0;
+	} else {
+		val &= ~B_CTRL_LED0;
+	}
+	writeb(val, BCSR_BASE + 0x04);
+}
+# endif

board/cpc45/pd67290.c

@@ -0,0 +1,68 @@
+/* pd67290.c - system configuration module for SPD67290
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * (C) 2004 DENX Software Engineering, Heiko Schocher <hs@denx.de>
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <net.h>
+#include <asm/io.h>
+#include <pci.h>
+
+/* imports */
+#include <mpc824x.h>
+
+static struct pci_device_id supported[] = {
+	{PCI_VENDOR_ID_CIRRUS, PCI_DEVICE_ID_CIRRUS_6729},
+	{}
+};
+
+/***************************************************************************
+*
+* SPD67290Init -
+*
+* RETURNS: -1 on error, 0 if OK
+*/
+
+int SPD67290Init (void)
+{
+	pci_dev_t devno;
+	int idx = 0;		/* general index */
+	ulong membaseCsr;	/* base address of device memory space */
+
+	/* find PD67290 device */
+	if ((devno = pci_find_devices (supported, idx++)) < 0) {
+		printf ("No PD67290 device found !!\n");
+		return -1;
+	}
+	/* - 0xfe000000 see MPC 8245 Users Manual Adress Map B */
+	membaseCsr = PCMCIA_IO_BASE - 0xfe000000;
+
+	/* set base address */
+	pci_write_config_dword (devno, PCI_BASE_ADDRESS_0, membaseCsr);
+
+	/* enable mapped memory and IO addresses */
+	pci_write_config_dword (devno,
+				PCI_COMMAND,
+				PCI_COMMAND_MEMORY |
+				PCI_COMMAND_IO | PCI_COMMAND_WAIT);
+	return 0;
+}

board/esd/cpci750/cpci750.c

@@ -494,18 +494,18 @@ static void move64 (unsigned long long *src, unsigned long long *dest)
 #if defined (CFG_DRAM_TEST_DATA)
 
 unsigned long long pattern[] = {
-	0xaaaaaaaaaaaaaaaa,
-	0xcccccccccccccccc,
-	0xf0f0f0f0f0f0f0f0,
-	0xff00ff00ff00ff00,
-	0xffff0000ffff0000,
-	0xffffffff00000000,
-	0x00000000ffffffff,
-	0x0000ffff0000ffff,
-	0x00ff00ff00ff00ff,
-	0x0f0f0f0f0f0f0f0f,
-	0x3333333333333333,
-	0x5555555555555555
+	0xaaaaaaaaaaaaaaaaLL,
+	0xccccccccccccccccLL,
+	0xf0f0f0f0f0f0f0f0LL,
+	0xff00ff00ff00ff00LL,
+	0xffff0000ffff0000LL,
+	0xffffffff00000000LL,
+	0x00000000ffffffffLL,
+	0x0000ffff0000ffffLL,
+	0x00ff00ff00ff00ffLL,
+	0x0f0f0f0f0f0f0f0fLL,
+	0x3333333333333333LL,
+	0x5555555555555555LL,
 };
 
 /*********************************************************************/

board/esd/cpci750/local.h

@@ -76,7 +76,9 @@
 #define CONFIG_ETHADDR          64:36:00:00:00:01
 
 /* next two ethernet hwaddrs */
+#define CONFIG_HAS_ETH1
 #define CONFIG_ETH1ADDR		86:06:2d:7e:c6:54
+#define CONFIG_HAS_ETH2
 #define CONFIG_ETH2ADDR		86:06:2d:7e:c6:55
 
 #define CONFIG_ENV_OVERWRITE

board/esd/pci405/pci405.c

@@ -306,7 +306,7 @@ int misc_init_r (void)
 /*	mtspr(ccr0, (mfspr(ccr0) & 0xff8fffff) | 0x00100000);	*/
 	mtspr(ccr0, (mfspr(ccr0) & 0xff8fffff) | 0x00000000);
 #endif
-	/*	printf("CCR0=%08x\n", mfspr(ccr0));*/ /* test-only */
+/*	printf("CCR0=%08x\n", mfspr(ccr0)); */ /* test-only */
 #endif
 
 	free(dst);

board/evb64260/local.h

@@ -53,7 +53,9 @@
 #define CONFIG_ETHADDR          00:11:22:33:44:55
 
 /* next two ethernet hwaddrs */
+#define CONFIG_HAS_ETH1
 #define CONFIG_ETH1ADDR		00:11:22:33:44:66
+#define CONFIG_HAS_ETH2
 #define CONFIG_ETH2ADDR		00:11:22:33:44:77
 
 #define CONFIG_ENV_OVERWRITE

board/jse/host_bridge.c

@@ -39,8 +39,6 @@ void host_bridge_init (void)
 	/* The bridge chip is at a fixed location. */
 	pci_dev_t dev = PCI_BDF (0, 10, 0);
 
-	int rc;
-
 	/* Set PCI Class code --
 	   The primary side sees this class code at 0x08 in the
 	   primary config space. This must be something other then a

board/pn62/pn62.c

@@ -145,11 +145,13 @@ int misc_init_r (void)
 	}
 	show_startup_phase (10);
 
+#ifdef CONFIG_HAS_ETH1
 	if (getenv ("eth1addr") == NULL &&
 		get_mac_address (1, mac, str, sizeof (str)) > 0) {
 		setenv ("eth1addr", str);
 		memcpy (gd->bd->bi_enet1addr, mac, 6);
 	}
+#endif /* CONFIG_HAS_ETH1 */
 	show_startup_phase (11);
 
 	/* Tell everybody that U-Boot is up and runnig */

board/xilinx/xilinx_iic/iic_adapter.c

@@ -328,8 +328,9 @@ convert_env(void)
 	s = getenv("E");
 	if (s != NULL) {
 		sprintf(temp, "%c%c.%c%c.%c%c.%c%c.%c%c.%c%c",
-			*s++, *s++, *s++, *s++, *s++, *s++,
-			*s++, *s++, *s++, *s++, *s++, *s);
+			s[0], s[1],  s[ 2], s[ 3],
+			s[4], s[5],  s[ 6], s[ 7], 
+			s[8], s[9],  s[10], s[11] );
 		setenv("ethaddr", temp);
 		setenv("E", NULL);
 	}

common/cmd_bdinfo.c

@@ -92,21 +92,21 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 		printf ("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]);
 	}
 
-#if defined(CONFIG_ETH1ADDR)
+#if defined(CONFIG_HAS_ETH1)
 	puts ("\neth1addr    =");
 	for (i=0; i<6; ++i) {
 		printf ("%c%02X", i ? ':' : ' ', bd->bi_enet1addr[i]);
 	}
 #endif
 
-#if defined(CONFIG_ETH2ADDR)
+#if defined(CONFIG_HAS_ETH2)
        puts ("\neth2addr    =");
        for (i=0; i<6; ++i) {
 		printf ("%c%02X", i ? ':' : ' ', bd->bi_enet2addr[i]);
 	}
 #endif
 
-#if defined(CONFIG_ETH3ADDR)
+#if defined(CONFIG_HAS_ETH3)
        puts ("\neth3addr    =");
        for (i=0; i<6; ++i) {
 		printf ("%c%02X", i ? ':' : ' ', bd->bi_enet3addr[i]);

common/cmd_flash.c

@@ -164,6 +164,10 @@ flash_fill_sect_ranges (ulong addr_first, ulong addr_last,
 			sect = s_last[bank];
 			addr_first = (sect == s_end) ? b_end + 1: info->start[sect + 1];
 			(*s_count) += s_last[bank] - s_first[bank] + 1;
+		} else if (addr_first >= info->start[0] && addr_first < b_end) {
+			puts ("Error: start address not on sector boundary\n");
+			rcode = 1;
+			break;
 		} else if (s_last[bank] >= 0) {
 			puts ("Error: cannot span across banks when they are"
 			       " mapped in reverse order\n");

common/cmd_ide.c

@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000-2002
+ * (C) Copyright 2000-2004
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -144,7 +144,7 @@ block_dev_desc_t ide_dev_desc[CFG_IDE_MAXDEVICE];
 /* ------------------------------------------------------------------------- */
 
 #ifdef CONFIG_IDE_LED
-#if !defined(CONFIG_KUP4K) &&  !defined(CONFIG_KUP4X) &&!defined(CONFIG_BMS2003)
+#if !defined(CONFIG_KUP4K) &&  !defined(CONFIG_KUP4X) &&!defined(CONFIG_BMS2003) &&!defined(CONFIG_CPC45)
 static void  ide_led   (uchar led, uchar status);
 #else
 extern void  ide_led   (uchar led, uchar status);
@@ -1548,11 +1548,12 @@ static void ide_reset (void)
 
 /* ------------------------------------------------------------------------- */
 
-#if defined(CONFIG_IDE_LED) && \
-   !defined(CONFIG_AMIGAONEG3SE) && \
-   !defined(CONFIG_KUP4K) && \
-   !defined(CONFIG_KUP4X) && \
-   !defined(CONFIG_HMI10)
+#if defined(CONFIG_IDE_LED)	&& \
+   !defined(CONFIG_AMIGAONEG3SE)&& \
+   !defined(CONFIG_CPC45)	&& \
+   !defined(CONFIG_HMI10)	&& \
+   !defined(CONFIG_KUP4K)	&& \
+   !defined(CONFIG_KUP4X)
 
 static	uchar	led_buffer = 0;		/* Buffer for current LED status	*/
 
@@ -1578,7 +1579,6 @@ static void ide_led (uchar led, uchar status)
  * ATAPI Support
  */
 
-
 #undef	ATAPI_DEBUG
 
 #ifdef	ATAPI_DEBUG
@@ -1661,7 +1661,6 @@ output_data_shorts(int dev, ushort *sect_buf, int shorts)
 	outsw(ATA_CURR_BASE(dev)+ATA_DATA_REG, sect_buf, shorts);
 }
 
-
 static void
 input_data_shorts(int dev, ushort *sect_buf, int shorts)
 {

common/cmd_pcmcia.c

@@ -67,6 +67,8 @@
 #include <asm/arch/pxa-regs.h>
 #endif
 
+#include <asm/io.h>
+
 #if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) || \
     ((CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD))
 
@@ -540,9 +542,18 @@ static int check_ide_device (int slot)
 
 	ide_devices_found |= (1 << slot);
 
+#if CONFIG_CPC45
+#else
 	/* set I/O area in config reg -> only valid for ARGOSY D5!!! */
 	*((uchar *)(addr + config_base)) = 1;
-
+#endif
+#if 0
+	printf("\n## Config_base = %04x ###\n", config_base);
+	printf("Configuration Option Register: %02x @ %x\n", readb(addr + config_base), addr + config_base);
+	printf("Card Configuration and Status Register: %02x\n", readb(addr + config_base + 2));
+	printf("Pin Replacement Register Register: %02x\n", readb(addr + config_base + 4));
+	printf("Socket and Copy Register: %02x\n", readb(addr + config_base + 6));
+#endif
 	return (0);
 }
 #endif	/* CONFIG_IDE_8xx_PCCARD */

common/cmd_universe.c

@@ -28,20 +28,8 @@
 
 #include <universe.h>
 
-
 #if (CONFIG_COMMANDS & CFG_CMD_UNIVERSE)
 
-#undef DBG
-
-#ifdef DBG
-# define UNI_DBG(fmt)	        printf fmt
-#else
-# define UNI_DBG(fmt)
-#endif
-
-#define UNI_PRINT(fmt)	        printf fmt
-
-
 #define PCI_VENDOR PCI_VENDOR_ID_TUNDRA
 #define PCI_DEVICE PCI_DEVICE_ID_TUNDRA_CA91C042
 
@@ -87,18 +75,18 @@ int universe_init(void)
 	val &= ~0xf;
 	dev->uregs = (UNIVERSE *)val;
 
-	UNI_DBG(("UNIVERSE-Base    : %p\n", dev->uregs));
+	debug ("UNIVERSE-Base    : %p\n", dev->uregs);
 
 	/* check mapping  */
-	UNI_DBG((" Read via mapping, PCI_ID = %08X\n", readl(&dev->uregs->pci_id)));
+	debug (" Read via mapping, PCI_ID = %08X\n", readl(&dev->uregs->pci_id));
 	if (((PCI_DEVICE <<16) | PCI_VENDOR) !=  readl(&dev->uregs->pci_id)) {
-		UNI_PRINT(("UNIVERSE: Cannot read PCI-ID via Mapping: %08x\n",
-			   readl(&dev->uregs->pci_id)));
+		printf ("UNIVERSE: Cannot read PCI-ID via Mapping: %08x\n",
+			readl(&dev->uregs->pci_id));
 		result = -1;
 		goto break_30;
 	}
 
-	UNI_DBG(("PCI_BS = %08X\n", readl(&dev->uregs->pci_bs)));
+	debug ("PCI_BS = %08X\n", readl(&dev->uregs->pci_bs));
 
 	dev->pci_bs = readl(&dev->uregs->pci_bs);
 
@@ -154,12 +142,12 @@ int universe_pci_slave_window(unsigned int pciAddr, unsigned int vmeAddr, int si
 	}
 
 	if (i == 4) {
-		UNI_PRINT(("universe: No Image available\n"));
+		printf ("universe: No Image available\n");
 		result = -1;
 		goto exit_10;
 	}
 
-	UNI_DBG(("universe: Using image %d\n", i));
+	debug ("universe: Using image %d\n", i);
 
 	writel(pciAddr , &dev->uregs->lsi[i].bs);
 	writel((pciAddr + size), &dev->uregs->lsi[i].bd);
@@ -219,11 +207,11 @@ int universe_pci_slave_window(unsigned int pciAddr, unsigned int vmeAddr, int si
 
 	writel(ctl, &dev->uregs->lsi[i].ctl);
 
-	UNI_DBG(("universe: window-addr=%p\n", &dev->uregs->lsi[i].ctl));
-	UNI_DBG(("universe: pci slave window[%d] ctl=%08x\n", i, readl(&dev->uregs->lsi[i].ctl)));
-	UNI_DBG(("universe: pci slave window[%d] bs=%08x\n", i, readl(&dev->uregs->lsi[i].bs)));
-	UNI_DBG(("universe: pci slave window[%d] bd=%08x\n", i, readl(&dev->uregs->lsi[i].bd)));
-	UNI_DBG(("universe: pci slave window[%d] to=%08x\n", i, readl(&dev->uregs->lsi[i].to)));
+	debug ("universe: window-addr=%p\n", &dev->uregs->lsi[i].ctl);
+	debug ("universe: pci slave window[%d] ctl=%08x\n", i, readl(&dev->uregs->lsi[i].ctl));
+	debug ("universe: pci slave window[%d] bs=%08x\n", i, readl(&dev->uregs->lsi[i].bs));
+	debug ("universe: pci slave window[%d] bd=%08x\n", i, readl(&dev->uregs->lsi[i].bd));
+	debug ("universe: pci slave window[%d] to=%08x\n", i, readl(&dev->uregs->lsi[i].to));
 
 	return 0;
 
@@ -251,12 +239,12 @@ int universe_vme_slave_window(unsigned int vmeAddr, unsigned int pciAddr, int si
 	}
 
 	if (i == 4) {
-		UNI_PRINT(("universe: No Image available\n"));
+		printf ("universe: No Image available\n");
 		result = -1;
 		goto exit_10;
 	}
 
-	UNI_DBG(("universe: Using image %d\n", i));
+	debug ("universe: Using image %d\n", i);
 
 	writel(vmeAddr , &dev->uregs->vsi[i].bs);
 	writel((vmeAddr + size), &dev->uregs->vsi[i].bd);
@@ -304,11 +292,11 @@ int universe_vme_slave_window(unsigned int vmeAddr, unsigned int pciAddr, int si
 
 	writel(ctl, &dev->uregs->vsi[i].ctl);
 
-	UNI_DBG(("universe: window-addr=%p\n", &dev->uregs->vsi[i].ctl));
-	UNI_DBG(("universe: vme slave window[%d] ctl=%08x\n", i, readl(&dev->uregs->vsi[i].ctl)));
-	UNI_DBG(("universe: vme slave window[%d] bs=%08x\n", i, readl(&dev->uregs->vsi[i].bs)));
-	UNI_DBG(("universe: vme slave window[%d] bd=%08x\n", i, readl(&dev->uregs->vsi[i].bd)));
-	UNI_DBG(("universe: vme slave window[%d] to=%08x\n", i, readl(&dev->uregs->vsi[i].to)));
+	debug ("universe: window-addr=%p\n", &dev->uregs->vsi[i].ctl);
+	debug ("universe: vme slave window[%d] ctl=%08x\n", i, readl(&dev->uregs->vsi[i].ctl));
+	debug ("universe: vme slave window[%d] bs=%08x\n", i, readl(&dev->uregs->vsi[i].bs));
+	debug ("universe: vme slave window[%d] bd=%08x\n", i, readl(&dev->uregs->vsi[i].bd));
+	debug ("universe: vme slave window[%d] to=%08x\n", i, readl(&dev->uregs->vsi[i].to));
 
 	return 0;
 

common/environment.c

@@ -130,6 +130,9 @@ env_t environment __PPCENV__ = {
 #ifdef	CONFIG_ETH2ADDR
 	"eth2addr="	MK_STR(CONFIG_ETH2ADDR)		"\0"
 #endif
+#ifdef	CONFIG_ETH3ADDR
+	"eth3addr="	MK_STR(CONFIG_ETH3ADDR)		"\0"
+#endif
 #ifdef	CONFIG_ETHPRIME
 	"ethprime="	CONFIG_ETHPRIME			"\0"
 #endif

cpu/74xx_7xx/config.mk

@@ -21,6 +21,6 @@
 # MA 02111-1307 USA
 #
 
-PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi
+PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -fno-strict-aliasing
 
 PLATFORM_CPPFLAGS += -DCONFIG_74xx_7xx -ffixed-r2 -ffixed-r29 -mstring

cpu/mpc8220/fec.c

@@ -809,14 +809,14 @@ int mpc8220_fec_initialize (bd_t * bis)
 {
 	mpc8220_fec_priv *fec;
 
-#ifdef CONFIG_ETH1ADDR
+#ifdef CONFIG_HAS_ETH1
 	mpc8220_fec_priv *fec2;
 #endif
 	struct eth_device *dev;
 	char *tmp, *end;
 	char env_enetaddr[6];
 
-#ifdef CONFIG_ETH1ADDR
+#ifdef CONFIG_HAS_ETH1
 	char env_enet1addr[6];
 #endif
 	int i;
@@ -826,7 +826,7 @@ int mpc8220_fec_initialize (bd_t * bis)
 	memset (dev, 0, sizeof *dev);
 
 	fec->eth = (ethernet_regs *) MMAP_FEC1;
-#ifdef CONFIG_ETH1ADDR
+#ifdef CONFIG_HAS_ETH1
 	fec2 = (mpc8220_fec_priv *) malloc (sizeof (*fec));
 	fec2->eth = (ethernet_regs *) MMAP_FEC2;
 #endif
@@ -860,7 +860,7 @@ int mpc8220_fec_initialize (bd_t * bis)
 		}
 		mpc8220_fec_set_hwaddr (fec, env_enetaddr);
 	}
-#ifdef CONFIG_ETH1ADDR
+#ifdef CONFIG_HAS_ETH1
 	tmp = getenv ("eth1addr");
 	if (tmp) {
 		for (i = 0; i < 6; i++) {

cpu/mpc824x/config.mk

@@ -21,6 +21,6 @@
 # MA 02111-1307 USA
 #
 
-PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi
+PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -fno-strict-aliasing
 
 PLATFORM_CPPFLAGS += -DCONFIG_MPC824X -ffixed-r2 -ffixed-r29 -mstring -mcpu=603e -msoft-float

cpu/mpc8xx/config.mk

@@ -21,6 +21,6 @@
 # MA 02111-1307 USA
 #
 
-PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi
+PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -fno-strict-aliasing
 
 PLATFORM_CPPFLAGS += -DCONFIG_8xx -ffixed-r2 -ffixed-r29 -mstring -mcpu=860 -msoft-float

cpu/ppc4xx/440gx_enet.c

@@ -1176,36 +1176,37 @@ int ppc_440x_eth_initialize (bd_t * bis)
 
 		/* See if we can actually bring up the interface, otherwise, skip it */
 		switch (eth_num) {
+		default:		/* fall through */
 		case 0:
 			if (memcmp (bis->bi_enetaddr, "\0\0\0\0\0\0", 6) == 0) {
 				bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
 				continue;
 			}
 			break;
+#ifdef CONFIG_HAS_ETH1
 		case 1:
 			if (memcmp (bis->bi_enet1addr, "\0\0\0\0\0\0", 6) == 0) {
 				bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
 				continue;
 			}
 			break;
+#endif
+#ifdef CONFIG_HAS_ETH2
 		case 2:
 			if (memcmp (bis->bi_enet2addr, "\0\0\0\0\0\0", 6) == 0) {
 				bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
 				continue;
 			}
 			break;
+#endif
+#ifdef CONFIG_HAS_ETH3
 		case 3:
 			if (memcmp (bis->bi_enet3addr, "\0\0\0\0\0\0", 6) == 0) {
 				bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
 				continue;
 			}
 			break;
-		default:
-			if (memcmp (bis->bi_enetaddr, "\0\0\0\0\0\0", 6) == 0) {
-				bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
-				continue;
-			}
-			break;
+#endif
 		}
 
 		/* Allocate device structure */
@@ -1227,26 +1228,29 @@ int ppc_440x_eth_initialize (bd_t * bis)
 		}
 
 		switch (eth_num) {
+		default:		/* fall through */
 		case 0:
 			hw->hw_addr = 0;
 			memcpy (dev->enetaddr, bis->bi_enetaddr, 6);
 			break;
+#ifdef CONFIG_HAS_ETH1
 		case 1:
 			hw->hw_addr = 0x100;
 			memcpy (dev->enetaddr, bis->bi_enet1addr, 6);
 			break;
+#endif
+#ifdef CONFIG_HAS_ETH2
 		case 2:
 			hw->hw_addr = 0x400;
 			memcpy (dev->enetaddr, bis->bi_enet2addr, 6);
 			break;
+#endif
+#ifdef CONFIG_HAS_ETH3
 		case 3:
 			hw->hw_addr = 0x600;
 			memcpy (dev->enetaddr, bis->bi_enet3addr, 6);
 			break;
-		default:
-			hw->hw_addr = 0;
-			memcpy (dev->enetaddr, bis->bi_enetaddr, 6);
-			break;
+#endif
 		}
 
 		hw->devnum = eth_num;

cpu/ppc4xx/config.mk

@@ -21,6 +21,6 @@
 # MA 02111-1307 USA
 #
 
-PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi
+PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -fno-strict-aliasing
 
 PLATFORM_CPPFLAGS += -DCONFIG_4xx -ffixed-r2 -ffixed-r29 -mstring -Wa,-m405 -mcpu=405 -msoft-float

drivers/i82365.c

@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2003
+ * (C) Copyright 2003-2004
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -40,32 +40,65 @@
 
 #include <pcmcia/ss.h>
 #include <pcmcia/i82365.h>
-#include <pcmcia/ti113x.h>
 #include <pcmcia/yenta.h>
-
-/* #define DEBUG */
+#ifdef CONFIG_CPC45
+#include <pcmcia/cirrus.h>
+#else
+#include <pcmcia/ti113x.h>
+#endif
 
 static struct pci_device_id supported[] = {
+#ifdef CONFIG_CPC45
+	{PCI_VENDOR_ID_CIRRUS, PCI_DEVICE_ID_CIRRUS_6729},
+#else
 	{PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1510},
+#endif
 	{0, 0}
 };
 
 #define CYCLE_TIME	120
 
+#ifdef CONFIG_CPC45
+extern int SPD67290Init (void);
+#endif
+
 #ifdef DEBUG
 static void i82365_dump_regions (pci_dev_t dev);
 #endif
 
 typedef struct socket_info_t {
-    pci_dev_t		dev;
-    u_short		bcr;
-    u_char		pci_lat, cb_lat, sub_bus, cache;
-    u_int		cb_phys;
-
-    socket_cap_t	cap;
-    ti113x_state_t	state;
+	pci_dev_t	dev;
+	u_short		bcr;
+	u_char		pci_lat, cb_lat, sub_bus, cache;
+	u_int		cb_phys;
+
+	socket_cap_t	cap;
+	u_short		type;
+	u_int		flags;
+#ifdef CONFIG_CPC45
+	cirrus_state_t	c_state;
+#else
+	ti113x_state_t	state;
+#endif
 } socket_info_t;
 
+#ifdef CONFIG_CPC45
+/* These definitions must match the pcic table! */
+typedef enum pcic_id {
+	IS_PD6710, IS_PD672X, IS_VT83C469
+} pcic_id;
+
+typedef struct pcic_t {
+	char *name;
+} pcic_t;
+
+static pcic_t pcic[] = {
+	{" Cirrus PD6710: "},
+	{" Cirrus PD672x: "},
+	{" VIA VT83C469: "},
+};
+#endif
+
 static socket_info_t socket;
 static socket_state_t state;
 static struct pccard_mem_map mem;
@@ -91,6 +124,7 @@ static int pci_writew (socket_info_t * s, int r, u_short v)
 {
 	return pci_write_config_word (s->dev, r, v);
 }
+#ifndef CONFIG_CPC45
 static int pci_readl (socket_info_t * s, int r, u_int * v)
 {
 	return pci_read_config_dword (s->dev, r, v);
@@ -99,14 +133,61 @@ static int pci_writel (socket_info_t * s, int r, u_int v)
 {
 	return pci_write_config_dword (s->dev, r, v);
 }
+#endif	/* !CONFIG_CPC45 */
+
+/*====================================================================*/
+
+#ifdef CONFIG_CPC45
+
+#define cb_readb(s)		readb((s)->cb_phys + 1)
+#define cb_writeb(s, v)		writeb(v, (s)->cb_phys)
+#define cb_writeb2(s, v)	writeb(v, (s)->cb_phys + 1)
+#define cb_readl(s, r)		readl((s)->cb_phys + (r))
+#define cb_writel(s, r, v)	writel(v, (s)->cb_phys + (r))
+
+
+static u_char i365_get (socket_info_t * s, u_short reg)
+{
+	u_char val;
+
+#ifdef CONFIG_PCMCIA_SLOT_A
+	int slot = 0;
+#else
+	int slot = 1;
+#endif
+
+	val = I365_REG (slot, reg);
+
+	cb_writeb (s, val);
+	val = cb_readb (s);
+
+	debug ("i365_get slot:%x reg: %x val: %x\n", slot, reg, val);
+	return val;
+}
+
+static void i365_set (socket_info_t * s, u_short reg, u_char data)
+{
+#ifdef CONFIG_PCMCIA_SLOT_A
+	int slot = 0;
+#else
+	int slot = 1;
+#endif
+
+	u_char val = I365_REG (slot, reg);
+
+	cb_writeb (s, val);
+	cb_writeb2 (s, data);
+
+	debug ("i365_set slot:%x reg: %x data:%x\n", slot, reg, data);
+}
+
+#else	/* ! CONFIG_CPC45 */
 
 #define cb_readb(s, r)		readb((s)->cb_phys + (r))
 #define cb_readl(s, r)		readl((s)->cb_phys + (r))
 #define cb_writeb(s, r, v)	writeb(v, (s)->cb_phys + (r))
 #define cb_writel(s, r, v)	writel(v, (s)->cb_phys + (r))
 
-/*====================================================================*/
-
 static u_char i365_get (socket_info_t * s, u_short reg)
 {
 	return cb_readb (s, 0x0800 + reg);
@@ -116,6 +197,7 @@ static void i365_set (socket_info_t * s, u_short reg, u_char data)
 {
 	cb_writeb (s, 0x0800 + reg, data);
 }
+#endif	/* CONFIG_CPC45 */
 
 static void i365_bset (socket_info_t * s, u_short reg, u_char mask)
 {
@@ -147,6 +229,116 @@ static void i365_set_pair (socket_info_t * s, u_short reg, u_short data)
 	i365_set (s, reg + 1, data >> 8);
 }
 
+#ifdef CONFIG_CPC45
+/*======================================================================
+
+    Code to save and restore global state information for Cirrus
+    PD67xx controllers, and to set and report global configuration
+    options.
+
+======================================================================*/
+
+#define flip(v,b,f) (v = ((f)<0) ? v : ((f) ? ((v)|(b)) : ((v)&(~b))))
+
+static void cirrus_get_state (socket_info_t * s)
+{
+	int i;
+	cirrus_state_t *p = &s->c_state;
+
+	p->misc1 = i365_get (s, PD67_MISC_CTL_1);
+	p->misc1 &= (PD67_MC1_MEDIA_ENA | PD67_MC1_INPACK_ENA);
+	p->misc2 = i365_get (s, PD67_MISC_CTL_2);
+	for (i = 0; i < 6; i++)
+		p->timer[i] = i365_get (s, PD67_TIME_SETUP (0) + i);
+
+}
+
+static void cirrus_set_state (socket_info_t * s)
+{
+	int i;
+	u_char misc;
+	cirrus_state_t *p = &s->c_state;
+
+	misc = i365_get (s, PD67_MISC_CTL_2);
+	i365_set (s, PD67_MISC_CTL_2, p->misc2);
+	if (misc & PD67_MC2_SUSPEND)
+		udelay (50000);
+	misc = i365_get (s, PD67_MISC_CTL_1);
+	misc &= ~(PD67_MC1_MEDIA_ENA | PD67_MC1_INPACK_ENA);
+	i365_set (s, PD67_MISC_CTL_1, misc | p->misc1);
+	for (i = 0; i < 6; i++)
+		i365_set (s, PD67_TIME_SETUP (0) + i, p->timer[i]);
+}
+
+static u_int cirrus_set_opts (socket_info_t * s)
+{
+	cirrus_state_t *p = &s->c_state;
+	u_int mask = 0xffff;
+
+#if DEBUG
+	char buf[200];
+
+	memset (buf, 0, 200);
+#endif
+
+	if (has_ring == -1)
+		has_ring = 1;
+	flip (p->misc2, PD67_MC2_IRQ15_RI, has_ring);
+	flip (p->misc2, PD67_MC2_DYNAMIC_MODE, dynamic_mode);
+#if DEBUG
+	if (p->misc2 & PD67_MC2_IRQ15_RI)
+		strcat (buf, " [ring]");
+	if (p->misc2 & PD67_MC2_DYNAMIC_MODE)
+		strcat (buf, " [dyn mode]");
+	if (p->misc1 & PD67_MC1_INPACK_ENA)
+		strcat (buf, " [inpack]");
+#endif
+
+	if (p->misc2 & PD67_MC2_IRQ15_RI)
+		mask &= ~0x8000;
+	if (has_led > 0) {
+#if DEBUG
+		strcat (buf, " [led]");
+#endif
+		mask &= ~0x1000;
+	}
+	if (has_dma > 0) {
+#if DEBUG
+		strcat (buf, " [dma]");
+#endif
+		mask &= ~0x0600;
+		flip (p->misc2, PD67_MC2_FREQ_BYPASS, freq_bypass);
+#if DEBUG
+		if (p->misc2 & PD67_MC2_FREQ_BYPASS)
+			strcat (buf, " [freq bypass]");
+#endif
+	}
+
+	if (setup_time >= 0)
+		p->timer[0] = p->timer[3] = setup_time;
+	if (cmd_time > 0) {
+		p->timer[1] = cmd_time;
+		p->timer[4] = cmd_time * 2 + 4;
+	}
+	if (p->timer[1] == 0) {
+		p->timer[1] = 6;
+		p->timer[4] = 16;
+		if (p->timer[0] == 0)
+			p->timer[0] = p->timer[3] = 1;
+	}
+	if (recov_time >= 0)
+		p->timer[2] = p->timer[5] = recov_time;
+
+	debug ("i82365 Opt: %s [%d/%d/%d] [%d/%d/%d]\n",
+		buf,
+		p->timer[0], p->timer[1], p->timer[2],
+		p->timer[3], p->timer[4], p->timer[5]);
+
+	return mask;
+}
+
+#else	/* !CONFIG_CPC45 */
+
 /*======================================================================
 
     Code to save and restore global state information for TI 1130 and
@@ -190,6 +382,7 @@ static u_int ti113x_set_opts (socket_info_t * s)
 
 	return mask;
 }
+#endif	/* CONFIG_CPC45 */
 
 /*======================================================================
 
@@ -213,8 +406,10 @@ static void cb_get_state (socket_info_t * s)
 
 static void cb_set_state (socket_info_t * s)
 {
+#ifndef CONFIG_CPC45
 	pci_writel (s, CB_LEGACY_MODE_BASE, 0);
 	pci_writel (s, PCI_BASE_ADDRESS_0, s->cb_phys);
+#endif
 	pci_writew (s, PCI_COMMAND, CMD_DFLT);
 	pci_writeb (s, PCI_CACHE_LINE_SIZE, s->cache);
 	pci_writeb (s, PCI_LATENCY_TIMER, s->pci_lat);
@@ -226,12 +421,14 @@ static void cb_set_state (socket_info_t * s)
 
 static void cb_set_opts (socket_info_t * s)
 {
+#ifndef CONFIG_CPC45
 	if (s->cache == 0)
 		s->cache = 8;
 	if (s->pci_lat == 0)
 		s->pci_lat = 0xa8;
 	if (s->cb_lat == 0)
 		s->cb_lat = 0xb0;
+#endif
 }
 
 /*======================================================================
@@ -245,9 +442,71 @@ static int cb_set_power (socket_info_t * s, socket_state_t * state)
 {
 	u_int reg = 0;
 
+#ifdef CONFIG_CPC45
+
+	if ((state->Vcc == 0) && (state->Vpp == 0)) {
+		u_char power, vcc, vpp;
+
+		power = i365_get (s, I365_POWER);
+		state->flags |= (power & I365_PWR_AUTO) ? SS_PWR_AUTO : 0;
+		state->flags |= (power & I365_PWR_OUT) ? SS_OUTPUT_ENA : 0;
+		vcc = power & I365_VCC_MASK;
+		vpp = power & I365_VPP1_MASK;
+		state->Vcc = state->Vpp = 0;
+		if (i365_get (s, PD67_MISC_CTL_1) & PD67_MC1_VCC_3V) {
+			if (power & I365_VCC_5V)
+				state->Vcc = 33;
+			if (vpp == I365_VPP1_5V)
+				state->Vpp = 33;
+		} else {
+			if (power & I365_VCC_5V)
+				state->Vcc = 50;
+			if (vpp == I365_VPP1_5V)
+				state->Vpp = 50;
+		}
+		if (power == I365_VPP1_12V)
+			state->Vpp = 120;
+		printf ("POWER Vcc:%d Vpp: %d\n", state->Vcc, state->Vpp);
+	}
+
+	reg = I365_PWR_NORESET;
+	if (state->flags & SS_PWR_AUTO)
+		reg |= I365_PWR_AUTO;
+	if (state->flags & SS_OUTPUT_ENA)
+		reg |= I365_PWR_OUT;
+	if (state->Vpp != 0) {
+		if (state->Vpp == 120) {
+			reg |= I365_VPP1_12V;
+			puts (" 12V card found: ");
+		} else if (state->Vpp == state->Vcc) {
+			reg |= I365_VPP1_5V;
+			puts (" 5V card found: ");
+		} else {
+			puts (" power not found: ");
+			return -1;
+		}
+	}
+	if (state->Vcc != 0) {
+		reg |= I365_VCC_5V;
+		if (state->Vcc == 33) {
+			puts (" 3.3V card found: ");
+			i365_bset (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V);
+		} else if (state->Vcc == 50) {
+			puts (" 5V card found: ");
+			i365_bclr (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V);
+		} else {
+			puts (" power not found: ");
+			return -1;
+		}
+	}
+	if (reg != i365_get (s, I365_POWER))
+		i365_set (s, I365_POWER, reg);
+
+#else	/* ! CONFIG_CPC45 */
+
 	/* restart card voltage detection if it seems appropriate */
 	if ((state->Vcc == 0) && (state->Vpp == 0) &&
-		!(cb_readl (s, CB_SOCKET_STATE) & CB_SS_VSENSE))
+	   !(cb_readl (s, CB_SOCKET_STATE) & CB_SS_VSENSE))
 		cb_writel (s, CB_SOCKET_FORCE, CB_SF_CVSTEST);
 	switch (state->Vcc) {
 	case 0:
@@ -279,6 +538,7 @@ static int cb_set_power (socket_info_t * s, socket_state_t * state)
 	}
 	if (reg != cb_readl (s, CB_SOCKET_CONTROL))
 		cb_writel (s, CB_SOCKET_CONTROL, reg);
+#endif	/* CONFIG_CPC45 */
 	return 0;
 }
 
@@ -290,7 +550,11 @@ static int cb_set_power (socket_info_t * s, socket_state_t * state)
 
 static void get_bridge_state (socket_info_t * s)
 {
+#ifdef CONFIG_CPC45
+	cirrus_get_state (s);
+#else
 	ti113x_get_state (s);
+#endif
 	cb_get_state (s);
 }
 
@@ -299,12 +563,20 @@ static void set_bridge_state (socket_info_t * s)
 	cb_set_state (s);
 	i365_set (s, I365_GBLCTL, 0x00);
 	i365_set (s, I365_GENCTL, 0x00);
+#ifdef CONFIG_CPC45
+	cirrus_set_state (s);
+#else
 	ti113x_set_state (s);
+#endif
 }
 
 static void set_bridge_opts (socket_info_t * s)
 {
+#ifdef CONFIG_CPC45
+	cirrus_set_opts (s);
+#else
 	ti113x_set_opts (s);
+#endif
 	cb_set_opts (s);
 }
 
@@ -314,6 +586,12 @@ static int i365_get_status (socket_info_t * s, u_int * value)
 {
 	u_int status;
 
+#ifdef CONFIG_CPC45
+	u_char val;
+	u_char power, vcc, vpp;
+#endif
+
+	status = i365_get (s, I365_IDENT);
 	status = i365_get (s, I365_STATUS);
 	*value = ((status & I365_CS_DETECT) == I365_CS_DETECT) ? SS_DETECT : 0;
 	if (i365_get (s, I365_INTCTL) & I365_PC_IOCARD) {
@@ -326,6 +604,71 @@ static int i365_get_status (socket_info_t * s, u_int * value)
 	*value |= (status & I365_CS_READY) ? SS_READY : 0;
 	*value |= (status & I365_CS_POWERON) ? SS_POWERON : 0;
 
+#ifdef CONFIG_CPC45
+	/* Check for Cirrus CL-PD67xx chips */
+	i365_set (s, PD67_CHIP_INFO, 0);
+	val = i365_get (s, PD67_CHIP_INFO);
+	s->type = -1;
+	if ((val & PD67_INFO_CHIP_ID) == PD67_INFO_CHIP_ID) {
+		val = i365_get (s, PD67_CHIP_INFO);
+		if ((val & PD67_INFO_CHIP_ID) == 0) {
+			s->type =
+				(val & PD67_INFO_SLOTS) ? IS_PD672X :
+				IS_PD6710;
+			i365_set (s, PD67_EXT_INDEX, 0xe5);
+			if (i365_get (s, PD67_EXT_INDEX) != 0xe5)
+				s->type = IS_VT83C469;
+		}
+	} else {
+		printf ("no Cirrus Chip found\n");
+		*value = 0;
+		return -1;
+	}
+
+	i365_bset (s, I365_POWER, I365_VCC_5V);
+	power = i365_get (s, I365_POWER);
+	state.flags |= (power & I365_PWR_AUTO) ? SS_PWR_AUTO : 0;
+	state.flags |= (power & I365_PWR_OUT) ? SS_OUTPUT_ENA : 0;
+	vcc = power & I365_VCC_MASK;
+	vpp = power & I365_VPP1_MASK;
+	state.Vcc = state.Vpp = 0;
+	if (i365_get (s, PD67_MISC_CTL_1) & PD67_MC1_VCC_3V) {
+		if (power & I365_VCC_5V)
+			state.Vcc = 33;
+		if (vpp == I365_VPP1_5V)
+			state.Vpp = 33;
+	} else {
+		if (power & I365_VCC_5V)
+			state.Vcc = 50;
+		if (vpp == I365_VPP1_5V)
+			state.Vpp = 50;
+	}
+	if (power == I365_VPP1_12V)
+		state.Vpp = 120;
+
+	/* IO card, RESET flags, IO interrupt */
+	power = i365_get (s, I365_INTCTL);
+	state.flags |= (power & I365_PC_RESET) ? 0 : SS_RESET;
+	if (power & I365_PC_IOCARD)
+		state.flags |= SS_IOCARD;
+	state.io_irq = power & I365_IRQ_MASK;
+
+	/* Card status change mask */
+	power = i365_get (s, I365_CSCINT);
+	state.csc_mask = (power & I365_CSC_DETECT) ? SS_DETECT : 0;
+	if (state.flags & SS_IOCARD)
+		state.csc_mask |= (power & I365_CSC_STSCHG) ? SS_STSCHG : 0;
+	else {
+		state.csc_mask |= (power & I365_CSC_BVD1) ? SS_BATDEAD : 0;
+		state.csc_mask |= (power & I365_CSC_BVD2) ? SS_BATWARN : 0;
+		state.csc_mask |= (power & I365_CSC_READY) ? SS_READY : 0;
+	}
+	debug ("i82365: GetStatus(0) = flags %#3.3x, Vcc %d, Vpp %d, "
+		"io_irq %d, csc_mask %#2.2x\n", state.flags,
+		state.Vcc, state.Vpp, state.io_irq, state.csc_mask);
+
+#else	/* !CONFIG_CPC45 */
+
 	status = cb_readl (s, CB_SOCKET_STATE);
 	*value |= (status & CB_SS_32BIT) ? SS_CARDBUS : 0;
 	*value |= (status & CB_SS_3VCARD) ? SS_3VCARD : 0;
@@ -334,7 +677,7 @@ static int i365_get_status (socket_info_t * s, u_int * value)
 	/* For now, ignore cards with unsupported voltage keys */
 	if (*value & SS_XVCARD)
 		*value &= ~(SS_DETECT | SS_3VCARD | SS_XVCARD);
-
+#endif	/* CONFIG_CPC45 */
 	return 0;
 }	/* i365_get_status */
 
@@ -350,6 +693,31 @@ static int i365_set_socket (socket_info_t * s, socket_state_t * state)
 	reg |= (state->flags & SS_IOCARD) ? I365_PC_IOCARD : 0;
 	i365_set (s, I365_INTCTL, reg);
 
+#ifdef CONFIG_CPC45
+	cb_set_power (s, state);
+
+#if 0
+	/* Card status change interrupt mask */
+	reg = s->cs_irq << 4;
+	if (state->csc_mask & SS_DETECT)
+		reg |= I365_CSC_DETECT;
+	if (state->flags & SS_IOCARD) {
+		if (state->csc_mask & SS_STSCHG)
+			reg |= I365_CSC_STSCHG;
+	} else {
+		if (state->csc_mask & SS_BATDEAD)
+			reg |= I365_CSC_BVD1;
+		if (state->csc_mask & SS_BATWARN)
+			reg |= I365_CSC_BVD2;
+		if (state->csc_mask & SS_READY)
+			reg |= I365_CSC_READY;
+	}
+	i365_set (s, I365_CSCINT, reg);
+	i365_get (s, I365_CSC);
+#endif	/* 0 */
+
+#else	/* !CONFIG_CPC45 */
+
 	reg = I365_PWR_NORESET;
 	if (state->flags & SS_PWR_AUTO)
 		reg |= I365_PWR_AUTO;
@@ -361,6 +729,7 @@ static int i365_set_socket (socket_info_t * s, socket_state_t * state)
 
 	if (reg != i365_get (s, I365_POWER))
 		i365_set (s, I365_POWER, reg);
+#endif	/* CONFIG_CPC45 */
 
 	return 0;
 }	/* i365_set_socket */
@@ -372,6 +741,10 @@ static int i365_set_mem_map (socket_info_t * s, struct pccard_mem_map *mem)
 	u_short base, i;
 	u_char map;
 
+	debug ("i82365: SetMemMap(%d, %#2.2x, %d ns, %#5.5lx-%#5.5lx, %#5.5x)\n",
+		mem->map, mem->flags, mem->speed,
+		mem->sys_start, mem->sys_stop, mem->card_start);
+
 	map = mem->map;
 	if ((map > 4) ||
 	    (mem->card_start > 0x3ffffff) ||
@@ -411,13 +784,23 @@ static int i365_set_mem_map (socket_info_t * s, struct pccard_mem_map *mem)
 	}
 	i365_set_pair (s, base + I365_W_STOP, i);
 
+#ifdef CONFIG_CPC45
+	i = 0;
+#else
 	i = ((mem->card_start - mem->sys_start) >> 12) & 0x3fff;
+#endif
 	if (mem->flags & MAP_WRPROT)
 		i |= I365_MEM_WRPROT;
 	if (mem->flags & MAP_ATTRIB)
 		i |= I365_MEM_REG;
 	i365_set_pair (s, base + I365_W_OFF, i);
 
+#ifdef CONFIG_CPC45
+	/* set System Memory map Upper Adress */
+	i365_set(s, PD67_EXT_INDEX, PD67_MEM_PAGE(map));
+	i365_set(s, PD67_EXT_DATA, ((mem->sys_start >> 24) & 0xff));
+#endif
+
 	/* Turn on the window if necessary */
 	if (mem->flags & MAP_ACTIVE)
 		i365_bset (s, I365_ADDRWIN, I365_ENA_MEM (map));
@@ -431,7 +814,7 @@ static int i365_set_io_map (socket_info_t * s, struct pccard_io_map *io)
 	map = io->map;
 	/* comment out: comparison is always false due to limited range of data type */
 	if ((map > 1) || /* (io->start > 0xffff) || (io->stop > 0xffff) || */
-		(io->stop < io->start))
+	    (io->stop < io->start))
 		return -1;
 	/* Turn off the window before changing anything */
 	if (i365_get (s, I365_ADDRWIN) & I365_ENA_IO (map))
@@ -461,19 +844,37 @@ int i82365_init (void)
 	u_int val;
 	int i;
 
+#ifdef CONFIG_CPC45
+	if (SPD67290Init () != 0)
+		return 1;
+#endif
 	if ((socket.dev = pci_find_devices (supported, 0)) < 0) {
 		/* Controller not found */
 		return 1;
 	}
+	debug ("i82365 Device Found!\n");
 
 	pci_read_config_dword (socket.dev, PCI_BASE_ADDRESS_0, &socket.cb_phys);
 	socket.cb_phys &= ~0xf;
 
+#ifdef CONFIG_CPC45
+	/* + 0xfe000000 see MPC 8245 Users Manual Adress Map B */
+	socket.cb_phys += 0xfe000000;
+#endif
+
 	get_bridge_state (&socket);
 	set_bridge_opts (&socket);
 
-	i365_get_status (&socket, &val);
+	i = i365_get_status (&socket, &val);
 
+#ifdef CONFIG_CPC45
+	if (i > -1) {
+		puts (pcic[socket.type].name);
+	} else {
+		printf ("i82365: Controller not found.\n");
+		return 1;
+	}
+#else	/* !CONFIG_CPC45 */
 	if (val & SS_DETECT) {
 		if (val & SS_3VCARD) {
 			state.Vcc = state.Vpp = 33;
@@ -482,17 +883,23 @@ int i82365_init (void)
 			state.Vcc = state.Vpp = 50;
 			puts (" 5.0V card found: ");
 		} else {
-			printf ("i82365: unsupported voltage key\n");
+			puts ("i82365: unsupported voltage key\n");
 			state.Vcc = state.Vpp = 0;
 		}
 	} else {
 		/* No card inserted */
+		puts ("No card\n");
 		return 1;
 	}
+#endif	/* CONFIG_CPC45 */
 
+#ifdef CONFIG_CPC45
+	state.flags |= SS_OUTPUT_ENA;
+#else
 	state.flags = SS_IOCARD | SS_OUTPUT_ENA;
 	state.csc_mask = 0;
 	state.io_irq = 0;
+#endif
 
 	i365_set_socket (&socket, &state);
 
@@ -504,8 +911,10 @@ int i82365_init (void)
 
 	if (i == 0) {
 		/* PC Card not ready for data transfer */
+		puts ("i82365 PC Card not ready for data transfer\n");
 		return 1;
 	}
+	debug (" PC Card ready for data transfer: ");
 
 	mem.map = 0;
 	mem.flags = MAP_ATTRIB | MAP_ACTIVE;
@@ -513,17 +922,28 @@ int i82365_init (void)
 	mem.sys_start = CFG_PCMCIA_MEM_ADDR;
 	mem.sys_stop = CFG_PCMCIA_MEM_ADDR + CFG_PCMCIA_MEM_SIZE - 1;
 	mem.card_start = 0;
+	i365_set_mem_map (&socket, &mem);
 
+#ifdef CONFIG_CPC45
+	mem.map = 1;
+	mem.flags = MAP_ACTIVE;
+	mem.speed = 300;
+	mem.sys_start = CFG_PCMCIA_MEM_ADDR + CFG_PCMCIA_MEM_SIZE;
+	mem.sys_stop = CFG_PCMCIA_MEM_ADDR + (2 * CFG_PCMCIA_MEM_SIZE) - 1;
+	mem.card_start = 0;
 	i365_set_mem_map (&socket, &mem);
 
+#else	/* !CONFIG_CPC45 */
+
 	io.map = 0;
 	io.flags = MAP_AUTOSZ | MAP_ACTIVE;
 	io.speed = 0;
 	io.start = 0x0100;
 	io.stop = 0x010F;
-
 	i365_set_io_map (&socket, &io);
 
+#endif	/* CONFIG_CPC45 */
+
 #ifdef DEBUG
 	i82365_dump_regions (socket.dev);
 #endif
@@ -550,8 +970,18 @@ void i82365_exit (void)
 
 	i365_set_mem_map (&socket, &mem);
 
-	socket.state.sysctl &= 0xFFFF00FF;
+#ifdef CONFIG_CPC45
+	mem.map = 1;
+	mem.flags = 0;
+	mem.speed = 0;
+	mem.sys_start = 0;
+	mem.sys_stop = 0x1000;
+	mem.card_start = 0;
 
+	i365_set_mem_map (&socket, &mem);
+#else	/* !CONFIG_CPC45 */
+	socket.state.sysctl &= 0xFFFF00FF;
+#endif
 	state.Vcc = state.Vpp = 0;
 
 	i365_set_socket (&socket, &state);
@@ -567,7 +997,7 @@ void i82365_exit (void)
 static void i82365_dump_regions (pci_dev_t dev)
 {
 	u_int tmp[2];
-	u_int *mem = (void *) sock.cb_phys;
+	u_int *mem = (void *) socket.cb_phys;
 	u_char *cis = (void *) CFG_PCMCIA_MEM_ADDR;
 	u_char *ide = (void *) (CFG_ATA_BASE_ADDR + CFG_ATA_REG_OFFSET);
 

include/asm-ppc/u-boot.h

@@ -86,15 +86,15 @@ typedef struct bd_info {
 	hymod_conf_t	bi_hymod_conf;	/* hymod configuration information */
 #endif
 
-#if defined(CONFIG_ETH1ADDR)
+#ifdef CONFIG_HAS_ETH1
 	/* second onboard ethernet port */
 	unsigned char   bi_enet1addr[6];
 #endif
-#if defined(CONFIG_ETH2ADDR)
+#ifdef CONFIG_HAS_ETH2
 	/* third onboard ethernet port */
 	unsigned char	bi_enet2addr[6];
 #endif
-#if defined(CONFIG_ETH3ADDR)
+#ifdef CONFIG_HAS_ETH3
 	unsigned char   bi_enet3addr[6];
 #endif
 

include/configs/Alaska8220.h

@@ -106,6 +106,7 @@
 #define CONFIG_BOOTDELAY	5    /* autoboot after 5 seconds */
 #define CONFIG_BOOTARGS		"root=/dev/ram rw"
 #define CONFIG_ETHADDR		00:e0:0c:bc:e0:60
+#define CONFIG_HAS_ETH1
 #define CONFIG_ETH1ADDR		00:e0:0c:bc:e0:61
 #define CONFIG_IPADDR		192.162.1.2
 #define CONFIG_NETMASK		255.255.255.0

include/configs/CATcenter.h

@@ -98,6 +98,7 @@
 /* Ethernet stuff */
 #define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */
 #define CONFIG_ETHADDR	00:50:C2:1E:AF:FE
+#define CONFIG_HAS_ETH1
 #define CONFIG_ETH1ADDR 00:50:C2:1E:AF:FD
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/

include/configs/CPC45.h

@@ -50,8 +50,6 @@
 #define CONFIG_BAUDRATE		9600
 #define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
-#define CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz	*/
-
 #define CONFIG_PREBOOT	"echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
 
 #define CONFIG_BOOTDELAY	5
@@ -63,7 +61,10 @@
 				CFG_CMD_DATE	| \
 				CFG_CMD_DHCP	| \
 				CFG_CMD_EEPROM	| \
+				CFG_CMD_FAT	| \
+				CFG_CMD_FLASH	| \
 				CFG_CMD_I2C	| \
+				CFG_CMD_IDE	| \
 				CFG_CMD_PCI	| \
 				CFG_CMD_SDRAM	)
 
@@ -344,7 +345,7 @@
 #define ST16552_B_BASE	0x80400000	/* ST16552 channel A		*/
 #define BCSR_BASE	0x80600000	/* board control / status registers */
 #define DISPLAY_BASE	0x80600040	/* DISPLAY base			*/
-#define PCMCIA_MEM_BASE 0x81000000	/* PCMCIA memory window base	*/
+#define PCMCIA_MEM_BASE 0x83000000	/* PCMCIA memory window base	*/
 #define PCMCIA_IO_BASE	0xFE000000	/* PCMCIA IO window base	*/
 
 
@@ -464,4 +465,46 @@
 #define PCI_ENET0_MEMADDR	0x82000000
 #define PCI_PLX9030_IOADDR	0x82100000
 #define PCI_PLX9030_MEMADDR	0x82100000
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ */
+
+#define CONFIG_I82365
+
+#define CFG_PCMCIA_MEM_ADDR	PCMCIA_MEM_BASE
+#define CFG_PCMCIA_MEM_SIZE	0x1000
+
+#define CONFIG_PCMCIA_SLOT_A
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for IDE not supported	*/
+#define	CONFIG_IDE_LED			/* LED   for IDE is  supported	*/
+
+#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_HMI10
+
+#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+
+#define CFG_ATA_DATA_OFFSET	CFG_PCMCIA_MEM_SIZE
+
+/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	CFG_PCMCIA_MEM_SIZE
+
+/* Offset for alternate registers	*/
+#define CFG_ATA_ALT_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x400)
+
+#define CONFIG_DOS_PARTITION
+
 #endif	/* __CONFIG_H */

include/configs/DB64360.h

@@ -105,6 +105,7 @@
 /* first ethernet */
 #define CONFIG_ETHADDR		64:36:00:00:00:01
 											     /* next two ethernet hwaddrs */
+#define CONFIG_HAS_ETH1
 #define CONFIG_ETH1ADDR		64:36:00:00:00:02
 /* in the atlantis 64360 we have only 2 ETH port on the board,
 if we use PCI it has its own MAC addr */

include/configs/DB64460.h

@@ -43,7 +43,9 @@
 #define __LOCAL_H
 
 #define CONFIG_ETHADDR		64:46:00:00:00:01
+#define CONFIG_HAS_ETH1
 #define CONFIG_ETH1ADDR		64:46:00:00:00:02
+#define CONFIG_HAS_ETH2
 #define CONFIG_ETH2ADDR		64:46:00:00:00:03
 
 #define CONFIG_ENV_OVERWRITE

include/configs/G2000.h

@@ -164,6 +164,7 @@
 /* adding Ethernet setting:  FTS OUI 00:11:0B */
 /*----------------------------------------------------------------------------*/
 #define CONFIG_ETHADDR          00:11:0B:00:00:01
+#define CONFIG_HAS_ETH1
 #define CONFIG_ETH1ADDR         00:11:0B:00:00:02
 #define CONFIG_IPADDR		10.48.8.178
 #define CONFIG_IP1ADDR		10.48.8.188

include/configs/HUB405.h

@@ -126,6 +126,7 @@
 /* Ethernet stuff */
 #define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */
 #define CONFIG_ETHADDR	00:50:C2:1E:AF:FE
+#define CONFIG_HAS_ETH1
 #define CONFIG_ETH1ADDR 00:50:C2:1E:AF:FD
 
 /*-----------------------------------------------------------------------

include/configs/ISPAN.h

@@ -177,8 +177,10 @@
 /* Environment is in flash, there is little space left in Serial EEPROM */
 #define CFG_ENV_IS_IN_FLASH
 #define CFG_ENV_SECT_SIZE	0x10000 	/* We use one complete sector	*/
+#define CFG_ENV_SIZE		(CFG_ENV_SECT_SIZE)
 #define CFG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
 #define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
 
 /*-----------------------------------------------------------------------
  * Hard Reset Configuration Words

include/configs/LANTEC.h

@@ -90,6 +90,7 @@
 					     & ~CFG_CMD_DTT	\
 					     & ~CFG_CMD_EEPROM	\
 					     & ~CFG_CMD_ELF	\
+					     & ~CFG_CMD_EXT2	\
 					     & ~CFG_CMD_FDC	\
 					     & ~CFG_CMD_FDOS	\
 					     & ~CFG_CMD_HWFLOW	\
@@ -106,6 +107,7 @@
 					     & ~CFG_CMD_REISER	\
 					     & ~CFG_CMD_SCSI	\
 					     & ~CFG_CMD_SPI	\
+					     & ~CFG_CMD_UNIVERSE\
 					     & ~CFG_CMD_USB	\
 					     & ~CFG_CMD_VFD	\
 					     & ~CFG_CMD_XIMG	)

include/configs/MPC8260ADS.h

@@ -185,6 +185,7 @@
 				 CFG_CMD_DTT	| \
 				 CFG_CMD_EEPROM | \
 				 CFG_CMD_ELF    | \
+				 CFG_CMD_EXT2	| \
 				 CFG_CMD_FAT    | \
 				 CFG_CMD_FDC	| \
 				 CFG_CMD_FDOS	| \
@@ -198,6 +199,7 @@
 				 CFG_CMD_REISER	| \
 				 CFG_CMD_SCSI	| \
 				 CFG_CMD_SPI	| \
+				 CFG_CMD_UNIVERSE | \
 				 CFG_CMD_USB	| \
 				 CFG_CMD_VFD	| \
 				 CFG_CMD_XIMG

include/configs/MPC8266ADS.h

@@ -155,6 +155,7 @@
 				 CFG_CMD_DTT	| \
 				 CFG_CMD_EEPROM | \
 				 CFG_CMD_ELF    | \
+				 CFG_CMD_EXT2	| \
 				 CFG_CMD_FDC	| \
 				 CFG_CMD_FDOS	| \
 				 CFG_CMD_HWFLOW	| \
@@ -168,6 +169,7 @@
 				 CFG_CMD_SCSI	| \
 				 CFG_CMD_SPI	| \
 				 CFG_CMD_VFD	| \
+				 CFG_CMD_UNIVERSE | \
 				 CFG_CMD_USB	| \
 				 CFG_CMD_XIMG	) )
 

include/configs/MPC8540ADS.h

@@ -458,7 +458,9 @@
 /* The mac addresses for all ethernet interface */
 #if defined(CONFIG_TSEC_ENET)
 #define CONFIG_ETHADDR   00:E0:0C:00:00:FD
+#define CONFIG_HAS_ETH1
 #define CONFIG_ETH1ADDR  00:E0:0C:00:01:FD
+#define CONFIG_HAS_ETH2
 #define CONFIG_ETH2ADDR  00:E0:0C:00:02:FD
 #endif
 

include/configs/MPC8541CDS.h

@@ -415,7 +415,9 @@ extern unsigned long get_clock_freq(void);
 /* The mac addresses for all ethernet interface */
 #if defined(CONFIG_TSEC_ENET)
 #define CONFIG_ETHADDR   00:E0:0C:00:00:FD
+#define CONFIG_HAS_ETH1
 #define CONFIG_ETH1ADDR  00:E0:0C:00:01:FD
+#define CONFIG_HAS_ETH2
 #define CONFIG_ETH2ADDR  00:E0:0C:00:02:FD
 #endif
 

include/configs/MPC8555CDS.h

@@ -415,7 +415,9 @@ extern unsigned long get_clock_freq(void);
 /* The mac addresses for all ethernet interface */
 #if defined(CONFIG_TSEC_ENET)
 #define CONFIG_ETHADDR   00:E0:0C:00:00:FD
+#define CONFIG_HAS_ETH1
 #define CONFIG_ETH1ADDR  00:E0:0C:00:01:FD
+#define CONFIG_HAS_ETH2
 #define CONFIG_ETH2ADDR  00:E0:0C:00:02:FD
 #endif
 

include/configs/MPC8560ADS.h

@@ -504,7 +504,9 @@
 /* The mac addresses for all ethernet interface */
 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
 #define CONFIG_ETHADDR   00:E0:0C:00:00:FD
+#define CONFIG_HAS_ETH1
 #define CONFIG_ETH1ADDR  00:E0:0C:00:01:FD
+#define CONFIG_HAS_ETH2
 #define CONFIG_ETH2ADDR  00:E0:0C:00:02:FD
 #endif
 

include/configs/OCOTEA.h

@@ -154,8 +154,11 @@
 #define CONFIG_NETMASK		255.255.255.0
 #define CONFIG_IPADDR		10.1.2.3
 #define CONFIG_ETHADDR		00:04:AC:E3:28:8A
+#define CONFIG_HAS_ETH1
 #define CONFIG_ETH1ADDR		00:04:AC:E3:28:8B
+#define CONFIG_HAS_ETH2
 #define CONFIG_ETH2ADDR		00:04:AC:E3:28:8C
+#define CONFIG_HAS_ETH3
 #define CONFIG_ETH3ADDR		00:04:AC:E3:28:8D
 #define CFG_RX_ETH_BUFFER	32	  /* Number of ethernet rx buffers & descriptors */
 #define CONFIG_SERVERIP		10.1.2.2

include/configs/PN62.h

@@ -102,6 +102,8 @@
 
 #define CONFIG_MISC_INIT_R	1		/* call misc_init_r() on init	*/
 
+#define CONFIG_HAS_ETH1		1		/* add support for eth1addr	*/
+
 #define CONFIG_SHOW_BOOT_PROGRESS 1		/* Show boot progress on LEDs   */
 
 /*

include/configs/PPChameleonEVB.h

@@ -92,6 +92,7 @@
 /* Ethernet stuff */
 #define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */
 #define CONFIG_ETHADDR	00:50:c2:1e:af:fe
+#define CONFIG_HAS_ETH1
 #define CONFIG_ETH1ADDR 00:50:c2:1e:af:fd
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/

include/configs/RBC823.h

@@ -98,6 +98,7 @@
 				~CFG_CMD_BSP	& \
 				~CFG_CMD_DATE	& \
 				~CFG_CMD_DTT	& \
+				~CFG_CMD_EXT2	& \
 				~CFG_CMD_FDC	& \
 				~CFG_CMD_FDOS	& \
 				~CFG_CMD_HWFLOW	& \
@@ -113,6 +114,7 @@
 				~CFG_CMD_SCSI	& \
 				~CFG_CMD_SETGETDCR & \
 				~CFG_CMD_SPI	& \
+				~CFG_CMD_UNIVERSE & \
 				~CFG_CMD_USB	& \
 				~CFG_CMD_VFD	& \
 				~CFG_CMD_XIMG	)

include/configs/SBC8540.h

@@ -400,9 +400,11 @@
 
 /*Note: change below for your network setting!!! */
 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
-  #define CONFIG_ETHADDR	00:vv:ww:xx:yy:8a
-  #define CONFIG_ETH1ADDR	00:vv:ww:xx:yy:8b
-  #define CONFIG_ETH2ADDR	00:vv:ww:xx:yy:8c
+#  define CONFIG_ETHADDR	00:vv:ww:xx:yy:8a
+#  define CONFIG_HAS_ETH1
+#  define CONFIG_ETH1ADDR	00:vv:ww:xx:yy:8b
+#  define CONFIG_HAS_ETH2
+#  define CONFIG_ETH2ADDR	00:vv:ww:xx:yy:8c
 #endif
 
 #define CONFIG_SERVERIP		YourServerIP

include/configs/SBC8560.h

@@ -388,9 +388,11 @@
 
 /*Note: change below for your network setting!!! */
 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
-  #define CONFIG_ETHADDR	00:vv:ww:xx:yy:8a
-  #define CONFIG_ETH1ADDR	00:vv:ww:xx:yy:8b
-  #define CONFIG_ETH2ADDR	00:vv:ww:xx:yy:8c
+#  define CONFIG_ETHADDR	00:vv:ww:xx:yy:8a
+#  define CONFIG_HAS_ETH1
+#  define CONFIG_ETH1ADDR	00:vv:ww:xx:yy:8b
+#  define CONFIG_HAS_ETH2
+#  define CONFIG_ETH2ADDR	00:vv:ww:xx:yy:8c
 #endif
 
 #define CONFIG_SERVERIP		YourServerIP

include/configs/SXNI855T.h

@@ -81,6 +81,8 @@
 #define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
 #endif
 
+#define CONFIG_HAS_ETH1
+
 /*-----------------------------------------------------------------------
  * Definitions for status LED
  */

include/configs/XPEDITE1K.h

@@ -177,6 +177,10 @@ extern void out32(unsigned int, unsigned long);
 #define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
 #define CFG_RX_ETH_BUFFER   32	/* Number of ethernet rx buffers & descriptors */
 
+#define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"	*/
+#define CONFIG_HAS_ETH2		1	/* add support for "eth2addr"	*/
+#define CONFIG_HAS_ETH3		1	/* add support for "eth3addr"	*/
+
 #define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
 				CFG_CMD_PCI	| \
 				CFG_CMD_IRQ	| \
@@ -186,7 +190,7 @@ extern void out32(unsigned int, unsigned long);
 				CFG_CMD_EEPROM	| \
 				CFG_CMD_PING | \
 				CFG_CMD_ELF | \
-			    CFG_CMD_MII | \
+				CFG_CMD_MII | \
 				CFG_CMD_DIAG | \
 				CFG_CMD_FAT )
 

include/configs/ep8260.h

@@ -277,6 +277,7 @@
 					CFG_CMD_DOC	| \
 					CFG_CMD_DTT	| \
 					CFG_CMD_EEPROM	| \
+					CFG_CMD_EXT2	| \
 					CFG_CMD_FDC	| \
 					CFG_CMD_FDOS	| \
 					CFG_CMD_HWFLOW	| \
@@ -291,6 +292,7 @@
 					CFG_CMD_REISER	| \
 					CFG_CMD_SCSI	| \
 					CFG_CMD_SPI	| \
+					CFG_CMD_UNIVERSE| \
 					CFG_CMD_USB	| \
 					CFG_CMD_VFD	| \
 					CFG_CMD_XIMG	) )

include/configs/hymod.h

@@ -177,6 +177,7 @@
 					CFG_CMD_BEDBUG	| \
 					CFG_CMD_BMP	| \
 					CFG_CMD_DOC	| \
+					CFG_CMD_EXT2	| \
 					CFG_CMD_FDC	| \
 					CFG_CMD_FDOS	| \
 					CFG_CMD_FPGA    | \
@@ -191,6 +192,7 @@
 					CFG_CMD_REISER	| \
 					CFG_CMD_SCSI	| \
 					CFG_CMD_SPI	| \
+					CFG_CMD_UNIVERSE| \
 					CFG_CMD_VFD	| \
 					CFG_CMD_XIMG	) )
 

include/configs/ml300.h

@@ -58,7 +58,7 @@
 
 #define CONFIG_SYSTEMACE	1
 #define CONFIG_DOS_PARTITION	1
-#define CFG_SYSTEMACE_BASE	XPAR_SYSACE_0_BASEADDR
+#define CFG_SYSTEMACE_BASE	XPAR_OPB_SYSACE_0_BASEADDR
 #define CFG_SYSTEMACE_WIDTH	XPAR_XSYSACE_MEM_WIDTH
 
 #define CFG_ENV_IS_IN_EEPROM	1	/* environment is in EEPROM */

include/configs/quantum.h

@@ -199,7 +199,8 @@
 
 #define CFG_ENV_IS_IN_FLASH	1
 #define CFG_ENV_OFFSET	    0x00F40000	/*   Offset   of Environment Sector	absolute address 0xfff40000*/
-#define CFG_ENV_SIZE		0x40000 /* Total Size of Environment Sector	*/
+#define CFG_ENV_SECT_SIZE	0x40000	/* Total Size of Environment Sector	*/
+#define CFG_ENV_SIZE		CFG_ENV_SECT_SIZE
 #define CFG_ENV_ADDR		(CFG_FLASH_BASE + CFG_ENV_OFFSET)
 
 /* Address and size of Redundant Environment Sector	*/

include/configs/sbc8560.h

@@ -382,9 +382,11 @@
 
 /*Note: change below for your network setting!!! */
 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
-  #define CONFIG_ETHADDR	00:01:af:07:9b:8a
-  #define CONFIG_ETH1ADDR	00:01:af:07:9b:8b
-  #define CONFIG_ETH2ADDR	00:01:af:07:9b:8c
+#  define CONFIG_ETHADDR	00:01:af:07:9b:8a
+#  define CONFIG_HAS_ETH1
+#  define CONFIG_ETH1ADDR	00:01:af:07:9b:8b
+#  define CONFIG_HAS_ETH2
+#  define CONFIG_ETH2ADDR	00:01:af:07:9b:8c
 #endif
 
 #define CONFIG_SERVERIP		192.168.0.131

include/configs/stxgp3.h

@@ -368,8 +368,10 @@
 
 /*Note: change below for your network setting!!! */
 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
-#define CONFIG_ETHADDR  00:e0:0c:07:9b:8a
+#define CONFIG_ETHADDR	 00:e0:0c:07:9b:8a
+#define CONFIG_HAS_ETH1
 #define CONFIG_ETH1ADDR  00:e0:0c:07:9b:8b
+#define CONFIG_HAS_ETH2
 #define CONFIG_ETH2ADDR  00:e0:0c:07:9b:8c
 #endif
 

include/pcmcia/cirrus.h

@@ -0,0 +1,174 @@
+/*
+ * cirrus.h 1.4 1999/10/25 20:03:34
+ *
+ * The contents of this file are subject to the Mozilla Public License
+ * Version 1.1 (the "License"); you may not use this file except in
+ * compliance with the License. You may obtain a copy of the License
+ * at http://www.mozilla.org/MPL/
+ *
+ * Software distributed under the License is distributed on an "AS IS"
+ * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
+ * the License for the specific language governing rights and
+ * limitations under the License.
+ *
+ * The initial developer of the original code is David A. Hinds
+ * <dahinds@users.sourceforge.net>.  Portions created by David A. Hinds
+ * are Copyright (C) 1999 David A. Hinds.  All Rights Reserved.
+ *
+ * Alternatively, the contents of this file may be used under the
+ * terms of the GNU General Public License version 2 (the "GPL"), in which
+ * case the provisions of the GPL are applicable instead of the
+ * above.  If you wish to allow the use of your version of this file
+ * only under the terms of the GPL and not to allow others to use
+ * your version of this file under the MPL, indicate your decision by
+ * deleting the provisions above and replace them with the notice and
+ * other provisions required by the GPL.  If you do not delete the
+ * provisions above, a recipient may use your version of this file
+ * under either the MPL or the GPL.
+ */
+
+#ifndef _LINUX_CIRRUS_H
+#define _LINUX_CIRRUS_H
+
+#ifndef PCI_VENDOR_ID_CIRRUS
+#define PCI_VENDOR_ID_CIRRUS		0x1013
+#endif
+#ifndef PCI_DEVICE_ID_CIRRUS_6729
+#define PCI_DEVICE_ID_CIRRUS_6729	0x1100
+#endif
+#ifndef PCI_DEVICE_ID_CIRRUS_6832
+#define PCI_DEVICE_ID_CIRRUS_6832	0x1110
+#endif
+
+#define PD67_MISC_CTL_1		0x16	/* Misc control 1 */
+#define PD67_FIFO_CTL		0x17	/* FIFO control */
+#define PD67_MISC_CTL_2		0x1E	/* Misc control 2 */
+#define PD67_CHIP_INFO		0x1f	/* Chip information */
+#define PD67_ATA_CTL		0x026	/* 6730: ATA control */
+#define PD67_EXT_INDEX		0x2e	/* Extension index */
+#define PD67_EXT_DATA		0x2f	/* Extension data */
+
+/* PD6722 extension registers -- indexed in PD67_EXT_INDEX */
+#define PD67_DATA_MASK0		0x01	/* Data mask 0 */
+#define PD67_DATA_MASK1		0x02	/* Data mask 1 */
+#define PD67_DMA_CTL		0x03	/* DMA control */
+
+/* PD6730 extension registers -- indexed in PD67_EXT_INDEX */
+#define PD67_EXT_CTL_1		0x03	/* Extension control 1 */
+#define PD67_MEM_PAGE(n)	((n)+5)	/* PCI window bits 31:24 */
+#define PD67_EXTERN_DATA	0x0a
+#define PD67_MISC_CTL_3		0x25
+#define PD67_SMB_PWR_CTL	0x26
+
+/* I/O window address offset */
+#define PD67_IO_OFF(w)		(0x36+((w)<<1))
+
+/* Timing register sets */
+#define PD67_TIME_SETUP(n)	(0x3a + 3*(n))
+#define PD67_TIME_CMD(n)	(0x3b + 3*(n))
+#define PD67_TIME_RECOV(n)	(0x3c + 3*(n))
+
+/* Flags for PD67_MISC_CTL_1 */
+#define PD67_MC1_5V_DET		0x01	/* 5v detect */
+#define PD67_MC1_MEDIA_ENA	0x01	/* 6730: Multimedia enable */
+#define PD67_MC1_VCC_3V		0x02	/* 3.3v Vcc */
+#define PD67_MC1_PULSE_MGMT	0x04
+#define PD67_MC1_PULSE_IRQ	0x08
+#define PD67_MC1_SPKR_ENA	0x10
+#define PD67_MC1_INPACK_ENA	0x80
+
+/* Flags for PD67_FIFO_CTL */
+#define PD67_FIFO_EMPTY		0x80
+
+/* Flags for PD67_MISC_CTL_2 */
+#define PD67_MC2_FREQ_BYPASS	0x01
+#define PD67_MC2_DYNAMIC_MODE	0x02
+#define PD67_MC2_SUSPEND	0x04
+#define PD67_MC2_5V_CORE	0x08
+#define PD67_MC2_LED_ENA	0x10	/* IRQ 12 is LED enable */
+#define PD67_MC2_FAST_PCI	0x10	/* 6729: PCI bus > 25 MHz */
+#define PD67_MC2_3STATE_BIT7	0x20	/* Floppy change bit */
+#define PD67_MC2_DMA_MODE	0x40
+#define PD67_MC2_IRQ15_RI	0x80	/* IRQ 15 is ring enable */
+
+/* Flags for PD67_CHIP_INFO */
+#define PD67_INFO_SLOTS		0x20	/* 0 = 1 slot, 1 = 2 slots */
+#define PD67_INFO_CHIP_ID	0xc0
+#define PD67_INFO_REV		0x1c
+
+/* Fields in PD67_TIME_* registers */
+#define PD67_TIME_SCALE		0xc0
+#define PD67_TIME_SCALE_1	0x00
+#define PD67_TIME_SCALE_16	0x40
+#define PD67_TIME_SCALE_256	0x80
+#define PD67_TIME_SCALE_4096	0xc0
+#define PD67_TIME_MULT		0x3f
+
+/* Fields in PD67_DMA_CTL */
+#define PD67_DMA_MODE		0xc0
+#define PD67_DMA_OFF		0x00
+#define PD67_DMA_DREQ_INPACK	0x40
+#define PD67_DMA_DREQ_WP	0x80
+#define PD67_DMA_DREQ_BVD2	0xc0
+#define PD67_DMA_PULLUP		0x20	/* Disable socket pullups? */
+
+/* Fields in PD67_EXT_CTL_1 */
+#define PD67_EC1_VCC_PWR_LOCK	0x01
+#define PD67_EC1_AUTO_PWR_CLEAR	0x02
+#define PD67_EC1_LED_ENA	0x04
+#define PD67_EC1_INV_CARD_IRQ	0x08
+#define PD67_EC1_INV_MGMT_IRQ	0x10
+#define PD67_EC1_PULLUP_CTL	0x20
+
+/* Fields in PD67_MISC_CTL_3 */
+#define PD67_MC3_IRQ_MASK	0x03
+#define PD67_MC3_IRQ_PCPCI	0x00
+#define PD67_MC3_IRQ_EXTERN	0x01
+#define PD67_MC3_IRQ_PCIWAY	0x02
+#define PD67_MC3_IRQ_PCI	0x03
+#define PD67_MC3_PWR_MASK	0x0c
+#define PD67_MC3_PWR_SERIAL	0x00
+#define PD67_MC3_PWR_TI2202	0x08
+#define PD67_MC3_PWR_SMB	0x0c
+
+/* Register definitions for Cirrus PD6832 PCI-to-CardBus bridge */
+
+/* PD6832 extension registers -- indexed in PD67_EXT_INDEX */
+#define PD68_EXT_CTL_2			0x0b
+#define PD68_PCI_SPACE			0x22
+#define PD68_PCCARD_SPACE		0x23
+#define PD68_WINDOW_TYPE		0x24
+#define PD68_EXT_CSC			0x2e
+#define PD68_MISC_CTL_4			0x2f
+#define PD68_MISC_CTL_5			0x30
+#define PD68_MISC_CTL_6			0x31
+
+/* Extra flags in PD67_MISC_CTL_3 */
+#define PD68_MC3_HW_SUSP		0x10
+#define PD68_MC3_MM_EXPAND		0x40
+#define PD68_MC3_MM_ARM			0x80
+
+/* Bridge Control Register */
+#define  PD6832_BCR_MGMT_IRQ_ENA	0x0800
+
+/* Socket Number Register */
+#define PD6832_SOCKET_NUMBER		0x004c	/* 8 bit */
+
+
+typedef struct cirrus_state_t {
+    u_char		misc1, misc2;
+    u_char		timer[6];
+} cirrus_state_t;
+
+/* Cirrus options */
+static int has_dma = -1;
+static int has_led = -1;
+static int has_ring = -1;
+static int dynamic_mode = 0;
+static int freq_bypass = -1;
+static int setup_time = -1;
+static int cmd_time = -1;
+static int recov_time = -1;
+
+
+#endif /* _LINUX_CIRRUS_H */

lib_ppc/board.c

@@ -805,7 +805,7 @@ void board_init_r (gd_t *id, ulong dest_addr)
 	load_sernum_ethaddr ();
 #endif
 
-#if defined(CONFIG_ETH1ADDR)
+#ifdef CONFIG_HAS_ETH1
 	/* handle the 2nd ethernet address */
 
 	s = getenv ("eth1addr");
@@ -816,7 +816,7 @@ void board_init_r (gd_t *id, ulong dest_addr)
 			s = (*e) ? e + 1 : e;
 	}
 #endif
-#if defined(CONFIG_ETH2ADDR)
+#ifdef CONFIG_HAS_ETH2
 	/* handle the 3rd ethernet address */
 
 	s = getenv ("eth2addr");
@@ -832,7 +832,7 @@ void board_init_r (gd_t *id, ulong dest_addr)
 	}
 #endif
 
-#if defined(CONFIG_ETH3ADDR)
+#ifdef CONFIG_HAS_ETH3
 	/* handle 4th ethernet address */
 	s = getenv("eth3addr");
 #if defined(CONFIG_XPEDITE1K)

tools/env/fw_env.c

@@ -106,6 +106,9 @@ static uchar default_environment[] = {
 #ifdef	CONFIG_ETH2ADDR
 	"eth2addr=" MK_STR (CONFIG_ETH2ADDR) "\0"
 #endif
+#ifdef	CONFIG_ETH3ADDR
+	"eth3addr=" MK_STR (CONFIG_ETH3ADDR) "\0"
+#endif
 #ifdef	CONFIG_ETHPRIME
 	"ethprime=" CONFIG_ETHPRIME "\0"
 #endif