Merge with /home/wd/git/u-boot/custodian/u-boot-arm

MAKEALL

@@ -186,7 +186,7 @@ LIST_SA="assabet dnp1110 gcplus lart shannon"
 LIST_ARM7="	\
 	armadillo	B2		ep7312		evb4510		\
 	impa7		integratorap	ap7		ap720t		\
-	lpc2292sodimm	modnet50					\
+	lpc2292sodimm	modnet50	SMN42				\
 "
 
 #########################################################################

Makefile

@@ -2139,7 +2139,10 @@ evb4510_config :	unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm720t evb4510
 
 lpc2292sodimm_config:	unconfig
-	@$(MKCONFIG) $(@:_config=) arm arm720t lpc2292sodimm
+	@$(MKCONFIG) $(@:_config=) arm arm720t lpc2292sodimm NULL lpc2292
+
+SMN42_config	:	unconfig
+	@$(MKCONFIG) $(@:_config=) arm arm720t SMN42 siemens lpc2292
 
 #########################################################################
 ## XScale Systems

board/lpc2292sodimm/Makefile

@@ -1,7 +1,6 @@
 #
-# (C) Copyright 2002
-# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
-# Marius Groeger <mgroeger@sysgo.de>
+# (C) Copyright 2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # See file CREDITS for list of people who contributed to this
 # project.
@@ -24,35 +23,29 @@
 
 include $(TOPDIR)/config.mk
 
-LIB	= lib$(BOARD).a
+LIB	= $(obj)lib$(BOARD).a
 
-OBJS	:= lpc2292sodimm.o flash.o mmc.o spi.o mmc_hw.o eth.o
-SOBJS	:= lowlevel_init.o iap_entry.o
+COBJS	:= flash.o lpc2292sodimm.o
+SOBJTS	:= lowlevel_init.o
 
-$(LIB):	$(OBJS) $(SOBJS)
-	$(AR) crv $@ $(OBJS) $(SOBJS)
+SRCS	:= $(SOBJTS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJTS))
 
-# this MUST be compiled as thumb code!
-iap_entry.o:
-	arm-linux-gcc  -D__ASSEMBLY__ -g  -Os   -fno-strict-aliasing  \
-	-fno-common -ffixed-r8 -msoft-float  -D__KERNEL__ \
-	-DTEXT_BASE=0x81500000  -I/home/garyj/proj/LPC/u-boot/include \
-	-fno-builtin -ffreestanding -nostdinc -isystem \
-	/opt/eldk/arm/usr/bin/../lib/gcc/arm-linux/4.0.0/include -pipe  \
-	-DCONFIG_ARM -D__ARM__ -march=armv4t -mtune=arm7tdmi -mabi=apcs-gnu \
-	-c -o iap_entry.o iap_entry.S
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
 
 clean:
 	rm -f $(SOBJS) $(OBJS)
 
 distclean:	clean
-	rm -f $(LIB) core *.bak .depend
+	rm -f $(LIB) core *.bak $(obj).depend
 
 #########################################################################
 
-.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
-		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
 
--include .depend
+sinclude $(obj).depend
 
 #########################################################################

board/lpc2292sodimm/flash.c

@@ -1,6 +1,9 @@
 /*
  * (C) Copyright 2006 Embedded Artists AB <www.embeddedartists.com>
  *
+ * Modified to use the routines in cpu/arm720t/lpc2292/flash.c by
+ * Gary Jennejohn <garyj@denx,de>
+ *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
@@ -20,84 +23,16 @@
 #include <common.h>
 #include <asm/arch/hardware.h>
 
-/* IAP commands use 32 bytes at the top of CPU internal sram, we
-   use 512 bytes below that */
-#define COPY_BUFFER_LOCATION 0x40003de0
-
-#define IAP_LOCATION 0x7ffffff1
-#define IAP_CMD_PREPARE 50
-#define IAP_CMD_COPY 51
-#define IAP_CMD_ERASE 52
-#define IAP_CMD_CHECK 53
-#define IAP_CMD_ID 54
-#define IAP_CMD_VERSION 55
-#define IAP_CMD_COMPARE 56
-
-#define IAP_RET_CMD_SUCCESS 0
-
 #define SST_BASEADDR 0x80000000
 #define SST_ADDR1 ((volatile ushort*)(SST_BASEADDR + (0x5555 << 1)))
 #define SST_ADDR2 ((volatile ushort*)(SST_BASEADDR + (0x2AAA << 1)))
 
 
-static unsigned long command[5];
-static unsigned long result[2];
-
 flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
 
-extern void iap_entry(unsigned long * command, unsigned long * result);
-
-/*-----------------------------------------------------------------------
- *
- */
-int get_flash_sector(flash_info_t * info, ulong flash_addr)
-{
-	int i;
-
-	for(i=1; i < (info->sector_count); i++) {
-		if (flash_addr < (info->start[i]))
-			break;
-	}
-
-	return (i-1);
-}
-
-/*-----------------------------------------------------------------------
- * This function assumes that flash_addr is aligned on 512 bytes boundary
- * in flash. This function also assumes that prepare have been called
- * for the sector in question.
- */
-int copy_buffer_to_flash(flash_info_t * info, ulong flash_addr)
-{
-	int first_sector;
-	int last_sector;
-
-	first_sector = get_flash_sector(info, flash_addr);
-	last_sector = get_flash_sector(info, flash_addr + 512 - 1);
-
-	/* prepare sectors for write */
-	command[0] = IAP_CMD_PREPARE;
-	command[1] = first_sector;
-	command[2] = last_sector;
-	iap_entry(command, result);
-	if (result[0] != IAP_RET_CMD_SUCCESS) {
-		printf("IAP prepare failed\n");
-		return ERR_PROG_ERROR;
-	}
-
-	command[0] = IAP_CMD_COPY;
-	command[1] = flash_addr;
-	command[2] = COPY_BUFFER_LOCATION;
-	command[3] = 512;
-	command[4] = CFG_SYS_CLK_FREQ >> 10;
-	iap_entry(command, result);
-	if (result[0] != IAP_RET_CMD_SUCCESS) {
-		printf("IAP copy failed\n");
-		return 1;
-	}
-
-	return 0;
-}
+extern int lpc2292_copy_buffer_to_flash(flash_info_t *, ulong);
+extern int lpc2292_flash_erase(flash_info_t *, int, int);
+extern int lpc2292_write_buff (flash_info_t *, uchar *, ulong, ulong);
 
 /*-----------------------------------------------------------------------
  *
@@ -220,56 +155,6 @@ void flash_print_info (flash_info_t * info)
 	printf ("\n");
 }
 
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase_philips (flash_info_t * info, int s_first, int s_last)
-{
-	int flag;
-	int prot;
-	int sect;
-
-	prot = 0;
-	for (sect = s_first; sect <= s_last; ++sect) {
-		if (info->protect[sect]) {
-			prot++;
-		}
-	}
-	if (prot)
-		return ERR_PROTECTED;
-
-
-	flag = disable_interrupts();
-
-	printf ("Erasing %d sectors starting at sector %2d.\n"
-	"This make take some time ... ",
-	s_last - s_first + 1, s_first);
-
-	command[0] = IAP_CMD_PREPARE;
-	command[1] = s_first;
-	command[2] = s_last;
-	iap_entry(command, result);
-	if (result[0] != IAP_RET_CMD_SUCCESS) {
-		printf("IAP prepare failed\n");
-		return ERR_PROTECTED;
-	}
-
-	command[0] = IAP_CMD_ERASE;
-	command[1] = s_first;
-	command[2] = s_last;
-	command[3] = CFG_SYS_CLK_FREQ >> 10;
-	iap_entry(command, result);
-	if (result[0] != IAP_RET_CMD_SUCCESS) {
-		printf("IAP erase failed\n");
-		return ERR_PROTECTED;
-	}
-
-	if (flag)
-		enable_interrupts();
-
-	return ERR_OK;
-}
-
 int flash_erase_sst (flash_info_t * info, int s_first, int s_last)
 {
 	int i;
@@ -294,7 +179,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
 		case (SST_MANUFACT & FLASH_VENDMASK):
 			return flash_erase_sst(info, s_first, s_last);
 		case (PHILIPS_LPC2292 & FLASH_VENDMASK):
-			return flash_erase_philips(info, s_first, s_last);
+			return lpc2292_flash_erase(info, s_first, s_last);
 		default:
 			return ERR_PROTECTED;
 	}
@@ -353,122 +238,13 @@ int write_buff_sst (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
 	return ret;
 }
 
-int write_buff_philips (flash_info_t * info,
-			uchar * src,
-			ulong addr,
-			ulong cnt)
-{
-	int first_copy_size;
-	int last_copy_size;
-	int first_block;
-	int last_block;
-	int nbr_mid_blocks;
-	uchar memmap_value;
-	ulong i;
-	uchar* src_org;
-	uchar* dst_org;
-	int ret = ERR_OK;
-
-	src_org = src;
-	dst_org = (uchar*)addr;
-
-	first_block = addr / 512;
-	last_block = (addr + cnt) / 512;
-	nbr_mid_blocks = last_block - first_block - 1;
-
-	first_copy_size = 512 - (addr % 512);
-	last_copy_size = (addr + cnt) % 512;
-
-#if 0
-	printf("\ncopy first block: (1) %lX -> %lX 0x200 bytes, "
-		"(2) %lX -> %lX 0x%X bytes, (3) %lX -> %lX 0x200 bytes\n",
-	(ulong)(first_block * 512),
-	(ulong)COPY_BUFFER_LOCATION,
-	(ulong)src,
-	(ulong)(COPY_BUFFER_LOCATION + 512 - first_copy_size),
-	first_copy_size,
-	(ulong)COPY_BUFFER_LOCATION,
-	(ulong)(first_block * 512));
-#endif
-
-	/* copy first block */
-	memcpy((void*)COPY_BUFFER_LOCATION,
-		(void*)(first_block * 512), 512);
-	memcpy((void*)(COPY_BUFFER_LOCATION + 512 - first_copy_size),
-		src, first_copy_size);
-	copy_buffer_to_flash(info, first_block * 512);
-	src += first_copy_size;
-	addr += first_copy_size;
-
-	/* copy middle blocks */
-	for (i = 0; i < nbr_mid_blocks; i++) {
-#if 0
-		printf("copy middle block: %lX -> %lX 512 bytes, "
-		"%lX -> %lX 512 bytes\n",
-		(ulong)src,
-		(ulong)COPY_BUFFER_LOCATION,
-		(ulong)COPY_BUFFER_LOCATION,
-		(ulong)addr);
-#endif
-		memcpy((void*)COPY_BUFFER_LOCATION, src, 512);
-		copy_buffer_to_flash(info, addr);
-		src += 512;
-		addr += 512;
-	}
-
-
-	if (last_copy_size > 0) {
-#if 0
-		printf("copy last block: (1) %lX -> %lX 0x200 bytes, "
-		"(2) %lX -> %lX 0x%X bytes, (3) %lX -> %lX x200 bytes\n",
-		(ulong)(last_block * 512),
-		(ulong)COPY_BUFFER_LOCATION,
-		(ulong)src,
-		(ulong)(COPY_BUFFER_LOCATION),
-		last_copy_size,
-		(ulong)COPY_BUFFER_LOCATION,
-		(ulong)addr);
-#endif
-		/* copy last block */
-		memcpy((void*)COPY_BUFFER_LOCATION,
-			(void*)(last_block * 512), 512);
-		memcpy((void*)COPY_BUFFER_LOCATION,
-			src, last_copy_size);
-		copy_buffer_to_flash(info, addr);
-	}
-
-	/* verify write */
-	memmap_value = GET8(MEMMAP);
-
-	disable_interrupts();
-
-	PUT8(MEMMAP, 01);		/* we must make sure that initial 64
-							   bytes are taken from flash when we
-							   do the compare */
-
-	for (i = 0; i < cnt; i++) {
-		if (*dst_org != *src_org){
-			printf("Write failed. Byte %lX differs\n", i);
-			ret = ERR_PROG_ERROR;
-			break;
-		}
-		dst_org++;
-		src_org++;
-	}
-
-	PUT8(MEMMAP, memmap_value);
-	enable_interrupts();
-
-	return ret;
-}
-
 int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
 {
 	switch (info->flash_id & FLASH_VENDMASK) {
 		case (SST_MANUFACT & FLASH_VENDMASK):
 			return write_buff_sst(info, src, addr, cnt);
 		case (PHILIPS_LPC2292 & FLASH_VENDMASK):
-			return write_buff_philips(info, src, addr, cnt);
+			return lpc2292_write_buff(info, src, addr, cnt);
 		default:
 			return ERR_PROG_ERROR;
 	}

board/siemens/SMN42/Makefile

@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= flash.o smn42.o
+SOBJTS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJTS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJTS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

board/siemens/SMN42/config.mk

@@ -0,0 +1,30 @@
+#
+# (C) Copyright 2000
+# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+# Marius Groeger <mgroeger@sysgo.de>
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#address where u-boot will be relocated
+#TEXT_BASE = 0x0
+TEXT_BASE = 0x81500000

board/siemens/SMN42/flash.c

@@ -0,0 +1,476 @@
+/*
+ * (C) Copyright 2006 Embedded Artists AB <www.embeddedartists.com>
+ *
+ * (C) Copyright 2007 Gary Jennejohn garyj@denx.de
+ * Modified to use the routines in cpu/arm720t/lpc2292/flash.c.
+ * Heavily modified to support the SMN42 board from Siemens
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/byteorder.h>
+#include <asm/arch/hardware.h>
+
+static unsigned long flash_addr_table[CFG_MAX_FLASH_BANKS] 
+						= CFG_FLASH_BANKS_LIST;
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+extern int lpc2292_copy_buffer_to_flash(flash_info_t *, ulong);
+extern int lpc2292_flash_erase(flash_info_t *, int, int);
+extern int lpc2292_write_buff (flash_info_t *, uchar *, ulong, ulong);
+static unsigned long ext_flash_init(void);
+static int ext_flash_erase(flash_info_t *, int, int);
+static int ext_write_buff(flash_info_t *, uchar *, ulong, ulong);
+
+/*-----------------------------------------------------------------------
+ */
+
+ulong flash_init (void)
+{
+	int j, k;
+	ulong size = 0;
+	ulong flashbase = 0;
+
+	flash_info[0].flash_id = PHILIPS_LPC2292;
+	flash_info[0].size = 0x003E000;	/* 256 - 8 KB */
+	flash_info[0].sector_count = 17;
+	memset (flash_info[0].protect, 0, 17);
+	flashbase = 0x00000000;
+	for (j = 0, k = 0; j < 8; j++, k++) {
+		flash_info[0].start[k] = flashbase;
+		flashbase += 0x00002000;
+	}
+	for (j = 0; j < 2; j++, k++) {
+		flash_info[0].start[k] = flashbase;
+		flashbase += 0x00010000;
+	}
+	for (j = 0; j < 7; j++, k++) {
+		flash_info[0].start[k] = flashbase;
+		flashbase += 0x00002000;
+	}
+	size += flash_info[0].size;
+
+	/* Protect monitor and environment sectors */
+	flash_protect (FLAG_PROTECT_SET,
+		 0x0,
+		 0x0 + monitor_flash_len - 1,
+		 &flash_info[0]);
+
+	flash_protect (FLAG_PROTECT_SET,
+		 CFG_ENV_ADDR,
+		 CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+		 &flash_info[0]);
+
+	size += ext_flash_init();
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+	int erased = 0;
+	unsigned long j;
+	unsigned long count;
+	unsigned char *p;
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case (PHILIPS_LPC2292 & FLASH_VENDMASK):
+		printf("Philips: ");
+		break;
+	case FLASH_MAN_AMD:
+		printf("AMD: ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case (PHILIPS_LPC2292 & FLASH_TYPEMASK):
+		printf("LPC2292 internal flash\n");
+		break;
+	case FLASH_S29GL128N:
+		printf ("S29GL128N (128 Mbit, uniform sector size)\n");
+		break;
+	default:
+		printf("Unknown Chip Type\n");
+		return;
+	}
+
+	printf ("  Size: %ld KB in %d Sectors\n",
+	  info->size >> 10, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; i++) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+		if (i < (info->sector_count - 1)) {
+			count = info->start[i+1] - info->start[i];
+		}
+		else {
+			count = info->start[0] + info->size - info->start[i];
+		}
+		p = (unsigned char*)(info->start[i]);
+		erased = 1;
+		for (j = 0; j < count; j++) {
+			if (*p != 0xFF) {
+				erased = 0;
+				break;
+			}
+			p++;
+		}
+		printf (" %08lX%s%s", info->start[i], info->protect[i] ? " RO" : "   ",
+			erased ? " E" : "  ");
+	}
+	printf ("\n");
+}
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	switch (info->flash_id & FLASH_TYPEMASK) {
+		case (PHILIPS_LPC2292 & FLASH_TYPEMASK):
+			return lpc2292_flash_erase(info, s_first, s_last);
+		case FLASH_S29GL128N:
+			return ext_flash_erase(info, s_first, s_last);
+		default:
+			return ERR_PROTECTED;
+	}
+	return ERR_PROTECTED;
+}
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	switch (info->flash_id & FLASH_TYPEMASK) {
+		case (PHILIPS_LPC2292 & FLASH_TYPEMASK):
+			return lpc2292_write_buff(info, src, addr, cnt);
+		case FLASH_S29GL128N:
+			return ext_write_buff(info, src, addr, cnt);
+		default:
+			return ERR_PROG_ERROR;
+	}
+	return ERR_PROG_ERROR;
+}
+
+/*--------------------------------------------------------------------------
+ * From here on is code for the external S29GL128N taken from cam5200_flash.c
+ */
+
+#define CFG_FLASH_WORD_SIZE unsigned short
+
+static int wait_for_DQ7_32(flash_info_t * info, int sect)
+{
+	ulong start, now, last;
+	volatile CFG_FLASH_WORD_SIZE *addr =
+		(CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+
+	start = get_timer(0);
+	last = start;
+	while ((addr[0] & (CFG_FLASH_WORD_SIZE) 0x00800080) !=
+			(CFG_FLASH_WORD_SIZE) 0x00800080) {
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf("Timeout\n");
+			return -1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc('.');
+			last = now;
+		}
+	}
+	return 0;
+}
+
+int ext_flash_erase(flash_info_t * info, int s_first, int s_last)
+{
+	volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
+	volatile CFG_FLASH_WORD_SIZE *addr2;
+	int flag, prot, sect, l_sect, ret;
+
+	ret = 0;
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN)
+			printf("- missing\n");
+		else
+			printf("- no sectors to erase\n");
+		return 1;
+	}
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect])
+			prot++;
+	}
+
+	if (prot)
+		printf("- Warning: %d protected sectors will not be erased!", prot);
+
+	printf("\n");
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+
+			addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+			addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+			addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080;
+			addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+			addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+			addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00300030;	/* sector erase */
+
+			l_sect = sect;
+			/*
+			 * Wait for each sector to complete, it's more
+			 * reliable.  According to AMD Spec, you must
+			 * issue all erase commands within a specified
+			 * timeout.  This has been seen to fail, especially
+			 * if printf()s are included (for debug)!!
+			 */
+			ret = wait_for_DQ7_32(info, sect);
+			if (ret) {
+				ret = ERR_PROTECTED;
+				break;
+			}
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay(1000);
+
+	/* reset to read mode */
+	addr = (CFG_FLASH_WORD_SIZE *) info->start[0];
+	addr[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
+
+	if (ret)
+		printf(" error\n");
+	else
+		printf(" done\n");
+	return ret;
+}
+
+static ulong flash_get_size(vu_long * addr, flash_info_t * info)
+{
+	short i;
+	CFG_FLASH_WORD_SIZE value;
+	ulong base = (ulong) addr;
+	volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+	addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+	addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00900090;
+	udelay(1000);
+
+	value = addr2[0];
+
+	switch (value) {
+		case (CFG_FLASH_WORD_SIZE) AMD_MANUFACT:
+			info->flash_id = FLASH_MAN_AMD;
+			break;
+		default:
+			info->flash_id = FLASH_UNKNOWN;
+			info->sector_count = 0;
+			info->size = 0;
+			return (0);	/* no or unknown flash  */
+	}
+
+	value = addr2[1];	/* device ID            */
+
+	switch (value) {
+		case (CFG_FLASH_WORD_SIZE)AMD_ID_MIRROR:
+			value = addr2[14];
+			switch(value) {
+				case (CFG_FLASH_WORD_SIZE)AMD_ID_GL128N_2:
+					value = addr2[15];
+					if (value != (CFG_FLASH_WORD_SIZE)AMD_ID_GL128N_3) {
+						info->flash_id = FLASH_UNKNOWN;
+					} else {
+						info->flash_id += FLASH_S29GL128N;
+						info->sector_count = 128;
+						info->size = 0x01000000;
+					}
+					break;
+				default:
+					info->flash_id = FLASH_UNKNOWN;
+					return(0);
+			}
+			break;
+
+		default:
+			info->flash_id = FLASH_UNKNOWN;
+			return (0);	/* => no or unknown flash */
+	}
+
+	/* set up sector start address table */
+	for (i = 0; i < info->sector_count; i++)
+		info->start[i] = base + (i * 0x00020000);
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]);
+
+		info->protect[i] = addr2[2] & 1;
+	}
+
+	/* issue bank reset to return to read mode */
+	addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0;
+
+	return (info->size);
+}
+
+static unsigned long ext_flash_init(void)
+{
+	unsigned long total_b = 0;
+	unsigned long size_b[CFG_MAX_FLASH_BANKS];
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i = 1; i < CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+		flash_info[i].sector_count = -1;
+		flash_info[i].size = 0;
+
+		/* call flash_get_size() to initialize sector address */
+		size_b[i] = flash_get_size((vu_long *) flash_addr_table[i],
+				&flash_info[i]);
+
+		flash_info[i].size = size_b[i];
+
+		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+			printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
+					i+1, size_b[i], size_b[i] << 20);
+			flash_info[i].sector_count = -1;
+			flash_info[i].size = 0;
+		}
+
+		total_b += flash_info[i].size;
+	}
+
+	return total_b;
+}
+
+static int write_word(flash_info_t * info, ulong dest, ushort data)
+{
+	volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
+	volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest;
+	volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) &data;
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*dest2 & *data2) != *data2) {
+		return (2);
+	}
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+	addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+	addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00A000A0;
+	*dest2 = *data2;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer(0);
+	while ((*dest2 & (CFG_FLASH_WORD_SIZE) 0x00800080) !=
+			(*data2 & (CFG_FLASH_WORD_SIZE) 0x00800080)) {
+
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			printf("WRITE_TOUT\n");
+			return (1);
+		}
+	}
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ * This is taken from the original flash.c for the LPC2292 SODIMM board
+ * and modified to suit.
+ */
+
+int ext_write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ushort tmp;
+	ulong i;
+	uchar* src_org;
+	uchar* dst_org;
+	ulong cnt_org = cnt;
+	int ret = ERR_OK;
+
+	src_org = src;
+	dst_org = (uchar*)addr;
+
+	if (addr & 1) {		/* if odd address */
+		tmp = *((uchar*)(addr - 1)); /* little endian */
+		tmp |= (*src << 8);
+		if (write_word(info, addr - 1, tmp))
+			return ERR_PROG_ERROR;
+		addr += 1;
+		cnt -= 1;
+		src++;
+	}
+	while (cnt > 1) {
+		tmp = ((*(src+1)) << 8) + (*src); /* little endian */
+		if (write_word(info, addr, tmp))
+			return ERR_PROG_ERROR;
+		addr += 2;
+		src += 2;
+		cnt -= 2;
+	}
+	if (cnt > 0) {
+		tmp = (*((uchar*)(addr + 1))) << 8;
+		tmp |= *src;
+		if (write_word(info, addr, tmp))
+			return ERR_PROG_ERROR;
+	}
+
+	for (i = 0; i < cnt_org; i++) {
+		if (*dst_org != *src_org) {
+			printf("Write failed. Byte %lX differs\n", i);
+			ret = ERR_PROG_ERROR;
+			break;
+		}
+		dst_org++;
+		src_org++;
+	}
+
+	return ret;
+}

board/siemens/SMN42/lowlevel_init.S

@@ -0,0 +1,123 @@
+/*
+ * (C) Copyright 2006 Embedded Artists AB <www.embeddedartists.com>
+ *
+ * Slight modifications made to support the SMN42 board from Siemens.
+ * 2007 Gary Jennejohn garyj@denx.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/hardware.h>
+
+/* some parameters for the board */
+/* setting up the CPU-internal memory */
+#define 	SRAM_START 	0x40000000
+#define 	SRAM_SIZE	0x00004000
+#define   BCFG0_VALUE 0x1000ffef
+#define   BCFG1_VALUE 0x10005D2F
+#define   BCFG2_VALUE 0x10005D2F
+/*
+ * For P0.18 to set ZZ to the SRAMs to 1. Also set P0.2 (SCL) and P0.3 (SDA)
+ * for the bit-banger I2C driver correctly.
+ */
+#define   IO0_VALUE   0x4000C
+
+_TEXT_BASE:
+	.word	TEXT_BASE
+MEMMAP_ADR:
+	.word	MEMMAP
+BCFG0_ADR:
+	.word BCFG0
+_BCFG0_VALUE:
+	.word BCFG0_VALUE
+BCFG1_ADR:
+	.word	BCFG1
+_BCFG1_VALUE:
+	.word	BCFG1_VALUE
+BCFG2_ADR:
+	.word	BCFG2
+_BCFG2_VALUE:
+	.word	BCFG2_VALUE
+IO0DIR_ADR:
+	.word	IO0DIR
+_IO0DIR_VALUE:
+	.word	IO0_VALUE
+IO0SET_ADR:
+	.word	IO0SET
+_IO0SET_VALUE:
+	.word	IO0_VALUE
+PINSEL2_ADR:
+	.word	PINSEL2
+PINSEL2_MASK:
+	.word	0x00000000
+PINSEL2_VALUE:
+	.word	0x0F804914
+
+.extern _start
+
+.globl lowlevel_init
+lowlevel_init:
+	/* set up memory control register for bank 0 */
+	ldr r0, _BCFG0_VALUE
+	ldr r1, BCFG0_ADR
+	str r0, [r1]
+
+	/* set up memory control register for bank 1 */
+	ldr	r0, _BCFG1_VALUE
+	ldr	r1, BCFG1_ADR
+	str	r0, [r1]
+
+	/* set up memory control register for bank 2 */
+	ldr	r0, _BCFG2_VALUE
+	ldr	r1, BCFG2_ADR
+	str	r0, [r1]
+
+	/* set IO0DIR to make P0.2, P0.3  and P0.18 outputs */
+	ldr	r0, _IO0DIR_VALUE
+	ldr	r1, IO0DIR_ADR
+	str	r0, [r1]
+
+	/* set P0.18 to 1 */
+	ldr	r0, _IO0SET_VALUE
+	ldr	r1, IO0SET_ADR
+	str	r0, [r1]
+
+	/* set up PINSEL2 for bus-pins */
+	ldr	r0, PINSEL2_ADR
+	ldr	r1, [r0]
+	ldr	r2, PINSEL2_MASK
+	ldr	r3, PINSEL2_VALUE
+	and	r1, r1, r2
+	orr	r1, r1, r3
+	str	r1, [r0]
+
+	/* move vectors to beginning of SRAM */
+	mov	r2, #SRAM_START
+	mov	r0, #0 /*_start*/
+	ldmneia r0!, {r3-r10}
+	stmneia r2!, {r3-r10}
+	ldmneia r0, {r3-r9}
+	stmneia r2, {r3-r9}
+
+	/* Set-up MEMMAP register, so vectors are taken from SRAM */
+	ldr	r0, MEMMAP_ADR
+	mov	r1, #0x02	/* vectors re-mapped to static RAM */
+	str	r1, [r0]
+
+	/* everything is fine now */
+	mov	pc, lr

board/siemens/SMN42/smn42.c

@@ -0,0 +1,62 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2005 Rowel Atienza <rowel@diwalabs.com>
+ * Armadillo board HT1070
+ *
+ * (C) Copyright 2007 Gary Jennejohn <garyj@denx.de>
+ * Siemens board SMN42
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <clps7111.h>
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* arch number MACH_TYPE_ARMADILLO - not official*/
+	gd->bd->bi_arch_number = 83;
+
+	/* location of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x00000100;
+
+	return 0;
+}
+
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return (0);
+}

board/siemens/SMN42/u-boot.lds

@@ -0,0 +1,55 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/arm720t/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}

common/soft_i2c.c

@@ -36,6 +36,9 @@
 #ifdef	CONFIG_IXP425			/* only valid for IXP425 */
 #include <asm/arch/ixp425.h>
 #endif
+#ifdef CONFIG_LPC2292
+#include <asm/arch/hardware.h>
+#endif
 #include <i2c.h>
 
 #if defined(CONFIG_SOFT_I2C)

cpu/arm720t/lpc2292/Makefile

@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2000-2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(SOC).a
+
+COBJS	= flash.o mmc.o mmc_hw.o spi.o
+SOBJS	= $(obj)iap_entry.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+all:	$(obj).depend $(LIB)
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+# this MUST be compiled as thumb code!
+$(SOBJS):
+	$(CC) $(AFLAGS) -march=armv4t -c -o $(SOBJS) iap_entry.S
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

cpu/arm720t/lpc2292/flash.c

@@ -0,0 +1,249 @@
+/*
+ * (C) Copyright 2006 Embedded Artists AB <www.embeddedartists.com>
+ *
+ * Modified to remove all but the IAP-command related code by
+ * Gary Jennejohn <garyj@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+
+/* IAP commands use 32 bytes at the top of CPU internal sram, we
+   use 512 bytes below that */
+#define COPY_BUFFER_LOCATION 0x40003de0
+
+#define IAP_LOCATION 0x7ffffff1
+#define IAP_CMD_PREPARE 50
+#define IAP_CMD_COPY 51
+#define IAP_CMD_ERASE 52
+#define IAP_CMD_CHECK 53
+#define IAP_CMD_ID 54
+#define IAP_CMD_VERSION 55
+#define IAP_CMD_COMPARE 56
+
+#define IAP_RET_CMD_SUCCESS 0
+
+static unsigned long command[5];
+static unsigned long result[2];
+
+extern void iap_entry(unsigned long * command, unsigned long * result);
+
+/*-----------------------------------------------------------------------
+ *
+ */
+static int get_flash_sector(flash_info_t * info, ulong flash_addr)
+{
+	int i;
+
+	for(i = 1; i < (info->sector_count); i++) {
+		if (flash_addr < (info->start[i]))
+			break;
+	}
+
+	return (i-1);
+}
+
+/*-----------------------------------------------------------------------
+ * This function assumes that flash_addr is aligned on 512 bytes boundary
+ * in flash. This function also assumes that prepare have been called
+ * for the sector in question.
+ */
+int lpc2292_copy_buffer_to_flash(flash_info_t * info, ulong flash_addr)
+{
+	int first_sector;
+	int last_sector;
+
+	first_sector = get_flash_sector(info, flash_addr);
+	last_sector = get_flash_sector(info, flash_addr + 512 - 1);
+
+	/* prepare sectors for write */
+	command[0] = IAP_CMD_PREPARE;
+	command[1] = first_sector;
+	command[2] = last_sector;
+	iap_entry(command, result);
+	if (result[0] != IAP_RET_CMD_SUCCESS) {
+		printf("IAP prepare failed\n");
+		return ERR_PROG_ERROR;
+	}
+
+	command[0] = IAP_CMD_COPY;
+	command[1] = flash_addr;
+	command[2] = COPY_BUFFER_LOCATION;
+	command[3] = 512;
+	command[4] = CFG_SYS_CLK_FREQ >> 10;
+	iap_entry(command, result);
+	if (result[0] != IAP_RET_CMD_SUCCESS) {
+		printf("IAP copy failed\n");
+		return 1;
+	}
+
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int lpc2292_flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag;
+	int prot;
+	int sect;
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+	if (prot)
+		return ERR_PROTECTED;
+
+
+	flag = disable_interrupts();
+
+	printf ("Erasing %d sectors starting at sector %2d.\n"
+	"This make take some time ... ",
+	s_last - s_first + 1, s_first);
+
+	command[0] = IAP_CMD_PREPARE;
+	command[1] = s_first;
+	command[2] = s_last;
+	iap_entry(command, result);
+	if (result[0] != IAP_RET_CMD_SUCCESS) {
+		printf("IAP prepare failed\n");
+		return ERR_PROTECTED;
+	}
+
+	command[0] = IAP_CMD_ERASE;
+	command[1] = s_first;
+	command[2] = s_last;
+	command[3] = CFG_SYS_CLK_FREQ >> 10;
+	iap_entry(command, result);
+	if (result[0] != IAP_RET_CMD_SUCCESS) {
+		printf("IAP erase failed\n");
+		return ERR_PROTECTED;
+	}
+
+	if (flag)
+		enable_interrupts();
+
+	return ERR_OK;
+}
+
+int lpc2292_write_buff (flash_info_t * info, uchar * src, ulong addr,
+			ulong cnt)
+{
+	int first_copy_size;
+	int last_copy_size;
+	int first_block;
+	int last_block;
+	int nbr_mid_blocks;
+	uchar memmap_value;
+	ulong i;
+	uchar* src_org;
+	uchar* dst_org;
+	int ret = ERR_OK;
+
+	src_org = src;
+	dst_org = (uchar*)addr;
+
+	first_block = addr / 512;
+	last_block = (addr + cnt) / 512;
+	nbr_mid_blocks = last_block - first_block - 1;
+
+	first_copy_size = 512 - (addr % 512);
+	last_copy_size = (addr + cnt) % 512;
+
+	debug("\ncopy first block: (1) %lX -> %lX 0x200 bytes, "
+		"(2) %lX -> %lX 0x%X bytes, (3) %lX -> %lX 0x200 bytes\n",
+	(ulong)(first_block * 512),
+	(ulong)COPY_BUFFER_LOCATION,
+	(ulong)src,
+	(ulong)(COPY_BUFFER_LOCATION + 512 - first_copy_size),
+	first_copy_size,
+	(ulong)COPY_BUFFER_LOCATION,
+	(ulong)(first_block * 512));
+
+	/* copy first block */
+	memcpy((void*)COPY_BUFFER_LOCATION,
+		(void*)(first_block * 512), 512);
+	memcpy((void*)(COPY_BUFFER_LOCATION + 512 - first_copy_size),
+		src, first_copy_size);
+	lpc2292_copy_buffer_to_flash(info, first_block * 512);
+	src += first_copy_size;
+	addr += first_copy_size;
+
+	/* copy middle blocks */
+	for (i = 0; i < nbr_mid_blocks; i++) {
+		debug("copy middle block: %lX -> %lX 512 bytes, "
+		"%lX -> %lX 512 bytes\n",
+		(ulong)src,
+		(ulong)COPY_BUFFER_LOCATION,
+		(ulong)COPY_BUFFER_LOCATION,
+		(ulong)addr);
+
+		memcpy((void*)COPY_BUFFER_LOCATION, src, 512);
+		lpc2292_copy_buffer_to_flash(info, addr);
+		src += 512;
+		addr += 512;
+	}
+
+
+	if (last_copy_size > 0) {
+		debug("copy last block: (1) %lX -> %lX 0x200 bytes, "
+		"(2) %lX -> %lX 0x%X bytes, (3) %lX -> %lX x200 bytes\n",
+		(ulong)(last_block * 512),
+		(ulong)COPY_BUFFER_LOCATION,
+		(ulong)src,
+		(ulong)(COPY_BUFFER_LOCATION),
+		last_copy_size,
+		(ulong)COPY_BUFFER_LOCATION,
+		(ulong)addr);
+
+		/* copy last block */
+		memcpy((void*)COPY_BUFFER_LOCATION,
+			(void*)(last_block * 512), 512);
+		memcpy((void*)COPY_BUFFER_LOCATION,
+			src, last_copy_size);
+		lpc2292_copy_buffer_to_flash(info, addr);
+	}
+
+	/* verify write */
+	memmap_value = GET8(MEMMAP);
+
+	disable_interrupts();
+
+	PUT8(MEMMAP, 01);		/* we must make sure that initial 64
+							   bytes are taken from flash when we
+							   do the compare */
+
+	for (i = 0; i < cnt; i++) {
+		if (*dst_org != *src_org){
+			printf("Write failed. Byte %lX differs\n", i);
+			ret = ERR_PROG_ERROR;
+			break;
+		}
+		dst_org++;
+		src_org++;
+	}
+
+	PUT8(MEMMAP, memmap_value);
+	enable_interrupts();
+
+	return ret;
+}

board/lpc2292sodimm/mmc.c → cpu/arm720t/lpc2292/mmc.c

@@ -23,7 +23,7 @@
 #include <part.h>
 #include <fat.h>
 #include "mmc_hw.h"
-#include "spi.h"
+#include <asm/arch/spi.h>
 
 #ifdef CONFIG_MMC
 
@@ -44,7 +44,7 @@ block_dev_desc_t * mmc_get_dev(int dev)
 unsigned long mmc_block_read(int dev,
 			     unsigned long start,
 			     lbaint_t blkcnt,
-			     unsigned long *buffer)
+			     void *buffer)
 {
 	unsigned long rc = 0;
 	unsigned char *p = (unsigned char *)buffer;
@@ -101,6 +101,9 @@ int mmc_init(int verbose)
 		printf("mmc_init\n");
 
 	spi_init();
+	/* this meeds to be done twice */
+	mmc_hw_init();
+	udelay(1000);
 	mmc_hw_init();
 
 	mmc_hw_get_parameters();

board/lpc2292sodimm/mmc_hw.c → cpu/arm720t/lpc2292/mmc_hw.c

@@ -20,7 +20,7 @@
 #include <config.h>
 #include <common.h>
 #include <asm/arch/hardware.h>
-#include "spi.h"
+#include <asm/arch/spi.h>
 
 #define MMC_Enable() PUT32(IO1CLR, 1l << 22)
 #define MMC_Disable() PUT32(IO1SET, 1l << 22)

board/lpc2292sodimm/spi.c → cpu/arm720t/lpc2292/spi.c

@@ -21,7 +21,7 @@
 #include <common.h>
 #include <asm/errno.h>
 #include <asm/arch/hardware.h>
-#include "spi.h"
+#include <asm/arch/spi.h>
 
 unsigned long spi_flags;
 unsigned char spi_idle = 0x00;

disk/part.c

@@ -180,6 +180,7 @@ void dev_print (block_dev_desc_t *dev_desc)
      (CONFIG_COMMANDS & CFG_CMD_SCSI)	|| \
      (CONFIG_COMMANDS & CFG_CMD_USB)	|| \
      defined(CONFIG_MMC)		|| \
+     (defined(CONFIG_MMC) && defined(CONFIG_LPC2292)) || \
      defined(CONFIG_SYSTEMACE)          )
 
 #if defined(CONFIG_MAC_PARTITION) || \
@@ -219,7 +220,8 @@ void init_part (block_dev_desc_t * dev_desc)
 }
 
 
-int get_partition_info (block_dev_desc_t *dev_desc, int part, disk_partition_t *info)
+int get_partition_info (block_dev_desc_t *dev_desc, int part
+					, disk_partition_t *info)
 {
 		switch (dev_desc->part_type) {
 #ifdef CONFIG_MAC_PARTITION
@@ -325,7 +327,8 @@ void print_part (block_dev_desc_t * dev_desc)
 
 
 #else	/* neither MAC nor DOS nor ISO partition configured */
-# error neither CONFIG_MAC_PARTITION nor CONFIG_DOS_PARTITION nor CONFIG_ISO_PARTITION configured!
+# error neither CONFIG_MAC_PARTITION nor CONFIG_DOS_PARTITION 
+# error nor CONFIG_ISO_PARTITION configured!
 #endif
 
 #endif	/* (CONFIG_COMMANDS & CFG_CMD_IDE) || CONFIG_COMMANDS & CFG_CMD_SCSI) */

drivers/Makefile

@@ -30,7 +30,7 @@ LIB	= $(obj)libdrivers.a
 COBJS	= 3c589.o 5701rls.o ali512x.o atmel_usart.o \
 	  bcm570x.o bcm570x_autoneg.o cfb_console.o cfi_flash.o \
 	  cs8900.o ct69000.o dataflash.o dc2114x.o dm9000x.o \
-	  e1000.o eepro100.o \
+	  e1000.o eepro100.o enc28j60.o \
 	  i8042.o inca-ip_sw.o keyboard.o \
 	  lan91c96.o macb.o \
 	  natsemi.o ne2000.o netarm_eth.o netconsole.o \

board/lpc2292sodimm/eth.c → drivers/enc28j60.c

@@ -17,9 +17,10 @@
 
 #include <config.h>
 #include <common.h>
+#ifdef CONFIG_ENC28J60
 #include <net.h>
 #include <asm/arch/hardware.h>
-#include "spi.h"
+#include <asm/arch/spi.h>
 
 /*
  * Control Registers in Bank 0
@@ -36,7 +37,7 @@
 #define CTL_REG_ERXSTL	 0x08
 #define CTL_REG_ERXSTH	 0x09
 #define CTL_REG_ERXNDL	 0x0A
-#define CTL_REG_ERXNDA	 0x0B
+#define CTL_REG_ERXNDH	 0x0B
 #define CTL_REG_ERXRDPTL 0x0C
 #define CTL_REG_ERXRDPTH 0x0D
 #define CTL_REG_ERXWRPTL 0x0E
@@ -137,7 +138,10 @@
 
 #define PHY_REG_PHID1 0x02
 #define PHY_REG_PHID2 0x03
-
+/* taken from the Linux driver */
+#define PHY_REG_PHCON1 0x00
+#define PHY_REG_PHCON2 0x10
+#define PHY_REG_PHLCON 0x14
 
 /*
  * Receive Filter Register (ERXFCON) bits
@@ -274,6 +278,9 @@
 /* Use the lower memory for receiver buffer. See errata pt. 5 */
 #define ENC_RX_BUF_START 0x0000
 #define ENC_TX_BUF_START 0x1800
+/* taken from the Linux driver */
+#define ENC_RX_BUF_END   0x17ff
+#define ENC_TX_BUF_END   0x1fff
 
 /* maximum frame length */
 #define ENC_MAX_FRM_LEN 1518
@@ -293,6 +300,7 @@ static void encBitClr (unsigned char regNo, unsigned char data);
 static void encReset (void);
 static void encInit (unsigned char *pEthAddr);
 static unsigned short phyRead (unsigned char addr);
+static void phyWrite(unsigned char, unsigned short);
 static void encPoll (void);
 static void encRx (void);
 
@@ -318,10 +326,12 @@ static int rxResetCounter = 0;
 #define RX_RESET_COUNTER 1000;
 
 /*-----------------------------------------------------------------------------
- * Returns 0 when failes otherwize 1
+ * Always returns 0
  */
 int eth_init (bd_t * bis)
 {
+	unsigned char estatVal;
+
 	/* configure GPIO */
 	(*((volatile unsigned long *) IO1DIR)) |= ENC_SPI_SLAVE_CS;
 	(*((volatile unsigned long *) IO1DIR)) |= ENC_RESET;
@@ -332,6 +342,14 @@ int eth_init (bd_t * bis)
 
 	spi_init ();
 
+	/* taken from the Linux driver - dangerous stuff here! */
+	/* Wait for CLKRDY to become set (i.e., check that we can communicate with
+	   the ENC) */
+	do
+	{
+		estatVal = m_nic_read(CTL_REG_ESTAT);
+	} while ((estatVal & 0x08) || (~estatVal & ENC_ESTAT_CLKRDY));
+
 	/* initialize controller */
 	encReset ();
 	encInit (bis->bi_enetaddr);
@@ -353,6 +371,10 @@ int eth_send (volatile void *packet, int length)
 	m_nic_write (CTL_REG_EWRPTL, (ENC_TX_BUF_START & 0xff));
 	m_nic_write (CTL_REG_EWRPTH, (ENC_TX_BUF_START >> 8));
 
+	/* set ETXND */
+	m_nic_write (CTL_REG_ETXNDL, (length + ENC_TX_BUF_START) & 0xFF);
+	m_nic_write (CTL_REG_ETXNDH, (length + ENC_TX_BUF_START) >> 8);
+
 	/* set ETXST */
 	m_nic_write (CTL_REG_ETXSTL, ENC_TX_BUF_START & 0xFF);
 	m_nic_write (CTL_REG_ETXSTH, ENC_TX_BUF_START >> 8);
@@ -360,9 +382,15 @@ int eth_send (volatile void *packet, int length)
 	/* write packet */
 	m_nic_write_data (length, (unsigned char *) packet);
 
-	/* set ETXND */
-	m_nic_write (CTL_REG_ETXNDL, (length + ENC_TX_BUF_START) & 0xFF);
-	m_nic_write (CTL_REG_ETXNDH, (length + ENC_TX_BUF_START) >> 8);
+	/* taken from the Linux driver */
+	/* Verify that the internal transmit logic has not been altered by excessive
+	   collisions.  See Errata B4 12 and 14.
+	 */
+	if (m_nic_read(CTL_REG_EIR) & ENC_EIR_TXERIF) {
+		m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_TXRST);
+		m_nic_bfc(CTL_REG_ECON1, ENC_ECON1_TXRST);
+	}
+	m_nic_bfc(CTL_REG_EIR, (ENC_EIR_TXERIF | ENC_EIR_TXIF));
 
 	/* set ECON1.TXRTS */
 	m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_TXRTS);
@@ -423,8 +451,10 @@ static void encPoll (void)
 	volatile unsigned char estat_reg;
 	unsigned char pkt_cnt;
 
+#ifdef CONFIG_USE_IRQ
 	/* clear global interrupt enable bit in enc28j60 */
 	m_nic_bfc (CTL_REG_EIE, ENC_EIE_INTIE);
+#endif
 	estat_reg = m_nic_read (CTL_REG_ESTAT);
 
 	eir_reg = m_nic_read (CTL_REG_EIR);
@@ -462,8 +492,10 @@ static void encPoll (void)
 		m_nic_bfc (CTL_REG_EIR, ENC_EIR_TXERIF);
 	}
 
+#ifdef CONFIG_USE_IRQ
 	/* set global interrupt enable bit in enc28j60 */
 	m_nic_bfs (CTL_REG_EIE, ENC_EIE_INTIE);
+#endif
 }
 
 static void encRx (void)
@@ -473,6 +505,7 @@ static void encRx (void)
 	unsigned short status;
 	unsigned char eir_reg;
 	unsigned char pkt_cnt = 0;
+	unsigned short rxbuf_rdpt;
 
 	/* switch to bank 0 */
 	m_nic_bfc (CTL_REG_ECON1, (ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0));
@@ -489,18 +522,19 @@ static void encRx (void)
 		status = buffer[4];
 		status |= (unsigned short) buffer[5] << 8;
 
-		if (pkt_len <= ENC_MAX_FRM_LEN) {
+		if (pkt_len <= ENC_MAX_FRM_LEN)
 			copy_len = pkt_len;
-		} else {
+		else
 			copy_len = 0;
-			/*      p_priv->stats.rx_dropped++; */
-			/* we will drop this packet */
-		}
 
-		if ((status & (1L << 7)) == 0) {	/* check Received Ok bit */
+		if ((status & (1L << 7)) == 0) /* check Received Ok bit */
+			copy_len = 0;
+
+		/* taken from the Linux driver */
+		/* check if next pointer is resonable */
+		if ((((unsigned int)next_pointer_msb << 8) |
+			(unsigned int)next_pointer_lsb) >= ENC_TX_BUF_START)
 			copy_len = 0;
-			/*      p_priv->stats.rx_errors++; */
-		}
 
 		if (copy_len > 0) {
 			m_nic_read_data (copy_len, buffer);
@@ -513,6 +547,22 @@ static void encRx (void)
 		/* decrease packet counter */
 		m_nic_bfs (CTL_REG_ECON2, ENC_ECON2_PKTDEC);
 
+		/* taken from the Linux driver */
+		/* Only odd values should be written to ERXRDPTL, 
+		 * see errata B4 pt.13 
+		 */
+		rxbuf_rdpt = (next_pointer_msb << 8 | next_pointer_lsb) - 1;
+		if ((rxbuf_rdpt < (m_nic_read(CTL_REG_ERXSTH) << 8 |
+				m_nic_read(CTL_REG_ERXSTL))) || (rxbuf_rdpt >
+				(m_nic_read(CTL_REG_ERXNDH) << 8 |
+				m_nic_read(CTL_REG_ERXNDL)))) {
+			m_nic_write(CTL_REG_ERXRDPTL, m_nic_read(CTL_REG_ERXNDL));
+			m_nic_write(CTL_REG_ERXRDPTH, m_nic_read(CTL_REG_ERXNDH));
+		} else {
+			m_nic_write(CTL_REG_ERXRDPTL, rxbuf_rdpt & 0xFF);
+			m_nic_write(CTL_REG_ERXRDPTH, rxbuf_rdpt >> 8);
+		}
+
 		/* move to bank 1 */
 		m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL1);
 		m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL0);
@@ -535,8 +585,6 @@ static void encRx (void)
 
 		eir_reg = m_nic_read (CTL_REG_EIR);
 	} while (pkt_cnt);	/* Use EPKTCNT not EIR.PKTIF flag, see errata pt. 6 */
-	m_nic_write (CTL_REG_ERXRDPTL, next_pointer_lsb);
-	m_nic_write (CTL_REG_ERXRDPTH, next_pointer_msb);
 }
 
 static void encWriteReg (unsigned char regNo, unsigned char data)
@@ -700,12 +748,6 @@ static void encReset (void)
 
 	/* sleep 1 ms. See errata pt. 2 */
 	udelay (1000);
-
-#if 0
-	(*((volatile unsigned long *) IO1CLR)) &= ENC_RESET;
-	mdelay (5);
-	(*((volatile unsigned long *) IO1SET)) &= ENC_RESET;
-#endif
 }
 
 static void encInit (unsigned char *pEthAddr)
@@ -720,44 +762,21 @@ static void encInit (unsigned char *pEthAddr)
 	 * Setup the buffer space. The reset values are valid for the
 	 * other pointers.
 	 */
-#if 0
 	/* We shall not write to ERXST, see errata pt. 5. Instead we
 	   have to make sure that ENC_RX_BUS_START is 0. */
 	m_nic_write_retry (CTL_REG_ERXSTL, (ENC_RX_BUF_START & 0xFF), 1);
 	m_nic_write_retry (CTL_REG_ERXSTH, (ENC_RX_BUF_START >> 8), 1);
-#endif
+
+	/* taken from the Linux driver */
+	m_nic_write_retry (CTL_REG_ERXNDL, (ENC_RX_BUF_END & 0xFF), 1);
+	m_nic_write_retry (CTL_REG_ERXNDH, (ENC_RX_BUF_END >> 8), 1);
+
 	m_nic_write_retry (CTL_REG_ERDPTL, (ENC_RX_BUF_START & 0xFF), 1);
 	m_nic_write_retry (CTL_REG_ERDPTH, (ENC_RX_BUF_START >> 8), 1);
 
 	next_pointer_lsb = (ENC_RX_BUF_START & 0xFF);
 	next_pointer_msb = (ENC_RX_BUF_START >> 8);
 
-	/*
-	 * For tracking purposes, the ERXRDPT registers should be programmed with
-	 * the same value. This is the read pointer.
-	 */
-	m_nic_write (CTL_REG_ERXRDPTL, (ENC_RX_BUF_START & 0xFF));
-	m_nic_write_retry (CTL_REG_ERXRDPTH, (ENC_RX_BUF_START >> 8), 1);
-
-	/* Setup receive filters. */
-
-	/* move to bank 1 */
-	m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL1);
-	m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL0);
-
-	/* OR-filtering, Unicast, CRC-check and broadcast */
-	m_nic_write_retry (CTL_REG_ERXFCON,
-			   (ENC_RFR_UCEN | ENC_RFR_CRCEN | ENC_RFR_BCEN), 1);
-
-	/* Wait for Oscillator Start-up Timer (OST). */
-	while ((m_nic_read (CTL_REG_ESTAT) & ENC_ESTAT_CLKRDY) == 0) {
-		static int cnt = 0;
-
-		if (cnt++ >= 1000) {
-			cnt = 0;
-		}
-	}
-
 	/* verify identification */
 	phid1 = phyRead (PHY_REG_PHID1);
 	phid2 = phyRead (PHY_REG_PHID2);
@@ -780,16 +799,34 @@ static void encInit (unsigned char *pEthAddr)
 	/* switch to bank 2 */
 	m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL0);
 	m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL1);
-	/* clear MAC reset bits */
-	m_nic_write_retry (CTL_REG_MACON2, 0, 1);
 
 	/* enable MAC to receive frames */
-	m_nic_write_retry (CTL_REG_MACON1, ENC_MACON1_MARXEN, 10);
+	/* added some bits from the Linux driver */
+	m_nic_write_retry (CTL_REG_MACON1
+		,(ENC_MACON1_MARXEN | ENC_MACON1_TXPAUS | ENC_MACON1_RXPAUS)
+		,10);
 
 	/* configure pad, tx-crc and duplex */
-	/* TODO maybe enable FRMLNEN */
-	m_nic_write_retry (CTL_REG_MACON3,
-			   (ENC_MACON3_PADCFG0 | ENC_MACON3_TXCRCEN), 10);
+	/* added a bit from the Linux driver */
+	m_nic_write_retry (CTL_REG_MACON3
+		,(ENC_MACON3_PADCFG0 | ENC_MACON3_TXCRCEN | ENC_MACON3_FRMLNEN)
+		,10);
+
+	/* added 4 new lines from the Linux driver */
+	/* Allow infinite deferals if the medium is continously busy */
+	m_nic_write_retry(CTL_REG_MACON4, (1<<6) /*ENC_MACON4_DEFER*/, 10);
+
+	/* Late collisions occur beyond 63 bytes */
+	m_nic_write_retry(CTL_REG_MACLCON2, 63, 10);
+
+	/* Set (low byte) Non-Back-to_Back Inter-Packet Gap. Recommended 0x12 */
+	m_nic_write_retry(CTL_REG_MAIPGL, 0x12, 10);
+
+	/*
+	* Set (high byte) Non-Back-to_Back Inter-Packet Gap. Recommended
+	* 0x0c for half-duplex. Nothing for full-duplex
+	*/
+	m_nic_write_retry(CTL_REG_MAIPGH, 0x0C, 10);
 
 	/* set maximum frame length */
 	m_nic_write_retry (CTL_REG_MAMXFLL, (ENC_MAX_FRM_LEN & 0xff), 10);
@@ -801,15 +838,6 @@ static void encInit (unsigned char *pEthAddr)
 	 */
 	m_nic_write_retry (CTL_REG_MABBIPG, 0x12, 10);
 
-	/* Set (low byte) Non-Back-to_Back Inter-Packet Gap. Recommended 0x12 */
-	m_nic_write_retry (CTL_REG_MAIPGL, 0x12, 10);
-
-	/*
-	 * Set (high byte) Non-Back-to_Back Inter-Packet Gap. Recommended
-	 * 0x0c for half-duplex. Nothing for full-duplex
-	 */
-	m_nic_write_retry (CTL_REG_MAIPGH, 0x0C, 10);
-
 	/* set MAC address */
 
 	/* switch to bank 3 */
@@ -823,18 +851,35 @@ static void encInit (unsigned char *pEthAddr)
 	m_nic_write_retry (CTL_REG_MAADR5, pEthAddr[0], 1);
 
 	/*
-	 * Receive settings
+	* PHY Initialization taken from the Linux driver
 	 */
 
-	/* auto-increment RX-pointer when reading a received packet */
-	m_nic_bfs (CTL_REG_ECON2, ENC_ECON2_AUTOINC);
+	/* Prevent automatic loopback of data beeing transmitted by setting
+	   ENC_PHCON2_HDLDIS */
+	phyWrite(PHY_REG_PHCON2, (1<<8));
+
+	/* LEDs configuration
+	 * LEDA: LACFG = 0100 -> display link status
+	 * LEDB: LBCFG = 0111 -> display TX & RX activity
+	 * STRCH = 1 -> LED pulses
+	 */
+	phyWrite(PHY_REG_PHLCON, 0x0472);
 
+	/* Reset PDPXMD-bit => half duplex */
+	phyWrite(PHY_REG_PHCON1, 0);
+
+	/*
+	 * Receive settings
+	 */
+
+#ifdef CONFIG_USE_IRQ
 	/* enable interrupts */
 	m_nic_bfs (CTL_REG_EIE, ENC_EIE_PKTIE);
 	m_nic_bfs (CTL_REG_EIE, ENC_EIE_TXIE);
 	m_nic_bfs (CTL_REG_EIE, ENC_EIE_RXERIE);
 	m_nic_bfs (CTL_REG_EIE, ENC_EIE_TXERIE);
 	m_nic_bfs (CTL_REG_EIE, ENC_EIE_INTIE);
+#endif
 }
 
 /*****************************************************************************
@@ -864,6 +909,11 @@ static unsigned short phyRead (unsigned char addr)
 	/* set MICMD.MIIRD */
 	m_nic_write (CTL_REG_MICMD, ENC_MICMD_MIIRD);
 
+	/* taken from the Linux driver */
+	/* move to bank 3 */
+	m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL0);
+	m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL1);
+
 	/* poll MISTAT.BUSY bit until operation is complete */
 	while ((m_nic_read (CTL_REG_MISTAT) & ENC_MISTAT_BUSY) != 0) {
 		static int cnt = 0;
@@ -875,6 +925,11 @@ static unsigned short phyRead (unsigned char addr)
 		}
 	}
 
+	/* taken from the Linux driver */
+	/* move to bank 2 */
+	m_nic_bfc(CTL_REG_ECON1, ENC_ECON1_BSEL0);
+	m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL1);
+
 	/* clear MICMD.MIIRD */
 	m_nic_write (CTL_REG_MICMD, 0);
 
@@ -883,3 +938,46 @@ static unsigned short phyRead (unsigned char addr)
 
 	return ret;
 }
+
+/*****************************************************************************
+ *
+ * Taken from the Linux driver.
+ * Description:
+ * Write PHY registers.
+ *
+ * NOTE! This function will change to Bank 3.
+ *
+ * Params:
+ * [in] addr address of the register to write to
+ * [in] data to be written
+ *
+ * Returns:
+ *    None
+ */
+static void phyWrite(unsigned char addr, unsigned short data)
+{
+	/* move to bank 2 */
+	m_nic_bfc(CTL_REG_ECON1, ENC_ECON1_BSEL0);
+	m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL1);
+
+	/* write address to MIREGADR */
+	m_nic_write(CTL_REG_MIREGADR, addr);
+
+	m_nic_write(CTL_REG_MIWRL, data & 0xff);
+	m_nic_write(CTL_REG_MIWRH, data >> 8);
+
+	/* move to bank 3 */
+	m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL0);
+	m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL1);
+
+	/* poll MISTAT.BUSY bit until operation is complete */
+	while((m_nic_read(CTL_REG_MISTAT) & ENC_MISTAT_BUSY) != 0) {
+		static int cnt = 0;
+
+		if(cnt++ >= 1000) {
+			cnt = 0;
+		}
+	}
+}
+
+#endif /* CONFIG_ENC28J60 */

fs/fat/fat.c

@@ -59,7 +59,8 @@ int disk_read (__u32 startblock, __u32 getsize, __u8 * bufptr)
 	if (cur_dev == NULL)
 		return -1;
 	if (cur_dev->block_read) {
-		return cur_dev->block_read (cur_dev->dev, startblock, getsize, (unsigned long *)bufptr);
+		return cur_dev->block_read (cur_dev->dev
+			, startblock, getsize, (unsigned long *)bufptr);
 	}
 	return -1;
 }
@@ -89,8 +90,11 @@ fat_register_device(block_dev_desc_t *dev_desc, int part_no)
 		part_offset=0;
 	}
 	else {
-#if (CONFIG_COMMANDS & CFG_CMD_IDE) || (CONFIG_COMMANDS & CFG_CMD_SCSI) || \
-    (CONFIG_COMMANDS & CFG_CMD_USB) || defined(CONFIG_SYSTEMACE)
+#if ((CONFIG_COMMANDS & CFG_CMD_IDE)	|| \
+     (CONFIG_COMMANDS & CFG_CMD_SCSI)	|| \
+     (CONFIG_COMMANDS & CFG_CMD_USB)	|| \
+     (defined(CONFIG_MMC) && defined(CONFIG_LPC2292)) || \
+     defined(CONFIG_SYSTEMACE)          )
 		disk_partition_t info;
 		if(!get_partition_info(dev_desc, part_no, &info)) {
 			part_offset = info.start;
@@ -993,7 +997,8 @@ file_fat_detectfs(void)
 	memcpy (vol_label, volinfo.volume_label, 11);
 	vol_label[11] = '\0';
 	volinfo.fs_type[5]='\0';
-	printf("Partition %d: Filesystem: %s \"%s\"\n",cur_part,volinfo.fs_type,vol_label);
+	printf("Partition %d: Filesystem: %s \"%s\"\n"
+			,cur_part,volinfo.fs_type,vol_label);
 	return 0;
 }
 

include/asm-arm/arch-arm720t/hardware.h

@@ -36,8 +36,6 @@
 /* include armadillo specific hardware file if there was one */
 #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
 /* include IntegratorCP/CM720T specific hardware file if there was one */
-#elif defined(CONFIG_LPC2292)
-#include <asm-arm/arch-arm720t/lpc2292_registers.h>
 #else
 #error No hardware file defined for this configuration
 #endif

include/asm-arm/arch-lpc2292/hardware.h

@@ -0,0 +1,33 @@
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+/*
+ * Copyright (c) 2004	Cucy Systems (http://www.cucy.com)
+ * Curt Brune <curt@cucy.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#if defined(CONFIG_LPC2292)
+#include <asm-arm/arch-lpc2292/lpc2292_registers.h>
+#else
+#error No hardware file defined for this configuration
+#endif
+
+#endif /* __ASM_ARCH_HARDWARE_H */

include/configs/SMN42.h

@@ -0,0 +1,199 @@
+/*
+ * (C) Copyright 2007
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Configuation settings for the SMN42 board from Siemens.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * If we are developing, we might want to start u-boot from ram
+ * so we MUST NOT initialize critical regs like mem-timing ...
+ */
+#undef CONFIG_INIT_CRITICAL		/* undef for developing */
+
+#undef CONFIG_SKIP_LOWLEVEL_INIT
+#undef CONFIG_SKIP_RELOCATE_UBOOT
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_ARM7		1	/* This is a ARM7 CPU	*/
+#define CONFIG_ARM_THUMB	1	/* this is an ARM720TDMI */
+#define CONFIG_LPC2292
+#undef  CONFIG_ARM7_REVD	 	/* disable ARM720 REV.D Workarounds */
+
+#undef CONFIG_USE_IRQ			/* don't need them anymore */
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_SERIAL1		1	/* we use Serial line 1 */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_BOOTP_MASK       (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
+
+/* enable I2C and select the hardware/software driver */
+#undef  CONFIG_HARD_I2C			/* I2C with hardware support	*/
+#define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
+/* this would be 0xAE if E0, E1 and E2 were pulled high */
+#define CFG_I2C_SLAVE		0xA0
+#define CFG_I2C_EEPROM_ADDR	(0xA0 >> 1)
+#define CFG_I2C_EEPROM_ADDR_LEN 2 /* 16 bit address */
+#define CFG_EEPROM_PAGE_WRITE_BITS 6 /* 64 bytes per write */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
+/* not used but required by devices.c */
+#define CFG_I2C_SPEED 10000
+
+#ifdef CONFIG_SOFT_I2C
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define SCL		0x00000004		/* P0.2 */
+#define SDA		0x00000008		/* P0.3 */
+
+#define	I2C_READ	((GET32(IO0PIN) & SDA) ? 1 : 0)
+#define	I2C_SDA(x)	{ if (x) PUT32(IO0SET, SDA); else PUT32(IO0CLR, SDA); }
+#define	I2C_SCL(x)	{ if (x) PUT32(IO0SET, SCL); else PUT32(IO0CLR, SCL); }
+#define	I2C_DELAY	{ udelay(100); }
+#define	I2C_ACTIVE	{ unsigned int i2ctmp; \
+ 					  i2ctmp = GET32(IO0DIR); \
+					  i2ctmp |= SDA; \
+					  PUT32(IO0DIR, i2ctmp); }
+#define	I2C_TRISTATE	{ unsigned int i2ctmp; \
+ 					      i2ctmp = GET32(IO0DIR); \
+					      i2ctmp &= ~SDA; \
+						  PUT32(IO0DIR, i2ctmp); }
+#endif /* CONFIG_SOFT_I2C */
+
+/*
+ * Supported commands
+ */
+#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_FAT		| \
+				CFG_CMD_MMC		| \
+				CFG_CMD_NET		| \
+				CFG_CMD_EEPROM	| \
+				CFG_CMD_PING)
+
+#define CONFIG_DOS_PARTITION
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY	5
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP				/* undef to save memory		*/
+#define	CFG_PROMPT		"SMN42 # " /* Monitor Command Prompt	*/
+#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x81800000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x83000000	/* 24 MB in SRAM	*/
+
+#undef  CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+
+#define	CFG_LOAD_ADDR		0x81000000	/* default load address	
+                                                 * for uClinux img is here*/
+
+#define CFG_SYS_CLK_FREQ        58982400        /* Hz */
+#define	CFG_HZ			2048		/* decrementer freq in Hz */
+
+						/* valid baudrates */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1	   /* we have 1 bank of SRAM */
+#define PHYS_SDRAM_1		0x81000000 /* SRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE	0x02000000 /* 32 MB SRAM */
+
+/* This is the external flash */
+#define PHYS_FLASH_1		0x80000000 /* Flash Bank #1 */
+#define PHYS_FLASH_SIZE		0x01000000 /* 16 MB */
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+/*
+ * The first entry in CFG_FLASH_BANKS_LIST is a dummy, but it must be present.
+ */
+#define CFG_FLASH_BANKS_LIST	{ 0, PHYS_FLASH_1 }
+#define CFG_FLASH_ADDR0			0x555
+#define CFG_FLASH_ADDR1			0x2AA
+#define CFG_FLASH_ERASE_TOUT	16384	/* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT	5	/* Timeout for Flash Write (in ms) */
+
+#define CFG_MAX_FLASH_SECT	128  /* max number of sectors on one chip    */
+
+#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+
+#define	CFG_ENV_IS_IN_FLASH	1
+/* The Environment Sector is in the CPU-internal flash */
+#define CFG_FLASH_BASE		0
+#define CFG_ENV_OFFSET		0x3C000
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + CFG_ENV_OFFSET)
+#define CFG_ENV_SIZE		0x2000 /* Total Size of Environment Sector	*/
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_MMC			1
+/* we use this ethernet chip */
+#define CONFIG_ENC28J60
+
+#endif	/* __CONFIG_H */

include/configs/lpc2292sodimm.h

@@ -1,12 +1,8 @@
 /*
- * (C) Copyright 2000
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
+ * (C) Copyright 2007
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * Configuation settings for the EP7312 board.
- *
- * Modified to work on Armadillo HT1070 ARM720T board
- * (C) Copyright 2005 Rowel Atienza rowel@diwalabs.com
+ * Configuation settings for the LPC2292SODIMM board from Embedded Artists.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -31,7 +27,7 @@
 #define __CONFIG_H
 
 /*
- * If we are developing, we might want to start armboot from ram
+ * If we are developing, we might want to start u-boot from ram
  * so we MUST NOT initialize critical regs like mem-timing ...
  */
 #undef CONFIG_INIT_CRITICAL		/* undef for developing */
@@ -105,7 +101,9 @@
 
 #undef  CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
 
-#define	CFG_LOAD_ADDR		0x00040000	/* default load address	for armadillo: kernel img is here*/
+#define	CFG_LOAD_ADDR		0x00040000	/* default load address	for 
+                                                 * armadillo: kernel img is here
+						 */
 
 #define CFG_SYS_CLK_FREQ        58982400        /* Hz */
 #define	CFG_HZ			2048		/* decrementer freq in Hz */
@@ -154,5 +152,7 @@
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_INITRD_TAG
 #define CONFIG_MMC 1
+/* we use this ethernet chip */
+#define CONFIG_ENC28J60
 
 #endif	/* __CONFIG_H */