SMN42.h 6.2 KB

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  1. /*
  2. * (C) Copyright 2007
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * Configuation settings for the SMN42 board from Siemens.
  6. *
  7. * See file CREDITS for list of people who contributed to this
  8. * project.
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License as
  12. * published by the Free Software Foundation; either version 2 of
  13. * the License, or (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23. * MA 02111-1307 USA
  24. */
  25. #ifndef __CONFIG_H
  26. #define __CONFIG_H
  27. /*
  28. * If we are developing, we might want to start u-boot from ram
  29. * so we MUST NOT initialize critical regs like mem-timing ...
  30. */
  31. #undef CONFIG_INIT_CRITICAL /* undef for developing */
  32. #undef CONFIG_SKIP_LOWLEVEL_INIT
  33. #undef CONFIG_SKIP_RELOCATE_UBOOT
  34. /*
  35. * High Level Configuration Options
  36. * (easy to change)
  37. */
  38. #define CONFIG_ARM7 1 /* This is a ARM7 CPU */
  39. #define CONFIG_ARM_THUMB 1 /* this is an ARM720TDMI */
  40. #define CONFIG_LPC2292
  41. #undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */
  42. #undef CONFIG_USE_IRQ /* don't need them anymore */
  43. /*
  44. * Size of malloc() pool
  45. */
  46. #define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
  47. #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
  48. /*
  49. * Hardware drivers
  50. */
  51. /*
  52. * select serial console configuration
  53. */
  54. #define CONFIG_SERIAL1 1 /* we use Serial line 1 */
  55. /* allow to overwrite serial and ethaddr */
  56. #define CONFIG_ENV_OVERWRITE
  57. #define CONFIG_BAUDRATE 115200
  58. #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
  59. /* enable I2C and select the hardware/software driver */
  60. #undef CONFIG_HARD_I2C /* I2C with hardware support */
  61. #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
  62. /* this would be 0xAE if E0, E1 and E2 were pulled high */
  63. #define CFG_I2C_SLAVE 0xA0
  64. #define CFG_I2C_EEPROM_ADDR (0xA0 >> 1)
  65. #define CFG_I2C_EEPROM_ADDR_LEN 2 /* 16 bit address */
  66. #define CFG_EEPROM_PAGE_WRITE_BITS 6 /* 64 bytes per write */
  67. #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
  68. /* not used but required by devices.c */
  69. #define CFG_I2C_SPEED 10000
  70. #ifdef CONFIG_SOFT_I2C
  71. /*
  72. * Software (bit-bang) I2C driver configuration
  73. */
  74. #define SCL 0x00000004 /* P0.2 */
  75. #define SDA 0x00000008 /* P0.3 */
  76. #define I2C_READ ((GET32(IO0PIN) & SDA) ? 1 : 0)
  77. #define I2C_SDA(x) { if (x) PUT32(IO0SET, SDA); else PUT32(IO0CLR, SDA); }
  78. #define I2C_SCL(x) { if (x) PUT32(IO0SET, SCL); else PUT32(IO0CLR, SCL); }
  79. #define I2C_DELAY { udelay(100); }
  80. #define I2C_ACTIVE { unsigned int i2ctmp; \
  81. i2ctmp = GET32(IO0DIR); \
  82. i2ctmp |= SDA; \
  83. PUT32(IO0DIR, i2ctmp); }
  84. #define I2C_TRISTATE { unsigned int i2ctmp; \
  85. i2ctmp = GET32(IO0DIR); \
  86. i2ctmp &= ~SDA; \
  87. PUT32(IO0DIR, i2ctmp); }
  88. #endif /* CONFIG_SOFT_I2C */
  89. /*
  90. * Supported commands
  91. */
  92. #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
  93. CFG_CMD_DHCP | \
  94. CFG_CMD_FAT | \
  95. CFG_CMD_MMC | \
  96. CFG_CMD_NET | \
  97. CFG_CMD_EEPROM | \
  98. CFG_CMD_PING)
  99. #define CONFIG_DOS_PARTITION
  100. /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
  101. #include <cmd_confdefs.h>
  102. #define CONFIG_BOOTDELAY 5
  103. /*
  104. * Miscellaneous configurable options
  105. */
  106. #define CFG_LONGHELP /* undef to save memory */
  107. #define CFG_PROMPT "SMN42 # " /* Monitor Command Prompt */
  108. #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
  109. #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
  110. #define CFG_MAXARGS 16 /* max number of command args */
  111. #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
  112. #define CFG_MEMTEST_START 0x81800000 /* memtest works on */
  113. #define CFG_MEMTEST_END 0x83000000 /* 24 MB in SRAM */
  114. #undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
  115. #define CFG_LOAD_ADDR 0x81000000 /* default load address
  116. * for uClinux img is here*/
  117. #define CFG_SYS_CLK_FREQ 58982400 /* Hz */
  118. #define CFG_HZ 2048 /* decrementer freq in Hz */
  119. /* valid baudrates */
  120. #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
  121. /*-----------------------------------------------------------------------
  122. * Stack sizes
  123. *
  124. * The stack sizes are set up in start.S using the settings below
  125. */
  126. #define CONFIG_STACKSIZE (128*1024) /* regular stack */
  127. #ifdef CONFIG_USE_IRQ
  128. #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
  129. #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
  130. #endif
  131. /*-----------------------------------------------------------------------
  132. * Physical Memory Map
  133. */
  134. #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SRAM */
  135. #define PHYS_SDRAM_1 0x81000000 /* SRAM Bank #1 */
  136. #define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB SRAM */
  137. /* This is the external flash */
  138. #define PHYS_FLASH_1 0x80000000 /* Flash Bank #1 */
  139. #define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */
  140. /*-----------------------------------------------------------------------
  141. * FLASH and environment organization
  142. */
  143. /*
  144. * The first entry in CFG_FLASH_BANKS_LIST is a dummy, but it must be present.
  145. */
  146. #define CFG_FLASH_BANKS_LIST { 0, PHYS_FLASH_1 }
  147. #define CFG_FLASH_ADDR0 0x555
  148. #define CFG_FLASH_ADDR1 0x2AA
  149. #define CFG_FLASH_ERASE_TOUT 16384 /* Timeout for Flash Erase (in ms) */
  150. #define CFG_FLASH_WRITE_TOUT 5 /* Timeout for Flash Write (in ms) */
  151. #define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
  152. #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
  153. #define CFG_ENV_IS_IN_FLASH 1
  154. /* The Environment Sector is in the CPU-internal flash */
  155. #define CFG_FLASH_BASE 0
  156. #define CFG_ENV_OFFSET 0x3C000
  157. #define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET)
  158. #define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
  159. #define CONFIG_CMDLINE_TAG
  160. #define CONFIG_SETUP_MEMORY_TAGS
  161. #define CONFIG_INITRD_TAG
  162. #define CONFIG_MMC 1
  163. /* we use this ethernet chip */
  164. #define CONFIG_ENC28J60
  165. #endif /* __CONFIG_H */