Merge branch 'fixes' into cleanups

Conflicts:

	board/atmel/atngw100/atngw100.c
	board/atmel/atstk1000/atstk1000.c
	cpu/at32ap/at32ap700x/gpio.c
	include/asm-avr32/arch-at32ap700x/clk.h
	include/configs/atngw100.h
	include/configs/atstk1002.h
	include/configs/atstk1003.h
	include/configs/atstk1004.h
	include/configs/atstk1006.h
	include/configs/favr-32-ezkit.h
	include/configs/hammerhead.h
	include/configs/mimc200.h

.gitignore

@@ -11,6 +11,7 @@
 *.a
 *.o
 *~
+*.swp
 *.patch
 
 #
@@ -46,9 +47,16 @@ patches-*
 patches
 series
 
+# gdb files
+.gdb_history
+
 # cscope files
 cscope.*
 
+# tags files
+/ctags
+/etags
+
 # OneNAND IPL files
 /onenand_ipl/onenand-ipl*
 /onenand_ipl/board/*/onenand*

CHANGELOG

@@ -1,3 +1,9522 @@
+commit 9e2a79b4c585ad31138fb90b68fd0234d64a8da8
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Tue Dec 16 23:13:46 2008 +0100
+
+    include/configs/at91cap9adk.h: fix typo.
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 45ca04f2377361593151d2d4da51f8ba4832d233
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Tue Dec 16 22:32:25 2008 +0100
+
+    board/trab/memory.c: Fix compile problems.
+
+    Apply changes from commit 44b4dbed to board/trab/memory.c, too.
+
+    Actually we'd need a major cleanup here - as it turns out,
+    board/trab/memory.c is more or less a verbatim copy of
+    post/drivers/memory.c ... but then, trab is EOL anyway,r
+    so this is not worth the effort.
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 584eedab66d0828f2d571a24b10526c4e65f547b
+Author: Ilya Yanok <yanok@emcraft.com>
+Date:	Thu Dec 11 05:51:57 2008 +0300
+
+    jffs2: include <linux/mtd/compat.h> instead of defining own min_t
+
+    Include <linux/mtd/compat.h> header for min_t definition instead of
+    providing our own one. Removes warnings in case of OneNAND support
+    enabled.
+
+    Although I thinks it's a bit silly to include <linux/mtd/compat.h>
+    just for min_t...
+
+    Signed-off-by: Ilya Yanok <yanok@emcraft.com>
+    Acked-by: Stefan Roese <sr@denx.de>
+
+commit b1ffecec37b57a59c139042267faac458e5324e9
+Author: Becky Bruce <beckyb@kernel.crashing.org>
+Date:	Wed Dec 3 23:04:37 2008 -0600
+
+    powerpc: fix io.h build warning with CONFIG_PHYS_64BIT
+
+    Casting a pointer to a phys_addr_t when it's an unsigned long long
+    on a 32-bit system without first casting to a non-pointer type
+    generates a compiler warning. Fix this.
+
+    Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
+
+commit 6cdadcb3f1b6eac4a1c4256acaa1438413f95351
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Tue Dec 16 16:22:50 2008 +0100
+
+    trab: make trab_fkt standalone code independent of libgcc
+
+    Use our own local functions in lib_arm/ instead.
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit aa1bcca3d2e22af4dea9f02132f9b56a30378ded
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Tue Dec 16 14:44:06 2008 +0100
+
+    post/Makefile: fix dependency problem with parallel builds
+
+    Parallel builds (using "make -jN") would occasionally fail with error
+    messages like
+	ppc_4xxFP-objdump: string.o: File format not recognized
+    or
+	post/libpost.a(cpu.o): In function `cpu_post_test':
+	/home/wd/git/u-boot/work/post/lib_ppc/cpu.c:130: undefined reference to `cpu_post_test_string'
+    or similar. We now make sure to run the 'postdeps" step before
+    attempting to build the specific POST libraries.
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 4a0f7538c5c0805fd9a791967bbabacc41deadd9
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Tue Dec 16 14:41:02 2008 +0100
+
+    Makefile: fix dependency problem with parallel builds
+
+    Parallel builds (using "make -jN") would occasionally fail with error
+    messages like
+	include/autoconf.mk:212: *** missing separator.  Stop.
+    Line numbers and affected boards were changing. Obviously some
+    Makefiles included autoconf.mk while it was still being written to.
+    As a fix, we now write to a temporary file first and then rename it,
+    so that it is really ready to use as soon as it appears.
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 455ae7e87f67c44e6aea68865c83acadd3fcd36c
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Tue Dec 16 01:02:17 2008 +0100
+
+    Coding style cleanup, update CHANGELOG.
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 84bc72d90c505fec3ef4b693995407a0bd4064e5
+Author: Mike Frysinger <vapier@gentoo.org>
+Date:	Thu Dec 11 18:39:08 2008 -0500
+
+    spi/stmicro: fix debug() display of cmd
+
+    The stmicro_wait_ready() func tries to show the actual opcode that was sent
+    to the device, but instead it displays the array pointer.  Fix it to pull
+    out the opcode from the start of the array.
+
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 5b3375ac8c36c29c87abb132fede0509eb21e5c9
+Author: Mike Frysinger <vapier@gentoo.org>
+Date:	Thu Dec 11 06:23:37 2008 -0500
+
+    env_sf: support embedded environments
+
+    If both CONFIG_ENV_SECT_SIZE and CONFIG_ENV_SIZE are defined, and the sect
+    size is larger than the env size, then it means the env is embedded in a
+    block.  So we have to save/restore the part of the sector which is not the
+    environment.  Previously, saving the environment in SPI flash in this
+    setup would probably brick the board as the rest of the sector tends to
+    contain actual U-Boot data/code.
+
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+    Acked-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
+
+commit ecf5f077c8e77454f532eaac3e3afb7cfc48c62d
+Author: Timur Tabi <timur@freescale.com>
+Date:	Wed Dec 3 11:28:30 2008 -0600
+
+    i2c: merge all i2c_reg_read() and i2c_reg_write() into inline functions
+
+    All implementations of the functions i2c_reg_read() and
+    i2c_reg_write() are identical. We can save space and simplify the
+    code by converting these functions into inlines and putting them in
+    i2c.h.
+
+    Signed-off-by: Timur Tabi <timur@freescale.com>
+    Acked-By: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit e39cd81c44740d7355d277ed3d38536cbe1e003d
+Author: Dave Liu <daveliu@freescale.com>
+Date:	Fri Dec 5 15:36:14 2008 +0800
+
+    lib_ppc: rework the flush_cache
+
+    - It is possible to miss flush/invalidate the last
+      cache line, we fix it at here.
+    - add the volatile and memory clobber.
+
+    They are pointed by Scott Wood.
+
+    Signed-off-by: Dave Liu <daveliu@freescale.com>
+
+commit 63240ba88cd6a220057a0f28e5bf97f5b17ac84b
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Sat Dec 13 17:20:28 2008 -0600
+
+    Introduce addr_map library
+
+    Add a library that helps in translating between virtual and physical
+    addresses.	This library can be useful as a simple means to implement
+    map_physmem() and virt_to_phys() for platforms that need functionality
+    beyond the simple 1:1 mapping.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 65e43a10631537dcb92c302d36301a12308216c3
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Sat Dec 13 17:20:27 2008 -0600
+
+    Introduce virt_to_phys()
+
+    virt_to_phys() returns the physical address given a virtual. In most
+    cases this will be just the input value as the vast majority of
+    systems run in a 1:1 mode.
+
+    However in systems that are not running this way it should report the
+    physical address or ~0 if no mapping exists for the given virtual
+    address.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 45845301af3de8675c1f7bbc815c6de35452605a
+Author: Yuri Tikhonov <yur@emcraft.com>
+Date:	Sun Dec 7 22:12:50 2008 +0100
+
+    POST Make: fix the sub-dir dependencies missing.
+
+    Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
+
+commit 22525779cb51f1bbe4e96fea7b778de1935a5a69
+Author: Martin Michlmayr <tbm@cyrius.com>
+Date:	Wed Aug 6 14:44:05 2008 +0300
+
+    Fix a typo in fw_env.config
+
+    Reported-by: Martin Michlmayr <tbm@cyrius.com>
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit ba490b7761c62b549c222a9723e532dc801a3899
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date:	Mon Dec 1 16:22:45 2008 -0600
+
+    Remove unused CONFIG_ADDR_STREAMING defines
+
+    Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+
+commit d16da93430520d3e46c1ab52eedacf36ab7a2311
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date:	Mon Nov 24 11:54:47 2008 -0600
+
+    cmd_mem: Remove unused variable
+
+    Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+
+commit 3aed3aa2c128ce9fb39ca3f4e9385a7499e93dbf
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Sun Dec 14 10:29:39 2008 +0100
+
+    Fix new found CFG_
+
+    Also fix some minor typos.
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 0e0c862efe7279e9609db74d758cd1b84c6c7209
+Author: Sergei Poselenov <sposelenov@emcraft.com>
+Date:	Fri Sep 19 12:07:34 2008 +0200
+
+    Remove compiler warning: target CPU does not support interworking
+
+    This warning is issued by modern ARM-EABI GCC on non-thumb targets.
+
+    Signed-off-by: Vladimir Panfilov <pvr@emcraft.com>
+    Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
+
+commit cd6734510a9ff0f41c4a73567d4080ea0033d2c1
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Mon Nov 24 13:33:51 2008 +0100
+
+    Fix FIT and FDT support to have CONFIG_OF_LIBFDT and CONFIG_FIT independent
+
+    FDT support is used for both FIT style images and for architectures
+    that can pass a fdt blob to an OS (ppc, m68k, sparc).
+
+    For other architectures and boards which do not pass a fdt blob to an
+    OS but want to use the new uImage format, we just need FIT support.
+
+    Now we can have the 4 following configurations :
+
+    1) FIT only		    CONFIG_FIT
+    2) fdt blob only	    CONFIG_OF_LIBFDT
+    3) both		    CONFIG_OF_LIBFDT & CONFIG_FIT
+    4) none		    none
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 19ef4f7a6ef3b725aa9fe4b4f5fb676a84160172
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Wed Dec 10 15:13:32 2008 +0100
+
+    ppc4xx: Disable EEPROM write access on PMC440 boards
+
+    This patch disables EEPROM wrtie access by default on PMC440 board.
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+
+commit 5b67a1439a73ba6c34007d9ff60a2c6aa90265df
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Wed Dec 10 15:12:56 2008 +0100
+
+    ppc4xx: Fix Ethernet PHY LED configuration on PMC440 boards
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+
+commit 71fa0714fe5134bc8718c38d5261d267e88582ba
+Author: Stefan Roese <sr@denx.de>
+Date:	Tue Nov 18 16:36:12 2008 +0100
+
+    MIPS: Flush data cache upon relocation
+
+    This patch now adds a flush to the data cache upon relocation. The
+    current implementation is missing this. Only a comment states that it
+    should be done. So let's really do it now.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+    Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
+
+commit 44174343688dba32571a34550dba08971c65fef1
+Author: Stefan Roese <sr@denx.de>
+Date:	Tue Nov 18 16:36:22 2008 +0100
+
+    MIPS: Add CONFIG_SKIP_LOWLEVEL_INIT
+
+    This patch adds the CONFIG_SKIP_LOWLEVEL_INIT option to start.S. This
+    enables support for boards where the lowlevel initialization is
+    already done when U-Boot runs (e.g. via OnChip ROM).
+
+    This will be used in the upcoming VCTH board support.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+    Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
+
+commit db08ecaa6eb8176904b3bae103a85ee8f735dc40
+Author: Stefan Roese <sr@denx.de>
+Date:	Wed Nov 12 13:18:02 2008 +0100
+
+    MIPS: Add board_early_init_f() to init_sequence
+
+    This patch adds the board_early_init_f() call to the MIPS init
+    sequence. A weak dummy implementation is also added which can be
+    overridden by a board specific version.
+
+    This will be used by the upcoming VCTH board support.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+    Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
+
+commit 9d23fc584c4b7b8bb9ecbee48920b1b04b08fa1b
+Author: Stefan Roese <sr@denx.de>
+Date:	Wed Nov 12 13:18:19 2008 +0100
+
+    MIPS: Add onenand_init() to board.c and move nand_init()
+
+    This patch adds a call to onenand_init() for OneNAND support and moves
+    the nand_init() call to an earlier place, so that the environment can
+    be used from NAND and OneNAND.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+    Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
+
+commit d8bbc51c7ba9b737a20984333d19fe28a3526431
+Author: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+Date:	Tue Dec 9 11:32:46 2008 +0900
+
+    sh: Update sh2/sh2a timer
+
+    Renesas SH2/SH2A timer broken.
+    This patch fix timer function.
+
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit a319f1496210117b73198e3d889ffffaf6825d00
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Fri Dec 5 07:27:37 2008 +0100
+
+    sh: r2dplus fix register access
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit 4d4a96055f6917335a89dbdf2e5556fa5ac329f6
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Tue Dec 2 07:40:03 2008 +0100
+
+    sh: r2dplus/lowlevel_init: coding style fix
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit c54b9a42d8f5ab5b2a039b3a2e6fde8b427745e5
+Author: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+Date:	Tue Nov 25 11:05:19 2008 +0900
+
+    sh: Changed value of CACHE_OC_NUM_ENTRIES and CACHE_OC_WAY_SHIFT
+
+    SH4 is different a value of CACHE_OC_NUM_ENTRIES and
+    CACHE_OC_WAY_SHIFT every CPU.
+    This patch corrects these values.
+
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit e9d5f35497885b3c65d494d09a525d443dcccd3b
+Author: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+Date:	Thu Nov 20 16:44:42 2008 +0900
+
+    sh: Update sh timer function
+
+    Change to write/readX function and fix timer problem.
+
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit b81786cff476c41e332eaeb679158f6527cd67d4
+Author: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+Date:	Tue Nov 4 11:58:58 2008 +0900
+
+    sh: Migo-R: Update BSC value
+
+    A value of BSC CS4 was wrong, Fixed it.
+
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit 5783758fd260a02f44566ad8f29f899565cd0403
+Author: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+Date:	Mon Nov 17 16:52:09 2008 +0900
+
+    sh: Update ms7722se board config
+
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit 15e2697c9f7fb2ba672a1a70f07cd6d9d4e92b51
+Author: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+Date:	Mon Nov 17 16:53:09 2008 +0900
+
+    sh: Update SuperH serial driver
+
+    The address of SCFSR register is wrong at SH7720/SH7721.
+    This patch fix this.
+
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit 9a1d3557dcd47365c12eeab584b822e57d994352
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Tue Nov 11 22:20:15 2008 +0100
+
+    sh: fix rsk7203 and MigoR out of tree build
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit 1951f847f0a851853871b613ad7cf21a5242226c
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Wed Dec 10 14:41:25 2008 +0100
+
+    ppc4xx: Update TEXT_BASE for CPCI405 boards
+
+    This patch fixes building U-Boot for CPCI405 boards.
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 8c92af7b2fbd60ae87379477f93c7ec9441b7452
+Author: Stefan Roese <sr@denx.de>
+Date:	Tue Dec 9 20:08:01 2008 +0100
+
+    ppc4xx: Remove some features from ALPR to fit into 256k again
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 3b089e4f889a2902449d55e081c886ae607cae89
+Author: Stefan Roese <sr@denx.de>
+Date:	Wed Dec 10 10:32:59 2008 +0100
+
+    UBI: Set ubi_dev.type back to DEV_TYPE_NONE upon failing initialization
+
+    With this patch we set the type back to NONE upon failing UBI partition
+    initialization. Otherwise further calls to the UBI subsystem would try
+    to really access the non-existing UBI partition.
+
+    Thanks to Michael Lawnick for pointing this out.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 817329351639a8895cd9b87b33aeff043f3d5a44
+Author: Stefan Roese <sr@denx.de>
+Date:	Wed Dec 10 10:28:33 2008 +0100
+
+    UBI: Return -ENOMEM upon failing malloc
+
+    Return with correct error code (-ENOMEM) from ubi_attach_mtd_dev() upon
+    failing malloc().
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 2145188bea2df8f2b47a87ec3071b55027e8d0ae
+Author: Ben Warren <biggerbadderben@gmail.com>
+Date:	Tue Dec 9 23:34:15 2008 -0800
+
+    Fix compile error in building MBX860T.
+
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 8fab49ea911fe925392fa5afcc9bc7373a3d0cee
+Author: Michal Simek <monstr@monstr.eu>
+Date:	Tue Nov 25 11:42:20 2008 +0100
+
+    microblaze: Remove XUPV2P board
+
+    ---
+
+    Microblaze platforms use generic settings and to have
+    many platforms is confusing that's why I decided to remove this
+    platform from U-BOOT. ml401 tree is sufficient for covering
+    all Microblaze platforms.
+
+    This change will go through microblaze custodian tree.
+
+commit 99ba6f353582720defff6e6e6761dc455a207d31
+Author: Michal Simek <monstr@monstr.eu>
+Date:	Mon Nov 24 18:25:41 2008 +0100
+
+    microblaze: Remove CONFIG_LIBFDT due to error in common files
+
+commit e7d591e823a991513833af7030468409e25a3b13
+Author: Michal Simek <monstr@monstr.eu>
+Date:	Mon Nov 24 11:43:00 2008 +0100
+
+    microblaze: Fix ml401 uart16550 setting
+
+    Signed-off-by: Michal Simek <monstr@monstr.eu>
+
+commit c85ff0553a8cfbcca51c15b947e1ed55d3810a39
+Author: Michal Simek <monstr@monstr.eu>
+Date:	Mon Nov 24 11:38:22 2008 +0100
+
+    microblaze: Set up relocation is done
+
+commit bcb6dd9187d4b23c748704767bd12d20c829e996
+Author: Mike Frysinger <vapier@gentoo.org>
+Date:	Tue Dec 9 23:20:31 2008 -0500
+
+    tools/netconsole: new script for working with netconsole over UDP
+
+    While the doc/README.NetConsole does have a snippet for people to
+    create their own netcat script, it's a lot easier to make a simple
+    dedicated script and tell people to use it.
+
+    Also spruce it up a bit to make it user friendly.
+
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 8c5170a7d088601d5f30d85093388dab1f1e8ec0
+Author: Sonic Zhang <Sonic.Zhang@analog.com>
+Date:	Tue Dec 9 23:20:18 2008 -0500
+
+    fs/fat: handle FAT on SATA
+
+    The FAT file system driver should also handle FAT on SATA devices.
+
+    Signed-off-by: Sonic Zhang <Sonic.Zhang@analog.com>
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 97a24a78ee6f34b89b821cb70eda1cf34aa11d97
+Author: Jerry Van Baren <gvb.uboot@gmail.com>
+Date:	Mon Nov 24 08:15:02 2008 -0500
+
+    libfdt: Fix redefined uintptr_t warning for USE_HOSTCC
+
+    Compiling U-Boot in an old OS environment (RedHat-7.3  :-)	gives the
+    following warnings from FDT:
+
+    include/libfdt_env.h:50: warning: redefinition of 'uintptr_t'
+    /usr/include/stdint.h:129: warning: 'uintptr_t' previously declared here
+
+    Fix: Protect the definition of uintptr_t when compiling on the host
+    system.
+
+    Signed-off-by: Gerald Van Baren <vanbaren@cideas.com>
+
+commit 1fc2b165c51d6f40c8d505f1b3eaefdb6599b17b
+Author: Graeme Russ <graeme.russ@gmail.com>
+Date:	Sat Nov 22 08:43:29 2008 +1100
+
+    Moved sc520 PCI definitions to stand-alone file
+
+    Signed Off By: Graeme Russ <graeme.russ@gmail.com>
+
+commit 1f5070c0c18fa5684bfce09c8abdf10c04ed48fa
+Author: Graeme Russ <graeme.russ@gmail.com>
+Date:	Sat Nov 22 08:43:21 2008 +1100
+
+    Fixed path to sc520 SSI include file
+
+    Signed Off By: Graeme Russ <graeme.russ@gmail.com>
+
+commit d4f70da544c33db3e4fce6473dea4ecca4322545
+Author: Graeme Russ <graeme.russ@gmail.com>
+Date:	Fri Nov 21 06:28:05 2008 +1100
+
+    Fixed build error due to #define of _LINUX_STRING_H_ in 82559_eeprom.c
+
+    Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
+
+commit c034075a713b60e654c64e88e87da29440f31bb4
+Author: Stefan Roese <sr@denx.de>
+Date:	Wed Nov 12 13:30:10 2008 +0100
+
+    serial: Add vcth UART driver
+
+    This patch adds the UART driver for the upcoming VCTH board support.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 142a80ffc3b537a9c45acd2444a42a77f147c602
+Author: Ilya Yanok <yanok@emcraft.com>
+Date:	Thu Nov 13 19:49:36 2008 +0300
+
+    jffs2: cache data_crc results
+
+    As we moved data_crc() invocation from jffs2_1pass_build_lists() to
+    jffs2_1pass_read_inode() data_crc is going to be calculated on each
+    inode access. This patch adds caching of data_crc() results. There
+    is no significant improvement in speed (because of flash access
+    caching added in previous patch I think, crc in RAM is really fast)
+    but this patch impacts memory usage -- every b_node structure uses
+    12 bytes instead of 8.
+
+    Signed-off-by: Alexey Neyman <avn@emcraft.com>
+    Signed-off-by: Ilya Yanok <yanok@emcraft.com>
+
+commit 9b7076229ec6a958bd835ab70745f7676297ce82
+Author: Ilya Yanok <yanok@emcraft.com>
+Date:	Thu Nov 13 19:49:35 2008 +0300
+
+    jffs2: summary support
+
+    This patch adds support for reading fs information from summary
+    node instead of scanning full eraseblock.
+
+    Signed-off-by: Ilya Yanok <yanok@emcraft.com>
+
+commit 70741004dc28946cd82c7af6789c4ddb3fc94526
+Author: Ilya Yanok <yanok@emcraft.com>
+Date:	Thu Nov 13 19:49:34 2008 +0300
+
+    jffs2: add buffer to cache flash accesses
+
+    With this patch JFFS2 code allocates memory buffer of max_totlen size
+    (size of the largest node, calculated during scan time) and uses it to
+    store entire node. Speeds up loading. If malloc fails we use old ways
+    to do things.
+
+    Signed-off-by: Alexey Neyman <avn@emcraft.com>
+    Signed-off-by: Ilya Yanok <yanok@emcraft.com>
+
+commit 8a36d31f72411144ac0412ee7e1880e801acd754
+Author: Ilya Yanok <yanok@emcraft.com>
+Date:	Thu Nov 13 19:49:33 2008 +0300
+
+    jffs2: rewrite jffs2 scanning code based on Linux one
+
+    Rewrites jffs2_1pass_build_lists() function in style of Linux's
+    jffs2_scan_medium() and jffs2_scan_eraseblock().
+    This includes:
+     - Caching flash acceses
+     - Smart dealing with free space
+
+    Signed-off-by: Alexey Neyman <avn@emcraft.com>
+    Signed-off-by: Ilya Yanok <yanok@emcraft.com>
+
+commit e0b5532579eda8b4629f1b4f6e49c3cc60f52237
+Author: Ilya Yanok <yanok@emcraft.com>
+Date:	Thu Nov 13 19:49:32 2008 +0300
+
+    jffs2: add sector_size field to part_info structure
+
+    This patch adds sector_size field to part_info structure (used
+    by new JFFS2 code).
+
+    Signed-off-by: Ilya Yanok <yanok@emcraft.com>
+
+commit f73846956778a7dfee83403ef9747aff77198848
+Author: Ilya Yanok <yanok@emcraft.com>
+Date:	Thu Nov 13 19:49:31 2008 +0300
+
+    jffs2: fix searching for latest version in jffs2_1pass_list_inodes()
+
+    We need to update i_version inside cycle to find really latest version
+    inside jffs2_1pass_list_inodes(). With that fixed we can use isize inside
+    dump_inode() instead of calling expensive jffs2_1pass_read_inode().
+
+    Signed-off-by: Alexey Neyman <avn@emcraft.com>
+    Signed-off-by: Ilya Yanok <yanok@emcraft.com>
+
+commit 1113cb764b3da256ef8a1f9539f4efbe221ff3c4
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Tue Dec 9 23:13:51 2008 +0100
+
+    evb64260: fix "cast to pointer from integer of different size" warnings
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit d2776827315c3d469b8cb4cec14d58877798daa2
+Author: Stefan Althoefer <stefan.althoefer@web.de>
+Date:	Sun Dec 7 19:39:11 2008 +0100
+
+    USB: descriptor handling
+
+    Hi,
+
+    I found a bug when working with the u-boot USB subsystem on IXP425 processor
+    (big endian Xscale aka ARMv5).
+    I recognized that the second usb_endpoint_descriptor of the attached memory
+    stick was corrupted.
+
+    The reason for this are the packed structures below (either u-boot and
+    u-boot-usb):
+
+    --------------
+    /* Endpoint descriptor */
+    struct usb_endpoint_descriptor {
+	unsigned char  bLength;
+	unsigned char  bDescriptorType;
+	unsigned char  bEndpointAddress;
+	unsigned char  bmAttributes;
+	unsigned short wMaxPacketSize;
+	unsigned char  bInterval;
+	unsigned char  bRefresh;
+	unsigned char  bSynchAddress;
+
+    } __attribute__ ((packed));
+    /* Interface descriptor */
+    struct usb_interface_descriptor {
+	unsigned char  bLength;
+	unsigned char  bDescriptorType;
+	unsigned char  bInterfaceNumber;
+	unsigned char  bAlternateSetting;
+	unsigned char  bNumEndpoints;
+	unsigned char  bInterfaceClass;
+	unsigned char  bInterfaceSubClass;
+	unsigned char  bInterfaceProtocol;
+	unsigned char  iInterface;
+
+	unsigned char  no_of_ep;
+	unsigned char  num_altsetting;
+	unsigned char  act_altsetting;
+	struct usb_endpoint_descriptor ep_desc[USB_MAXENDPOINTS];
+    } __attribute__ ((packed));
+    ------------
+
+    As usb_endpoint_descriptor is only 7byte in length, the start of all
+    odd ep_desc[] structures is not word aligned. This makes wMaxPacketSize
+    of these structures also not word aligned.
+
+    ARMv5 Architecture however does not support non-aligned multibyte
+    data type (see A2.8 of ARM Architecture Reference Manual).
+
+    Signed-off-by: Stefan Althoefer <stefan.althoefer@web.de>
+    Signed-off-by: Remy Böhmer <linux@bohmer.net>
+
+commit 4c253fdb2a175ea3472c38a1455a16faa58e81f0
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Tue Dec 9 10:27:33 2008 -0600
+
+    drivers/fsl_pci_init: Fix compile warning
+
+    fsl_pci_init.c: In function 'fsl_pci_setup_inbound_windows':
+    fsl_pci_init.c:122: warning: comparison is always true due to limited range of data type
+
+    The check only makes sense if we are CONFIG_PHYS_64BIT
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit dedacc18a8c2b3951581eb721fa055a4e0ac4845
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Sun Dec 7 09:45:35 2008 +0100
+
+    usbtty/omap: update to current API
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+    Signed-off-by: Remy Böhmer <linux@bohmer.net>
+
+commit ee2e9ba917a62cc2e3a484bb79c8da0e01cb93ed
+Author: Anatolij Gustschin <agust@denx.de>
+Date:	Tue Dec 9 17:52:05 2008 +0100
+
+    video: fix FADS823 and RRvision compiling issues
+
+    Since commit 561858ee building for FADS823 and RRvision
+    doesn't work. Let's include version.h and timestamp.h
+    unconditionally to fix the problem.
+
+    Signed-off-by: Anatolij Gustschin <agust@denx.de>
+
+commit 2d2e05727fe4013f807ffa814dff0e75259a1db4
+Author: Stefan Roese <sr@denx.de>
+Date:	Tue Dec 2 10:53:47 2008 +0100
+
+    UBI: Fix size parsing in "ubi create"
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 2ee951ba2ac9874d2a93d52e7a187d3184be937e
+Author: Stefan Roese <sr@denx.de>
+Date:	Thu Nov 27 14:07:09 2008 +0100
+
+    UBI: Enable re-initializing of the "ubi part" command
+
+    With this patch now, the user can call "ubi part" multiple times to
+    re-connect the UBI device to another MTD partition.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 9def12cae33d2d3ea2dd56b197fd3dfb3ad60bf4
+Author: Stefan Roese <sr@denx.de>
+Date:	Thu Nov 27 14:05:15 2008 +0100
+
+    MTD: Fix problem based on non-working relocation (list head mtd_partitions)
+
+    Don't use LIST_HEAD() but initialize the struct via INIT_LIST_HEAD() upon
+    first call of add_mtd_partitions(). Otherwise this won't work on platforms
+    where the relocation is broken (like MIPS or PPC).
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 5e3ab68e9acf9edf304b8aa32ad7e005483a2c47
+Author: Trent Piepho <tpiepho@freescale.com>
+Date:	Wed Nov 12 17:29:48 2008 -0800
+
+    Section name should be ".data", not "data"
+
+    Signed-off-by: Trent Piepho <tpiepho@freescale.com>
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 7fa6a2f3b66579dea8bc1a9177646e1141731b15
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Tue Dec 9 00:39:08 2008 +0100
+
+    MAKEALL: Automatically use parallel builds
+
+    Add logic to the MAKEALL script to determine the number of CPU cores
+    on the system, and run a parallel build if there is more than one.
+    Usually this significantrly accelerates builds.
+
+    Allow to manually adjust the number of parallel make jobs by using
+    the "BUILD_NCPUS" environment variable.
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 268405fa7c44156c5192a70779920c70906af8d6
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Tue Dec 9 00:24:30 2008 +0100
+
+    vxworks.h: Fix build problem introduced by commits 29a4c24d/e9084b23
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 153176a9414120ca1736f3cc4951623d6e14e6af
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Tue Nov 11 06:08:59 2008 +0100
+
+    avr32/bootm: remove unused variable 'ret'
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+    Acked-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
+
+commit 434c51a5e62f608a2a78ed5398ac43a1c77cc183
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date:	Wed Nov 12 13:06:48 2008 -0600
+
+    Remove unneeded CONFIG_SHELL references
+
+    Make should be using the bash shell by default which makes
+    CONFIG_SHELL unnecessary
+
+    Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+
+commit cf7a7b99794bac936899819b95539be1dbd71708
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date:	Wed Nov 12 12:33:20 2008 -0600
+
+    Use bash for default GNU Make shell application
+
+    Some Make script commands rely on bash-specific features like brace
+    expansion, so default to bash for the SHELL variable with a fallback
+    to the standard sh shell
+
+    Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+
+commit 4b530018764934ad5689196e9aa5714a6f4d1a6c
+Author: Heiko Schocher <hs@denx.de>
+Date:	Wed Nov 12 09:50:45 2008 +0100
+
+    jffs2: rename devices_init () in common/jffs2.c
+
+    rename devices_init () in common/jffs2.c to
+    jffs2_devices_init (), because there is also a
+    devices_init () in common/devices.c.
+
+    Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit af5eb847a10f1037590001355d88bab3fe7be48b
+Author: Daniel Hellstrom <daniel@gaisler.com>
+Date:	Mon Nov 10 12:46:20 2008 +0000
+
+    SPARC: Fixed compiler error introduced by commit c160a9544743
+
+    This patch fixes a build error for the SPARC platform. It was
+    introduced by commit c160a9544743e80e8889edb2275538e7764ce334.
+
+    Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
+
+commit 4c60259899aa00f59db0d936b8807f9a26411c0f
+Author: Gary Jennejohn <garyj@denx.de>
+Date:	Sun Nov 9 12:50:59 2008 +0100
+
+    mgsuvd add the board-specific part of the HDLC driver
+
+    Signed-off-by: Gary Jennejohn <garyj@denx.de>
+
+commit 534a4359666af48bd69a3743d8a8c2bdb1d3ec70
+Author: Gary Jennejohn <garyj@denx.de>
+Date:	Sun Nov 9 12:45:03 2008 +0100
+
+    mgcoge add the board-specific part of the HDLC driver
+
+    Signed-off-by: Gary Jennejohn <garyj@denx.de>
+
+commit 135f5534538bb8ea4f38a7030da12187d22ef7e0
+Author: Gary Jennejohn <garyj@denx.de>
+Date:	Sun Nov 9 12:36:15 2008 +0100
+
+    keymile add the common parts of the HDLC driver
+
+    This implements the ICN protocol used across the backplane and is
+    needed by all the keymile boards.
+
+    Signed-off-by: Gary Jennejohn <garyj@denx.de>
+
+commit 1cb82a9207a550557399eabc7fe47f21bbd9ddf8
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Fri Nov 7 22:46:22 2008 +0100
+
+    drivers/bios_emulator: Move conditional compilation to Makefile
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit bcdf1d2cf6b24fb905fd7da80da4b3c65a7995b5
+Author: Richard Retanubun <RichardRetanubun@RuggedCom.com>
+Date:	Thu Nov 6 14:01:51 2008 -0500
+
+    common/cmd_ide.c: Corrected endian order printing for compact flash serial number.
+
+    Corrected endian order printing for compact flash serial number.
+
+    Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com>
+
+commit 16a28ef219c27423a1ef502f19070c4d375079b8
+Author: Gary Jennejohn <garyj@denx.de>
+Date:	Thu Nov 6 15:04:23 2008 +0100
+
+    IOMUX: Add console multiplexing support.
+
+    Modifications to support console multiplexing.  This is controlled using
+    CONFIG_SYS_CONSOLE_MUX in the board configuration file.
+
+    This allows a user to specify multiple console devices in the environment
+    with a command like this: setenv stdin serial,nc.  As a result, the user can
+    enter text on both the serial and netconsole interfaces.
+
+    All devices - stdin, stdout and stderr - can be set in this manner.
+
+    1) common/iomux.c and include/iomux.h contain the environment setting
+    implementation.
+    2) doc/README.iomux contains a somewhat more detailed description.
+    3) The implementation in (1) is called from common/cmd_nvedit.c to
+    handle setenv and from common/console.c to handle initialization of
+    input/output devices at boot time.
+    4) common/console.c also contains the code needed to poll multiple console
+    devices for input and send output to all devices registered for output.
+    5) include/common.h includes iomux.h and common/Makefile generates iomux.o
+    when CONFIG_SYS_CONSOLE_MUX is set.
+
+    Signed-off-by: Gary Jennejohn <garyj@denx.de>
+
+commit 774ce72026f74ac9641bcbbc588b20f2e13f7ab8
+Author: Mike Frysinger <vapier@gentoo.org>
+Date:	Tue Nov 4 16:03:46 2008 -0500
+
+    strings: use puts() rather than printf()
+
+    When running `strings` on really long strings, the stack tends to get
+    smashed due to printf().  Switch to puts() instead since we're only passing
+    the data through.
+
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit b03150b52e3c491a86a3cc0945274f0e8f9872e7
+Author: Niklaus Giger <niklaus.giger@member.fsf.org>
+Date:	Mon Nov 3 22:16:18 2008 +0100
+
+    Use new CONFIG_SYS_VXWORKS parameters for Netstal boards
+
+    Signed-off-by: Niklaus Giger <niklaus.giger@member.fsf.org>
+
+commit 29a4c24de99d8cb4ac32991c04cab87ed94ca1f9
+Author: Niklaus Giger <niklaus.giger@member.fsf.org>
+Date:	Mon Nov 3 22:15:34 2008 +0100
+
+    cmd_elf.c: Cleanup bootvx and handle new CONFIG_SYS_VXWORKS parameters
+
+    - fix size too small by one in sprintf
+    - changed old (pre 2004) device name ibmEmac to emac
+    - boot device may be overriden in board config
+    - servername may be defined in board config
+    - additional parameters may be defined in board config
+    - fixed some line wrappings
+    - replaced	redundant MAX define by max
+
+    Signed-off-by: Niklaus Giger <niklaus.giger@member.fsf.org>
+
+commit e9084b23d16102f44ace24379a1c0c352497ef80
+Author: Niklaus Giger <niklaus.giger@member.fsf.org>
+Date:	Mon Nov 3 22:14:36 2008 +0100
+
+    Add vxworks.h to handle CONFIG_SYS_VXWORKS parameters
+
+    Signed-off-by: Niklaus Giger <niklaus.giger@member.fsf.org>
+
+commit 0b2f4ecad473d785959c7976f20d2a00bd0ee01f
+Author: Niklaus Giger <niklaus.giger@member.fsf.org>
+Date:	Mon Nov 3 22:13:47 2008 +0100
+
+    README: Document CONFIG_SYS parameters for vxworks
+
+    Signed-off-by: Niklaus Giger <niklaus.giger@member.fsf.org>
+
+commit ace514837cac656e29c37a19569cb8ea83071126
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date:	Fri Oct 31 11:12:38 2008 -0500
+
+    lcd: Let the board code show board-specific info cleanup
+
+    remove unneeded version.h from lcd.c
+
+    Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 561858ee7d0274c3e89dc98d4d0698cb6fcf6fd9
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date:	Mon Nov 3 09:30:59 2008 -0600
+
+    Update U-Boot's build timestamp on every compile
+
+    Use the GNU 'date' command to auto-generate a new U-Boot
+    timestamp on every compile.
+
+    Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+
+commit 83ad179e2f0f625b88adb8ef5696709e46fb9077
+Author: Remy Bohmer <linux@bohmer.net>
+Date:	Thu Dec 4 22:25:57 2008 +0100
+
+    Remove redundant armv4 flag from arm926ejs compile flags
+
+    Currently the arm926ejs tree has the armv4 option set during compilation.
+    This flag does not belong here because a arm926 CPU is always a armv5 CPU.
+
+    Signed-off-by: Remy Bohmer <linux@bohmer.net>
+
+commit 89a7a87f084c657f8e32b513a77b50eca07e17ec
+Author: Nicolas Ferre <nicolas.ferre@atmel.com>
+Date:	Sat Dec 6 13:11:14 2008 +0100
+
+    at91: Choose environment variables location within make config target
+
+    This patch adds the possiblity to choose the media where the environment will
+    be located. This allow to choose this fundamental configuration without editing
+    config files.
+
+    Documentation file added.
+
+    Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
+    Acked-by: Stelian Pop <stelian@popies.net>
+    Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 1450c4a6682378567030414a9f1198c39b7730c7
+Author: Anatolij Gustschin <agust@denx.de>
+Date:	Mon Nov 3 15:30:34 2008 +0100
+
+    lwmon, tqm8xx: Fix build errors
+
+    Commit 6b59e03e0237a40a2305ea385defdfd92000978b
+    lcd: Let the board code show board-specific info
+
+    introduced some bugs which prevent U-Boot building
+    for lwmon board if CONFIG_LCD_INFO_BELOW_LOGO will
+    be defined in the board configuration.
+
+    Also "LCD enabled" building for TQM823L doesn't work
+    since this commit.
+
+    This patch fixes above-mentioned issues.
+
+    Signed-off-by: Anatolij Gustschin <agust@denx.de>
+
+commit bfa0af6b22ff25b0719a8910f9b6d1f975aa6fb0
+Author: Mike Frysinger <vapier@gentoo.org>
+Date:	Sun Nov 2 01:18:18 2008 -0400
+
+    ignore .gdb_history files
+
+    When using gdb, history files will often get generated.  So ignore them.
+
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit c8aa7dfc18f7cc90d0aea6c7becbb67dfc5bba4b
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Fri Oct 31 12:26:55 2008 +0100
+
+    FPGA: move fpga drivers to drivers/fpga
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 6a86bb6c25376f0358478219fa28d7c84dd01ed0
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date:	Mon Dec 1 16:29:38 2008 -0600
+
+    net: Fix TftpStart() ip:filename bug
+
+    The TftpStart() function modifies the 'BootFile'
+    string when 'BootFile' contains both an IP address
+    and filename (eg 1.2.3.4:/path/file). This causes
+    subsequent calls to TftpStart to incorrectly parse
+    the TFTP filename and server IP address to use.
+    For example:
+
+    => tftp 0x100000 10.52.0.62:/home/ptyser/non_existant
+    Speed: 100, half duplex
+    Using eTSEC1 device
+    TFTP from server 10.52.0.62; our IP address is 10.52.253.79
+		     ^^^^^^^^^^ CORRECT
+    Filename '/home/ptyser/non_existant'.
+	      ^^^^^^^^^^^^^^^^^^^^^^^^^ CORRECT
+    Load address: 0x100000
+    Loading: *
+    TFTP error: 'File not found' (1)
+    Starting again
+
+    eTSEC2: No link.
+    Speed: 100, half duplex
+    Using eTSEC1 device
+    TFTP from server 10.52.0.33; our IP address is 10.52.253.79
+		     ^^^^^^^^^^ WRONG
+    Filename '10.52.0.62'.
+	      ^^^^^^^^^^ WRONG
+    Load address: 0x100000
+    Loading: *
+    TFTP error: 'File not found' (1)
+    Starting again
+
+    TftpStart() was modified to not modify the 'BootFile' string.
+
+    Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit d32c5be50bf0600bfdc54223ef341ee9c63db445
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date:	Mon Dec 1 16:26:21 2008 -0600
+
+    net: Add additional IP fragmentation check
+
+    Ignore IP packets which have the "more fragments" flag bit
+    set.  This flag indicates the IP packet is fragmented and
+    must be ignored by U-Boot.
+
+    Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit e0c07b868cab405ab4b5335a0247899bfc5ea0b6
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date:	Mon Dec 1 16:26:20 2008 -0600
+
+    net: Define IP flag field values
+
+    These defines were pulled from the "Add simple
+    IP/UDP fragmentation support" patch from Frank
+    Haverkamp <haver@vnet.ibm.com>.
+
+    Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 23afaba65ec5206757e589ef334a8b38168c045f
+Author: Anatolij Gustschin <agust@denx.de>
+Date:	Tue Dec 2 10:31:04 2008 +0100
+
+    net: tsec: Fix Marvell 88E1121R phy init
+
+    This patch tries to ensure that phy interrupt pin
+    won't be asserted after booting. We experienced
+    following issues with current 88E1121R phy init:
+
+    Marvell 88E1121R phy can be hardware-configured
+    to share MDC/MDIO and interrupt pins for both ports
+    P0 and P1 (e.g. as configured on socrates board).
+    Port 0 interrupt pin will be shared by both ports
+    in such configuration. After booting Linux and
+    configuring eth0 interface, port 0 phy interrupts
+    are enabled. After rebooting without proper eth0
+    interface shutdown port 0 phy interrupts remain
+    enabled so any change on port 0 (link status, etc.)
+    cause assertion of the interrupt. Now booting Linux
+    and configuring eth1 interface will cause permanent
+    phy interrupt storm as the registered phy 1 interrupt
+    handler doesn't acknowledge phy 0 interrupts. This
+    of course should be fixed in Linux driver too.
+
+    Signed-off-by: Anatolij Gustschin <agust@denx.de>
+    Acked-by: Andy Fleming <afleming@freescale.com>
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 2e4970d8109d690adcf615d9e3cac7b5b2e8eaed
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date:	Tue Dec 2 12:59:51 2008 -0600
+
+    net: Fix download command parsing
+
+    When CONFIG_SYS_HUSH_PARSER is defined network download
+    commands with 1 argument in the format 'tftp "/path/file"'
+    do not work as expected. The hush command parser strips
+    the quotes from "/path/file" which causes the network
+    commands to interpret "/path/file" as an address
+    instead of the intended filename.
+
+    The previous check for a leading quote in netboot_common()
+    was replaced with a check which ensures only valid
+    numbers are treated as addresses.
+
+    Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 3c2c2f427905040c1513d0c51d637689cba48346
+Author: Remy Bohmer <linux@bohmer.net>
+Date:	Thu Nov 27 22:30:27 2008 +0100
+
+    Remove non-ascii characters from fat code
+
+    This code contains some non-ascii characters in comment lines and code.
+    Most editors do not display those characters properly and editing those
+    files results always in diffs at these places which are usually not required
+    to be changed at all. This is error prone.
+
+    So, remove those weird characters and replace them by normal C-style
+    equivalents for which the proper defines were already in the header.
+
+    Signed-off-by: Remy Bohmer <linux@bohmer.net>
+
+commit dc889e865356497d3e495570118c2245ebce2631
+Author: Dave Liu <daveliu@freescale.com>
+Date:	Fri Nov 28 20:16:58 2008 +0800
+
+    85xx: fix the wrong DDR settings for MPC8572DS
+
+    The default DDR freq is 400MHz or 800M data rate,
+    the old settings is pure wrong for the default case.
+
+    Signed-off-by: Dave Liu <daveliu@freescale.com>
+    Acked-by: Andy Fleming <afleming@freescale.com>
+
+commit 9df59533f77de2829b4b66e5b7620e04edaa391c
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Mon Nov 24 10:29:26 2008 -0600
+
+    85xx: init gd as early as possible
+
+    Moved up the initialization of GD so C code like set_tlb() can use
+    gd->flags to determine if we've relocated or not in the future.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+    Acked-by: Andy Fleming <afleming@freescale.com>
+
+commit aed461af81012a398a205e9be67ab37667491838
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Mon Nov 24 10:29:25 2008 -0600
+
+    85xx: Fix relocation of CCSRBAR
+
+    If the virtual address for CCSRBAR is the same after relocation but
+    the physical address is changing we'd end up having two TLB entries with
+    the same VA.  Instead we new us the new CCSRBAR virt address + 4k as a
+    temp virt address to access the old CCSRBAR to relocate it.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+    Acked-by: Andy Fleming <afleming@freescale.com>
+
+commit ea154a1781135d822eedee7567cc156089eae93c
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Mon Nov 24 10:25:14 2008 -0600
+
+    FSL: Moved BR_PHYS_ADDR for localbus to common header
+
+    The BR_PHYS_ADDR macro is useful on all machines that have local bus
+    which is pretty much all 83xx/85xx/86xx chips.
+
+    Additionally most 85xx & 86xx will need it if they want to support
+    36-bit physical addresses.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+    Acked-by: Andy Fleming <afleming@freescale.com>
+
+commit 9427ccde0355a2ebf47454e8e1be59f5b9864e08
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date:	Mon Dec 1 13:47:12 2008 -0600
+
+    85xx: Add PORDEVSR_PCI1 define
+
+    Add define used to determine if PCI1 interface is in PCI or PCIX mode.
+
+    Convert users of the old PORDEVSR_PCI constant to use MPC85xx_PORDEVSR_PCI1
+
+    Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+    Signed-off-by: Andy Fleming <afleming@freescale.com>
+
+commit 35db1c6d34b57ae15e99cf03c8e8f8a6148d74f3
+Author: Becky Bruce <becky.bruce@freescale.com>
+Date:	Fri Nov 21 19:24:22 2008 -0600
+
+    drivers/fsl_pci_init: Fix inbound window mapping bug
+
+    The current code will cause the creation of a 4GB window
+    starting at 0 if we have more than 4GB of RAM installed,
+    which overlaps with PCI_MEM space and causes pci_bus_to_phys()
+    to return erroneous information. Limit the size to 4GB - 1;
+    which causes the code to create one 2GB and one 1GB window
+    instead.
+
+    Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+    Acked-by: Andy Fleming <afleming@freescale.com>
+
+commit 5a105a333dab6a23e92d763ce76d6f31d57f45df
+Author: Jon Loeliger <jdl@freescale.com>
+Date:	Thu Nov 20 15:36:48 2008 -0600
+
+    Removed unused CONFIG_L1_INIT_RAM symbol.
+
+    Prevent further viral propogation of the unused
+    symbol CONFIG_L1_INIT_RAM by just removing it.
+
+    Signed-off-by: Jon Loeliger <jdl@freescale.com>
+    Acked-by: Andy Fleming <afleming@freescale.com>
+
+commit 7008d26a40a76f90cae5824c812cfed449fb97b8
+Author: Ed Swarthout <Ed.Swarthout@freescale.com>
+Date:	Wed Oct 29 09:21:44 2008 -0500
+
+    fsl ddr skip interleaving if not supported.
+
+    Removed while(1) hang if memctl_intlv_ctl is set wrong.
+    Remove embedded tabs from strings.
+
+    Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
+    Acked-by: Kumar Gala <galak@kernel.crashing.org>
+    Acked-by: Andy Fleming <afleming@freescale.com>
+
+commit dd332e18d082de75eca3fc2c7c778f5d4571a096
+Author: Anatolij Gustschin <agust@denx.de>
+Date:	Thu Nov 13 18:08:57 2008 +0100
+
+    85xx: socrates: fix DDR SDRAM tlb entry configuration
+
+    since commit be0bd8234b9777ecd63c4c686f72af070d886517
+    tlb entry for socrates DDR SDRAM will be reconfigured
+    by setup_ddr_tlbs() from initdram() causing an
+    inconsistency with previously configured DDR SDRAM tlb
+    entry from tlb_table:
+
+    socrates>l2cam 7 9
+    IDX  PID	  EPN  SIZE V TS	   RPN U0-U3 WIMGE UUUSSS
+      7 : 00 00000000 256MB V  0 -> 0_00000000	0000 -I-G- ---RWX
+      8 : 00 00000000 256MB V  0 -> 0_00000000	0000 ----- ---RWX
+      9 : 00 10000000 256MB V  0 -> 0_10000000	0000 ----- ---RWX
+
+    This patch makes the presence of the DDR SDRAM tlb entry in
+    the tlb_table dependent on CONFIG_SPD_EEPROM to avoid this
+    inconsistency.
+
+    Signed-off-by: Anatolij Gustschin <agust@denx.de>
+    Acked-by: Andy Fleming <afleming@freescale.com>
+
+commit a2cd50ed6ef0ac6b127b3d6db756979a8336718d
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date:	Tue Nov 11 10:17:10 2008 -0600
+
+    85xx: Add CPU 2 errata workaround to all 8548 boards
+
+    All mpc8548-based boards should implement the suggested workaround
+    to CPU 2 errata. Without the workaround, its possible for the
+    8548's core to hang while executing a msync or mbar 0 instruction
+    and a snoopable transaction from an I/O master tagged to make
+    quick forward progress is present.
+
+    Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+    Acked-by: Andy Fleming <afleming@freescale.com>
+
+commit e57f0fa1333cdf3ca36110aac2900712a5f82976
+Author: Dave Liu <daveliu@freescale.com>
+Date:	Tue Oct 28 17:53:45 2008 +0800
+
+    85xx: the DDR tlb is missed for the !CONFIG_SPD_EEPROM case
+
+    we need TLB entry for DDR at !SPD case.
+
+    Signed-off-by: Dave Liu <daveliu@freescale.com>
+    Acked-by: Andy Fleming <afleming@freescale.com>
+
+commit 9b0ad1b1c7a15ff674978705c7c52264978dc5d8
+Author: Dave Liu <daveliu@freescale.com>
+Date:	Tue Oct 28 17:53:38 2008 +0800
+
+    85xx: remove the unused ddr_enable_ecc in the board file
+
+    The DDR controller of 8548/8544/8568/8572/8536 processors
+    have the ECC data init feature, and the new DDR code is
+    using the feature, and we don't need the way with DMA to
+    init memory any more.
+
+    Signed-off-by: Dave Liu <daveliu@freescale.com>
+    Acked-by: Andy Fleming <afleming@freescale.com>
+
+commit 4a129a57d923f7c15aa1f567028a80a32d66a100
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Sun Nov 30 19:36:53 2008 +0100
+
+    at91rm9200dk: Fix typo
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit ed3b18e05c9a8ffa5fb643da9bcec7452e5d5e01
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Sun Nov 30 19:36:50 2008 +0100
+
+    AT91: remove non supported board AT91RM9200DF macro
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit bd876772ee04095e5dd943d97515a1f14bad4b1c
+Author: Ilko Iliev <iliev@ronetix.at>
+Date:	Tue Dec 2 17:27:54 2008 +0100
+
+    mtd/dataflash.c: fix a problem with the last partition
+
+    This patch fix the problem that only the [NB_DATAFLASH_AREA - 1] dataflash
+    partition can be defined to use the area to the end of dataflash size.
+    Now it is possible to have only one dataflash partition from 0 to the end
+    of of dataflash size.
+
+    Signed-off-by: Ilko Iliev <iliev@ronetix.at>
+
+commit 03f797793b124dccaae145b977d15d6cb9e74504
+Author: Ilko Iliev <iliev@ronetix.at>
+Date:	Tue Dec 2 17:20:17 2008 +0100
+
+    fix some coding style violations.
+
+    This patch fix some coding style violations.
+
+    Signed-off-by: Ilko Iliev <iliev@ronetix.at>
+
+commit 5e46b1e54112f4b7fd5185665e571510132c12a7
+Author: Stefan Roese <sr@denx.de>
+Date:	Thu Nov 27 14:11:37 2008 +0100
+
+    OneNAND: Add missing mtd info struct before calling onenand_erase()
+
+    Without this patch "saveenv" crashes when MTD partitions are enabled (e.g.
+    for use in UBI) via CONFIG_MTD_PARTITIONS.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+    Signed-off-by: Scott Wood <scottwood@freescale.com>
+
+commit 29382d4064fbaff5daacff4c3209370fa5713966
+Author: Becky Bruce <becky.bruce@freescale.com>
+Date:	Thu Nov 20 16:43:52 2008 -0600
+
+    mpc8641: Fix error in README
+
+    I made some updates to the code that didn't make it into the
+    README - fix this
+
+    Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
+
+commit 801a194616d95e6fc426a176d9615ccbf9876c7f
+Author: Jon Loeliger <jdl@freescale.com>
+Date:	Thu Nov 20 12:01:02 2008 -0600
+
+    Removed unused CONFIG_L1_INIT_RAM symbol.
+
+    Prevent further viral propogation of the unused
+    symbol CONFIG_L1_INIT_RAM by just removing it.
+
+    Signed-off-by: Jon Loeliger <jdl@freescale.com>
+
+commit f698738e46cb461e28c2d58228bb34a2fcf5a475
+Author: Jon Loeliger <jdl@freescale.com>
+Date:	Thu Nov 20 14:02:56 2008 -0600
+
+    86xx: Fix non-64-bit compilation problems.
+
+    Introducing 64-bit (36-bit) support for the MPC8641HPCN
+    failed to accomodate the other two 86xx boards.
+    Introduce definitions for CONFIG_SYS_CCSRBAR_PHYS_{LOW,HIGH}
+    CONFIG_SYS_CCSR_DEFAULT_DBAT{U,L} and CONFIG_SYS_CCSR_DEFAULT_IBAT{U,L}
+    with nominal 32-bit values.
+
+    Signed-off-by: Jon Loeliger <jdl@freescale.com>
+    Acked-by: Becky Bruce <becky.bruce@freescale.com>
+
+commit bebfc6ef3ec994c8e18783269b1d8d41f8e38afd
+Author: Michael Trimarchi <trimarchi@gandalf.sssup.it>
+Date:	Wed Nov 26 17:40:37 2008 +0100
+
+    Remove obsolete command (apply afte USB style patch, 80 chars strict)
+
+    Remove USB obsolete commmand
+
+    Signed-off-by: Michael Trimarchi <trimarchi@gandalf.sssup.it>
+    Signed-off-by: Remy Böhmer <linux@bohmer.net>
+
+commit de39f8c19d7c12017248c49d432dcb81db68f724
+Author: Michael Trimarchi <trimarchi@gandalf.sssup.it>
+Date:	Wed Nov 26 17:41:34 2008 +0100
+
+    USB style patch, 80 chars strict
+
+    USB Code style patch
+
+    Signed-off-by: Michael Trimarchi <trimarchi@gandalf.sssup.it>
+    Signed-off-by: Remy Böhmer <linux@bohmer.net>
+
+commit d10c5a87cb8affbb4d35a311370316d4383d598e
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Fri Nov 7 22:46:21 2008 +0100
+
+    drivers/usb: Move conditional compilation to Makefile
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+    Signed-off-by: Remy Böhmer <linux@bohmer.net>
+
+commit 2077e348c2a84901022ad95311b47b70361e6daa
+Author: Scott Wood <scottwood@freescale.com>
+Date:	Tue Nov 25 10:47:02 2008 -0600
+
+    NAND: Fix misplaced return statement in nand_{read,write}_skip_bad().
+
+    This caused the operation to be needlessly repeated if there were
+    no bad blocks and no errors.
+
+    Signed-off-by: Valeriy Glushkov <gvv@lstec.com>
+    Signed-off-by: Scott Wood <scottwood@freescale.com>
+
+commit 89295028e7d8f7a524f485328279d72fdb102385
+Author: Michal Simek <monstr@monstr.eu>
+Date:	Mon Nov 24 12:09:50 2008 +0100
+
+    ppc4xx: ml300 remove Xilinx BSP from ml300 folder
+
+    This BSP should be outside u-boot source tree.
+    The second reason is that xilinx ppc405 was moved to generic platform.
+
+    Signed-off-by: Michal Simek <monstr@monstr.eu>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 24eea623d4974a169026a975ba12fb23d48154b1
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Mon Nov 24 15:11:10 2008 +0100
+
+    ppc4xx: Remove unused features
+
+    This patch disables some unused features from the PCI405 configuration
+    to keep U-Boot image size below 192k.
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 0c2385c3bb51f5d3911fce1ec4720db86b534c2b
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Mon Nov 24 15:11:09 2008 +0100
+
+    ppc4xx: Use correct io accessors for PCI405
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 348c849d86a6f0785752b9bc497a34658713d1d1
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Mon Nov 24 15:11:08 2008 +0100
+
+    ppc4xx: Remove unused code from PCI405 code
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 58c696eed839af894e0265064669c402dc28b371
+Author: Wolfgang Denk <wd@xpert.denx.de>
+Date:	Mon Nov 24 21:50:59 2008 +0100
+
+    AT91RM9200DK: fix broken boot from NOR flash
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 8052352f20b33bef8f9872fc983eac73d4693c38
+Author: Jens Scharsig <esw@bus-elektronik.de>
+Date:	Tue Nov 18 10:48:46 2008 +0100
+
+    at91rm9200: fix broken boot from nor flash
+
+    This patch fix the broken boot from NOR Flash on AT91RM9200 boards, if
+    CONFIG_AT91RM9200 is defined and nor preloader is used.
+
+    Signed-off-by: Jens Scharsig <esw@bus-elektronik.de>
+
+commit 25ea652e907516a283b38237e83712a918f125d7
+Author: Piotr Ziecik <kosmo@semihalf.com>
+Date:	Mon Nov 17 15:58:00 2008 +0100
+
+    UBI: Add proof-of-concept CFI flash support
+
+    With this patch UBI can be used on CFI flash chips.
+
+    Signed-off-by: Piotr Ziecik <kosmo@semihalf.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit e6a7edbc1778d27431ac663b40a71dafa5d20578
+Author: Piotr Ziecik <kosmo@semihalf.com>
+Date:	Mon Nov 17 15:57:59 2008 +0100
+
+    mtd: Remove a printf() from add_mtd_device().
+
+    Remove a printf() from add_mtd_device(), which produces spurious output.
+
+    Signed-off-by: Piotr Ziecik <kosmo@semihalf.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 91809ed51d8327a8dbbf29aa98a091154c282171
+Author: Piotr Ziecik <kosmo@semihalf.com>
+Date:	Mon Nov 17 15:57:58 2008 +0100
+
+    cfi-mtd: Add cfi-mtd driver.
+
+    Add cfi-mtd driver, which exports CFI flash to MTD layer.
+    This allows CFI flash devices to be used from MTD layer.
+
+    Building of the new driver is controlled by CONFIG_FLASH_CFI_MTD
+    option. Initialization is done by calling cfi_mtd_init() from
+    flash_init().
+
+    Signed-off-by: Piotr Ziecik <kosmo@semihalf.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 6ea808efdf9aa5d9067fbfac32acde8539129ed2
+Author: Piotr Ziecik <kosmo@semihalf.com>
+Date:	Mon Nov 17 15:49:32 2008 +0100
+
+    cfi_flash: Add interface for flash verbosity control
+
+    Add interface for flash verbosity control. It allows
+    to disable output from low-level flash API. It is useful
+    when calling these low-level functions from context other
+    than flash commands (for example the MTD/CFI interface
+    implmentation).
+
+    Signed-off-by: Piotr Ziecik <kosmo@semihalf.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit ebc9784ce6528385bb8d2558e783622d4bbf20f8
+Author: Piotr Ziecik <kosmo@semihalf.com>
+Date:	Thu Nov 20 15:17:38 2008 +0100
+
+    cfi_flash: Export flash_sector_size() function.
+
+    Export flash_sector_size() function from drivers/mtd/cfi_flash.c,
+    so that it can be used in the upcoming cfi-mtd driver.
+
+    Signed-off-by: Piotr Ziecik <kosmo@semihalf.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 45aa5a7f4d5bcb79927ddfc896c1d7c4326e235d
+Author: Stefan Roese <sr@denx.de>
+Date:	Mon Nov 17 14:45:22 2008 +0100
+
+    cfi_flash: Make all flash access functions weak
+
+    This patch defines all flash access functions as weak so that
+    they can be overridden by board specific versions.
+
+    This will be used by the upcoming VCTH board support where the NOR
+    FLASH unfortunately can't be accessed memory-mapped. Special
+    accessor functions are needed here.
+
+    To enable this weak functions you need to define
+    CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS in your board config header.
+    Otherwise the "old" default functions will be used resulting
+    in smaller code.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+    Acked-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
+
+commit a5c4067017631d903e1afa6ad615f0ce19fea517
+Author: Stefan Roese <sr@denx.de>
+Date:	Mon Nov 24 08:31:16 2008 +0100
+
+    UBI: Change parsing of size in commands to default to hex
+
+    Currently the size parameters of the UBI commands (e.g. "ubi write") are
+    decoded as decimal instead of hex as default. This patch now interprets
+    all these values consistantly as hex, as all other standard U-Boot commands
+    do.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit de01c76c3ccc4e6c5989228eed58e955a3a1a968
+Author: Stefan Roese <sr@denx.de>
+Date:	Fri Nov 21 13:06:06 2008 +0100
+
+    ppc4xx: ML2 shouldn't include the 4xx EMAC driver
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 1a6a00dcc5bdfc6e9b4b00f39c1f583a7f96fc7f
+Author: Yuri Tikhonov <yur@emcraft.com>
+Date:	Fri Nov 14 16:19:19 2008 +0300
+
+    ppc4xx: katmai: Change default config
+
+     This patch enables support for EXT2, and increases the
+    CONFIG_SYS_BOOTMAPSZ size for the default configuration
+    of the katmai boards to use them as the RAID-reference
+    AMCC setups.
+
+     EXT2 enabling allows one to boot kernels from the EXT2
+    formatted Compact Flash cards.
+
+     CONFIG_SYS_BOOTMAPSZ increasing allows one to boot the
+    Linux kernels, which use PAGE_SIZE of 256KB. Otherwise,
+    the memory area with DTB file (which is placed at the
+    end of the bootmap area) will turn out to be overlapped
+    with the BSS segment of the 256KB kernel, and zeroed
+    in early_init() of Linux.
+
+     Actually, increasing of the bootmap size could be done
+    via setting of the bootm_size U-Boot variable, but it looks
+    like the current U-Boot implementation have some bootm_size-
+    related functionality lost. In many places through the U-Boot
+    code the CONFIG_SYS_BOOTMAPSZ definition is used directly
+    (instead of trying to read the corresponding value from the
+    environment). The same is truth for the boot_jump_linux()
+    function in lib_ppc/bootm.c, where U-Boot transfers control
+    to Linux passing the CONFIG_SYS_BOOTMAPSZ (not bootm_size)
+    value to the booting kernel.
+
+    Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
+    Signed-off-by: Ilya Yanok <yanok@emcraft.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit ddf45cc758d394591fb9bcdcbe96530f733f2bce
+Author: Dave Mitchell <dmitch71@gmail.com>
+Date:	Thu Nov 20 14:09:50 2008 -0600
+
+    ppc4xx: Changed 460EX/GT OCM TLB and internal SRAM initialization
+
+    Expanded OCM TLB to allow access to 64K OCM as well as 256K of
+    internal SRAM.
+
+    Adjusted internal SRAM initialization to match updated user
+    manual recommendation.
+
+    OCM & ISRAM are now mapped as follows:
+	    physical	    virtual	    size
+    ISRAM   0x4_0000_0000   0xE300_0000     256k
+    OCM     0x4_0004_0000   0xE304_0000     64k
+
+    A single TLB was used for this mapping.
+
+    Signed-off-by: Dave Mitchell <dmitch71@gmail.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit b14ca4b61a681f75f3125676e09d7ce6af66e927
+Author: Dave Mitchell <dmitch71@gmail.com>
+Date:	Thu Nov 20 14:00:49 2008 -0600
+
+    ppc4xx: Added ppc4xx-isram.h for internal SRAM and L2 cache DCRs
+
+    Added include/asm-ppc/ppc4xx-isram.h and moved internal SRAM and
+    L2 cache DCRs from ppc440.h to this new header.
+
+    Also converted these DCR defines from lowercase to uppercase and
+    modified referencing modules to use them.
+
+    Signed-off-by: Dave Mitchell <dmitch71@gmail.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 711e2b2af820d21d9931d4cf8057d3894600fd54
+Author: Steven A. Falco <sfalco@harris.com>
+Date:	Thu Nov 20 14:37:57 2008 -0500
+
+    ppc4xx: Delete unused definitions for SDR0_DDRCFG from ppc4xx.h
+
+    The definitions of bits in SDR_CFG are incorrect, and not used within
+    U-Boot.  Therefore, they can be removed.
+
+    The naming of the sdr_ddrdl/sdr_cfg registers do not follow conventions,
+    and are unused, so they can be removed too.
+
+    A definition for SDR0_DDRCFG is added.
+
+    Signed-off-by: Steven A. Falco <sfalco@harris.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit e23c7c95a96eb0f068efe5c532215a10a1512a95
+Author: Dirk Behme <dirk.behme@gmail.com>
+Date:	Mon Nov 10 20:15:25 2008 +0100
+
+    ARM: OMAP: Convert IO macros
+
+    Convert IO macros to readx/writex.
+
+    Signed-off-by: Dirk Behme <dirk.behme@gmail.com>
+
+commit 263b749e2e25473a48776d317bd2a7e2ddcdd212
+Author: Ilko Iliev <iliev@ronetix.at>
+Date:	Sun Nov 9 15:53:14 2008 +0100
+
+    lib_arm: do_bootm_linux() - correct a small mistake
+
+    This patch corrects a small bug in the "if" condition:
+    the parameter "flag" is 0 and the "if" condition is always true.
+    The result is - the boom command doesn't start the kernel.
+    Affected targets: all arm based.
+
+    Signed-off-by: Ilko Iliev <iliev@ronetix.at>
+
+commit 3e0cda071a67cb5709e3fa4faf6b31a731859acc
+Author: Stelian Pop <stelian@popies.net>
+Date:	Sun Nov 9 00:14:46 2008 +0100
+
+    AT91: Enable PLLB for USB
+
+    At least some (old ?) versions of the AT91Bootstrap do not set up the
+    PLLB correctly to 48 MHz in order to make USB host function correctly.
+
+    This patch sets up the PLLB to the same values Linux uses, and makes USB
+    work ok on the following CPUs:
+	- AT91CAP9
+	- AT91SAM9260
+	- AT91SAM9263
+
+    This patch also defines CONFIG_USB_STORAGE and CONFIG_CMD_FAT for all
+    the relevant AT91CAP9/AT91SAM9 atmel boards.
+
+    Signed-off-by: Stelian Pop <stelian@popies.net>
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit ad229a44e162af0f65e57e4e3dc133d5f0364ecb
+Author: Stelian Pop <stelian@popies.net>
+Date:	Fri Nov 7 13:55:14 2008 +0100
+
+    AT91: Use AT91_CPU_CLOCK in displays
+
+    Introduce AT91_CPU_CLOCK and use it for displaying the CPU
+    speed in the LCD driver.
+
+    Also make AT91_MAIN_CLOCK and AT91_MASTER_CLOCK reflect the
+    corresponding board clocks.
+
+    Signed-off-by: Stelian Pop <stelian@popies.net>
+
+commit 25fb4eaaeab3f8866020818f4729d990dcc91cf0
+Author: Stefan Roese <sr@denx.de>
+Date:	Thu Nov 20 11:46:20 2008 +0100
+
+    ppc4xx: Clear all potentially pending exceptions in MCSR
+
+    This is needed on Canyonlands which still has an exception pending
+    while running relocate_code(). This leads to a failure after trap_init()
+    is moved to the top of board_init_r().
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit facdad5f2602e899a01746916beddbf9e856b5ee
+Author: Heiko Schocher <hs@denx.de>
+Date:	Wed Nov 19 10:10:30 2008 +0100
+
+    powerpc: 83xx: add missing TIMING_CFG1_CASLAT_* defines
+
+    Signed-off-by: Heiko Schocher <hs@denx.de>
+    Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit 2f2a5c3714d17f4ead18b713128b7226e0e822f4
+Author: Howard Gregory <Greg.Howard@freescale.com>
+Date:	Tue Nov 4 14:55:33 2008 +0800
+
+    mpc83xx: Improve the performance of DDR memory
+
+    modify the CAS timings. my understanding is that these
+    settings decrease various wait times in the DDR interface.
+    Because these wait times are in clock cycles, and the DDR
+    clock on the 8315 RDB runs slower than on some other 83xx
+    platforms, we can dial down these values without a problem,
+    thereby decreasing the latency of memory a little.
+
+    Signed-off-by: Howard Gregory <Greg.Howard@freescale.com>
+    Signed-off-by: Dave Liu <daveliu@freescale.com>
+    Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit 8000b086b33a5a81f3f390f37e178db7956dc08b
+Author: Kyungmin Park <kyungmin.park@samsung.com>
+Date:	Fri Oct 24 14:55:33 2008 +0200
+
+    ARM: Add Apollon UBI support
+
+    To enable UBI on Apollon you need to uncomment the CONFIG_SYS_USE_UBI
+    macro.
+
+    Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 694a0b3f1c0accd0de94b89555155d69f8022824
+Author: Kyungmin Park <kyungmin.park@samsung.com>
+Date:	Wed Nov 19 11:47:05 2008 +0100
+
+    UBI: Add UBI command support
+
+    This patch adds these UBI commands:
+
+    ubi part [nand|onenand] [part] - Show or set current partition
+    ubi info [l[ayout]] -Display volume and UBI layout information
+    ubi create[vol] volume [size] [type] - Create volume name with size
+    ubi write[vol] address volume size - Write volume from address with size
+    ubi read[vol] address volume [size] - Read volume to address with size
+    ubi remove[vol] volume - Remove volume
+
+    Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 58be3a1056d88c6d05f3e914389282807e69923a
+Author: Kyungmin Park <kyungmin.park@samsung.com>
+Date:	Wed Nov 19 16:38:24 2008 +0100
+
+    UBI: Add basic UBI support to U-Boot (Part 8/8)
+
+    This patch adds basic UBI (Unsorted Block Image) support to U-Boot.
+    It's based on the Linux UBI version and basically has a "OS"
+    translation wrapper that defines most Linux specific calls
+    (spin_lock() etc.) into no-ops. Some source code parts have been
+    uncommented by "#ifdef UBI_LINUX". This makes it easier to compare
+    this version with the Linux version and simplifies future UBI
+    ports/bug-fixes from the Linux version.
+
+    Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 47ae6693f54f80455ae32c2e0d995e0e4bdc15b9
+Author: Kyungmin Park <kyungmin.park@samsung.com>
+Date:	Wed Nov 19 16:36:36 2008 +0100
+
+    UBI: Add basic UBI support to U-Boot (Part 7/8)
+
+    This patch adds basic UBI (Unsorted Block Image) support to U-Boot.
+    It's based on the Linux UBI version and basically has a "OS"
+    translation wrapper that defines most Linux specific calls
+    (spin_lock() etc.) into no-ops. Some source code parts have been
+    uncommented by "#ifdef UBI_LINUX". This makes it easier to compare
+    this version with the Linux version and simplifies future UBI
+    ports/bug-fixes from the Linux version.
+
+    Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 7e6ee7ad27de5216db1baef76f38c3429c8f4a2a
+Author: Kyungmin Park <kyungmin.park@samsung.com>
+Date:	Wed Nov 19 16:32:36 2008 +0100
+
+    UBI: Add basic UBI support to U-Boot (Part 6/8)
+
+    This patch adds basic UBI (Unsorted Block Image) support to U-Boot.
+    It's based on the Linux UBI version and basically has a "OS"
+    translation wrapper that defines most Linux specific calls
+    (spin_lock() etc.) into no-ops. Some source code parts have been
+    uncommented by "#ifdef UBI_LINUX". This makes it easier to compare
+    this version with the Linux version and simplifies future UBI
+    ports/bug-fixes from the Linux version.
+
+    Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit c91a719daa331b5856109313371e4ece5ec06d96
+Author: Kyungmin Park <kyungmin.park@samsung.com>
+Date:	Wed Nov 19 16:28:06 2008 +0100
+
+    UBI: Add basic UBI support to U-Boot (Part 5/8)
+
+    This patch adds basic UBI (Unsorted Block Image) support to U-Boot.
+    It's based on the Linux UBI version and basically has a "OS"
+    translation wrapper that defines most Linux specific calls
+    (spin_lock() etc.) into no-ops. Some source code parts have been
+    uncommented by "#ifdef UBI_LINUX". This makes it easier to compare
+    this version with the Linux version and simplifies future UBI
+    ports/bug-fixes from the Linux version.
+
+    Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit f412fefa079c6aa9a9763f6869bf787ea6bf6e1b
+Author: Kyungmin Park <kyungmin.park@samsung.com>
+Date:	Wed Nov 19 16:27:23 2008 +0100
+
+    UBI: Add basic UBI support to U-Boot (Part 4/8)
+
+    This patch adds basic UBI (Unsorted Block Image) support to U-Boot.
+    It's based on the Linux UBI version and basically has a "OS"
+    translation wrapper that defines most Linux specific calls
+    (spin_lock() etc.) into no-ops. Some source code parts have been
+    uncommented by "#ifdef UBI_LINUX". This makes it easier to compare
+    this version with the Linux version and simplifies future UBI
+    ports/bug-fixes from the Linux version.
+
+    Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 2d262c4853cb5b6ddce1a28a9641f2de3688d7ea
+Author: Kyungmin Park <kyungmin.park@samsung.com>
+Date:	Wed Nov 19 16:26:54 2008 +0100
+
+    UBI: Add basic UBI support to U-Boot (Part 3/8)
+
+    This patch adds basic UBI (Unsorted Block Image) support to U-Boot.
+    It's based on the Linux UBI version and basically has a "OS"
+    translation wrapper that defines most Linux specific calls
+    (spin_lock() etc.) into no-ops. Some source code parts have been
+    uncommented by "#ifdef UBI_LINUX". This makes it easier to compare
+    this version with the Linux version and simplifies future UBI
+    ports/bug-fixes from the Linux version.
+
+    Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 961df83361aff9a14f226214224eb8a06e05ba24
+Author: Kyungmin Park <kyungmin.park@samsung.com>
+Date:	Wed Nov 19 16:25:44 2008 +0100
+
+    UBI: Add basic UBI support to U-Boot (Part 2/8)
+
+    This patch adds basic UBI (Unsorted Block Image) support to U-Boot.
+    It's based on the Linux UBI version and basically has a "OS"
+    translation wrapper that defines most Linux specific calls
+    (spin_lock() etc.) into no-ops. Some source code parts have been
+    uncommented by "#ifdef UBI_LINUX". This makes it easier to compare
+    this version with the Linux version and simplifies future UBI
+    ports/bug-fixes from the Linux version.
+
+    Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit f399d4a281713d5ef2d764f05d545fe61e3bd569
+Author: Kyungmin Park <kyungmin.park@samsung.com>
+Date:	Wed Nov 19 16:23:06 2008 +0100
+
+    UBI: Add basic UBI support to U-Boot (Part 1/8)
+
+    This patch adds basic UBI (Unsorted Block Image) support to U-Boot.
+    It's based on the Linux UBI version and basically has a "OS"
+    translation wrapper that defines most Linux specific calls
+    (spin_lock() etc.) into no-ops. Some source code parts have been
+    uncommented by "#ifdef UBI_LINUX". This makes it easier to compare
+    this version with the Linux version and simplifies future UBI
+    ports/bug-fixes from the Linux version.
+
+    Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit e29c22f5abe6e0f4baa6251efed6074cdfc3db79
+Author: Kyungmin Park <kyungmin.park@samsung.com>
+Date:	Wed Nov 19 16:20:36 2008 +0100
+
+    MTD: Add MTD paritioning infrastructure
+
+    This MTD part infrastructure will be used by the upcoming
+    UBI support.
+
+    Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 9b827cf1720acda2473afa516956eab6f7cca9a1
+Author: Selvamuthukumar <selva.muthukumar@e-coninfotech.com>
+Date:	Thu Oct 16 22:54:03 2008 +0530
+
+    Align end of bss by 4 bytes
+
+    Most of the bss initialization loop increments 4 bytes
+    at a time. And the loop end is checked for an 'equal'
+    condition. Make the bss end address aligned by 4, so
+    that the loop will end as expected.
+
+    Signed-off-by: Selvamuthukumar <selva.muthukumar@e-coninfotech.com>
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 3f510db522d160179dff3ddcce9b18f6241c2c24
+Author: Becky Bruce <becky.bruce@freescale.com>
+Date:	Mon Nov 10 19:45:35 2008 -0600
+
+    mpc8641: fix address-cells default in old .dts detection
+
+    address-cells defaults to 2, not 1; so in the unlikely
+    event that it isn't specified, this patch is required
+    for correct operation.
+
+    Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
+
+commit d025aa4b20a0618a2bada0132a9a0a4afb717f1a
+Author: Becky Bruce <becky.bruce@freescale.com>
+Date:	Fri Oct 31 17:14:39 2008 -0500
+
+    lib_ppc: Move trap_init to occur earlier
+
+    Doing trap_init immediately once we're running from RAM
+    means we're no longer dependent on the physical location of
+    the flash on non-BookE platforms. Before trap_init, those
+    platforms switch to real mode and go to 0xfff00100 on exception.
+    After the switch, they go to 0x00000100  This makes it easier to
+    move the flash location.
+
+    Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
+
+commit d52082b12c6e545705a19433a2f4142526536189
+Author: Becky Bruce <becky.bruce@freescale.com>
+Date:	Fri Nov 7 13:46:19 2008 -0600
+
+    mpc8641: Try to detect old .dts files
+
+    Since we've changed the memory map of the board, be nice and
+    add some checking to try to catch out-of-date .dts files.  We do
+    this by checking the CCSRBAR location in the .dts and comparing
+    it to the CCSRBAR location in u-boot.  If they don't match, a
+    warning msg is printed.  This isn't foolproof, but it's simple and
+    will catch most of the cases where an out-of-date .dts is present,
+    including all of the cases where a new u-boot is used with an old
+    standard MPC8641 .dts file as supplied with Linux.
+
+    Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
+
+commit 8db0400a27839f91c047dcb83f4a0f09e054a180
+Author: Becky Bruce <becky.bruce@freescale.com>
+Date:	Thu Nov 6 13:04:09 2008 -0600
+
+    toplevel Makefile: Add MPC8641HPCN_36BIT target
+
+    This will enable CONFIG_PHYS_36BIT for MPC8641HPCN.
+
+    Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
+
+commit 3111d32c494e8251b90917447796a7206b757e1e
+Author: Becky Bruce <becky.bruce@freescale.com>
+Date:	Thu Nov 6 17:37:35 2008 -0600
+
+    mpc8641: Support 36-bit physical addressing
+
+    This patch creates a memory map with all the devices
+    in 36-bit physical space, in addition to the 32-bit map.
+    The CCSR relocation is moved (again, sorry) to
+    allow for the physical address to be 36 bits - this
+    requires translation to be enabled.  With 36-bit physical
+    addressing enabled, we are no longer running with VA=PA
+    translations.  This means we have to distinguish between
+    the two in the config file.  The existing region name is
+    used to indicate the virtual address, and a _PHYS variety
+    is created to represent the physical address.
+
+    Large physical addressing is not enabled by default.
+    Set CONFIG_PHYS_64BIT in the config file to turn this on.
+
+    Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
+
+commit c759a01a0022de9378a3a761f49786f87684c916
+Author: Becky Bruce <becky.bruce@freescale.com>
+Date:	Thu Nov 6 17:36:04 2008 -0600
+
+    mpc8641: Change 32-bit memory map
+
+    The memory map on the 8641hpcn is modified to look more like
+    the 85xx boards; this is a step towards a more standardized
+    layout going forward. As part of this change, we now relocate
+    the flash.
+
+    The regions for some of the mappings were far larger than they
+    needed to be.  I have reduced the mappings to match the
+    actual sizes supported by the hardware.
+
+    In addition I have removed the comments at the head
+    of the BAT blocks in the config file, rather than updating
+    them.  These get horribly out of date, and it's a simple
+    matter to look at the defines to see what they are set to
+    since everything is right here in the same file.
+
+    Documentation has been changed to reflect the new map, as this
+    change is user visible, and affects the OS which runs post-uboot.
+
+    Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
+
+commit bf9a8c34309ed9276258295db9e9212aabb2531a
+Author: Becky Bruce <becky.bruce@freescale.com>
+Date:	Wed Nov 5 14:55:35 2008 -0600
+
+    mpc86xx: Change early FLASH mapping to 1M at CONFIG_MONITOR_BASE_EARLY
+
+    We define CONFIG_MONITOR_BASE_EARLY to define the initial location
+    of the bootpage in flash.	Use this to create an early mapping
+    definition for the FLASH, and change the early_bats code to use this.
+
+    This  change facilitates the relocation of the flash since the early
+    mappings are no longer tied to the final location of the flash.
+
+    Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
+
+commit c1e1cf69547b138173f87a7f81c42a5d8dbfde3d
+Author: Becky Bruce <becky.bruce@freescale.com>
+Date:	Wed Nov 5 14:55:34 2008 -0600
+
+    mpc86xx: Use SRR0/1/rfi to enable address translation, not blr
+
+    Using a mtmsr/blr means that you have to be executing at the
+    same virtual address once you enable translation.  This is
+    unnecessarily restrictive, and is not really how this is
+    usually done.  Change it to use the more common mtspr SRR0/SRR1
+    and rfi method.
+
+    Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
+
+commit 6bf98b1362f0cb237620355ed3e6762fff82388d
+Author: Becky Bruce <becky.bruce@freescale.com>
+Date:	Wed Nov 5 14:55:33 2008 -0600
+
+    mpc8641: make DIAG_ADDR == FLASH_BASE
+
+    Currently, that's what it is, but it's hardcoded.
+
+    Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
+
+commit 170deacb1ddc39164bdb68f3963e0c0456a5369b
+Author: Becky Bruce <becky.bruce@freescale.com>
+Date:	Wed Nov 5 14:55:32 2008 -0600
+
+    mpc8641: Drop imaginary second flash bank, map 8MB
+
+    There's a lot of setup and foo for the second flash
+    bank.  The problem is, this board doesn't actually have one.
+    Clean this up.  Also, the flash is 8M in size.  Get rid
+    of the confusing aliased overmapping, and just map 8M.
+
+    Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
+
+commit 0f2d66027bfc60dc7eea2f096af8891988c5abe4
+Author: Becky Bruce <becky.bruce@freescale.com>
+Date:	Wed Nov 5 14:55:31 2008 -0600
+
+    mpc8641: only define CONFIG_ENV_SIZE once
+
+    It's currently defined twice inside in an if/else block, but
+    both halves set the same value.  Move the define outside
+    the if.
+
+    Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
+
+commit 24bfb48c35fed6ad1f047e3e4a27df302482cd93
+Author: Becky Bruce <becky.bruce@freescale.com>
+Date:	Wed Nov 5 14:55:30 2008 -0600
+
+    mpc86xx: Move setup_bats into cpu_init_f
+
+    In order to later allow for a physical relocation of the
+    flash, setup_bats, which sets up the final BAT mapping
+    for the board, needs to happen *after* init_laws().
+    Otherwise, there will be no window programmed for the flash
+    at the new physical location at the point when we change
+    the mmu translation.
+
+    Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
+
+commit 05df3e5a638be8c5b0899eae1766bbe8e4b92c17
+Author: Becky Bruce <becky.bruce@freescale.com>
+Date:	Wed Nov 5 14:55:29 2008 -0600
+
+    mpc8641: Remove extra "0" from BR2 define
+
+    Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
+
+commit edf3fe7d39a1ee07353128af5221422ce9ccfad6
+Author: Richard Retanubun <RichardRetanubun@RuggedCom.com>
+Date:	Thu Oct 23 09:08:18 2008 -0400
+
+    drivers/qe/uec_phy.c: Added PHY-less (fixed PHY) driver.
+
+    Copied over the fixed PHY driver as used in pp4xx/4xx_enet.c.
+    This adds support for PHY-less MAC connections to the UEC.
+
+    Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com>
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 54bdcc9fb6670afde9c26dcf364f582879bf21d6
+Author: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Date:	Thu Oct 23 16:27:24 2008 +0000
+
+    ColdFire: Add mii driver in drivers/net
+
+    All CF platforms' mii.c are consolidated into one
+
+    Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 25a859066b3af1070eb69f12022113c0a91bd813
+Author: Ben Warren <biggerbadderben@gmail.com>
+Date:	Mon Oct 27 23:53:17 2008 -0700
+
+    Moved initialization of PPC4xx EMAC to cpu_eth_init()
+
+    Removed initialization of the driver from net/eth.c
+
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+    Acked-by: Stefan Roese <sr@denx.de>
+
+commit 4d03a4e20e58552cb96d61a0e8b56cdb6cc60126
+Author: Ben Warren <biggerbadderben@gmail.com>
+Date:	Sun Nov 9 21:29:23 2008 -0800
+
+    Moved PPC4xx EMAC driver to drivers/net
+
+    Also changed path in all linker scripts that reference this driver
+
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+    Acked-by: Stefan Roese <sr@denx.de>
+
+commit 96e21f86e8266ed40759e5495ee461265d7f6d28
+Author: Ben Warren <biggerbadderben@gmail.com>
+Date:	Mon Oct 27 23:50:15 2008 -0700
+
+    Changed PPC4xx EMAC driver to require CONFIG_PPC4xx_EMAC
+
+    All in-tree IBM/AMCC PPC4xx boards using the EMAC get this new CONFIG
+
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+    Acked-by: Stefan Roese <sr@denx.de>
+
+commit 9eb79bd8856bcab896ed5e1f1bca159807a124dd
+Author: Ben Warren <biggerbadderben@gmail.com>
+Date:	Thu Oct 23 22:02:49 2008 -0700
+
+    Moved initialization of MPC8XX SCC to cpu_eth_init()
+
+    Removed initialization of the driver from net/eth.c
+
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit a9bec96d6359ac9f90a852962bf3040cad9e0256
+Author: Ben Warren <biggerbadderben@gmail.com>
+Date:	Wed Oct 22 23:47:51 2008 -0700
+
+    Moved initialization of MPC8220 FEC to cpu_eth_init()
+
+    Removed initialization of the driver from net/eth.c
+
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 0e8454e990385a58f708c2fc26d31ac041c7a6c5
+Author: Ben Warren <biggerbadderben@gmail.com>
+Date:	Wed Oct 22 23:32:48 2008 -0700
+
+    Moved initialization of QE Ethernet controller to cpu_eth_init()
+
+    Removed initialization of the driver from net/eth.c
+
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 3456a148276d5494b53ee40242efb6462d163504
+Author: Ben Warren <biggerbadderben@gmail.com>
+Date:	Wed Oct 22 23:20:29 2008 -0700
+
+    Moved initialization of FCC Ethernet controller to cpu_eth_init
+
+    Affected boards:
+	Several MPC8xx boards
+	Several MPC8260/MPC8272 boards
+	Several MPC85xx boards
+
+    Removed initialization of the driver from net/eth.c
+
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 62e15b497f5c6334c059512678c8db7940ae4c61
+Author: Ben Warren <biggerbadderben@gmail.com>
+Date:	Thu Oct 30 22:15:35 2008 -0700
+
+    Fix typo in cpu/mpc85xx/cpu.c
+
+    CONFIG_MPC85xx_FEC -> CONFIG_MPC85XX_FEC
+
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 5dfb3ee3f54e2382a08d72906f0e79ecf944f6e3
+Author: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
+Date:	Sun Oct 19 12:08:50 2008 +0900
+
+    net: Move initialization of Au1x00 SoC ethernet MAC to cpu_eth_init
+
+    This patch will move au1x00_eth_initialize from net/eth.c to cpu_eth_init
+    as a part of ongoing eth_initialize cleanup work.  The function ret value
+    is also fixed as it should be negative on fail.
+
+    Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit cc94074ecac1885d18ddb683eb934b3c0268aa5b
+Author: Ben Warren <biggerbadderben@gmail.com>
+Date:	Fri Sep 5 01:55:22 2008 -0400
+
+    Moved initialization of IXP4XX_NPE Ethernet controller to cpu_eth_init()
+
+    Also, removed the driver initialization from net/eth.c
+
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit f2a7806fc23e82d30c8548911369e0c530607354
+Author: Clive Stubbings <uboot@xentech.co.uk>
+Date:	Mon Oct 27 15:05:00 2008 +0000
+
+    xilinx_emaclite buffer overrun
+
+    Patch to fix buffer allocation size and alignment. Buffer needs to be u32 aligned and
+    PKTSIZE_ALIGN bytes long.
+
+    Acked-by: Michal Simek <monstr@monstr.eu>
+
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 0115b1953718a2969f6469d3d5da51ba11e12d42
+Author: richardretanubun <richardretanubun@ruggedcom.com>
+Date:	Fri Sep 26 08:59:12 2008 -0400
+
+    NET: QE: UEC: Make uec_miiphy_read() and uec_miiphy_write() use the devname arg.
+
+    The current uec_miiphy_read and uec_miiphy_write hardcode access devlist[0]
+    This patch makes these function use the devname argument that is passed in to
+    allow access to the phy registers of other devices in devlist[].
+
+    Signed-of-by: Richard Retanubun <RichardRetanubun@RugggedCom.com>
+
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 44dcb7332033db8de2810f2fffcae3084f15c8d4
+Author: richardretanubun <richardretanubun@ruggedcom.com>
+Date:	Mon Oct 6 15:31:43 2008 -0400
+
+    Adds two more ethernet interface to 83xx
+
+    Fixed compiler warning "declared but unused" eth5_uec_info and eth6_uec_info.
+    Signed-off-by: Richard Retanubun <RichardRetanubun@RugggedCom.com>
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit d8003fa03733901b73d6c4667b4d80fc8eb1ddd3
+Author: Stelian Pop <stelian@popies.net>
+Date:	Fri Nov 7 13:54:31 2008 +0100
+
+    AT91: Replace AT91_BASE_EMAC by the board specific values.
+
+    AT91_BASE_EMAC is never used outside the board specific files,
+    so replace its usage by the board specific AT91xxx_BASE_EMAC.
+
+    Signed-off-by: Stelian Pop <stelian@popies.net>
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit c91e17affa175ce06afa89b04752301eb4a61666
+Author: Stelian Pop <stelian@popies.net>
+Date:	Fri Nov 7 12:09:21 2008 +0100
+
+    AT91: Replace (undefined) AT91_ID_US* by the board specific values.
+
+    AT91_ID_US0 / AT91_ID_US1 / AT91_ID_US2 were used but never defined.
+    Since they are never used outside the board specific files, they can
+    be replaced by the board specific AT91xxx_ID_US0 / AT91xxx_ID_US1 /
+    AT91xxx_ID_US2.
+
+    Bug spotted by Jesus Alvarez <jalvarez@micromint.com>.
+
+    Signed-off-by: Stelian Pop <stelian@popies.net>
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 28962f5a2de81bc0eed1c0b08c6bfaa1cc134ea2
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Sat Nov 1 10:47:59 2008 +0100
+
+    Makefile/at91sam9: move some at91sam9 to the correct subsection for arm926ejs
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 1079432e04ccf71aa3684181186182cd63512f19
+Author: Sergey Lapin <slapin@ossfans.org>
+Date:	Fri Oct 31 12:28:43 2008 +0100
+
+    Custom AFEB9260 board support
+
+    This patch provides support for AFEB9260 board, a product of
+    OpenSource hardware and software. Some commertial projects
+    are made with this design. A board is basically AT91SAM9260-EK
+    with some modifications and different peripherals and different
+    parts used. Main purpose of this project is to gain experience in
+    hardware design.
+    More info: http://groups.google.com/group/arm9fpga-evolution-board
+    (In Russian only, sorry).
+    Subversion repository: svn://194.85.238.22/home/users/george/svn/arm9eb
+
+    Signed-off-by: Sergey Lapin <slapin@ossfans.org>
+
+commit 26eecd24f97130e56e9c2c2af0e714e05bce6e00
+Author: Tomohiro Masubuchi <tomohiro_masubuchiattripeaks.co.jp>
+Date:	Tue Oct 21 13:17:16 2008 +0900
+
+    Change to use "do_div" macro
+
+    Signed-off-by: Tomohiro Masubuchi <tomohiro_masubuchi@tripeaks.co.jp>
+
+commit e352495318d8056a00faa21b633b3e4374bfbf52
+Author: Roman Mashak <romez777@gmail.com>
+Date:	Wed Oct 22 16:00:26 2008 -0400
+
+    ARM926EJ-S: relocate OMAP specific 'cpuinfo.c' into OMAP directory
+
+    OMAP identification is implemented in 'cpuinfo.c' and located in ARM926EJ-S directory.
+    It makes sense to place this file in OMAP specific subdirectory, i.e. cpu/arm926ejs/omap
+
+    Signed-off-by: Roman Mashak <romez777@gmail.com>
+
+commit 248b2c367210c06dbd5fbdecf27e97fbe9d05fdb
+Author: Roman Mashak <romez777@gmail.com>
+Date:	Tue Oct 21 03:01:41 2008 -0700
+
+    ARM/Versatile port: Removed unused functions
+
+    Removal of never used functions.
+
+    Signed-off-by: Roman Mashak <romez777@gmail.com>
+
+commit 1266df887781c779deaf6d05eea2ef90a470cb34
+Author: Becky Bruce <becky.bruce@freescale.com>
+Date:	Mon Nov 3 15:44:01 2008 -0600
+
+    powerpc: change 86xx SMP boot method
+
+    We put the bootpg for the secondary cpus into memory and use
+    BPTR to get to it.	This is a step towards converting to the
+    ePAPR boot methodology.  Also, the code is written to
+    deal properly with more than 4GB of RAM.
+
+    Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
+
+commit b5431560682d8f318fbc49db87cfe13ab41d2ee4
+Author: Becky Bruce <becky.bruce@freescale.com>
+Date:	Fri Oct 31 17:13:49 2008 -0500
+
+    8641HPCN: Config file cleanup
+
+    There are several items in the config file that were hardcoded
+    but that should really be based on other config options, since
+    the regions are contiguous and depend on being so.	This cleans
+    that up a bit.  Also, add BR_PHYS_ADDR() macro to convert
+    addresses into the proper format for BR registers.
+
+    Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
+
+commit 4c77de3f144ca088c3867bd6240718c10f5a9d69
+Author: Becky Bruce <becky.bruce@freescale.com>
+Date:	Fri Oct 31 17:13:32 2008 -0500
+
+    86xx: Make dram_size a phys_size_t
+
+    It's currently a long and should be phys_size_t.
+
+    Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
+
+commit 104992fc541302a6bac74448e01e7fdad20abca0
+Author: Becky Bruce <becky.bruce@freescale.com>
+Date:	Sun Nov 2 18:19:32 2008 -0600
+
+    powerpc 86xx: Handle CCSR relocation earlier
+
+    Currently, the CCSR gets relocated while translation is
+    enabled, meaning we need 2 BAT translations to get to both the
+    old location and the new location.	Also, the DEFAULT
+    CCSR location has a dependency on the BAT that maps the
+    FLASH region.  Moving the relocation removes this unnecessary
+    dependency. This makes it easier and more intutive to
+    modify the board's memory map.
+
+    Swap BATs 3 and 4 on 8610 so that all 86xx boards use the same
+    BAT for CCSR space.
+
+    Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
+
+commit af5d100e8d5cd49d69d52d20f1181eb06ddb4ddf
+Author: Becky Bruce <becky.bruce@freescale.com>
+Date:	Fri Oct 31 17:14:14 2008 -0500
+
+    mpc8641: Make PCI and RIO mutually exclusive, fix non-PCI build
+
+    You can't actually have both, and with some coming changes to
+    change the memory map for the board and support 36-bit physical,
+    we need the extra BAT that is being consumed by having both.
+
+    I also make non-PCI configs build cleanly, for the sake of sanity.
+
+    Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
+
+commit 98693b85d42ff438375dc6d6dcadc70eb7b050bb
+Author: Becky Bruce <becky.bruce@freescale.com>
+Date:	Fri Oct 31 17:14:00 2008 -0500
+
+    mpc8641: Stop supporting non-PCI_PNP configs
+
+    We don't actually ever do this, remove the code so we
+    can stop maintaining it.
+
+    Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
+
+commit e4f69d1bd21a12049744989d2dd6b5199c9b8f23
+Author: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Date:	Fri Oct 24 12:59:12 2008 +0000
+
+    ColdFire: Fix M5329EVB and M5373EVB nand issue
+
+    Fix compilation issue caused by a few mismatches.
+    Provide proper nand chip select enable/disable in
+    nand_hwcontrol() rather than in board_nand_init()
+    just enable once. Remove redundant local nand driver
+    functions - nand_read_byte(), nand_write_byte() and
+    nand_dev_ready() to use common nand driver.
+
+    Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+
+commit 1b2708442224a551a0b865b52710306333888932
+Author: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Date:	Wed Oct 22 11:55:30 2008 +0000
+
+    ColdFire: Fix compilation error
+
+    The error was caused by the change for strmhz() in cpu.c.
+    A few of them were one extra close parenthesis.
+
+    Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+
+commit 536e7dac16769954915a484e682a2efb28699133
+Author: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Date:	Wed Oct 22 11:38:21 2008 +0000
+
+    ColdFire: Add MCF5301x CPU and M53017EVB support
+
+    Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+
+commit a21d0c2cc9add8894d971ab791f4032f077db817
+Author: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Date:	Tue Oct 21 15:37:02 2008 +0000
+
+    ColdFire: Add SBF support for M52277EVB
+
+    Add serial boot support
+
+    Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+
+commit b202816c61042c183fe67d097a5893b0f2dafba0
+Author: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Date:	Tue Oct 21 14:19:26 2008 +0000
+
+    ColdFire: Use CFI driver for M5272C3
+
+    Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+
+commit f3962d3f574e5a1cffacd4e9bc48713060a2a314
+Author: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Date:	Tue Oct 21 13:47:54 2008 +0000
+
+    ColdFire: Relocate FEC's GPIO and mii functions protocols
+
+    Place FEC pin assignments in cpu_init.c from platform's
+    mii.c
+
+    Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+
+commit 6e80f5aa09f8d41bac50b38dc7488ecd22107802
+Author: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Date:	Tue Oct 21 12:15:44 2008 +0000
+
+    ColdFire: Remove platforms mii.c file
+
+    Will use mcfmii.c driver in drivers/net rather than
+    keep creating new mii.c for each future platform.
+    Remove EB+MCF-EV123, cobra5272, idmr, M5235EVB,
+    M5271EVB, M5272C3, M5275EVB, M5282EVB, M5329EVB,
+    M5373EVB, M54451EVB, M54455EVB, M547xEVB, and M548xEVB's
+    mii.c
+
+    Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+
+commit 012522fef3b382469125beb46a315ab4dee02fb0
+Author: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Date:	Tue Oct 21 10:03:07 2008 +0000
+
+    ColdFire: Modules header files cleanup
+
+    Consolidate ATA, ePORT, QSPI, FlexCan, PWM, RNG,
+    MDHA, SKHA, INTC, and FlexBus structures and
+    definitions in immap_5xxx.h to more unify modules
+    header files. Append DSPI support for m547x_8x.
+    SSI cleanup. Remove USB Host structure from immap_539.h.
+    Apply changes to use FlexBus structures in mcf52x2's
+    cpu_init.c and platform configuration files.
+
+    Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+
+commit ac2331aee99ad36be0fcfed8c49922e3c61b576d
+Author: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Date:	Tue Oct 21 08:52:36 2008 +0000
+
+    ColdFire: Remove linker file
+
+    Each different build for M54455EVB and M5235EVB will
+    create a u-boot.lds linker file. It is redundant to
+    keep the u-boot.lds
+
+    Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+
+commit 0829323073c505556ed5f5073f91adb504584d45
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date:	Fri Oct 31 11:26:44 2008 -0500
+
+    ppc: Fix compile warnings when !CONFIG_OF_LIBFDT
+
+    Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+
+commit a80b21d5127583171d6e9bc7f722947641898012
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Fri Oct 31 12:12:12 2008 +0100
+
+    common/Makefile: create others group for non core, environment and command files
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 60c68d9c1c6d18ce02c862a05718fd94f97c13d0
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Fri Oct 31 01:13:37 2008 +0100
+
+    TQM8260: use CFI flash driver instead of custom driver.
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 20d04774f4ef3f6e38974636e0e36ae0f0b5501f
+Author: Andy Fleming <afleming@freescale.com>
+Date:	Thu Oct 30 17:35:30 2008 -0500
+
+    Consolidate MAX/MIN definitions
+
+    There were several, now there is one (two if you count the lower-case
+    versions).
+
+    Signed-off-by: Andy Fleming <afleming@freescale.com>
+
+commit 298e476c66fd88d0bc4f0371118652d2b5de4e8a
+Author: Heiko Schocher <hs@denx.de>
+Date:	Thu Oct 30 09:23:09 2008 +0100
+
+    mgsuvd: remove unused defines in config file.
+
+    Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit 3cbd823116ea8b7c654e275a8c2fca87cd1f5dc5
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Sun Nov 2 16:14:22 2008 +0100
+
+    Coding Style cleanup, update CHANGELOG
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit a47f957ab523019992fdef857af01bd71c58a4da
+Author: Alessandro Rubini <rubini-list@gnudd.com>
+Date:	Fri Oct 31 22:33:21 2008 +0100
+
+    NAND: Allow NAND and OneNAND to coexist
+
+    This removes in nand.h code that is verbatim duplicated from bbm.h,
+    including directly bbm.h in nand.h. The previous state of affairs
+    prevented compiling code for a board hosting both NAND and OneNAND chips.
+
+    Reported-by: Scott Wood <scottwood@freescale.com>
+    Signed-off-by: Alessandro Rubini <rubini@unipv.it>
+    Signed-off-by: Scott Wood <scottwood@freescale.com>
+
+commit 2f77c7f45b9a37ef265a8dbe3c18efa706fed214
+Author: Scott Wood <scottwood@freescale.com>
+Date:	Fri Oct 31 13:51:12 2008 -0500
+
+    JFFS2: Eliminate compiler error when both NAND and OneNAND are enabled.
+
+    Reported-by: Alessandro Rubini <rubini-list@gnudd.com>
+    Signed-off-by: Scott Wood <scottwood@freescale.com>
+
+commit c57fc28947e248fb03c49a28b467686299895055
+Author: Jason Jin <Jason.Jin@freescale.com>
+Date:	Fri Oct 31 05:07:04 2008 -0500
+
+    NAND: Add NAND support for MPC8536DS board
+
+    This patch defines 1M TLB&LAW size for NAND on MPC8536DS, assigns 0xffa00000
+    for CONFIG_SYS_NAND_BASE and adds other NAND supports in config file.
+    It also moves environment(CONFIG_ENV_ADDR) outside of u-boot image.
+
+    Singed-off-by: Jason Jin <Jason.Jin@freescale.com>
+    Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 6fc110bd8a8d642b8f7b0653bd9a08a0b7c3d50b
+Author: Haiying Wang <Haiying.Wang@freescale.com>
+Date:	Fri Oct 31 05:06:14 2008 -0500
+
+    NAND: Fix CONFIG_ENV_ADDR for MPC8572DS
+
+    CONFIG_ENV_ADDR should be (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE).
+
+    Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 51b572a801be57790fe26adaa530210e7fba59cc
+Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Date:	Fri Oct 24 10:49:48 2008 +0900
+
+    sh: rsk7203: Moved rsk7203 board to board/renesas
+
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit 58453b00b3ebb26aaa901210023f99504a90bb00
+Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Date:	Fri Oct 24 10:48:31 2008 +0900
+
+    sh: MigoR: Moved MigoR board to board/renesas
+
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit c1da2a22817ba85b437afa2f4e715e658b219fd1
+Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Date:	Fri Oct 24 10:39:44 2008 +0900
+
+    sh: r2dplus: Moved r2dplus board to board/renesas
+
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit 78385bf2359d828184d0b3649f7ae6b933420000
+Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Date:	Fri Oct 24 10:36:13 2008 +0900
+
+    sh: sh7763rdp: Moved sh7763rdp board to board/renesas
+
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit c6525d459c350bfc246ea7826456af77e1e314eb
+Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Date:	Fri Oct 24 10:35:19 2008 +0900
+
+    sh: sh7785lcr: Moved sh7785lcr board to board/renesas
+
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit acd3e30d09a73f876222f0d496c4f52ee9d0771d
+Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Date:	Fri Oct 24 10:34:21 2008 +0900
+
+    sh: r7780mp: Moved r7780mp board to board/renesas
+
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit f84e6ea275353b8fea772ec7553ff7e4b1f642e0
+Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Date:	Fri Oct 24 10:32:14 2008 +0900
+
+    sh: ap325rxa: Moved ap325rxa board to board/renesas
+
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit 9abda6ba735efb059f63dcb25d78b174bfcad1ad
+Author: Wolfgang Denk <wd@xpert.denx.de>
+Date:	Fri Oct 31 01:12:28 2008 +0100
+
+    CFI Driver: Fix "flash not ready" problem
+
+    This patch fixes a problem on systems where the NOR flash is attached
+    to a 64 bit bus.  The toggle bit detection in flash_toggle() is based
+    on the assumption that the same flash address is read twice without
+    any other interjacent flash accesses.  However, on 32 bit systems the
+    function flash_read64() [as currently implemented] does not perform
+    an atomic 64 bit read - instead, this is broken down into two 32 bit
+    read accesses on addresses "addr" and "addr + 4".  So instead of
+    reading a 64 bit value twice from "addr", we see a sequence of 4 32
+    bit reads from "addr", "addr + 4", "addr", and "addr + 4".	The
+    consequence is that flash_toggle() fails to work.
+
+    This patch implements a simple, but somewhat ugly solution, as it
+    avoids the use of flash_read64() in this critical place (by breaking
+    it down manually into 32 bit read operations) instead of rewriting
+    flash_read64() such to perform atomic 64 bit reads as one could
+    expect.  However, such a rewrite would require the use of floating
+    point load operations, which becomes pretty complex:
+
+	save MSR;
+	set Floating Point Enable bit in MSR;
+	use "lfd" instruction to perform atomic 64 bit read;
+	use "stfd" to store value to temporary variable on stack;
+	load u64 value from temporary variable;
+	restore saved MSR;
+	return u64 value;
+
+    The benefit-cost ratio of such an implementation was considered too
+    bad to actually attempt this, especially as we can expect that such
+    an implementation would not only have a bigger memory footprint but
+    also cause a performance degradation.
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit cdd4fe63b094d4b767f12ff241d72566b461ee61
+Author: Stefan Roese <sr@denx.de>
+Date:	Fri Oct 31 10:48:08 2008 +0100
+
+    ppc4xx: Fix spelling error in MAINTAINERS file
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit be270798900b75ad9c47c7b79c72f70441196c56
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Tue Oct 28 13:37:00 2008 +0100
+
+    ppc4xx: Update PMC440 board support
+
+    This patch brings PMC440 board support up to date:
+
+    - fix GPIO configuration
+    - add misc_init_f()
+    - use better values for usbact variable
+    - fix USB 2.0 phy reset sequence
+    - shrink BAR2 to save PCI address space
+    - add FDT support
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 75183b1a7fc04206d9779d13f16e03853d7e965d
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Tue Oct 28 13:36:59 2008 +0100
+
+    ppc4xx: Fix PMC440 BSP commands
+
+    This patch fixes the PMC440 BSP commands painit and selfreset
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 76b565b69f886d5ae748db65e44f464b0e70d41a
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Tue Oct 28 13:36:58 2008 +0100
+
+    ppc4xx: Update PMC440 board configuration
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit ca0c2d42b93116a8e1b8ef8ad4493c7dc9b5f2e4
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Tue Oct 28 13:36:57 2008 +0100
+
+    ppc4xx: Fix esd loadpci command
+
+    This patch fixes esd's loadpci command when not all
+    memory on adapter boards is accessable via PCI.
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 492aa9ea13791ca4591b5bde895a425e27ae2d10
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Tue Oct 28 13:36:56 2008 +0100
+
+    ppc4xx: Clean up PMC440 header
+
+    -Codingstyle cleanup
+    -Remove unused GPIO define
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 295133258a44f97a57fb2ec339aecfda11f4db95
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Tue Oct 28 13:36:55 2008 +0100
+
+    ppc4xx: Handle other board variant in PMC440 FPGA code
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit cc2dc9b08cf7c09f9f237f8cb9303f11603d4fb0
+Author: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es>
+Date:	Mon Oct 27 12:35:59 2008 +0100
+
+    ppc4xx: Merge xilinx-ppc440 and xilinx-ppc405 cfg
+
+    Xilinx ppc440 and ppc405 have many similarities. This patch merge the
+    config files of both infrastuctures
+
+    Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 3befd85633d33c4dcca1f359c3f4848c5ab8e4d2
+Author: Stefan Roese <sr@denx.de>
+Date:	Sat Oct 25 06:45:31 2008 +0200
+
+    ppc4xx: Correctly configure the GPIO pin muxing on Arches
+
+    Arches doesn't use PerCS3 but GPIO43, so let's configure the GPIO
+    pin multiplexing correctly
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 7c84fe6a06dad9f793ed85b39b1e6c11a7882f5c
+Author: Bartlomiej Sieka <tur@semihalf.com>
+Date:	Thu Oct 30 23:22:04 2008 +0100
+
+    Fix to the auto-update feature documentation (CONFIG_UPDATE_TFTP_MSEC_MAX)
+
+    Signed-off-by: Bartlomiej Sieka <tur@semihalf.com>
+
+commit 4bc7deee9095f21e243b724ca3d634251c1d5432
+Author: David Gibson <david@gibson.dropbear.id.au>
+Date:	Wed Oct 29 23:27:45 2008 -0500
+
+    libfdt: Fix bug in fdt_subnode_offset_namelen()
+
+    There's currently an off-by-one bug in fdt_subnode_offset_namelen()
+    which causes it to keep searching after it's finished the subnodes of
+    the given parent, and into the subnodes of siblings of the original
+    node which come after it in the tree.
+
+    Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit f242a08871839eac081ba5b599af979f3a148a0d
+Author: Peter Korsgaard <jacmet@sunsite.dk>
+Date:	Tue Oct 28 08:26:52 2008 +0100
+
+    fdt_resize(): ensure minimum padding
+
+    fdt_add_mem_rsv() requires space for a struct fdt_reserve_entry
+    (16 bytes), so make sure that fdt_resize at least adds that much
+    padding, no matter what the location or size of the fdt is.
+
+    Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
+    Acked-by: Andy Fleming <afleming@freescale.com>
+
+commit d685b74c64a38849f1a129b3ab846fbf67dd937e
+Author: Dave Liu <daveliu@freescale.com>
+Date:	Thu Oct 23 21:59:35 2008 +0800
+
+    74xx: use r4 instead of r2 in lock_ram_in_cache and unlock_ram_in_cache
+
+    The patch is following the commit 392438406041415fe64ab8748ec5ab5ad01d1cf7
+
+    mpc86xx: use r4 instead of r2 in lock_ram_in_cache and unlock_ram_in_cache
+
+    This is needed in unlock_ram_in_cache() because it is called from C and
+    will corrupt the small data area anchor that is kept in R2.
+
+    lock_ram_in_cache() is modified similarly as good coding practice, but
+    is not called from C.
+
+    Signed-off-by: Nick Spence <nick.spence@freescale.com>
+
+    also, the r2 is used as global data pointer.
+
+    Signed-off-by: Dave Liu <daveliu@freescale.com>
+
+commit e053ab1903ccae6048ef759025b9f675bba91450
+Author: Scott Wood <scottwood@freescale.com>
+Date:	Tue Oct 28 11:45:04 2008 -0500
+
+    mpc83xx pci: Round up memory size in inbound window.
+
+    The current calculation will fail to cover all memory if
+    its size is not a power of two.
+
+    Signed-off-by: Scott Wood <scottwood@freescale.com>
+    Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit 1c671977dc81359628be27ac99c174e76e8069ba
+Author: Dave Liu <daveliu@freescale.com>
+Date:	Thu Oct 23 21:19:13 2008 +0800
+
+    86xx: remove the unused definition
+
+    Signed-off-by: Dave Liu <daveliu@freescale.com>
+
+commit eaa44c5dc83756c3067b9e6c9db626facd0b0660
+Author: Dave Liu <daveliu@freescale.com>
+Date:	Tue Oct 28 17:47:49 2008 +0800
+
+    86xx: remove the redundant r2 global data pointer save
+
+    The commit 67256678f00c09b0a7f19e862e5c1847553d31bc add
+    the another global data pointer save, but in fact the
+    global data pointer will be initialized in the board_init_r,
+    so remove it such as the 85xx/83xx family.
+
+    Signed-off-by: Dave Liu <daveliu@freescale.com>
+    Acked-by: Kumar Gala <kumar.gala@freescale.com>
+
+commit bd888e9544419665334a6f47f81f34011cea38f3
+Author: Dave Liu <daveliu@freescale.com>
+Date:	Tue Oct 28 17:47:41 2008 +0800
+
+    86xx: remove the unused code for 86xx family
+
+    I believe these code was copied from 74xx family, but for
+    86xx, it is unused.
+
+    Signed-off-by: Dave Liu <daveliu@freescale.com>
+    Acked-by: Kumar Gala <kumar.gala@freescale.com>
+
+commit 5ba1ef507402bc5e344dc374203792a40f222e8a
+Author: Dave Liu <daveliu@freescale.com>
+Date:	Tue Oct 28 17:46:35 2008 +0800
+
+    86xx: remove the second DDR LAW setting for mpc8641hpcn
+
+    The DDR1 LAW will precedence the DDR2 LAW, so remove
+    the second DDR LAW.
+
+    Signed-off-by: Dave Liu <daveliu@freescale.com>
+    Acked-by: Becky Bruce <becky.bruce@freescale.com>
+
+commit 137a2dfd11ac51ae3154f13f323609b33a4a072e
+Author: Dave Liu <daveliu@freescale.com>
+Date:	Tue Oct 28 17:46:23 2008 +0800
+
+    86xx: remove the unused ddr_enable_ecc in the board file
+
+    The DDR controller of 86xx processors have the ECC data init
+    feature, and the new DDR code is using the feature, we don't
+    need the way with DMA to init memory again.
+
+    Signed-off-by: Dave Liu <daveliu@freescale.com>
+    Acked-by: Kumar Gala <kumar.gala@freescale.com>
+
+commit dc2adad85bf580d65916c940683f6e9671e8a5dd
+Author: Dave Liu <daveliu@freescale.com>
+Date:	Tue Oct 28 17:46:12 2008 +0800
+
+    86xx: Move the clear_tlbs before MMU turn on
+
+    We must invalidate TLBs before MMU turn on, but
+    currently the code is not, if there are some stale
+    TLB entry valid in the TLBs, it will cause strange
+    issue.
+
+    Signed-off-by: Dave Liu <daveliu@freescale.com>
+    Acked-by: Becky Bruce <becky.bruce@freescale.com>
+
+commit 5cdade07b118d07154cb882650f9778cecc8a87c
+Author: Scott Wood <scottwood@freescale.com>
+Date:	Mon Oct 27 15:57:08 2008 -0500
+
+    mpc8313erdb: Document NAND boot.
+
+    Previously, the documentation claimed that NAND boot is not supported.
+    This is no longer true.
+
+    Signed-off-by: Scott Wood <scottwood@freescale.com>
+
+commit bd78bc6b2aebf5566aac464f936b88dfd97ab0bd
+Author: Scott Wood <scottwood@freescale.com>
+Date:	Wed Oct 29 14:20:26 2008 -0500
+
+    NAND: Properly create JFFS2 cleanmarkers.
+
+    As reported by Ilko Iliev <iliev@ronetix.at>, the "nand erase clean"
+    command is currently broken, and among other things causes all blocks
+    to be marked bad.
+
+    This implements it properly using MTD_OOB_AUTO, along with some
+    indentation fixes.
+
+    Signed-off-by: Scott Wood <scottwood@freescale.com>
+
+commit f7fe57c09866b44692d18c8cf22828bd137ec58d
+Author: Scott Wood <scottwood@freescale.com>
+Date:	Wed Oct 29 13:42:41 2008 -0500
+
+    NAND fsl elbc: Set FMR[ECCM] based on page size.
+
+    Hardware expects ECCM 0 for small page and ECCM 1 for large page
+    when booting from NAND, so use those defaults.
+
+    Signed-off-by: Scott Wood <scottwood@freescale.com>
+
+commit c013b74975dab0805ef6d369b013230c4e8a660d
+Author: Haiying Wang <Haiying.Wang@freescale.com>
+Date:	Wed Oct 29 13:32:59 2008 -0400
+
+    NAND: Add support for MPC8572DS board
+
+    This patch defines 1M TLB&LAW size for NAND on MPC8572DS, assigns
+    0xffa00000 for CONFIG_SYS_NAND_BASE and adds other NAND supports in
+    config file.
+
+    It also moves environment(CONFIG_ENV_ADDR) outside of u-boot image, to
+    make room for the increased code size with NAND enabled.
+
+    Signed-off-by: Jason Jin <Jason.Jin@freescale.com>
+    Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
+    Signed-off-by: Scott Wood <scottwood@freescale.com>
+
+commit 4e190b03aaf2309bd2e025d1187a2ca880fedc95
+Author: Haiying Wang <Haiying.Wang@freescale.com>
+Date:	Wed Oct 29 11:05:55 2008 -0400
+
+    Make Freescale local bus registers available for both 83xx and 85xx.
+
+    - Rename lbus83xx_t to fsl_lbus_t and move it to asm/fsl_lbc.h so that it
+      can be shared by both 83xx and 85xx
+    - Remove lbus83xx_t and replace it with fsl_lbus_t in all 83xx boards
+      files which use lbus83xx_t.
+    - Move FMR, FIR, FCR, FPAR, LTESR from mpc83xx.h to asm/fsl_lbc.h so that
+      85xx can share them.
+
+    Signed-off-by: Jason Jin <Jason.Jin@freescale.com>
+    Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
+    Signed-off-by: Scott Wood <scottwood@freescale.com>
+
+commit 695c130e4bf75b444720ddfd83aca88f41c046cf
+Author: Scott Wood <scottwood@freescale.com>
+Date:	Mon Oct 27 15:38:30 2008 -0500
+
+    NAND: Align right column of the shorthelp with other commands.
+
+    I accidentally broke this in when making consistent the partial
+    alignment of the longhelp.
+
+    Signed-off-by: Scott Wood <scottwood@freescale.com>
+
+commit 33efde5ecac91ab118ff00b95a181fd6d75f8645
+Author: Karl Beldan <karl.beldan@gmail.com>
+Date:	Mon Sep 15 16:08:03 2008 +0200
+
+    NAND: Reset chip on power-up
+
+    Some chips require a RESET after power-up (e.g. Micron MT29FxGxxxxx).
+    The first command sent is NAND_CMD_READID.
+    Issue a NAND_CMD_RESET in nand_scan_ident before reading the device id.
+    Tested with an MT29F4G08AAC.
+
+    Signed-off-by: Karl Beldan <karl.beldan@gmail.com>
+    Signed-off-by: Scott Wood <scottwood@freescale.com>
+
+commit c45912d8abc52de796b9059a58faf7c4166eab58
+Author: Scott Wood <scottwood@freescale.com>
+Date:	Fri Oct 24 16:20:43 2008 -0500
+
+    NAND: sync with 2.6.27
+
+    This brings the core NAND code up to date with the Linux kernel.
+
+    Since there were several drivers in Linux as of the last update that are
+    not in u-boot, I'm not bringing over new drivers that have been added
+    since in the absence of an interested party.
+
+    I did not update OneNAND since it was recently synced by Kyungmin Park,
+    and I'm not sure exactly what the common ancestor is.
+
+    Signed-off-by: Scott Wood <scottwood@freescale.com>
+
+commit b1d0db1805c3395149777e507b6da53410abac4e
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Tue Oct 21 17:25:47 2008 -0500
+
+    bootm: Added CONFIG_BOOTM_{LINUX, NETBSD, RTEMS}
+
+    Added the ability to config out bootm support for Linux, NetBSD, RTEMS
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 5a98127d81a6eefc5a78a704df619bfe362eeb87
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Tue Oct 21 17:25:46 2008 -0500
+
+    bootm: support subcommands in linux ppc bootm
+
+    Add support for 'bdt', 'cmdline', 'prep' to the linux PPC bootm.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 49c3a861d11735838f1f1b11999ce433006dc919
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Tue Oct 21 17:25:45 2008 -0500
+
+    bootm: Add subcommands
+
+    Add the ability to break the steps of the bootm command into several
+    subcommands: start, loados, ramdisk, fdt, bdt, cmdline, prep, go.
+
+    This allows us to do things like manipulate device trees before
+    they are passed to a booting kernel or setup memory for a secondary
+    core in multicore situations.
+
+    Not all OS types support all subcommands (currently only start, loados,
+    ramdisk, fdt, and go are supported).
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit be08315933537f061bc1ce61f33a29c56458bbad
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Tue Oct 21 17:25:44 2008 -0500
+
+    bootm: Move to using a function pointer table for the boot os function
+
+    This removes a bit of code and makes it easier for the upcoming sub bootm
+    command support to call into the proper OS specific handler.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit a369f4a492fa2805d87775d27380f0eeaca35aa6
+Author: Graeme Russ <graeme.russ@gmail.com>
+Date:	Mon Sep 29 23:03:14 2008 +1000
+
+    i386: Renamed show_boot_progress in assembler code
+
+    Renamed show_boot_progress in assembler init phase to
+    show_boot_progress_asm to avoid link conflicts with C version
+
+    Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
+
+commit 4442f45b0e1cbad35aa22d4cad22b90a57e3f32d
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date:	Mon Oct 27 16:42:00 2008 -0500
+
+    85xx: Update MPC85xx_PORDEVSR_IO_SEL mask
+
+    The MPC8572 has a 4-bit wide PORDEVSR IO_SEL field. Other MPC85xx
+    processors have a 3-bit wide IO_SEL field but have the most
+    significant bit is wired to 0 so this change should not affect
+    them.
+
+    Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+
+commit cd4251624205cb97104f6e32679dc7754934f711
+Author: Becky Bruce <becky.bruce@freescale.com>
+Date:	Mon Oct 27 16:09:42 2008 -0500
+
+    powerpc: fix pci window initialization to work with > 4GB DRAM
+
+    The existing code has a few errors that need to be fixed in
+    order to support large RAM sizes.  Fix those, and add a
+    comment to make it clearer.
+
+    Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
+    Acked-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 219542a1a66ca017b12860920714a9859b18a5d7
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Mon Oct 27 13:16:20 2008 -0500
+
+    pci/fsl_pci_init: Removed a bunch pointless trailing backslashes.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 6b59e03e0237a40a2305ea385defdfd92000978b
+Author: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
+Date:	Mon Sep 1 16:21:22 2008 +0200
+
+    lcd: Let the board code show board-specific info
+
+    The information displayed when CONFIG_LCD_INFO is set is inherently
+    board-specific, so it should be done by the board code. The current code
+    dealing with this only handles two cases, and is already a horrible mess
+    of #ifdeffery.
+
+    Yes, this duplicates some code, but it also allows boards to print more
+    board-specific information; this used to be very difficult.
+
+    Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
+    Signed-off-by: Anatolij Gustschin <agust@denx.de>
+
+commit 6f93d2b8fca504200a5758f7c6dd2d6852900765
+Author: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
+Date:	Mon Sep 1 16:21:21 2008 +0200
+
+    lcd: Set lcd_is_enabled before clearing the screen
+
+    This allows the logo/info rendering routines to use the regular
+    lcd_putc/lcd_puts/lcd_printf calls.
+
+    Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
+    Signed-off-by: Anatolij Gustschin <agust@denx.de>
+
+commit 15b17ab52b7c15d46d9fc631cc06092e1e764de2
+Author: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
+Date:	Mon Sep 1 16:21:20 2008 +0200
+
+    lcd: Implement lcd_printf()
+
+    lcd_printf() has a prototype in include/lcd.h but no implementation. Fix
+    this by borrowing the lcd_printf() implementation from the cogent board
+    code (which appears to use its own LCD framework.)
+
+    Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
+    Signed-off-by: Anatolij Gustschin <agust@denx.de>
+
+commit 70dbc54c0a5c798bcf82ae2a1e227404f412e892
+Author: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
+Date:	Mon Sep 1 16:21:19 2008 +0200
+
+    atmel_lcdfb: Straighten out funky vl_sync logic
+
+    If the board _didn't_ request INVLINE_INVERTED, we set INVLINE_INVERTED,
+    otherwise we don't. WTF?
+
+    Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
+    Signed-off-by: Anatolij Gustschin <agust@denx.de>
+
+commit 23bb28f0f76b46c4b573374b0bb3b3f23d85ef55
+Author: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
+Date:	Mon Sep 1 16:21:18 2008 +0200
+
+    atmel_lcdfb: Eliminate unneeded #include <asm/arch/hardware.h>
+
+    atmel_lcdfb doesn't actually need anything from asm/arch/hardware.h. It
+    includes a file that does, asm/arch/gpio.h, but this file doesn't
+    include <asm/arch/hardware.h> like it's supposed to.
+
+    Add the missing include to asm/arch/gpio.h and remove the workaround
+    from the atmel_lcdfb driver. This makes the driver compile on avr32.
+
+    Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
+    Signed-off-by: Anatolij Gustschin <agust@denx.de>
+
+commit c2083e0e11a03ef8be2e9f0ed8720fdc20832f3e
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Wed Oct 22 14:38:55 2008 -0500
+
+    86xx: Convert all fsl_pci_init users to new APIs
+
+    Converted MPC8610HCPD, MPC8641HPCN, and SBC8641D to use
+    fsl_pci_setup_inbound_windows() and ft_fsl_pci_setup().
+
+    With these changes the board code is a bit smaller and we get dma-ranges
+    set in the device tree for these boards.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+    Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
+    Acked-by: Jon Loeliger <jdl@freescale.com>
+
+commit 2dba0dea98c0dee1799ffd6fd6eb541645dbbd98
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Tue Oct 21 08:28:33 2008 -0500
+
+    85xx: Convert all fsl_pci_init users to new APIs
+
+    Converted ATUM8548, MPC8536DS, MPC8544DS, MPC8548CDS, MPC8568MDS,
+    MPC8572DS, TQM85xx, and SBC8548 to use fsl_pci_setup_inbound_windows()
+    and ft_fsl_pci_setup().
+
+    With these changes the board code is a bit smaller and we get dma-ranges
+    set in the device tree for these boards.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+    Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
+
+commit a2aab460727e5f674353a83a81000ef794bffcae
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Thu Oct 23 00:01:06 2008 -0500
+
+    pci/fsl_pci_init: Added fdt helper for setting up bus-ranges & dma-ranges
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+    Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
+
+commit b9a1fa9787a3a79573f5f932a4f8aa216bcb1785
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Wed Oct 22 14:06:24 2008 -0500
+
+    pci/fsl_pci_init: Add a common PCI inbound setup function
+
+    Add a common setup function that determines the pci_region(s) based
+    on how much memory we have in the system.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+    Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
+
+commit 612ea01018a459234d54ed57ec6a5a244ce75678
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Tue Oct 21 10:13:14 2008 -0500
+
+    pci/fsl_pci_init: Enable larger address and setting inbound windows properly
+
+    * PCI Inbound window was setup incorrectly.  The PCI address and system
+      address were swapped.  The PCI address should be setting piwar/piwbear
+      and the system address should be setting pitar.
+
+    * Removed masking of addresses to allow for system address to support
+      system address & PCI address >32-bits
+
+    * Set PIWBEAR & POTEAR to allow for full 64-bit PCI addresses
+
+    * Respect the PCI_REGION_PREFETCH for inbound windows
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+    Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
+
+commit 8ab451c46b846f2bbd7122b29ffdd9a4a04da228
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Wed Oct 22 23:33:56 2008 -0500
+
+    fdt: Added helper to set PCI dma-ranges property
+
+    Added fdt_pci_dma_ranges() that parses the pci_region info from the
+    struct pci_controller and populates the dma-ranges based on it.
+
+    The max # of windws/dma-ranges we support is 3 since on embedded
+    PowerPC based systems this is the max number of windows.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+    Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
+
+commit 3bed2aaf2d50fd13273c14d17d4fd40ef42e0d0f
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Thu Oct 23 00:05:47 2008 -0500
+
+    fdt: Add fdt_getprop_u32_default helpers
+
+    Add helper functions to return find a node and return it's property
+    or a default value.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+    Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
+    Acked-by: Gerald Van Baren <vanbaren@cideas.com>
+
+commit 8ba93f68a1bae89e033527ce67b41b4a87aa5b7f
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Tue Oct 21 18:06:15 2008 -0500
+
+    86xx: Enable 64-bit PCI resources on all Freescale boards
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+    Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
+
+commit 0151cbaccf4504821ecfde0217299bd740086bb6
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Tue Oct 21 11:33:58 2008 -0500
+
+    85xx: Enable 64-bit PCI resources on all Freescale boards
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+    Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
+
+commit 30e76d5e3bc4c5208ee63585fe12b409d9308cd8
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Tue Oct 21 08:36:08 2008 -0500
+
+    pci: Allow for PCI addresses to be 64-bit
+
+    PCI bus is inherently 64-bit.  While not all system require access to
+    the full 64-bit PCI address range some do.	This allows those systems
+    to enable the full PCI address width via CONFIG_SYS_PCI_64BIT.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+    Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
+    Acked-by: Wolfgang Denk <wd@denx.de>
+
+commit ae5f943ba8ede448a4b1a145fd8911856701ecc5
+Author: Dave Liu <daveliu@freescale.com>
+Date:	Thu Oct 23 21:18:53 2008 +0800
+
+    85xx: Fix the incorrect register used for DDR erratum1
+
+    The 8572 DDR erratum1:
+    DDR controller may enter an illegal state when operating
+    in 32-bit bus mode with 4-beat bursts.
+
+    Description:
+    When operating with a 32-bit bus, it is recommended that
+    DDR_SDRAM_CFG[8_BE] is cleared when DDR2 memories are used.
+    This forces the DDR controller to use 4-beat bursts when
+    communicating to the DRAMs. However, an issue exists that
+    could lead to data corruption when the DDR controller is
+    in 32-bit bus mode while using 4-beat bursts.
+
+    Projected Impact:
+    If the DDR controller is operating in 32-bit bus mode with
+    4-beat bursts, then the controller may enter into a bad state.
+    All subsequent reads from memory is corrupted.
+    Four-beat bursts with a 32-bit bus only is used with DDR2 memories.
+    Therefore, this erratum does not affect DDR3 mode.
+
+    Work Arounds:
+    To work around this issue, software must set DEBUG_1[31] in
+    DDR memory mapped space (CCSRBAR offset + 0x2f00 for DDR_1
+    and CCSRBAR offset + 0x6f00 for DDR_2).
+
+    Currenlty, the code is using incorrect register DDR_SDRAM_CFG_2
+    as condition, but it should be DDR_SDRAM_CFG register.
+
+    Signed-off-by: Dave Liu <daveliu@freescale.com>
+
+commit d5b693090ed08d24c18491df9d8fc7387b2906f3
+Author: Dave Liu <daveliu@freescale.com>
+Date:	Thu Oct 23 21:17:19 2008 +0800
+
+    85xx: remove unused config definition
+
+    Signed-off-by: Dave Liu <daveliu@freescale.com>
+
+commit 0f060c3bf82832331a509f2e5d2442539e7aad09
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Thu Oct 23 01:47:38 2008 -0500
+
+    85xx: Add basic e500mc core support
+
+    Introduce CONFIG_E500MC to deal with the minor differences between
+    e500v2 and e500mc.
+
+    * Certain fields of HID0/1 don't exist anymore on e500mc
+    * Cache line size is 64-bytes on e500mc
+    * reset value of PIR is different
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit a38a5b6edd30f29fd5fdb1d7f674521906c0e677
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Thu Oct 23 01:47:37 2008 -0500
+
+    85xx: Use CONFIG_SYS_CACHELINE_SIZE instead of magic number
+
+    Using CONFIG_SYS_CACHELINE_SIZE instead of 31 means we can handle
+    e500mc's 64-byte cacheline properly when it gets added.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 5deb8022c3749faac30e9ad9694691e2442b5c93
+Author: Georg Schardt <schardt@team-ctech.de>
+Date:	Fri Oct 24 13:51:52 2008 +0200
+
+    ppc4xx: New board avnet fx12 minimodul
+
+    This patch adds support for the avnet fx12 minimodul.
+    It needs the "ppc4xx: Generic architecture for xilinx ppc405"
+    patch from Ricardo.
+
+    Signed-off-by: Georg Schardt <schardt@team-ctech.de>
+    Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 1f4d53260ec6f8f122aed75cce7c757d97a551e0
+Author: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es>
+Date:	Tue Oct 21 18:29:46 2008 +0200
+
+    ppc4xx: Generic architecture for xilinx ppc405(v3)
+
+    As "ppc44x: Unification of virtex5 pp440 boards" did for the xilinx
+    ppc440 boards, this patch presents a common architecture for all the
+    xilinx ppc405 boards.
+
+    Any custom xilinx ppc405 board can be added very easily with no code
+    duplicity.
+
+    This patch also adds a simple generic board, that can be used on almost
+    any design with xilinx ppc405 replacing the file ppc405-generic/xparameters.h
+
+    This patch is prepared to work with the latest version of EDK (10.1)
+
+    Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 485c00a57fab86f72a3769480c66bf1ca22e1459
+Author: Stefan Roese <sr@denx.de>
+Date:	Fri Oct 24 08:56:09 2008 +0200
+
+    ppc4xx: Disable DDR2 autocalibration on Kilauea for now
+
+    Since the new autocalibration still has some problems on some Kilauea
+    boards with 200MHz DDR2 frequency we disable the autocalibration and
+    use the hardcoded values as done before. This seems to work reliably
+    on all known DDR2 frequencies.
+
+    After the autocalibration issue is fixed we will enable it again.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit f177f4250c729727b1629fa8d8d6556c999e9b8c
+Author: Mike Frysinger <vapier@gentoo.org>
+Date:	Wed Apr 9 02:02:07 2008 -0400
+
+    Blackfin: fix up UART status bit handling
+
+    Some Blackfin UARTs are read-to-clear while others are write-to-clear.
+    This can cause problems when we poll the LSR and then later try and handle
+    any errors detected.
+
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit ae0910298f31f5bb3d33a64b8467c60ea3c5d6d0
+Author: Mike Frysinger <vapier@gentoo.org>
+Date:	Sat Oct 11 20:42:17 2008 -0400
+
+    Blackfin: bf561-ezkit: drop redundant code
+
+    Common Blackfin code already announces CPU information.
+
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit e2eea98bff1369f77a9f59a5fd0bd4928bc3332e
+Author: Mike Frysinger <vapier@gentoo.org>
+Date:	Sat Oct 11 20:43:10 2008 -0400
+
+    Blackfin: bf561-ezkit: drop pointless USB code
+
+    The USB/LAN register settings are not actually used/needed in order to
+    drive things from U-Boot, so drop the code.
+
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit c23bff63fb03cb9dbcd26522841e53f9b34fa1ab
+Author: Mike Frysinger <vapier@gentoo.org>
+Date:	Sat Oct 11 20:47:58 2008 -0400
+
+    Blackfin: linker scripts: force start.o and set initcode boundaries
+
+    Make sure that the start.o object is always the first object in our linker
+    script regardless of configuration settings, and add some linker symbols
+    so the ldr utility can properly locate the initcode when generating a LDR.
+
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit bd33e5c613cf70e3cb51a73fdd653fe83b942bb0
+Author: Mike Frysinger <vapier@gentoo.org>
+Date:	Sat Oct 11 21:19:39 2008 -0400
+
+    Blackfin: small cpu init optimization while setting interrupt mask
+
+    Use the sti instruction to set the initial interrupt mask rather than
+    banging on the core IMASK MMR to save both space and time.
+
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 960922291c9594acb575cec7e47d7bed9b58182c
+Author: Mike Frysinger <vapier@gentoo.org>
+Date:	Sat Oct 11 21:18:10 2008 -0400
+
+    Blackfin: set initial stack correctly according to Blackfin ABI
+
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 25cd33d82ea521b7bd90ca858f8919fae1e9732b
+Author: Mike Frysinger <vapier@gentoo.org>
+Date:	Sun Apr 20 03:11:53 2008 -0400
+
+    Blackfin: make baud calculation more accurate
+
+    We should use the algorithm in the Linux kernel so that the UART divisor
+    calculation is more accurate.  It also fixes problems on some picky UARTs
+    that have sampling anomalies.
+
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 0ba1da116e5edcb0c5ae4a7585d73f6548400a06
+Author: Mike Frysinger <vapier@gentoo.org>
+Date:	Mon Oct 6 04:21:41 2008 -0400
+
+    Blackfin: decode hwerrcause/excause when crashing
+
+    Having to decode hwerrcause/excause values is a pain, so automate it.
+
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 2de95bb20c488f20298df6881b700a5a757ee780
+Author: Mike Frysinger <vapier@gentoo.org>
+Date:	Mon Oct 6 04:20:54 2008 -0400
+
+    Blackfin: fix register dump messages
+
+    Make sure we report RETI/IPEND correctly.
+
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 7133999e6f62a9a01f6a8ffe234b8532b3ad1e4b
+Author: Mike Frysinger <vapier@gentoo.org>
+Date:	Mon Oct 6 04:19:34 2008 -0400
+
+    Blackfin: don't bother displaying reboot msg when crashing
+
+    The hang function already tells you to reboot, so no point in showing it
+    twice.
+
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 70c4c032ea112cc42aa1ce959c33fc4825eaef95
+Author: Mike Frysinger <vapier@gentoo.org>
+Date:	Sun Jun 1 01:23:48 2008 -0400
+
+    Blackfin: enable support for nested interrupts
+
+    During cpu init, make sure we initialize the CEC properly so that
+    interrupts can fire and be handled while U-Boot is running.
+
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 39782727e185860faa4884c2b04e84cb33d1c6cf
+Author: Mike Frysinger <vapier@gentoo.org>
+Date:	Mon Oct 6 03:55:25 2008 -0400
+
+    Blackfin: init NAND before relocating env
+
+    If booting out of NAND, we need to make sure we initialize it properly
+    before attempting to relocate the environment.
+
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 0f9a8819416ba40a53de50af148847a0e508f84d
+Author: Mike Frysinger <vapier@gentoo.org>
+Date:	Thu Aug 7 18:40:13 2008 -0400
+
+    Blackfin: check cache bits, not cplb bits
+
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 2c1ea9e370cb72dd6a5aa32338e87a8a1f77bd76
+Author: Mike Frysinger <vapier@gentoo.org>
+Date:	Thu Aug 7 17:52:59 2008 -0400
+
+    Blackfin: drop unused cache flush code
+
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 50f0d211912a648e31aa9123b4665a0444bb8ca9
+Author: Mike Frysinger <vapier@gentoo.org>
+Date:	Thu Aug 7 15:21:47 2008 -0400
+
+    Blackfin: unify cache handling code
+
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 3c8798983403cb68a827d7a0d09b1134524a1b7d
+Author: Mike Frysinger <vapier@gentoo.org>
+Date:	Mon Oct 6 03:39:07 2008 -0400
+
+    Blackfin: only initialize the RTC when actually used
+
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 621e579b812dd1a2e6777f7cbf6e55e736505823
+Author: Mike Frysinger <vapier@gentoo.org>
+Date:	Mon Oct 6 03:44:33 2008 -0400
+
+    Blackfin: fix SWRST register definition
+
+    The SWRST register is a 16bit, not 32bit, register.
+
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 06121c4e2d183887dcd7a4ca2dcd395b213ea15b
+Author: Mike Frysinger <vapier@gentoo.org>
+Date:	Thu Aug 7 18:54:57 2008 -0400
+
+    Blackfin: build with -fomit-frame-pointer
+
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit adbfeeb7b32f737a9738daa583350d2bb9ed017a
+Author: Mike Frysinger <vapier@gentoo.org>
+Date:	Thu Aug 7 17:50:26 2008 -0400
+
+    Blackfin: document some of the blackfin directories
+
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit e4337968e43698a68ba608369f46d4a4114111ca
+Author: Mike Frysinger <vapier@gentoo.org>
+Date:	Thu Aug 7 15:16:56 2008 -0400
+
+    Blackfin: only enable hardware error irq by default
+
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 2b66f08f257ef6a06785f27b3c6dc2a4cfc9cac4
+Author: Mike Frysinger <vapier@gentoo.org>
+Date:	Thu Aug 7 13:36:43 2008 -0400
+
+    Blackfin: punt old unused mem_init.h header
+
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit bcc121a01608042066a19ab5bff5bcfb805bf406
+Author: Mike Frysinger <vapier@gentoo.org>
+Date:	Thu Aug 7 13:18:55 2008 -0400
+
+    Blackfin: delete unused page_descriptor_table_size define
+
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 30fb9d24ae16e5b0ed39e5b7cc85981165ca98bc
+Author: Mike Frysinger <vapier@gentoo.org>
+Date:	Thu Aug 7 13:17:03 2008 -0400
+
+    Blackfin: fix typo in boot mode comment and add NAND define
+
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 2e5cbe5461c5c4c6665e318cfe950a5a150d999c
+Author: Ben Maan <moo@cow>
+Date:	Thu Aug 7 13:14:21 2008 -0400
+
+    Blackfin: fix port mux defines for BF54x
+
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 0656ef2ba274910d31364fe022f6c7db0051660d
+Author: Mike Frysinger <vapier@gentoo.org>
+Date:	Thu Aug 7 13:09:50 2008 -0400
+
+    Blackfin: update anomaly lists
+
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 50ca95402876cf7bac4e2d4f7855f616a038763f
+Author: Mike Frysinger <vapier@gentoo.org>
+Date:	Thu Aug 7 13:08:54 2008 -0400
+
+    Blackfin: unify DSPID/DBGSTAT MMR definitions
+
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit d9d8c7c696dec370ca714c03beb6e79d4c90bd5e
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Tue Oct 21 15:53:51 2008 +0200
+
+    Fix strmhz(): avoid printing negative fractions
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 4a7f6b750d8de543fdf8e58acd86745010054571
+Author: Richard Retanubun <RichardRetanubun@ruggedcom.com>
+Date:	Fri Oct 17 08:55:51 2008 -0400
+
+    mpc83xx: Removed #ifdef CONFIG_MPC834X dependency on upmconfig function
+
+    This is done to allow other 83XX based platforms which also have UPM
+    (e.g. 8360) to configure and use their UPM in u-boot.
+
+    Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com>
+    Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit 3bf1be3c0cfb1129b68cc1474119e5f323536488
+Author: Anton Vorontsov <avorontsov@ru.mvista.com>
+Date:	Tue Oct 14 22:58:53 2008 +0400
+
+    mpc83xx: add support for switching between USB Host/Function for MPC837XEMDS
+
+    With this patch u-boot can fixup the dr_mode and phy_type properties
+    for the Dual-Role USB controller.
+
+    While at it, also remove #ifdefs around includes, they are not needed.
+
+    Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
+    Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit b3379f3fd13969934c00097c05754e7a8990fd39
+Author: Anton Vorontsov <avorontsov@ru.mvista.com>
+Date:	Wed Oct 8 20:52:54 2008 +0400
+
+    mpc83xx: add ELBC NAND support for the MPC837XEMDS boards
+
+    Though NAND chip is replaceable on the MPC837XE-MDS boards, the
+    current settings don't work with the default chip on the board.
+    Nevertheless Freescale's U-Boot sets the option register correctly,
+    so I just dumped the register from the working u-boot. My guess is
+    that the old settings were applicable for some pilot boards, not
+    found in the production.
+
+    This patch also enables FSL ELBC driver so that we could access
+    the NAND storage in the u-boot.
+
+    The NAND support costs about 45KB, so the u-boot no longer fits
+    into two 128KB NOR flash sectors, thus we also have to adjust
+    environment location: add another 128KB to the monitor length.
+
+    Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
+
+    It is due to hardware design and logic defect, that is the
+    I/O[0:7] of NAND chip is connected to LAD[7:0], so when
+    the NAND chip connected to nLCS3,  you have to set up the
+    OR3[BCTLD] = '1' for normal operation, otherwise it will have
+    bus contention due to the pin 48/25 of U60 is enabled.
+
+    Setup the OR3[BCTLD] = '1' , that meaning the LBCTL is not
+    asserted upon access to the NAND chip, keep the default state.
+
+    Acked-by: Dave Liu <daveliu@freescale.com>
+    Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit 00f7bbae92e3b13f2b37aeb1def9bb12445521b7
+Author: Anton Vorontsov <avorontsov@ru.mvista.com>
+Date:	Thu Oct 2 19:17:33 2008 +0400
+
+    mpc83xx: fix PCI scan hang on the standalone MPC837xE-MDS boards
+
+    The MPC837xE-MDS board's CPLD can auto-detect if the board is on the PIB,
+    standalone or acting as a PCI agent. User's Guide says:
+
+    - When the CPLD recognizes its location on the PIB it automatically
+      configures RCW to the PCI Host.
+    - If the CPLD fails to recognize its location then it is automatically
+      configured as an Agent and the PCI is configured to an external arbiter.
+
+    This sounds good. Though in the standalone setup the CPLD sets PCI_HOST
+    flag (it's ok, we can't act as PCI agents since we receive CLKIN, not
+    PCICLK), but the CPLD doesn't set the ARBITER_ENABLE flag, and without
+    any arbiter bad things will happen (here the board hangs during any config
+    space reads).
+
+    In this situation we must disable the PCI. And in case of anybody really
+    want to use an external arbiter, we provide "pci_external_aribter"
+    environment variable.
+
+    Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
+    Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit 1da83a63d8e1b4bddeb82581b1745a09aac3e2d3
+Author: Anton Vorontsov <avorontsov@ru.mvista.com>
+Date:	Thu Oct 2 18:32:25 2008 +0400
+
+    mpc83xx: add SGMII riser module support for the MPC8378E-MDS boards
+
+    This involves configuring the SerDes and fixing up the flags and
+    PHY addresses for the TSECs.
+
+    For Linux we also fix up the device tree.
+
+    Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
+    Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit e6d9c8916de9c24f2c52d0b01cf00d2e74a04cd8
+Author: Anton Vorontsov <avorontsov@ru.mvista.com>
+Date:	Thu Oct 2 18:31:59 2008 +0400
+
+    mpc83xx: add TSECs' HRCWH masks for MPC837x processors
+
+    We'll use these masks to parse TSEC modes out of HRCWH.
+
+    Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
+    Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit 6f9cc6608b4e1cefde56c0fb99ae1c95c42575ff
+Author: Anton Vorontsov <avorontsov@ru.mvista.com>
+Date:	Thu Oct 2 18:31:56 2008 +0400
+
+    mpc83xx: serdes: add forgotten shifts for rfcks
+
+    The rfcks should be shifted by 28 bits left. We didn't notice the bug
+    because we were using only 100MHz clocks (for which rfcks == 0).
+
+    Though, for SGMII we'll need 125MHz clocks.
+
+    Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
+    Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit 55c531984dcf933e4cd13a187a7e08e873b7ced1
+Author: Anton Vorontsov <avorontsov@ru.mvista.com>
+Date:	Thu Oct 2 18:31:53 2008 +0400
+
+    mpc83xx: fix serdes setup for the MPC8378E boards
+
+    MPC837xE specs says that SerDes1 has:
+
+    — Two lanes running x1 SGMII at 1.25 Gbps;
+    — Two lanes running x1 SATA at 1.5 or 3.0 Gbps.
+
+    And for SerDes2:
+
+    — Two lanes running x1 PCI Express at 2.5 Gbps;
+    — One lane running x2 PCI Express at 2.5 Gbps;
+    — Two lanes running x1 SATA at 1.5 or 3.0 Gbps.
+
+    The spec also explicitly states that PEX options are not valid for
+    the SD1.
+
+    Nevertheless MPC8378 RDB and MDS boards configure the SD1 for PEX,
+    which is wrong to do.
+
+    Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
+    Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit 5c2ff323a94e27e481f70c44838d43fcd844dd46
+Author: Anton Vorontsov <avorontsov@ru.mvista.com>
+Date:	Wed Sep 10 18:12:37 2008 +0400
+
+    mpc83xx: mpc8360emds: rework LBC SDRAM setup
+
+    Currently 64M of LBC SDRAM are mapped at 0xF0000000 which makes
+    it difficult to use (b/c then the memory is discontinuous and
+    there is quite big memory hole between the DDR/SDRAM regions).
+
+    This patch reworks LBC SDRAM setup so that now we dynamically
+    place the LBC SDRAM near the DDR (or at 0x0 if there isn't any
+    DDR memory).
+
+    With this patch we're able to:
+
+    - Boot without external DDR memory;
+    - Use most "DDR + SDRAM" setups without need to support for
+      sparse/discontinuous memory model in the software.
+
+    Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
+    Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit def0819e920b05b34b56d8b42e1e43d9b89a52d6
+Author: Wolfgang Denk <wd@xpert.denx.de>
+Date:	Tue Oct 21 11:23:56 2008 +0200
+
+    FDT: don't use private kernel header files
+
+    On some systems (for example Fedora Core 4) U-Boot builds with the
+    following wanrings only:
+
+    ...
+    In file included from /home/wd/git/u-boot/include/libfdt_env.h:33,
+		     from fdt.c:51:
+		 /usr/include/asm/byteorder.h:6:2: warning: #warning using private kernel header; include <endian.h> instead!
+
+    This patch fixes this problem.
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit f4d14c55504ce40287321bd63ee269e3233ee4ae
+Author: Stefan Roese <sr@denx.de>
+Date:	Mon Oct 13 15:15:31 2008 +0200
+
+    ppc4xx: Add 1.0 & 1.066 GHz to canyonlands bootstrap command for PLL setup
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 43cbce69d48d052574d71f50724be546d90a46a4
+Author: Stefan Roese <sr@denx.de>
+Date:	Mon Oct 13 10:45:14 2008 +0200
+
+    ppc4xx: Correctly setup ranges property in ebc node
+
+    Previously only the NOR flash mapping was written into the ranges
+    property of the ebc node. This patch now writes all enabled chip
+    select areas into the ranges property.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit d7b26d58328f137471ea97de382bfa63f7239931
+Author: Dirk Eibach <eibach@gdsys.de>
+Date:	Wed Oct 8 15:37:50 2008 +0200
+
+    ppc4xx: Add GDSys neo 405EP board support
+
+    Signed-off-by: Dirk Eibach <eibach@gdsys.de>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit c11da194545d2f4bbb54be1bb5e504e20ce8c16c
+Author: Niklaus Giger <niklaus.giger@netstal.com>
+Date:	Wed Oct 1 14:46:13 2008 +0200
+
+    ppc4xx: Update configs for Netstal boards
+
+    I reorganized my config files, putting the common stuff into netstal-common.h
+    (got the idea by looking a amcc-common.h from Stefan).
+
+    Added stuff to boot the new powerpc linux via NFS (only tested with HCU4).
+
+    Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit c9c11d751e4242cf29c3c3c290d971f6d0cb1d15
+Author: Adam Graham <agraham@amcc.com>
+Date:	Wed Oct 8 10:13:19 2008 -0700
+
+    ppc4xx: Add routine to retrieve CPU number
+
+    Provide a weak defined routine to retrieve the CPU number for
+    reference boards that have multiple CPU's.	Default behavior
+    is the existing single CPU print output.  Reference boards with
+    multiple CPU's need to provide a board specific routine.
+    See board/amcc/arches/arches.c for an example.
+
+    Signed-off-by: Adam Graham <agraham@amcc.com>
+    Signed-off-by: Victor Gallardo <vgallardo@amcc.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 59217bae40e90982ab5400d849c08af683ace036
+Author: Adam Graham <agraham@amcc.com>
+Date:	Wed Oct 8 10:13:14 2008 -0700
+
+    ppc4xx: Add static support for 44x IBM SDRAM Controller
+
+    This patch add the capability to configure a PPC440 based IBM SDRAM
+    Controller with static, compiled-in, values. PPC440 memory subsystem
+    includes a Memory Queue core.
+
+    Signed-off-by: Adam Graham <agraham@amcc.com>
+    Signed-off-by: Victor Gallardo <vgallardo@amcc.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit f09f09d3899017aaaa2b031bba63c271e9c48e4d
+Author: Adam Graham <agraham@amcc.com>
+Date:	Wed Oct 8 10:12:53 2008 -0700
+
+    ppc4xx: Add AMCC Arches board support (dual 460GT)
+
+    The Arches Evaluation board is based on the AMCC 460GT SoC chip.
+    This board is a dual processor board with each processor providing
+    independent resources for Rapid IO, Gigabit Ethernet, and serial
+    communications. Each 460GT has it's own 512MB DDR2 memory, 32MB NOR
+    FLASH, UART, EEPROM and temperature sensor, along with a shared debug
+    port. The two 460GT's will communicate with each other via shared
+    memory, Gigabit Ethernet and x1 PCI-Express.
+
+    Signed-off-by: Adam Graham <agraham@amcc.com>
+    Signed-off-by: Victor Gallardo <vgallardo@amcc.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 055b12f2ffd7c34eea7e983a0588b24f2e69e0e3
+Author: Wolfgang Denk <wd@xpert.denx.de>
+Date:	Sun Oct 19 21:54:30 2008 +0200
+
+    TQM8260: environment in flash instead EEPROM, baudrate 115k
+
+    Several customers have reported problems with the environment in
+    EEPROM, including corrupted content after board reset. Probably the
+    code to prevent I2C Enge Conditions is not working sufficiently.
+
+    We move the environment to flash now, which allows to have a backup
+    copy plus gives much faster boot times.
+
+    Also, change the default console initialization to 115200 bps as used
+    on most other boards.
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 1836881190b3d8a6918b0d64b39fe32bbbdf85d8
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Sun Oct 19 12:49:19 2008 -0500
+
+    85xx: Fix compile warning in mpc8536ds.c
+
+    mpc8536ds.c: In function 'is_sata_supported':
+    mpc8536ds.c:615: warning: unused variable 'devdisr'
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 8ed44d91c8122d00368523b0b746691c895d3b3c
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Sun Oct 19 02:35:50 2008 +0200
+
+    Cleanup: fix "MHz" spelling
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 08ef89ecd174969b3544f3f0c7cd1de3c57f737b
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Sun Oct 19 02:35:49 2008 +0200
+
+    Use strmhz() to format clock frequencies
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit d50c7d4be150b2252c0d2e16cfcf69643bdd6dc9
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Sun Oct 19 02:35:48 2008 +0200
+
+    strmhz(): Round numbers when printing clock frequencies
+
+    Round clock frequencies for printing.
+
+    Many boards printed off clock frequencies like 399 MHz instead of the
+    exact 400 MHz because numberes were not rounded. This is fixed now.
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 681c02d05b29c6d46093525052c74b9c4ddc8b08
+Author: Timur Tabi <timur@freescale.com>
+Date:	Mon Oct 20 15:16:47 2008 -0500
+
+    85xx: properly document MPC85xx_PORDEVSR2_SEC_CFG
+
+    Commit f7d190b1 corrected the value of MPC85xx_PORDEVSR2_SEC_CFG, but forgot
+    to add a comment that the correct value disagrees with the 8544 reference
+    manual.  The changelog for that commit is also wrong, as it says "bit 28"
+    when it should be "bit 24".
+
+    Signed-off-by: Timur Tabi <timur@freescale.com>
+
+commit 360fe71e82b83e264c964c9447c537e9a1f643c8
+Author: Heiko Schocher <hs@denx.de>
+Date:	Fri Oct 17 18:24:06 2008 +0200
+
+    mgcoge: add redundant environment sector
+
+    Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit 53ebf0c470c87d5f9fa76462e5f4064d26a9b16a
+Author: Heiko Schocher <hs@denx.de>
+Date:	Fri Oct 17 18:23:27 2008 +0200
+
+    mgsuvd: update size of environment
+
+    Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit 2e26d837f11460c0e6dede7d65424a31e0183d09
+Author: Jason Jin <Jason.jin@freescale.com>
+Date:	Fri Oct 10 11:41:00 2008 +0800
+
+    Enabled the Freescale SGMII riser card on 8536DS
+
+    Signed-off-by: Jason Jin <Jason.jin@freescale.com>
+
+commit 7e183cad0c5ab6415dca95d6ac290ea918b28c55
+Author: Liu Yu <yu.liu@freescale.com>
+Date:	Fri Oct 10 11:40:59 2008 +0800
+
+    Enabled the Freescale SGMII riser card on 8572DS
+
+    This patch based on Andy's work.
+    Including command 'pixis_set_sgmii' support.
+
+    Signed-off-by: Liu Yu <yu.liu@freescale.com>
+
+commit bff188baf9427c35745356439435acf3864d4c65
+Author: Liu Yu <yu.liu@freescale.com>
+Date:	Fri Oct 10 11:40:58 2008 +0800
+
+    Make pixis_set_sgmii more general to support MPC85xx boards.
+
+    The pixis sgmii command depend on the FPGA support on the board, some 85xx
+    boards support SGMII riser card but did not support this command, define
+    CONFIG_PIXIS_SGMII_CMD for those boards which support the sgmii command.
+
+    Not like 8544, 8572 has 4 eTsec so that the other two's pixis bits
+    are not supported by 8544. Therefor, define PIXIS_VSPEED2_MASK and
+    PIXIS_VCFGEN1_MASK in header file for both boards.
+
+    Signed-off-by: Liu Yu <yu.liu@freescale.com>
+
+commit 5e981d683d2363204c76773941c2e9c2044c808f
+Author: Ed Swarthout <Ed.Swarthout@freescale.com>
+Date:	Wed Oct 8 23:38:02 2008 -0500
+
+    Add cpu/8xxx to TAGS_SUBDIRS
+
+    Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
+
+commit e1f7d22b8b52fc08c4d17a6a7db1e664281aed63
+Author: Ed Swarthout <Ed.Swarthout@freescale.com>
+Date:	Thu Oct 9 01:25:55 2008 -0500
+
+    fsl_law clear enable before changing.
+
+    Debug sessions may have left enabled laws.
+    Changing lawbar with an unkown enabled tgtid could cause problems.
+
+    Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
+
+commit 86be510f7b5443e7e937f696bfbe037fdc740b15
+Author: Ed Swarthout <Ed.Swarthout@freescale.com>
+Date:	Thu Oct 9 00:29:27 2008 -0500
+
+    mpc8572 additional end-point mode
+
+    mpc8572 supports all pcie controllers as end-points with cfg_host_agent=0.
+    Include host_agent == 0 decode for end-point determination.
+
+    This is not needed for the ds reference board since pcie3 will be a host
+    in order to connect to the uli chip.  Include it here as a reference for
+    other mpc8572 boards.
+
+    Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
+
+commit 6856b3d0221a838580e6bb06f61425fd7529ba93
+Author: Ed Swarthout <Ed.Swarthout@freescale.com>
+Date:	Wed Oct 8 23:37:59 2008 -0500
+
+    85xx if NUM_CPUS>1, print cpu number
+
+    Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
+
+commit f7fecc3e25050a036c9f50f0d2b85bc3199a96e0
+Author: Ed Swarthout <Ed.Swarthout@freescale.com>
+Date:	Wed Oct 8 23:38:01 2008 -0500
+
+    pixis do not print long help if not configured
+
+    Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
+
+commit 0e17f02a8a78d85225a4d805f6a1ea95a0a460b5
+Author: Andy Fleming <afleming@freescale.com>
+Date:	Tue Oct 7 08:09:50 2008 -0500
+
+    Have u-boot pass stashing parameters into device tree
+
+    Some cores don't support ethernet stashing at all, and some
+    instances have errata.  Adds 3 properties to gianfar nodes
+    which support stashing.  For now, just add this support to
+    85xx SoCs.
+
+    Signed-off-by: Andy Fleming <afleming@freescale.com>
+
+commit c21617fd265b7c126c6e2f2d8a23cdb00d4fade7
+Author: Haiying Wang <Haiying.Wang@freescale.com>
+Date:	Fri Oct 3 12:37:57 2008 -0400
+
+    Add DDR options setting on MPC8641HPCN board
+
+    * Add board specific parameter table to choose correct cpo, clk_adjust,
+    write_data_delay based on board ddr frequency and n_ranks.
+
+    * Set odt_rd_cfg and odt_wr_cfg based on the dimm# and CS#.
+
+    Signed-off-by: James Yang <James.Yang@freescale.com>
+    Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
+
+commit 4ca06607d60d0a6378812ef58fd1eab2a7f77111
+Author: Haiying Wang <Haiying.Wang@freescale.com>
+Date:	Fri Oct 3 12:37:41 2008 -0400
+
+    Add ddr interleaving suppport for MPC8572DS board
+
+    * Add board specific parameter table to choose correct cpo, clk_adjust,
+    write_data_delay, 2T based on board ddr frequency and n_ranks.
+
+    * Set odt_rd_cfg and odt_wr_cfg based on the dimm# and CS#.
+
+    * Set memory controller interleaving mode to bank interleaving, and disable
+    bank(chip select) interleaving mode by default, because the default on-board
+    DDR DIMMs are 2x512MB single-rank.
+
+    * Change CONFIG_ICS307_REFCLK_HZ from 33333333 to 33333000.
+
+    Signed-off-by: James Yang <James.Yang@freescale.com>
+    Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
+
+commit 1f293b417ac6ab8e317ca2b770377ca93edf2370
+Author: Haiying Wang <Haiying.Wang@freescale.com>
+Date:	Fri Oct 3 12:37:26 2008 -0400
+
+    Add debug information for DDR controller registers
+
+    Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
+
+commit c9ffd839b1ada502c86f88edaf1534426b6688ce
+Author: Haiying Wang <Haiying.Wang@freescale.com>
+Date:	Fri Oct 3 12:37:10 2008 -0400
+
+    Check DDR interleaving mode
+
+    * Check DDR interleaving mode from environment by reading memctl_intlv_ctl and
+    ba_intlv_ctl.
+    * Print DDR interleaving mode information
+    * Add doc/README.fsl-ddr to describe the interleaving setting
+
+    Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
+
+commit dfb49108e4f86c2224e1f30124328b0de66ef72e
+Author: Haiying Wang <Haiying.Wang@freescale.com>
+Date:	Fri Oct 3 12:36:55 2008 -0400
+
+    Pass dimm parameters to populate populate controller options
+
+    Because some dimm parameters like n_ranks needs to be used with the board
+    frequency to choose the board parameters like clk_adjust etc. in the
+    board_specific_paramesters table of the board ddr file, we need to pass
+    the dimm parameters to the board file.
+
+    * move ddr dimm parameters header file from /cpu to /include directory.
+    * add ddr dimm parameters to populate board specific options.
+    * Fix fsl_ddr_board_options() for all the 8xxx boards which call this function.
+
+    Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
+
+commit dbbbb3abeff325855cae76e33d69d5665631443f
+Author: Haiying Wang <Haiying.Wang@freescale.com>
+Date:	Fri Oct 3 12:36:39 2008 -0400
+
+    Make DDR interleaving mode work correctly
+
+    Fix some bugs:
+      1. Correctly set intlv_ctl in cs_config.
+      2. Correctly set sa, ea in cs_bnds when bank interleaving mode is enabled.
+      3. Set base_address and total memory for each ddr controller in memory
+	 controller interleaving mode.
+
+    Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
+
+commit 1c9aa76bf9013069e24258f46f4687c9f98a02d6
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Mon Sep 22 23:40:42 2008 -0500
+
+    85xx: Enable interrupt and setexpr commands on Freescale 85xx boards
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 7c0d4a7508d252d2d7c137eeb376814132dda30f
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Mon Sep 22 14:11:11 2008 -0500
+
+    85xx: Improve flash remapping on MPC8572DS & MPC8536DS
+
+    Changing the flash from cacheable to cache-inhibited was taking a significant
+    amount of time due to the fact that we were iterating over the full 256M of
+    flash.  Instead we can just flush the L1 d-cache and invalidate the i-cache.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 54e091d3b603a3332c619199ca83a07e95960da4
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Mon Sep 22 14:11:10 2008 -0500
+
+    85xx: Export invalidate_{i,d}cache and add flush_dcache
+
+    Added the ability for C code to invalidate the i/d-cache's and
+    to flush the d-cache.  This allows us to more efficient change mappings
+    from cache-able to cache-inhibited.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 6250f0f6297c5ba9aecdea6290799a95c5d4b1da
+Author: Heiko Schocher <hs@denx.de>
+Date:	Fri Oct 17 16:11:52 2008 +0200
+
+    mgcoge, mgsuvd: extract more common code
+
+    in ft_blob_update () for both boards was an unneccessary
+    repetition of code, which this patch moves in a common
+    function for this boards.
+
+    Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit 9e299192ca9850cf725456388042a5aa5a6f3ec7
+Author: Heiko Schocher <hs@denx.de>
+Date:	Fri Oct 17 12:15:55 2008 +0200
+
+    mgcoge, mgsuvd: use in_*/out_* accesors
+
+    Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit a21ca95f8b9dca22714952b348e4905ac157b5cd
+Author: Heiko Schocher <hs@denx.de>
+Date:	Fri Oct 17 13:52:51 2008 +0200
+
+    mgsuvd: fix compiler warning when using soft_i2c driver
+
+    Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit cac9cf7875c2a01d63422820ed4732a9bdf5ab7b
+Author: Heiko Schocher <hs@denx.de>
+Date:	Fri Oct 17 12:15:05 2008 +0200
+
+    mgsuvd: fix coding style
+
+    Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit 5f4c3137f4f051787707c548133823f1656eb508
+Author: Heiko Schocher <hs@denx.de>
+Date:	Fri Oct 17 12:13:30 2008 +0200
+
+    mgcoge: Second Flash on CS5 not on CS1
+
+    Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit 76da19df5b8e186d269f29190696bd31fb6c836b
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Thu Oct 16 21:52:08 2008 -0500
+
+    Added arch_lmb_reserve to allow arch specific memory regions protection
+
+    Each architecture has different ways of determine what regions of memory
+    might not be valid to get overwritten when we boot.  This provides a
+    hook to allow them to reserve any regions they care about.	Currently
+    only ppc, m68k and sparc need/use this.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit e02d4a9904c8f36395994c0c81469d552b82f5ea
+Author: Heiko Schocher <hs@denx.de>
+Date:	Thu Oct 16 16:32:35 2008 +0200
+
+    mgcoge: added CONFIG_FIT to support the new u-boot image format
+
+    Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit 6d0f6bcf337c5261c08fabe12982178c2c489d76
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Thu Oct 16 15:01:15 2008 +0200
+
+    rename CFG_ macros to CONFIG_SYS
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 71edc271816ec82cf0550dd6980be2da3cc2ad9e
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Mon Oct 13 14:12:55 2008 -0500
+
+    74xx/7xx/86xx: Rename flush_data_cache to flush_dcache to match 85xx version
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit b799cb4c0eebb0762e91e9653d8b9cc9a98440e3
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Tue Sep 23 10:05:02 2008 -0500
+
+    Expose command table search for sub-commands
+
+    Sub-command can benefit from using the same table and search functions
+    that top level commands have.  Expose this functionality by refactoring
+    find_cmd() and introducing find_cmd_tbl() that sub-command processing
+    can call.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit f7e51b27508446f8cae3927975817137979ad5e8
+Author: Heiko Schocher <hs@denx.de>
+Date:	Wed Oct 15 09:41:33 2008 +0200
+
+    mgsuvd, mgcoge: added BOOTCOUNT feature.
+
+    Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit 8f64da7f83b553889bc08400c97047998382e9d2
+Author: Heiko Schocher <hs@denx.de>
+Date:	Wed Oct 15 09:41:00 2008 +0200
+
+    mgcoge, mgsuvd: added support for the IVM EEprom.
+
+    The EEprom contains some Manufacturerinformation,
+    which are read from u-boot at boot time, and saved
+    in same hush shell variables.
+
+    Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit 81473f67810c4c9b7efaed8dee258ed6bc4c7983
+Author: Heiko Schocher <hs@denx.de>
+Date:	Wed Oct 15 09:40:28 2008 +0200
+
+    hush: add showvar command for hush shell.
+
+    This new command shows the local variables defined in
+    the hush shell:
+
+    => help showvar
+    showvar
+	- print values of all hushshell variables
+    showvar name ...
+	- print value of hushshell variable 'name'
+
+    Also make the set_local_var() and unset_local_var ()
+    no longer static, so it is possible to define local
+    hush shell variables at boot time. If CONFIG_HUSH_INIT_VAR
+    is defined, u-boot calls hush_init_var (), where
+    boardspecific code can define local hush shell
+    variables at boottime.
+
+    Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit 67b23a322848d828a5e45c0567b72762bfde7abf
+Author: Heiko Schocher <hs@denx.de>
+Date:	Wed Oct 15 09:39:47 2008 +0200
+
+    I2C: adding new "i2c bus" Command to the I2C Subsystem.
+
+    With this Command it is possible to add new I2C Busses,
+    which are behind 1 .. n I2C Muxes. Details see README.
+
+    Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit c24853644ddd2dd2e4246b5854a93e6254a14092
+Author: Heiko Schocher <hs@denx.de>
+Date:	Wed Oct 15 09:39:08 2008 +0200
+
+    mgcoge, mgsuvd: add board specific I2C deblocking mechanism.
+
+    As documented in doc/I2C_Edge_Conditions, adding a
+    board specific deblocking mechanism via CFG_I2C_INIT_BOARD
+    for the mgcoge and mgsuvd board.
+
+    This code was originally written by Keymile in association
+    with Anatech and Atmel in 1998. The Code toggels the SCL
+    until the SCA line goes to HIGH (max. 16 times).
+    And after this, a start condition is sent.
+
+    This is another approach to deblock the I2C Bus. The
+    soft I2C driver actually sends 9 clocks with SDA High,
+    and then a stop at the end, to deblock the I2C Bus.
+
+    Maybe we should use the approach from Keymile as
+    the new standard?
+
+    Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit 4ca107effebfbabac1057c39632105dacef95957
+Author: Heiko Schocher <hs@denx.de>
+Date:	Wed Oct 15 09:38:38 2008 +0200
+
+    soft_i2c: Add CFG_I2C_INIT_BOARD option
+
+    This patch adds the option for a boardspecific
+    I2C deblocking mechanism for the soft i2c driver.
+
+    Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit e5e4edd9f1f76210a09c34ee835f6cff60fdbbd1
+Author: Heiko Schocher <hs@denx.de>
+Date:	Wed Oct 15 09:38:07 2008 +0200
+
+    mgcoge, mgsuvd: add DTT (LM75) support.
+
+    Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit 8e442df438ab677057571e3ac01846bff7719bce
+Author: Heiko Schocher <hs@denx.de>
+Date:	Wed Oct 15 09:37:34 2008 +0200
+
+    lm75: Make the LM75 MULTI_BUS compatible.
+
+    Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit 12f1678127c1df2b2878ba93c88948bedc060775
+Author: Heiko Schocher <hs@denx.de>
+Date:	Wed Oct 15 09:37:04 2008 +0200
+
+    lm75: fix Codingstyle issues.
+
+    Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit f2202450c75ba6934b356024101500ddcde6e2a6
+Author: Heiko Schocher <hs@denx.de>
+Date:	Wed Oct 15 09:36:33 2008 +0200
+
+    mgcoge, mgsuvd: added EEprom support.
+
+    Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit 9661bf9d120f760238b2a073b84f2baf05010057
+Author: Heiko Schocher <hs@denx.de>
+Date:	Wed Oct 15 09:36:03 2008 +0200
+
+    mgcoge, mgsuvd: add I2C support.
+
+    Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit 98aed379586a155292efbf3209356836584b601c
+Author: Heiko Schocher <hs@denx.de>
+Date:	Wed Oct 15 09:35:26 2008 +0200
+
+    soft_i2c: prevent compiler warnings if driver does not use CPU Pins.
+
+    This patch fixes the following warnings, when using
+    the soft_i2c driver using no CPU pins on MPC82xx or MPC8xx
+    systems:
+
+    soft_i2c.c: In function 'send_reset':
+    soft_i2c.c:93: warning: unused variable 'immr'
+    soft_i2c.c: In function 'send_start':
+    soft_i2c.c:124: warning: unused variable 'immr'
+    soft_i2c.c: In function 'send_stop':
+    soft_i2c.c:146: warning: unused variable 'immr'
+    soft_i2c.c: In function 'send_ack':
+    soft_i2c.c:171: warning: unused variable 'immr'
+    soft_i2c.c: In function 'write_byte':
+    soft_i2c.c:196: warning: unused variable 'immr'
+    soft_i2c.c: In function 'read_byte':
+    soft_i2c.c:244: warning: unused variable 'immr'
+
+    Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit 799b784aa00cb03a352847ab9f9acdde79b72d21
+Author: Heiko Schocher <hs@denx.de>
+Date:	Wed Oct 15 09:34:45 2008 +0200
+
+    i2c: add CONFIG_I2C_MULTI_BUS for soft_i2c and mpc8260 i2c driver.
+
+    Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit 0809ea2f4340ab2047400c7d3d3047f97987d0fd
+Author: Heiko Schocher <hs@denx.de>
+Date:	Wed Oct 15 09:34:05 2008 +0200
+
+    mgcoge: fix Coding Style issues.
+
+    Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit e43a27c49712203fe8848a17714330623edfb2eb
+Author: Heiko Schocher <hs@denx.de>
+Date:	Wed Oct 15 09:33:30 2008 +0200
+
+    I2C: add new command i2c reset.
+
+    If I2C Bus is blocked (see doc/I2C_Edge_Conditions),
+    it is not possible to get out of this, until the
+    complete Hardware gets a reset. This new commando
+    calls again i2c_init (and that calls i2c_init_board
+    if defined), which will deblock the I2C Bus.
+
+    Signed-off-by: Heiko Schocher <hs@denx.de>
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 86e9cdf8c415c1a9725e9dae5237ba1e7bd9f686
+Author: Heiko Schocher <hs@denx.de>
+Date:	Wed Oct 15 09:32:25 2008 +0200
+
+    mgsuvd, mgcoge: move this 2 boards in one dir.
+
+    There are some more extensions, which are for both boards
+    and some more boards from this manufacturer will follow soon.
+
+    Signed-off-by: Heiko Schocher <hs@denx.de>
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 1c6fe6eac75d695fde677af8330c0dbe75fb6a2b
+Author: Dirk Eibach <eibach@gdsys.de>
+Date:	Wed Oct 8 13:44:27 2008 +0200
+
+    hwmon: Add LM63 support
+
+    This patch adds support for the National LM63 temperature
+    sensor with integrated fan control. It's used on the GDSys
+    Neo board (405EP) which will be submitted later.
+
+    Signed-off-by: Dirk Eibach <eibach@gdsys.de>
+    Acked-by: Stefan Roese <sr@denx.de>
+
+commit 7ba890bf2f2b92831420243c058951aa831119fd
+Author: Kyungmin Park <kmpark@infradead.org>
+Date:	Wed Oct 8 11:01:17 2008 +0900
+
+    Add Red Black Tree support
+
+    Now it's used at UBI module. Of course other modules can use it.
+    If you want to use it, please define CONFIG_RBTREE
+
+    Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
+
+commit fbd85ad65dd9c98f36ed3fb12fe41f381b7d4794
+Author: richardretanubun <richardretanubun@ruggedcom.com>
+Date:	Mon Oct 6 16:10:53 2008 -0400
+
+    CONFIG_EFI_PARTITION: Added support for EFI partition in cmd_ext2fs.c
+
+    Added support for CONFIG_EFI_PARTITION to ext2 commands.
+    Signed-off-by: Richard Retanubun <RichardRetanubun@RugggedCom.com>
+
+commit 07f3d789b9beb7ce3278c974f4d5c8f51b6ab567
+Author: richardretanubun <richardretanubun@ruggedcom.com>
+Date:	Fri Sep 26 11:13:22 2008 -0400
+
+    Add support for CONFIG_EFI_PARTITION (GUID Partition Table)
+
+    The GUID (Globally Unique Identifier) Partition Table (GPT) is a part
+    of EFI. See http://en.wikipedia.org/wiki/GUID_Partition_Table
+
+    Based on linux/fs/partitions/efi.[ch]
+
+    Signed-off-by: Richard Retanubun <RichardRetanubun@RugggedCom.com>
+
+commit fbc87dc0546dff709b38f358e2c5d5e39c4ca374
+Author: Bartlomiej Sieka <tur@semihalf.com>
+Date:	Wed Oct 1 15:26:32 2008 +0200
+
+    FIT: output image load address for type 'firmware', fix message while there
+
+    Now that the auto-update feature uses the 'firmware' type for updates, it is
+    useful to inspect the load address of such images.
+
+    Signed-off-by: Bartlomiej Sieka <tur@semihalf.com>
+
+commit 4bae90904b69ce3deb9f7c334ef12ed74e18a275
+Author: Bartlomiej Sieka <tur@semihalf.com>
+Date:	Wed Oct 1 15:26:31 2008 +0200
+
+    Automatic software update from TFTP server
+
+    The auto-update feature allows to automatically download software updates
+    from a TFTP server and store them in Flash memory during boot. Updates are
+    contained in a FIT file and protected with SHA-1 checksum.
+
+    More detailed description can be found in doc/README.update.
+
+    Signed-off-by: Rafal Czubak <rcz@semihalf.com>
+    Signed-off-by: Bartlomiej Sieka <tur@semihalf.com>
+
+commit 3f0cf51dabacc2724731c5079a60ea989103bb8f
+Author: Bartlomiej Sieka <tur@semihalf.com>
+Date:	Wed Oct 1 15:26:27 2008 +0200
+
+    flash: factor out adjusting of Flash address to the end of sector
+
+    The upcoming automatic update feature needs the ability to adjust an
+    address within Flash to the end of its respective sector. Factor out
+    this functionality to a new function flash_sect_roundb().
+
+    Signed-off-by: Rafal Czubak <rcz@semihalf.com>
+    Signed-off-by: Bartlomiej Sieka <tur@semihalf.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit e83cc06375ac2bea0830c6ed0f9d8fdc3c1b27d5
+Author: Bartlomiej Sieka <tur@semihalf.com>
+Date:	Wed Oct 1 15:26:29 2008 +0200
+
+    net: Make TFTP server timeout configurable
+
+    There are two aspects of a TFTP transfer involving timeouts:
+    1. timeout waiting for initial server reply after sending RRQ
+    2. timeouts while transferring actual data from the server
+
+    Since the upcoming auto-update feature attempts a TFTP download during each
+    boot, it is undesirable to have a long delay when the TFTP server is not
+    available. Thus, this commit makes the server timeout (1.) configurable by two
+    global variables:
+
+    TftpRRQTimeoutMSecs
+    TftpRRQTimeoutCountMax
+
+    TftpRRQTimeoutMSecs overrides default timeout when trying to connect to a TFTP
+    server, TftpRRQTimeoutCountMax overrides default number of connection retries.
+    The total delay when trying to download a file from a non-existing TFTP server
+    is TftpRRQTimeoutMSecs x TftpRRQTimeoutCountMax milliseconds.
+
+    Timeouts during file transfers (2.) are unaffected.
+
+    Signed-off-by: Rafal Czubak <rcz@semihalf.com>
+    Signed-off-by: Bartlomiej Sieka <tur@semihalf.com>
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 49f3bdbba8071f56d950a9498b6cdb998b35340a
+Author: Bartlomiej Sieka <tur@semihalf.com>
+Date:	Wed Oct 1 15:26:28 2008 +0200
+
+    net: express the first argument to NetSetTimeout() in milliseconds
+
+    Enforce millisecond semantics of the first argument to NetSetTimeout() --
+    the change is transparent for well-behaving boards (CFG_HZ == 1000 and
+    get_timer() countiing in milliseconds).
+
+    Rationale for this patch is to enable millisecond granularity for
+    network-related timeouts, which is needed for the upcoming automatic
+    software update feature.
+
+    Summary of changes:
+    - do not scale the first argument to NetSetTimeout() by CFG_HZ
+    - change timeout values used in the networking code to milliseconds
+
+    Signed-off-by: Rafal Czubak <rcz@semihalf.com>
+    Signed-off-by: Bartlomiej Sieka <tur@semihalf.com>
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit c68a05feeb88de9fcf158e67ff6423c4cc988f88
+Author: richardretanubun <richardretanubun@ruggedcom.com>
+Date:	Mon Sep 29 18:28:23 2008 -0400
+
+    Adds two more ethernet interface to 83xx
+
+    Added as a convenience for other platforms that uses MPC8360 (has 8 UCC).
+    Six eth interface is chosen because the platform I am using combines
+    UCC1&2 and UCC3&4 as 1000 Eth and the other four UCCs as 10/100 Eth.
+
+    Signed-off-by: Richard Retanubun <RichardRetanubun@RugggedCom.com>
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 41410eee472b0f42e03a77f961bbc55ef58f3c01
+Author: Haiying Wang <Haiying.Wang@freescale.com>
+Date:	Wed Sep 24 11:42:12 2008 -0500
+
+    Change UEC PHY interface to RGMII on MPC8568MDS
+
+    Change UEC phy interface from GMII to RGMII on MPC8568MDS board
+
+    Because on MPC8568MDS, GMII interface is only recommended for 1000Mbps speed,
+    but RGMII interface can work at 10/100/1000Mbps, and RGMII interface works more stable.
+
+    Now both UEC1 and UEC2 can work properly under u-boot.
+
+    It is also in consistent with the kernel setting for 8568 UEC phy interface.
+
+    Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit b59b16ca24bc7e77ec113021a6d77b9b32fcf192
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Sat Oct 18 21:30:31 2008 +0200
+
+    Prepare v2008.10 release: update CHANGELOG & Makefile
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit f7a35a60cf45491871a5c28e9ad24db005487857
+Author: Heiko Schocher <hs@denx.de>
+Date:	Fri Oct 17 18:24:06 2008 +0200
+
+    mgcoge: add redundant environment sector
+
+    Signed-off-by: Heiko Schocher <hs@denx.de>
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit c2537ee85954af9d036b18b644f3e18d837bf4a5
+Author: Heiko Schocher <hs@denx.de>
+Date:	Fri Oct 17 18:23:27 2008 +0200
+
+    mgsuvd: update size of environment
+
+    Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit fa7b1c07e9371aea8f87ee6d3c2ea5564bd8cc8d
+Author: Lepcha Suchit <Suchit.Lepcha@freescale.com>
+Date:	Thu Oct 16 13:38:00 2008 -0500
+
+    83xx NAND boot: wait for LTESR[CC]
+
+    At least some revisions of the 8313, and possibly other chips, do not
+    wait for all pages of the initial 4K NAND region to be loaded before
+    beginning execution; thus, we wait for it before branching out of the
+    first NAND page.
+
+    This fixes warm reset problems when booting from NAND on 8313erdb.
+
+    Signed-off-by: Scott Wood <scottwood@freescale.com>
+    Acked-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit bf29e0ea0af03d593c64614136acc723a7a022a2
+Author: Yuri Tikhonov <yur@emcraft.com>
+Date:	Fri Oct 17 12:54:18 2008 +0200
+
+    ppc4xx: PPC44x MQ initialization
+
+    Set the MQ Read Passing & MCIF Cycle limits to the recommended by AMCC
+    values. This fixes the occasional 440SPe hard locking issues when the 440SPe's
+    dedicated DMA engines are used (e.g. by the h/w accelerated RAID driver).
+
+    Previously the appropriate initialization had been made in Linux, by the
+    ppc440spe ADMA driver, which is wrong because modifying the MQ configuration
+    registers after normal operation has begun is not supported and could
+    have unpredictable results.
+
+    Comment from Stefan: This patch doesn't change the resulting value of the
+    MQ registers. It explicitly sets/clears all bits to the desired state which
+    better documents the resulting register value instead of relying on pre-set
+    default values.
+
+    Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit ec081c2c190148b374e86a795fb6b1c49caeb549
+Author: Stefan Roese <sr@denx.de>
+Date:	Fri Oct 17 12:51:46 2008 +0200
+
+    ppc4xx: PPC44x MQ initialization
+
+    Set the MQ Read Passing & MCIF Cycle limits to the recommended by AMCC
+    values. This fixes the occasional 440SPe hard locking issues when the 440SPe's
+    dedicated DMA engines are used (e.g. by the h/w accelerated RAID driver).
+
+    Previously the appropriate initialization had been made in Linux, by the
+    ppc440spe ADMA driver, which is wrong because modifying the MQ configuration
+    registers after normal operation has begun is not supported and could
+    have unpredictable results.
+
+    Comment from Stefan: This patch doesn't change the resulting value of the
+    MQ registers. It explicitly sets/clears all bits to the desired state which
+    better documents the resulting register value instead of relying on pre-set
+    default values.
+
+    Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit f7d190b1c0b3ab7fc53074ad2862f7de99de37ff
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Thu Oct 16 21:58:50 2008 -0500
+
+    85xx: Using proper I2C source clock divider for MPC8544
+
+    The MPC8544 RM incorrect shows the SEC_CFG bit in PORDEVSR2 as being
+    bit 26, instead it should be bit 28.  This caused in incorrect
+    interpretation of the i2c_clk which is the same as the SEC clk on
+    MPC8544.  The SEC clk is controlled by cfg_sec_freq that is reported
+    in PORDEVSR2.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 42653b826adb319a1df06e24ef26096b2a5d9d2a
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Thu Oct 16 21:58:49 2008 -0500
+
+    Revert "85xx: Using proper I2C source clock divider for MPC8544"
+
+    This reverts commit dffd2446fb041f38ef034b0fcf41e51e5e489159.
+
+    The fix introduced by this patch is not correct.  The problem is
+    that the documentation is not correct for the MPC8544 with regards
+    to which bit in PORDEVSR2 is for the SEC_CFG.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 2179c4766bffeece98e5e92040629a96c97e230c
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Wed Oct 15 10:19:41 2008 -0500
+
+    85xx: Fix compile warning
+
+    mpc8536ds.c: In function 'is_sata_supported':
+    mpc8536ds.c:614: warning: unused variable 'devdisr'
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 9029b68f3f81b3013044f167ea025e836e6c8c0e
+Author: Jason Jin <Jason.jin@freescale.com>
+Date:	Wed Oct 15 10:40:24 2008 +0800
+
+    Fix the function conflict in x86emu when DEBUG is on
+
+    The function parse_line() in common/main.c was exposed globally by commit
+    6636b62a6efc7f14e6e788788631ae7a7fca4537, Result in conflict with the same
+    name funciton in drivers/bios_emulator/x86emu/debug.c when define the DEBUG.
+    This patch fix this by renaming the function in the debug.c file.
+
+    Signed-off-by: Jason Jin <Jason.jin@freescale.com>
+
+commit b4dbacf69a669a17487054552fc2761149dd6767
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Wed Oct 15 15:50:45 2008 +0200
+
+    Coding Style cleanup, update CHANGELOG, prepare 2008.10-rc3
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 374b9038293d01d8744a46af9b7854a6fd99b228
+Author: Heiko Schocher <hs@denx.de>
+Date:	Wed Oct 15 09:51:19 2008 +0200
+
+    Fix compiler warning in lib_ppc/board.c
+
+    Fix compiler warning introduced by commit 0f8cbc18
+
+    Signed-off-by: Heiko Schocher <hs@denx.de>
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 9724555755a6f1066636481b41f7094e0ce93a69
+Author: Selvamuthukumar <selva.muthukumar@e-coninfotech.com>
+Date:	Thu Oct 9 10:29:14 2008 +0530
+
+    mpc83xx: wait till UPM completes the write to array
+
+    Reference manual states that MxMR[MAD] increment is the indication
+    of write to UPM array is complete. Honour that. Also, make the dummy
+    write explicit.
+
+    also fix the comment.
+
+    Signed-off-by: Selvamuthukumar <selva.muthukumar@e-coninfotech.com>
+    Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit 03e2dbb18e858e2f7a6aaa437f290f3690d02d51
+Author: Selvamuthukumar <selva.muthukumar@e-coninfotech.com>
+Date:	Wed Oct 8 18:12:20 2008 -0500
+
+    Remove unwanted ';' at end of define.
+
+    Currently this is not creating any problem. But it will result
+    in compilation error when used as below.
+
+    printf("CFG_SDRAM_CFG2 - %08x\n", CFG_SDRAM_CFG2);
+
+    Signed-off-by: Selvamuthukumar <selva.muthukumar@e-coninfotech.com>
+
+    continuation of the theme based on git grep "^#define CFG_.*;$" include/
+
+    Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit b2934a56650e9a6c54432f9ce6dc36757967385e
+Author: Hugo Villeneuve <hugo.villeneuve@lyrtech.com>
+Date:	Mon Oct 6 10:53:59 2008 -0400
+
+    ARM DaVinci: Add maintainer information for SFFSDR board.
+
+    Signed-off-by: Hugo Villeneuve <hugo.villeneuve@lyrtech.com>
+
+commit 12c6670f873ed632c264a6f3e8bf1297d5c3ddbc
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Sat Oct 4 19:26:16 2008 +0200
+
+    api: fix type mismatch
+
+    This patch fixes a type mismatch and thus removes a compiler
+    warning when compiling with CONFIG_API on powerpc.
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+
+commit 9bc2e4eee3bcb8e63847d7a733e0c607807d6141
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date:	Wed Oct 1 12:25:04 2008 -0500
+
+    cmd_i2c: Fix help for CONFIG_I2C_CMD_TREE && !CONFIG_I2C_MULTI_BUS
+
+    Original code displayed:
+     => help i2c
+     i2c i2c speed [speed] - show or set I2C bus speed
+     i2c md chip address[.0, .1, .2] [# of objects] - read from I2C device
+     ...
+
+    Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+
+commit a0b1b610e980e253d4c2519ee15bd0937c3f8be1
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Tue Oct 14 22:13:41 2008 +0200
+
+    Update CHANGELOG
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 0f8cbc1829d9c7d9616fd29b366a99d037facdcd
+Author: Jason Jin <Jason.jin@freescale.com>
+Date:	Fri Oct 10 11:41:01 2008 +0800
+
+    Do not init SATA when disabled on 8536DS.
+
+    SGMII and SATA share the serdes on MPC8536 CPU, When SATA disabled and the
+    driver still try to access the SATA registers, the cpu will hangup.
+    This patch try to fix this by reading the serdes status before the SATA
+    initialize.
+
+    Signed-off-by: Jason Jin <Jason.jin@freescale.com>
+    Acked-by: Andy Fleming <afleming@freescale.com>
+
+commit 9dbc366744960013965fce8851035b6141f3b3ae
+Author: Remy Bohmer <linux@bohmer.net>
+Date:	Fri Oct 10 10:23:22 2008 +0200
+
+    The PIPE_INTERRUPT flag is used wrong
+
+    At a lot of places in the code the PIPE_INTERRUPT flags and friends
+    are used wrong. The wrong bits are compared to this flag resulting
+    in wrong conditions. Also there are macros that should be used for
+    PIPE_* flags.
+    This patch tries to fix them all, however, I was not able to test the
+    changes, because I do not have any of these boards.
+
+    Review required!
+
+    Signed-off-by: Remy Bohmer <linux@bohmer.net>
+    Signed-off-by: Markus Klotzbuecher <mk@denx.de>
+
+commit 48867208444cb2a82e2af9c3249e90b7ed4a1751
+Author: Remy Bohmer <linux@bohmer.net>
+Date:	Fri Oct 10 10:23:21 2008 +0200
+
+    fix USB initialisation procedure
+
+    The max packet size is encoded as 0,1,2,3 for 8,16,32,64 bytes.
+    At some places directly 8,16,32,64 was used instead of the encoded
+    value. Made a enum for the options to make this more clear and to help
+    preventing similar errors in the future.
+
+    After fixing this bug it became clear that another bug existed where
+    the 'pipe' is and-ed with PIPE_* flags, where it should have been
+    'usb_pipetype(pipe)', or even better usb_pipeint(pipe).
+
+    Also removed the triple 'get_device_descriptor' sequence, it has no use,
+    and Windows nor Linux behaves that way.
+    There is also a poll going on with a timeout when usb_control_msg() fails.
+    However, the poll is useless, because the flag will never be set on a error,
+    because there is no code that runs in a parallel that can set this flag.
+    Changed this to something more logical.
+
+    Tested on AT91SAM9261ek and compared the flow on the USB bus to what
+    Linux is doing. There is no difference anymore in the early initialisation
+    sequence.
+
+    Signed-off-by: Remy Bohmer <linux@bohmer.net>
+    Signed-off-by: Markus Klotzbuecher <mk@denx.de>
+
+commit ec4d8c1c1d94a790c1473ae8aace282b817c3123
+Author: Nikita V. Youshchenko <yoush@cs.msu.su>
+Date:	Fri Oct 3 00:03:55 2008 +0400
+
+    fsl_diu: fix alignment error that caused malloc corruption
+
+    When aligning malloc()ed screen_base, invalid offset was added.
+    This not only caused misaligned result (which did not cause hardware
+    misbehaviour), but - worse - caused screen_base + smem_len to
+    be out of malloc()ed space, which in turn caused breakage of
+    futher malloc()/free() operation.
+
+    This patch fixes screen_base alignment.
+
+    Also this patch makes memset() that cleans framebuffer to be executed
+    on first initialization of diu, not only on re-initialization. It looks
+    correct to clean the framebuffer instead of displaying random garbage;
+    I believe that was disabled only because that memset caused breakage
+    of malloc/free described above - which no longer happens with the fix
+    described above.
+
+    Signed-off-by: Nikita V. Youshchenko <yoush@debian.org>
+
+commit 3d0ea3110f3431b6c2aee882784f39f97b20bce9
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Wed Sep 24 10:29:37 2008 +0200
+
+    api: Fix building with CONFIG_API
+
+    This patch fixes building with CONFIG_API and CONFIG_USB_STORAGE.
+
+    USB_MAX_STOR_DEV is defined in include/usb.h, but
+    needed in api/api_storage.c.
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+
+commit abbb90666d5ef2f500ebbedbb80ff60adc56b043
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date:	Tue Sep 23 12:39:40 2008 -0500
+
+    Remove unused CFG_EEPROM_PAGE_WRITE_ENABLE references
+
+    Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+
+commit 81e612014c40c922ec35488d17c504d4e9286f06
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date:	Tue Sep 23 12:38:42 2008 -0500
+
+    Remove CFG_EEPROM_PAGE* dependencies for temperature sensors
+
+    The checks for CFG_EEPROM_PAGE_WRITE_ENABLE and
+    CFG_EEPROM_PAGE_WRITE_BITS in various temperature
+    sensor drivers are not necessary
+
+    Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+
+commit c46980f6d2135ade345dadc1fb1f1f4c8bbf255a
+Author: Mike Frysinger <vapier@gentoo.org>
+Date:	Tue Oct 14 07:04:38 2008 -0400
+
+    cmd_spi: remove broken signed casting for display
+
+    Since we're working with unsigned data, you can't apply a signed pointer
+    cast and then attempt to print the result.	Otherwise you get wrong output
+    when the sign bit is set like "0xFF" incorrectly extended to "0xFFFFFFFF".
+
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit d5fd0b49210c941de8a1fce3947ace92243ab5ca
+Author: Mike Frysinger <vapier@gentoo.org>
+Date:	Tue Oct 14 07:05:24 2008 -0400
+
+    strings cmd: drop old CONFIG_CFG_STRINGS define
+
+    We don't need CONFIG_CFG_STRINGS anymore now that we have the define
+    CONFIG_CMD_STRINGS and Makefile control.
+
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit fecb5ade3b37f62981f2b05b621005850173aaa9
+Author: Jason Jin <Jason.jin@freescale.com>
+Date:	Fri Sep 19 17:32:49 2008 +0800
+
+    Fix the NAND size overflow issue.
+
+    When the total size of all NAND devices exceeds 4 GiB, the size  will
+    overflow. This patch tries to fix this.
+
+    Note that we still have a problem when a single NAND device is bigger
+    than 4 GiB: then the overflow would actually happen earlier, i. e.
+    when storing the size in nand_info[].size, as nand_info[].size is an
+    "u_int32_t".
+
+    Signed-off-by: Jason Jin <Jason.jin@freescale.com>
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 30f574717277238b9014b8136c90eea77196490f
+Author: Louis Su <louis@asix.com.tw>
+Date:	Wed Jul 9 11:01:37 2008 +0800
+
+    AX88180: new gigabit network driver
+
+    Signed-off-by: Louis Su <louis@asix.com.tw>
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit c9d6b6925344740ca1db2f8a6bab7921ff820de3
+Author: Andre Schwarz <andre.schwarz@matrix-vision.de>
+Date:	Tue Aug 19 16:07:03 2008 +0200
+
+    enable 10/100M at VSC8601 at tsec driver
+
+    Currently VSC8601 doesn't link with 10/100M partners if the
+    EEPROM/Strapping is not set up.
+    Setting the auto-neg register fixes this.
+
+    Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de>
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 702c85b0e876d587c11acdbb55738ee52acd54f4
+Author: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+Date:	Tue Sep 30 15:02:53 2008 +0900
+
+    net: ne2000: Divided a function of NE2000 driver
+
+    get_prom function was used __attriute__ , but it is not enable.
+    ax88796.o does not do link besides ne2000.o. When ld is carried
+    out, get_prom function of ax88796.c is ignored.
+    This problem is a thing by specifications of ld.
+    I checked and test this patch on SuperH and MIPS.
+
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 05c7e9070fe4d751e029fd9524bfbbc93cbb1393
+Author: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+Date:	Tue Oct 14 11:10:59 2008 +0900
+
+    sh: rsk7203: Add smc911x driver support to board config file
+
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit cae6f909baf86357b3c0bd01acfc414348c4d175
+Author: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+Date:	Thu Oct 9 13:54:33 2008 +0900
+
+    sh: Fix cannot execute a stand-alone application
+
+    Address calculated in EXPORT_FUNC in SuperH was wrong, I revised it.
+
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit 6df0efd5c86ca1689deeb2738b46b7d83ce228ef
+Author: Ed Swarthout <Ed.Swarthout@freescale.com>
+Date:	Wed Oct 8 23:38:00 2008 -0500
+
+    fsl_pci_init do not scan bus when configured as an end-point
+
+    Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
+    Acked-by: Andy Fleming <afleming@freescale.com>
+
+commit 6f099bbac1ba5dfb46ee7ad29dc53713f0501ba5
+Author: Hugo Villeneuve <hugo.villeneuve@lyrtech.com>
+Date:	Tue Sep 16 17:07:53 2008 -0400
+
+    ARM DaVinci: Remove redundant setting of GD_FLG_RELOC for sffsdr board.
+
+    This is no longer necessary now that the GD_FLG_RELOC flag is set for
+    all ARM boards.
+
+    Signed-off-by: Hugo Villeneuve <hugo.villeneuve@lyrtech.com>
+
+commit d977a57356657ba241256231efca32828a5822f9
+Author: Luigi 'Comio' Mantellini <luigi.mantellini@idf-hit.com>
+Date:	Sat Sep 13 10:04:32 2008 +0200
+
+    Fix lzma uncompress call (image_start wrongly used instead image_len)
+
+    Signed-off-by: Luigi 'Comio' Mantellini <luigi.mantellini@idf-hit.com>
+
+commit 392438406041415fe64ab8748ec5ab5ad01d1cf7
+Author: Nick Spence <nick.spence@freescale.com>
+Date:	Thu Aug 28 14:09:15 2008 -0700
+
+    mpc86xx: use r4 instead of r2 in lock_ram_in_cache and unlock_ram_in_cache
+
+    This is needed in unlock_ram_in_cache() because it is called from C and
+    will corrupt the small data area anchor that is kept in R2.
+
+    lock_ram_in_cache() is modified similarly as good coding practice, but
+    is not called from C.
+
+    Signed-off-by: Nick Spence <nick.spence@freescale.com>
+
+commit 5c7cbcd34d0ee566875a4fd0f2a3e5a62bba921c
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Tue Aug 19 15:05:34 2008 -0500
+
+    86xx: remove redudant code with lib_ppc/interrupts.c
+
+    For some reason we duplicated the majority of code in lib_ppc/interrupts.c
+    Not know how that happened, but there is no good reason for it.
+
+    Use the interrupt_init_cpu() and timer_interrupt_cpu() since its why
+    they exist.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 0d01f66d235118515b5086b88f82498bc0695d6a
+Author: Ed Swarthout <Ed.Swarthout@freescale.com>
+Date:	Thu Oct 9 01:26:36 2008 -0500
+
+    CFI: cfi_flash write fix for AMD legacy
+
+    The flash_unlock_seq requires a sector for AMD_LEGACY.
+    Fix a retcode check typeo.
+
+    Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 542b385a620a1783454a00424930e51895f45073
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Tue Oct 7 13:13:10 2008 +0200
+
+    ppc4xx: Fix USB 2.0 phy reset sequence
+
+    This patch fixes USB 2.0 communication issues on some DU440 boards.
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit df8c1ce11114c2260dedb5547281945f7db8fa5c
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Tue Oct 7 13:13:09 2008 +0200
+
+    ppc4xx: Add strapping mode for 667MHz CPU frequency on DU440 board
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 6a133d6a00b1fc7b9257cd5925d8cb67f75ecda2
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Tue Oct 7 13:13:08 2008 +0200
+
+    ppc4xx: Fix DU440 GPIO configuration
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 35dd025c70fcc4389317db2f2a9d14795172137d
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Tue Oct 7 13:13:07 2008 +0200
+
+    ppc4xx: Update DU440 config
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit f3bf9273939ffe1a60a32a2eef909097f15df56b
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Wed Oct 8 15:36:39 2008 -0500
+
+    MPC8572DS: Fix compile warnings
+
+    Commit 445a7b38308eb05b41de74165b20855db58c7ee5 introduced the following
+    compile warnings:
+
+    cmd_i2c.c:112: warning: missing braces around initializer
+    cmd_i2c.c:112: warning: (near initialization for 'i2c_no_probes[0]')
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit dffd2446fb041f38ef034b0fcf41e51e5e489159
+Author: Wolfgang Grandegger <wg@grandegger.com>
+Date:	Tue Sep 30 10:55:57 2008 +0200
+
+    85xx: Using proper I2C source clock divider for MPC8544
+
+    Measurements with our MPC8544 board showed that the I2C bus frequency
+    is wrong by a factor of 1.5. Obviously, the interpretation of the
+    MPC85xx_PORDEVSR2_SEC_CFG bit of the cfg_sec_freq register is not
+    correct. There seems to be an error in the 8544 RM.
+
+    Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
+
+commit e46c7bfb8bc3c304cedd20f7a365d6e78d7eaf17
+Author: Rafal Czubak <rcz@semihalf.com>
+Date:	Wed Oct 8 13:41:30 2008 +0200
+
+    FSL: Fix get_cpu_board_revision() return value.
+
+    get_cpu_board_revision() returned board revision based on information stored
+    in global static struct eeprom. It should instead use one from local struct
+    board_eeprom, to which the data is actually read from EEPROM. The bug led to
+    system hang after printing L1 cache information on U-Boot startup. The problem
+    was observed on MPC8555CDS system and possibly affects other Freescale MPC85xx
+    boards using CFG_I2C_EEPROM_CCID.
+
+    The change has been successfully tested on MPC8555CDS system.
+
+    Signed-off-by: Rafal Czubak <rcz@semihalf.com>
+
+commit 747f316cca484ed627a97dd3391febabce384186
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Tue Sep 30 20:08:49 2008 +0200
+
+    update uImage FIT multi documentation
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 77a0355f60b801f232ce0a5bfbe95331fa3b6bc0
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Tue Sep 30 20:08:36 2008 +0200
+
+    move README.imx31 to doc/ and merge with README.mx31
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 1ed7a7f0f571b13d46530f8f8b9aff3957f15a96
+Author: Guennadi Liakhovetski <lg@denx.de>
+Date:	Thu Sep 25 20:54:37 2008 +0200
+
+    i.MX31: switch to CFG_HZ=1000
+
+    Switch to the standard CFG_HZ=1000 value, while at it, minor white-space
+    cleanup, remove CFG_CLKS_IN_HZ from config-headers. Tested on mx31ads,
+    provides 2% or 0.4% precision depending on the
+    CONFIG_MX31_TIMER_HIGH_PRECISION flag. Measured with stop-watch on 100s
+    boot-delay.
+
+    Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
+
+commit f41b144c11341b571eab7dcef6c4b8e03c92d2b2
+Author: gnusercn <gnusercn@gmail.com>
+Date:	Wed Oct 8 18:58:58 2008 +0200
+
+    Fix bug: in arch-arm, env_get_char dose not work fine
+
+    due to the arm implementation which supposed that U-Boot is in RAM
+    when we jump to start_armboot
+
+    Signed-off-by: gnusercn <gnusercn@gmail.com>
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit f8a00dea841d5d75de1f8e8107e90ee1beeddf5f
+Author: Adam Graham <agraham@amcc.com>
+Date:	Mon Oct 6 10:16:13 2008 -0700
+
+    ppc4xx: Reset and relock memory DLL after SDRAM_CLKTR change
+
+    After changing SDRAM_CLKTR phase value rerun the memory preload
+    initialization sequence (INITPLR) to reset and relock the memory
+    DLL. Changing the SDRAM_CLKTR memory clock phase coarse timing
+    adjustment effects the phase relationship of the internal, to the
+    PPC chip, and external, to the PPC chip, versions of MEMCLK_OUT.
+
+    Signed-off-by: Adam Graham <agraham@amcc.com>
+    Signed-off-by: Victor Gallardo <vgallardo@amcc.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 5297246bbaa9943c0da1ec2e717b72e4ab6b830e
+Author: Haiying Wang <Haiying.Wang@freescale.com>
+Date:	Fri Oct 3 11:48:03 2008 -0400
+
+    Remove redundant #define for MPC8536DS
+
+    Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
+
+commit 445a7b38308eb05b41de74165b20855db58c7ee5
+Author: Haiying Wang <Haiying.Wang@freescale.com>
+Date:	Fri Oct 3 11:47:30 2008 -0400
+
+    Add ID EEPROM support for MPC8572DS
+
+    The ID EEPROM on MPC8572DS board locates on I2C bus 1. Its the storage for
+    system information like mac addresses etc. This patch enables it.
+
+    Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
+
+commit 1f3ba317a5c5f3a7aabf580fddc211f4bb5a4540
+Author: Haiying Wang <Haiying.Wang@freescale.com>
+Date:	Fri Oct 3 11:46:59 2008 -0400
+
+    Minor fixes for I2C address on MPC8572DS
+
+    MPC8572DS has two i2c buses. This patch moves the DDR SPD_EEPROM to i2c bus 1
+    according to the board spec, and adds the 2nd i2c bus offset.
+
+    Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
+
+commit c0391111c33c22fabeddf8f4ca801ec7645b4f5c
+Author: Jason Jin <Jason.jin@freescale.com>
+Date:	Sat Sep 27 14:40:57 2008 +0800
+
+    Fix the incorrect DDR clk freq reporting on 8536DS
+
+    On 8536DS board, When the DDR clk is set async mode(SW3[6:8] != 111),
+    The display is still sync mode DDR freq. This patch try to fix
+    this. The display DDR freq is now the actual freq in both
+    sync and async mode.
+
+    Signed-off-by: Jason Jin <Jason.jin@freescale.com>
+
+commit bac6a1d1fa1cd80aa57881fa9c2152b853cd0ed4
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Tue Oct 7 10:28:46 2008 -0500
+
+    85xx: Remove setting of *cache-line-size in device trees
+
+    ePAPR says if the *cache-block-size is the same as *cache-line-size
+    than we don't need the *cache-line-size property.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit cd3cb0d9269d155276b00207e3816a9347fd1c92
+Author: Gerald Van Baren <vanbaren@cideas.com>
+Date:	Sat Oct 4 07:56:06 2008 -0400
+
+    libfdt: Fix error in documentation for fdt_get_alias_namelen()
+
+    Oops, screwed up the function name in the documenting comment for this
+    function.  Trivial correction in this patch.
+
+    Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
+    Acked-by: Gerald Van Baren <vanbaren@cideas.com>
+
+commit 9a6cf73a88ddab2e1ac39088f2806177982cc62c
+Author: David Gibson <david@gibson.dropbear.id.au>
+Date:	Wed Aug 20 16:55:14 2008 +1000
+
+    libfdt: Add function to explicitly expand aliases
+
+    Kumar has already added alias expansion to fdt_path_offset().
+    However, in some circumstances it may be convenient for the user of
+    libfdt to explicitly get the string expansion of an alias.	This patch
+    adds a function to do this, fdt_get_alias(), and uses it to implement
+    fdt_path_offset().
+
+    Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
+
+commit 2215987e100d2a841ae6d48a7cc9bb83fcf22737
+Author: Mike Frysinger <vapier@gentoo.org>
+Date:	Thu Oct 2 01:55:38 2008 -0400
+
+    cfi_flash: do not reset flash when probe fails
+
+    The CFI flash driver starts at flash_init() which calls down into
+    flash_get_size().  This starts by calling flash_detect_cfi().  If said
+    function fails, flash_get_size() finishes by attempting to reset the
+    flash.  Unfortunately, it does this with an info->portwidth set to 0x10
+    which filters down into flash_make_cmd() and that happily smashes the
+    stack by sticking info->portwidth bytes into a cfiword_t variable that
+    lives on the stack.  On a 64bit system you probably won't notice, but
+    killing the last 8 bytes on a 32bit system usually leads to a corrupt
+    return address.  Which is what happens on a Blackfin system.
+
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 3e38577208e4256956bc33bb8bcd0a6b6fab55c3
+Author: Stefan Roese <sr@denx.de>
+Date:	Fri Sep 26 17:03:26 2008 +0200
+
+    fdt: Overwrite /chosen node in bootm if it already exists in the dtb
+
+    Set force parameter in fdt_chosen() call in do_bootm_linux() call.
+    Without this, the chosen node is not overwritten if it already
+    exists.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 741a6d010d09b5bafca8e4cdfb6b2f8a2c07994d
+Author: Jon Loeliger <jdl@freescale.com>
+Date:	Thu Sep 25 11:02:17 2008 -0500
+
+    Fix an overflow case in fdt_offset_ptr() detected by GCC 4.3.
+
+    Using Gcc 4.3 detected this problem:
+
+	../dtc/libfdt/fdt.c: In function 'fdt_next_tag':
+	../dtc/libfdt/fdt.c:82: error: assuming signed overflow does not
+	occur when assuming that (X + c) < X is always false
+
+    To fix the problem, treat the offset as an unsigned int.
+
+    The problem report and proposed fix were provided
+    by Steve Papacharalambous <stevep@freescale.com>.
+
+    Signed-off-by: Jon Loeliger <jdl@freescale.com>
+
+commit bbdbc7cb3abefda5bd998edbcf0508fe6256327d
+Author: David Gibson <david@gibson.dropbear.id.au>
+Date:	Fri Aug 29 14:19:13 2008 +1000
+
+    libfdt: Fix bugs in fdt_get_path()
+
+    The current implementation of fdt_get_path() has a couple of bugs,
+    fixed by this patch.
+
+    First, contrary to its documentation, on success it returns the length
+    of the node's path, rather than 0.	The testcase is correspondingly
+    wrong, and the patch fixes this as well.
+
+    Second, in some circumstances, it will return -FDT_ERR_BADOFFSET
+    instead of -FDT_ERR_NOSPACE when given insufficient buffer space.
+    Specifically this happens when there is insufficient space even to
+    hold the path's second last component.  This behaviour is corrected,
+    and the testcase updated to check it.
+
+    Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
+
+commit 33af3e6656e84660d397b5dd95abab2dccc36f83
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Wed Oct 1 12:34:58 2008 +0200
+
+    TQM5200: enable support for ATAPI devices
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit d13ff2358ff8c384f52eaf46f5d60258acf96ea6
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Mon Sep 15 05:48:25 2008 +0200
+
+    Revert "ARM: set GD_FLG_RELOC for boards skipping relocation to RAM"
+
+    we need this due to the arm implementation which supposed that U-Boot
+    is in RAM when we jump to start_armboot
+
+    This reverts commit f96b44cef897bd372beb86dde1b33637c119d84d.
+    in order to do it for all arm board
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 7fd0bea2e4a78eab7e6693140940f9f9a0009bc2
+Author: Kim Phillips <kim.phillips@freescale.com>
+Date:	Wed Sep 24 08:46:25 2008 -0500
+
+    mpc83xx: don't disable autoboot
+
+    bootdelay set to -1 'permanently' disables autobooting, even if
+    bootcmd is specified.  Change to a positive value to allow
+    autobooting when a bootcmd is set.
+
+    Reported-by: Coray Tate <Coray.Tate@freescale.com>
+    Cc: Scott Wood <scottwood@freescale.com>
+    Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit 2fb29c520c42b7bfef33ea3fd1527eba64099164
+Author: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+Date:	Wed Sep 24 10:42:15 2008 +0900
+
+    mpc83xx: Fix typo in include/mpc83xx.h
+
+    Fixed typo from CONIFG_MPC837X to CONFIG_MPC837X
+
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+    Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit 162c41c03179727a1d14262f703c9a8bc40231fa
+Author: Kim Phillips <kim.phillips@freescale.com>
+Date:	Tue Sep 23 09:38:49 2008 -0500
+
+    mpc83xx: add h/w flash protection to board configs
+
+    the operating system may leave flash in a h/w locked state after writing.
+    This allows u-boot to continue to write flash by enabling h/w unlocking
+    by default.
+
+    Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit d26154c9a692586b66eb6d1f8e1b67c75e40ea70
+Author: Anton Vorontsov <avorontsov@ru.mvista.com>
+Date:	Thu Sep 11 21:35:36 2008 +0400
+
+    mpc83xx: spd_sdram: fix ddr sdram base address assignment bug
+
+    The spd_dram code shifts the base address, then masks 20 bits, but
+    forgets to shift the base address back. Fix this by just masking the
+    base address correctly.
+
+    Found this bug while trying to relocate a DDR memory at the base != 0.
+
+    Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
+    Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit 8fd4166c467a46773f80208bda1ec3b4757747bc
+Author: Stefan Roese <sr@denx.de>
+Date:	Mon Sep 22 16:10:43 2008 +0200
+
+    ppc4xx: Canyonlands: Remove unnecessary FDT warning upon DTB fixup
+
+    Depending on the configuration jumper "SATA SELECT", U-Boot disabled
+    either one PCIe node or the SATA node in the device tree blob. This
+    patch removes the unnecessary and even confusing warning, when the node
+    is not found at all.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 6e24a1eb1490aa043770bcf0061ac1fad0864fd9
+Author: Remy Bohmer <linux@bohmer.net>
+Date:	Fri Sep 19 13:30:06 2008 +0200
+
+    Add missing device types to dev_print() in part.c
+
+    Signed-off-by: Remy Bohmer <linux@bohmer.net>
+
+commit 5fdc215f0b351b0c36cc3f8a0fa5850f24454bed
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Mon Sep 22 22:23:06 2008 +0200
+
+    Fix DPRAM memory leak when CFG_ALLOC_DPRAM is defined, which
+    eventually leads to a machine check. This change assures that DPRAM
+    is allocated only once in that case.
+
+    Signed-off-by: Gary Jennejohn <garyj@denx.de>
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit a07faf7b9ad5a86763a577c79922c4ff9a70ef23
+Author: Laurent Pinchart <laurentp@cse-semaphore.com>
+Date:	Wed Sep 17 17:57:34 2008 +0200
+
+    Fix Spartan-3 definitions.
+
+    A few Spartan-3 definitions erroneously use Spartan-3E size
+    constants. This patch fixes them.
+
+    Signed-off-by: Laurent Pinchart <laurentp@cse-semaphore.com>
+
+commit 28113e1f0da4146b823ffce37680d31d5685a60b
+Author: Laurent Pinchart <laurentp@cse-semaphore.com>
+Date:	Wed Sep 17 17:41:58 2008 +0200
+
+    Remove duplicate Spartan-3E definition.
+
+    Signed-off-by: Laurent Pinchart <laurentp@cse-semaphore.com>
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 5c65ecf7cd94df250b295621f3b24135cbcfe579
+Author: Anatolij Gustschin <agust@denx.de>
+Date:	Wed Sep 17 13:46:17 2008 +0200
+
+    socrates: change default mtest address range
+
+    Running mtest command on socrates without specifying
+    an address range crashes the board. This patch changes
+    default mtest address range to prevent this behavior.
+
+    Signed-off-by: Anatolij Gustschin <agust@denx.de>
+
+commit d666b2d59674b5e002c0821b7ab83ec3ff90d670
+Author: Anatolij Gustschin <agust@denx.de>
+Date:	Wed Sep 17 12:34:45 2008 +0200
+
+    socrates: fix crash after relocation
+
+    Currently U-Boot crashes after relocation to RAM.
+    Changing the CPO value of the DDR SDRAM TIMING_CFG_2
+    register to READ_LAT + 1 (to the value it was before
+    conversion of socrates to new DDR code) fixes the
+    problem.
+
+    Signed-off-by: Anatolij Gustschin <agust@denx.de>
+
+commit 562788b0a303f3528b920d81f547f5ca77ba528e
+Author: Anatolij Gustschin <agust@denx.de>
+Date:	Wed Sep 17 11:45:51 2008 +0200
+
+    socrates: fix SPD EEPROM address
+
+    Commit be0bd8234b9777ecd63c4c686f72af070d886517
+    changed SPD EEPROM address to 0x51 and DDR SDRAM
+    detection stopped working. Change this address
+    back to 0x50.
+
+    Signed-off-by: Anatolij Gustschin <agust@denx.de>
+
+commit 023824549a370bd185d7129d9a6c86f9be7b86a8
+Author: Stefan Roese <sr@denx.de>
+Date:	Mon Sep 22 11:06:50 2008 +0200
+
+    Revert "ppc4xx: Fix DDR2 auto calibration on Kilauea 600MHz (200MHz PLB)"
+
+    This reverts commit 3eec160a3a405b29ce9c06920f6427b9047dd8a8.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit e58c41e26cf3c8accd60311be579f452e368e97e
+Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Date:	Thu Sep 18 20:13:08 2008 +0900
+
+    usb: Fix compile warning of r8a66597-hcd
+
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+    Signed-off-by: Markus Klotzbuecher <mk@denx.de>
+
+commit b5d10a13525c07ec6374adf840d7c87553b5f189
+Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Date:	Thu Sep 18 19:34:36 2008 +0900
+
+    sh: Fix compile warning
+
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit 4a065abf926f128beb36d93449defa0d690e7fef
+Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Date:	Thu Sep 18 19:04:26 2008 +0900
+
+    sh: Add support watchdog for SH4A core
+
+    Add support watchdog for SH4A core (SH7763, SH7780 and SH7785).
+    And fix some compile warning.
+
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit a03c09c5fdb8430fe2ae6a03f88a0cf7bcc0aa57
+Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Date:	Wed Sep 17 11:45:26 2008 +0900
+
+    sh: Fix typo in SH serial driver
+
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit 6b44a439215ba7c63f666f8099213ea4f05f2b07
+Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Date:	Wed Sep 17 11:08:36 2008 +0900
+
+    sh: Add support any page size and empty_zero_page to SH Linux uImage
+
+    Old U-Boot supported 4KB page size only. If this version, Linux
+    kernel can not get command line from U-Boot.
+    SH Linux kernel can change page size and empty_zero_page.
+    This patch support this function and fix promlem.
+
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit ce9f99ddb59628f41dc534e892368a7d66dfc774
+Author: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+Date:	Thu Aug 28 13:40:52 2008 +0900
+
+    sh: rsk7203: Add support pkt_data_pull and pkt_data_push function
+
+    Add function of smc911x, pkt_data_pull and pkt_data_push.
+
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit dd820b03a2f45e86e7960e26729a3b58e3dda44a
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Thu Sep 18 13:57:32 2008 +0200
+
+    ADS5121: fix typo in "rootpath" default setting
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit c9e8436b10cca53fca4904ecbadcd6231ad72c38
+Author: Remy Bohmer <linux@bohmer.net>
+Date:	Tue Sep 16 14:55:44 2008 +0200
+
+    USB layer of U-Boot causes USB protocol errors while using USB memory sticks
+
+    There are several differences between Linux, Windows and U-boot for initialising the
+    USB devices. While analysing the behaviour of U-boot it turned out that U-boot does
+    things really different, and some are wrong (compared to the USB standard).
+
+    This patch fixes some errors:
+    * The NEW_init procedure that was already in the code is good, while the old procedure
+      is wrong. See code comments for more info.
+    * On a Control request the data returned by the device can be more than 8 bytes, while
+      the host limits it to 8 bytes. This caused the host to generate a DataOverrun error.
+      This results in a lot of USB sticks not being recognised, and the transmission ended
+      frequently with a CTL:TIMEOUT Error.
+    * Added a flag CONFIG_LEGACY_USB_INIT_SEQ to allow users to use the old init procedure.
+
+    Signed-off-by: Remy Bohmer <linux@bohmer.net>
+    Signed-off-by: Markus Klotzbuecher <mk@denx.de>
+
+commit 6f5794a6f78b313231256958fd73673c6aacc116
+Author: Remy Bohmer <linux@bohmer.net>
+Date:	Tue Sep 16 14:55:43 2008 +0200
+
+    Refactoring parts of the common USB OHCI code
+
+    This patch refactors some large routines of the USB OHCI code by
+    making some routines smaller and more readable which helps
+    debugging and understanding the code. (Makes the code looks
+    somewhat more like the Linux implementation.)
+
+    Also made entire file compliant to Linux Coding Rules (checkpatch.pl compliant)
+
+    Signed-off-by: Remy Bohmer <linux@bohmer.net>
+    Signed-off-by: Markus Klotzbuecher <mk@denx.de>
+
+commit be19d324edc1a1d7f393d24e10d164cd94c91a00
+Author: Remy Bohmer <linux@bohmer.net>
+Date:	Tue Sep 16 14:55:42 2008 +0200
+
+    Fix for USB sticks not working on ARM while using GCC 4.x compilers
+
+    The GCC-compiler makes an optimisation error while optimising the routine
+    usb_set_maxpacket(). This should be fixed in the compiler in the first place,
+    but there lots of compilers out there that makes this error, that it is
+    probably wiser to workaround it in U-boot itself.
+
+    What happens is that the register r3 is used as loop-counter 'i', but gets
+    overwritten later on. From there it starts using register r3 for several other
+    things and the assembler code is becoming a big mess. This is clearly a compiler bug.
+
+    This error occurs on at least several versions of Code Sourcery Lite compilers
+    for ARM. Like the Edition 2008q1, and 2008q3, It has also been seen on other
+    compilers, while compiling for armv4t, or armv5te with Os, O1 and O2.
+
+    We work around it by splitting up this routine in 2 parts, and making sure that
+    the split out part is NOT inlined any longer. This will make GCC spit out assembler
+    that do not show this problem. Another possibility is to adapt the Makefile to stop
+    optimisation for the complete file. I think this solution is nicer.
+
+    Signed-off-by: Remy Bohmer <linux@bohmer.net>
+    Signed-off-by: Markus Klotzbuecher <mk@denx.de>
+
+commit 87b4ef560cf2da4ccc9e59711ad1ff7fafe96670
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Wed Sep 17 10:17:55 2008 +0200
+
+    Coding style cleanup; update CHANEGLOG
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 3eec160a3a405b29ce9c06920f6427b9047dd8a8
+Author: Victor Gallardo <vgallardo@amcc.com>
+Date:	Tue Sep 16 06:59:13 2008 -0700
+
+    ppc4xx: Fix DDR2 auto calibration on Kilauea 600MHz (200MHz PLB)
+
+    Signed-off-by: Victor Gallardo <vgallardo@amcc.com>
+    Signed-off-by: Adam Graham <agraham@amcc.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit ce47eb402c5e29a025399dc282246414fc492940
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date:	Tue Sep 16 10:04:47 2008 -0500
+
+    Support for multiple SGMII/TBI interfaces for TSEC ethernet
+
+    Fix TBI PHY accesses to use the proper offset in CPU register space. The
+    previous code would incorrectly access the TBI PHY by reading/writing to CPU
+    register space at the same location as would be used to access external PHYs.
+
+    Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+    Acked-by: Andy Fleming <afleming@freescale.com>
+
+commit 7c803be2eb3cae245dedda438776e08fb122250f
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Tue Sep 16 18:02:19 2008 +0200
+
+    TQM8xx: Fix CFI flash driver support for all TQM8xx based boards
+
+    After switching to using the CFI flash driver, the correct remapping
+    of the flash banks was forgotten.
+
+    Also, some boards were not adapted, and the old legacy flash driver
+    was not removed yet.
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit c0d2f87d6c450128b88e73eea715fa3654f65b6c
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Sun Sep 14 00:59:35 2008 +0200
+
+    Prepare v2008.10-rc2
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit f12e4549b6fb01cd2654348af95a3c7a6ac161e7
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Sat Sep 13 02:23:05 2008 +0200
+
+    Coding style cleanup, update CHANGELOG
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 0c32565f536609d78feef35c88bbc39d3ac53a73
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date:	Wed Sep 10 09:18:34 2008 -0500
+
+    Update mailing list email and archive addresses
+
+    Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+
+commit fb661ea444ae61de60520f66ae84cdb5dd5a3246
+Author: u-boot@bugs.denx.de <u-boot@bugs.denx.de>
+Date:	Thu Sep 11 15:40:01 2008 +0200
+
+    85xx: socrates: autoprobe Lime chip
+
+    This patch is an attempt to implement autoprobing for the Lime
+    presence on the bus.
+    Configure GPCM for Lime CS2 and try to access chip ID registers.
+    Second read atempt delivers register values if the chip is present.
+
+    Signed-off-by: Anatolij Gustschin <agust@denx.de>
+
+commit e99b607a5ec56ce66e0bcccb78480d5e16fb7bc5
+Author: u-boot@bugs.denx.de <u-boot@bugs.denx.de>
+Date:	Thu Sep 11 15:40:01 2008 +0200
+
+    85xx: socrates: Add support for new image format.
+
+    Signed-off-by: Detlev Zundel <dzu@denx.de>
+
+commit 3c094b652d4107b34641f300a8e9fe16ca15e3d8
+Author: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+Date:	Thu Sep 11 17:28:18 2008 +0900
+
+    sh: Fix compile error for r2dplus
+
+    netdev.h was not include by r2dplus.
+
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+
+commit 56844a22b76c719e600047e23b80465a44d76abd
+Author: Heiko Schocher <hs@denx.de>
+Date:	Thu Sep 11 08:11:23 2008 +0200
+
+    powerpc: Fix bootm to boot up again with a Ramdisk
+
+    Commit 2a1a2cb6 didnt remove the dummy mem reservation in fdt_chosen,
+    and this stopped Linux from booting with a Ramdisk. This patch fixes
+    this, by deleting the useless dummy mem reservation.
+
+    When booting with a Ramdisk, a fix offset FDT_RAMDISK_OVERHEAD is now
+    added to of_size, so we dont need anymore a dummy mem reservation.
+
+    I measured the value of FDT_RAMDISK_OVERHEAD on a MPC8270 based
+    system (=0x44 bytes) and rounded it up to 0x80).
+
+    Signed-off-by: Heiko Schocher <hs@denx.de>
+    Acked-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit fc9c1727b5b3483ce49c3cb668e8332fb001b8a7
+Author: Luigi 'Comio' Mantellini <luigi.mantellini@idf-hit.com>
+Date:	Mon Sep 8 02:46:13 2008 +0200
+
+    Add support for LZMA uncompression algorithm.
+
+    Signed-off-by: Luigi 'Comio' Mantellini <luigi.mantellini@idf-hit.com>
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 0008b6d968160abe2bfd936493f3a516a7c8da20
+Author: Anton Vorontsov <avorontsov@ru.mvista.com>
+Date:	Fri Jun 27 23:04:20 2008 +0400
+
+    fsl_elbc_nand: ecclayout cleanups
+
+    This patch deletes oobavail assignments, they're calculated by the nand
+    core code in nand_scan_tail, plus current oobavail values are wrong for
+    the LP NANDs.
+
+    Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
+    Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
+    Signed-off-by: Scott Wood <scottwood@freescale.com>
+
+commit 8f42bf1c393d53a70c2545e9f329d11c46d74794
+Author: Anton Vorontsov <avorontsov@ru.mvista.com>
+Date:	Fri Jun 27 23:04:13 2008 +0400
+
+    fsl_elbc_nand: implement support for flash-based BBT
+
+    This patch implements support for flash-based BBT for chips working
+    through ELBC NAND controller, so that NAND core will not have to re-scan
+    for bad blocks on every boot.
+
+    Because ELBC controller may provide HW-generated ECCs we should adjust
+    bbt pattern and bbt version positions in the OOB free area.
+
+    Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
+    Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
+    Signed-off-by: Scott Wood <scottwood@freescale.com>
+
+commit 97ae023648e764f794ffb9c52da109d6caf09c47
+Author: Anton Vorontsov <avorontsov@ru.mvista.com>
+Date:	Fri Jun 27 23:04:04 2008 +0400
+
+    fsl_elbc_nand: fix OOB workability for large page NAND chips
+
+    For large page chips, nand_bbt is looking into OOB area, and checking
+    for "0xff 0xff" pattern at OOB offset 0. That is, two bytes should be
+    reserved for bbt means.
+
+    But ELBC driver is specifying ecclayout so that oobfree area starts at
+    offset 1, so only one byte left for the bbt purposes.
+
+    This causes problems with any OOB users, namely JFFS2: after first mount
+    JFFS2 will fill all OOBs with "erased marker", so OOBs will contain:
+
+      OOB Data: ff 19 85 20 03 00 ff ff ff 00 00 08 ff ff ff ff
+      OOB Data: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
+      OOB Data: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
+      OOB Data: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
+
+    And on the next boot, NAND core will rescan for bad blocks, then will
+    see "0xff 0x19" pattern, and will mark all blocks as bad ones.
+
+    To fix the issue we should implement our own bad block pattern: just one
+    byte at OOB start. Though, this will work only for x8 chips. For x16
+    chips two bytes must be checked. Since ELBC driver does not support x16
+    NANDs (yet), we're safe for now.
+
+    Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
+    Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
+    Signed-off-by: Scott Wood <scottwood@freescale.com>
+
+commit 7238ada313057a85409485b8ee21515dc10c07a5
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Fri Sep 12 13:52:21 2008 +0200
+
+    MPC512x: reduce timeout waiting for Ethernet autonegotiation to 2.5s
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit b18410e508a12ba0a177dfc2a386857c806fa96d
+Author: Stefan Roese <sr@denx.de>
+Date:	Thu Sep 11 13:05:56 2008 +0200
+
+    ppc4xx: Enable device tree (FDT) support in zeus board port
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 7bf5ecfa50722a9feb45ea8f04da75f5d406f20b
+Author: Stefan Roese <sr@denx.de>
+Date:	Wed Sep 10 16:53:47 2008 +0200
+
+    ppc4xx: Fix SDRAM inititialization of multiple 405 based board ports
+
+    This patch fixes a problem introdiced with patch
+    bbeff30c [ppc4xx: Remove superfluous dram_init() call or replace it by
+    initdram()].
+
+    The boards affected are:
+    - PCI405
+    - PPChameleonEVB
+    - quad100hd
+    - taihu
+    - zeus
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 61737c59a3285f6fadf96a5836879898c04ec28d
+Author: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es>
+Date:	Thu Sep 11 19:41:26 2008 -0400
+
+    ppc4xx: Add .gitignore file to xilinx-ppc440 boards
+
+    Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 2bec498ed1164a58cd8437b561bdc4551d69f9bf
+Author: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es>
+Date:	Thu Sep 11 19:41:25 2008 -0400
+
+    ppc4xx: Fix compilation of v5fx30teval_flash
+
+    Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 4bed9deebbd7ee6f0ba746b44d47a922156f7404
+Author: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es>
+Date:	Wed Sep 10 17:44:30 2008 -0400
+
+    ppc4xx: Fix in-tree build for ppc440-generic boards
+
+    Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 06c4ab50f5ccfb55ea2dd324aa28b2b06102e416
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Fri Sep 12 02:20:47 2008 +0200
+
+    ARM: synchronize mach-types.h with linux 2.6.27-rc6
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 3ee9f03f588ad605e3fd10530237f9e3e2e7ab4c
+Author: Jens Scharsig <esw@bus-elektronik.de>
+Date:	Fri Sep 12 02:20:47 2008 +0200
+
+    at91rm9200: fix errors with CONFIG_CMD_I2C_TREE
+
+    This patch prevents linker error on AT91RM9200 boards, if
+    CONFIG_CMD_I2_TREE is set.
+    It implements i2c_set_bus_speed and i2c_get_bus_speed as a dummy function.
+
+    Signed-off-by: Jens Scharsig <esw@bus-elektronik.de>
+
+commit b5b0344957d32e3d07a8dd72fce64fb48e680ba4
+Author: Hugo Villeneuve <hugo.villeneuve@lyrtech.com>
+Date:	Fri Sep 12 02:20:47 2008 +0200
+
+    ARM DaVinci: Remove duplicate code in cpu/arm926ejs/davinci/dp83848.c
+
+    ARM DaVinci: Remove duplicate code in cpu/arm926ejs/davinci/dp83848.c
+
+    Signed-off-by: Hugo Villeneuve <hugo.villeneuve@lyrtech.com>
+
+commit 03db53335c8eba656a7c44d1555b1a4514383e33
+Author: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
+Date:	Fri Sep 12 02:20:46 2008 +0200
+
+    make: Remove redundant __ARM__ addition when cross-compiling on *BSD
+
+    __ARM__ is given by arm_config.mk automatically.
+
+    Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
+
+commit 8cc62a7d9c77f8ef5166fb57322c4a6ddac320b4
+Author: Claudio Scordino <claudio@evidence.eu.com>
+Date:	Fri Sep 12 02:20:46 2008 +0200
+
+    Fix MACH_TYPE for the AT91RM9200DK board.
+
+    Signed-off-by: Claudio Scordino <claudio@evidence.eu.com>
+
+commit 274737e5eb25b2bcd3af3a96da923effd543284f
+Author: Andrew Dyer <adyer@righthandtech.com>
+Date:	Fri Sep 12 02:20:46 2008 +0200
+
+    i.mx change get_timer(base) to return time since base
+
+    This patch changes get_timer() for i.MX to return the time since
+    'base' instead of the time since the counter was at zero.
+
+    Symptom seen is flash timeout errors when erasing or programming a
+    sector using the common cfi flash code.
+
+    Signed-off-by: Andrew Dyer <adyer@righthandtech.com>
+
+commit 48fed40575b3e8eae960eb0141509ddd9a73012a
+Author: Andrew Dyer <adyer@righthandtech.com>
+Date:	Fri Sep 12 02:20:46 2008 +0200
+
+    i.MX use u-boot baud rate and don't assume UART master clock
+
+    1) Change the i.MX serial driver to use the baud rate set in the
+     u-boot environment
+
+    2) don't assume a 16MHz value for PERCLK1 in baud rate calculations
+
+    3) don't write a 1 to the RDR bit in the USR2 reg. (bit is not "write
+     one to clear" like other status bits in the reg.)
+
+    Signed-off-by: Andrew Dyer <adyer@righthandtech.com>
+
+commit 6e1551a870d360805b9d172dc56d935064abe71d
+Author: Andrew Dyer <adyer@righthandtech.com>
+Date:	Fri Sep 12 02:20:46 2008 +0200
+
+    arm920t fix constant error in start.S
+
+    Code in cpu/arm920t/start.S will die with a compilation error if
+    CONFIG_STACKSIZE + CFG_MALLOC_LEN works out to an invalid constant for
+    the ARM sub instruction.  Change the code so that each is subtracted
+    independently to avoid the error.
+
+    Signed-off-by: Andrew Dyer <adyer@righthandtech.com>
+
+commit b23253835f871cd9bd8e955b9a971d18a7d4ff56
+Author: Gururaja Hebbar K R <gururajakr@sanyo.co.in>
+Date:	Fri Sep 12 02:20:40 2008 +0200
+
+    ARM OMAP : Correct Invalid Timer Register Field Declaration in omap1510.h & omap730.h
+
+    - Correct Invalid #define of MPUTIM_PTV_MASK for
+       omap1510 & omap730 register definition
+
+     MPUTIM_PTV_MASK is defined as
+     #define MPUTIM_PTV_MASK		(0x7<<PTV_BIT)
+
+     while it should have been
+     #define MPUTIM_PTV_MASK		(0x7<<MPUTIM_PTV_BIT)
+
+    - Below Patch corrects the same
+
+    Signed-off-by: Gururaja Hebbar <gururajakr@sanyo.co.in>
+
+commit c455d07396dddc9864fd8dbb965ee10fe95ce8cf
+Author: Adrian Filipi <adrian.filipi@eurotech.com>
+Date:	Fri Jul 18 11:52:02 2008 -0400
+
+    Set up SD/MMC OCR as comment describes. i.e. 3.2-3.4v.
+
+    Signed-off-by: Adrian Filipi <adrian.filipi@eurotech.com>
+
+commit eb16135df20535b0d19969f50fb5bd17f95e9c25
+Author: Guennadi Liakhovetski <lg@denx.de>
+Date:	Thu Aug 28 12:25:11 2008 +0200
+
+    i.MX31: document timer precision option
+
+    Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
+
+commit 1a6337b01351b82a45b0defa76f08744511c580b
+Author: Magnus Lilja <lilja.magnus@gmail.com>
+Date:	Fri Aug 29 10:36:18 2008 +0200
+
+    i.MX31: Make the SPI bus and chip select configurable for MC13783
+
+    The i.MX31 has three SPI buses and each bus has several chip selects
+    and the MC13783 chip can be connected to any of these. The current
+    RTC driver for MC13783 is hardcoded for CSPI2/SS2.
+
+    This patch makes make MC13783 SPI bus and chip select configurable
+    via CONFIG_MC13783_SPI_BUS and CONFIG_MC13783_SPI_CS.
+
+    Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
+
+commit 8c4ebec25b21e355b8488698ec1594da9701fff4
+Author: Magnus Lilja <lilja.magnus@gmail.com>
+Date:	Fri Aug 29 10:36:17 2008 +0200
+
+    i.MX31: Add reset_timer() and modify get_timer_masked().
+
+    This patch adds the reset_timer() function (needed by nand_base.c) and
+    modifies the get_timer_masked() to work in the same way as the omap24xx
+    function.
+
+    Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
+
+commit deeec4991a55de243787002ede24d2331d234fc8
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Wed Sep 10 22:48:09 2008 +0200
+
+    ap325rxa: remove duplicate CONFIG_FLASH_CFI_DRIVER
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit a3a08c0cedd329edf5256e1d6b2bad0fca002725
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Wed Sep 10 22:48:09 2008 +0200
+
+    bootm arm/avr32/blackfin/microblaze/nios2/sh: remove no more need 'error' label
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 0e8d158664a913392cb01fb11a948d83f72e105e
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Wed Sep 10 22:48:06 2008 +0200
+
+    rename CFG_ENV macros to CONFIG_ENV
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 1ede78710c3bf9ad6f4a53aaddc3bcc86fedd9df
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Wed Sep 10 22:48:05 2008 +0200
+
+    nvedit: rename error comment to CONFIG_ENV_IS_IN_
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit b64b775e7546ed138df360ceb3a71ee358cb9a01
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Wed Sep 10 22:48:05 2008 +0200
+
+    cmd_mem: Move conditional compilation to Makefile
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 8a40fb148efa442d6526eac46a2001e4c64d28ff
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Wed Sep 10 22:48:05 2008 +0200
+
+    move cmd_get_data_size to command.c
+
+    add CMD_DATA_SIZE macro to enable it
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 507641d2491980531932b9f25dab37fe5e6c3a1a
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Wed Sep 10 22:48:04 2008 +0200
+
+    env_flash: Move conditional compilation to Makefile
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 5a1aceb0689e2f731491838970884a673ef7e7d3
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Wed Sep 10 22:48:04 2008 +0200
+
+    rename CFG_ENV_IS_IN_FLASH in CONFIG_ENV_IS_IN_FLASH
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 7d9b5bae5ba558c7464d89d033aca04acaf01172
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Wed Sep 10 22:48:03 2008 +0200
+
+    cleanup use of CFG_ENV_IS_IN_FLASH
+
+    - #if CFG_ENV_IS_IN_FLASH
+    - #if (CFG_ENV_IS_IN_FLASH == 1)
+    - #define CFG_ENV_IS_IN_FLASH 0
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 0cf4fd3cf8d0e00605bec5fc56f89c6415015a46
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Wed Sep 10 22:48:01 2008 +0200
+
+    rename environment.c in env_embedded.c to reflect is functionality
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit c0878af6e32f0fd8e13a6ca315b9add64441115a
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Wed Sep 10 22:48:01 2008 +0200
+
+    env_nowhere: Move conditional compilation to Makefile
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 93f6d72544da4510a146bc4c93d609b0116cde37
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Wed Sep 10 22:48:00 2008 +0200
+
+    rename CFG_ENV_IS_NOWHERE in CONFIG_ENV_IS_NOWHERE
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 2556ef78113b5f089dfcac5da90bf31dd568397b
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Wed Sep 10 22:48:00 2008 +0200
+
+    env_sf: Move conditional compilation to Makefile
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 0b5099a8419bf9c828df5e3e2c6878dc300d98e3
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Wed Sep 10 22:48:00 2008 +0200
+
+    rename CFG_ENV_IS_IN_SPI_FLASH in CONFIG_ENV_IS_IN_SPI_FLASH
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 55c5f49910ec8225347aa1d211352a84de6649b4
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Wed Sep 10 22:48:00 2008 +0200
+
+    env_onenand: Move conditional compilation to Makefile
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 9656138ff1a34d4c4768db6b490deffc40ee674b
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Wed Sep 10 22:47:59 2008 +0200
+
+    rename CFG_ENV_IS_IN_ONENAND in CONFIG_ENV_IS_IN_ONENAND
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 957a0e69575683efd70ace147746bbb3d8e7c501
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Wed Sep 10 22:47:59 2008 +0200
+
+    env_nvram: Move conditional compilation to Makefile
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 9314cee6917444ab88bd4e758da7a30975120187
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Wed Sep 10 22:47:59 2008 +0200
+
+    rename CFG_ENV_IS_IN_NVRAM in CONFIG_ENV_IS_IN_NVRAM
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 06f61354397911a4c121dfa51b6ccbf7e300d48b
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Wed Sep 10 22:47:59 2008 +0200
+
+    env_nand: Move conditional compilation to Makefile
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 51bfee192099206a4397f15f3b93516e01f58ab0
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Wed Sep 10 22:47:58 2008 +0200
+
+    rename CFG_ENV_IS_IN_NAND in CONFIG_ENV_IS_IN_NAND
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit d8cc04d0ac9c7c0d12454708aaf5489f8532bbf9
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Wed Sep 10 22:47:58 2008 +0200
+
+    env_dataflash: Move conditional compilation to Makefile
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 057c849c45b9ee19df8ff3acdeee66be52819962
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Wed Sep 10 22:47:58 2008 +0200
+
+    rename CFG_ENV_IS_IN_DATAFLASH in CONFIG_ENV_IS_IN_DATAFLASH
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit d1034bc8db60fa6bd419328baf6a75cb0645cee8
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Wed Sep 10 22:47:52 2008 +0200
+
+    cmd_eeprom: Move conditional compilation to Makefile
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit bf5a7710ec70e90e98f451b4ba0eb65f9ffc34eb
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Fri Sep 5 09:19:54 2008 +0200
+
+    env_eeprom: Move conditional compilation to Makefile
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit bb1f8b4f8bb0bfce52e0faa4637b975b745824b3
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Fri Sep 5 09:19:30 2008 +0200
+
+    rename CFG_ENV_IS_IN_EEPROM in CONFIG_ENV_IS_IN_EEPROM
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 32628c5008105a732212003d83b75f05e5243bb2
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Sat Aug 30 23:54:58 2008 +0200
+
+    cmd_mac: Move conditional compilation to Makefile
+
+    finish remaning CFG_ID_EEPROM in CONFIG_ID_EEPROM
+    start in commit ad8f8687b78c3e917b173f038926695383c55555
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit e5648acab153f0f429bfc714902c5aaa7879f71b
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Sat Aug 30 23:47:41 2008 +0200
+
+    cmd_fdc: Move conditional compilation to Makefile
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 2d02d91d530e831f2dab228085963fc1d5b71cb0
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Sat Aug 30 23:47:38 2008 +0200
+
+    common/Makefile: add core command section
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 0d92d4a699fb1a39381d98571dc51fb97e5bcf9e
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Sat Aug 30 23:29:57 2008 +0200
+
+    cmd_vfd: Move conditional compilation to Makefile
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 6644641d072aee3087da129d8443187196a4d8a9
+Author: Scott Wood <scottwood@freescale.com>
+Date:	Wed Sep 10 11:48:49 2008 -0500
+
+    delta, zylonite: Update nand_oobinfo to nand_ecclayout.
+
+    This is part of the switch to newer upstream MTD code.
+
+    Signed-off-by: Scott Wood <scottwood@freescale.com>
+
+commit 9b05aa788bfdd3264ff1bc9418cb19550a7234e4
+Author: Hugo Villeneuve <hugo.villeneuve@lyrtech.com>
+Date:	Sat Aug 30 17:06:55 2008 -0400
+
+    ARM DaVinci: Fix broken HW ECC for large page NAND.
+
+    Based on original patch by Bernard Blackham <bernard@largestprime.net>
+
+    U-boot's HW ECC support for large page NAND on Davinci is completely
+    broken.  Some kernels, such as the 2.6.10 one supported by
+    MontaVista for DaVinci, rely upon this broken behaviour as they
+    share the same code for ECCs. In the existing scheme, error
+    detection *might* work on large page, but error correction
+    definitely does not.  Small page ECC correction works, but the
+    format is not compatible with the mainline git kernel.
+
+    This patch adds ECC code that matches what is currently in the
+    Davinci git repository (since NAND support was added in 2.6.24).
+    This makes the ECC and OOB layout written by u-boot compatible with
+    Linux for both small page and large page devices and fixes ECC
+    correction for large page devices.
+
+    The old behaviour can be restored by defining the macro
+    CFG_DAVINCI_BROKEN_ECC, which is undefined by default.
+
+    Signed-off-by: Hugo Villeneuve <hugo.villeneuve@lyrtech.com>
+    Acked-by: Sergey Kubushyn <ksi@koi8.net>
+    Signed-off-by: Scott Wood <scottwood@freescale.com>
+
+commit 0b7c5639891f4103a0e31ec7ae0beb3e97ed3836
+Author: Heiko Schocher <hs@denx.de>
+Date:	Wed Sep 10 11:15:28 2008 +0200
+
+    muas3001: update BR4 settings
+
+    Also set up the port pins for using I2C.
+
+    Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit 3591293509e0c0bcf244b0f974775bff2e25697e
+Author: Petri Lehtinen <petri.lehtinen@inoi.fi>
+Date:	Wed Sep 10 09:43:49 2008 +0300
+
+    autoscr: Fix one-character lines and non-newline terminated scripts
+
+    When not using hush, the autoscr command now executes lines that are
+    only one character long. It also runs the last line of scripts even if
+    it does not end in a newline.
+
+    Signed-off-by: Petri Lehtinen <petri.lehtinen@inoi.fi>
+
+commit 9ebbb54f7a25055010fa6668eba40c72a4c4f985
+Author: Victor Gallardo <vgallardo@amcc.com>
+Date:	Tue Sep 9 15:13:29 2008 -0700
+
+    ppc4xx: Allow DTT_I2C_DEV_CODE configured by CFG_I2C_DTT_ADDR
+
+    On AMCC Arches board DTT_I2C_DEV_CODE is different then canyonlands
+    and glacier.
+
+    Signed-off-by: Victor Gallardo <vgallardo@amcc.com>
+
+commit 245f6ef3e11828cb46188e396fb1e67f7b07cd03
+Author: Heiko Schocher <hs@denx.de>
+Date:	Mon Sep 8 10:21:11 2008 +0200
+
+    muas3001: added support for the LM75 sensor.
+
+    Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit 4a02a2dca82aeab8f839db9dd35fda9d5412dacb
+Author: Heiko Schocher <hs@denx.de>
+Date:	Mon Sep 8 10:20:19 2008 +0200
+
+    muas3001: activate WDT for the muas3001 board.
+
+    Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit a55d074dac24dc941f1afb5b4e94b1509bfdda4e
+Author: Heiko Schocher <hs@denx.de>
+Date:	Mon Sep 8 10:19:36 2008 +0200
+
+    muas3001: added 64MB SDRAM autodetection.
+
+    Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit 5251469943895de4bb9a04d5053352cc22acb7d5
+Author: Andrew Klossner <andrew@cesa.opbu.xerox.com>
+Date:	Thu Aug 21 07:12:26 2008 -0700
+
+    Fix printf errors under -DDEBUG
+
+    Fix printf format-string/arg mismatches under -DDEBUG.
+
+    These warnings occur with DEBUG defined for a platform using
+    cpu/mpc85xx.  Users of other architectures can unearth similar
+    problems by adding the line "CFLAGS += -DDEBUG=1" in config.mk right
+    after "CFLAGS += $(call cc-option,-fno-stack-protector)".
+
+    Signed-off-by: Andrew Klossner <andrew@cesa.opbu.xerox.com>
+    Signed-off-by: Andy Fleming <afleming@freescale.com>
+
+commit 8b9e4787641719d709bfa2ebeb72e8bd4952bee7
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Tue Sep 9 23:55:18 2008 +0200
+
+    Update CHANGELOG, prepare 2008-10-rc1 release
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit e0ff3d350d6b7960deb5a881dfc5acf3a63ef676
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Mon Sep 8 08:51:29 2008 -0500
+
+    85xx: Ensure timebase is zero on secondary cores
+
+    The e500um says the timebase is volatile out of reset.  To ensure
+    TB sync works we need to make sure its zero.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 54b4ab3c961a2012a1c2a09c259a6343323ec551
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Tue Sep 9 22:18:24 2008 +0200
+
+    bootm_load_os: fix load_end debug message
+
+    print load_end value not pointer
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 1d9af0be764960e6cc1c093e97176c3542796820
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Tue Sep 9 22:18:23 2008 +0200
+
+    bootm: enable fdt support only on ppc, m68k and sparc
+
+    ...as done in image.c
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 748b5274e76f81df85cfcffaffedc323678d0623
+Author: Markus Heidelberg <markus.heidelberg@web.de>
+Date:	Tue Sep 9 18:51:05 2008 +0200
+
+    common/cmd_mem.c: remove nested #if defined(CONFIG_CMD_MEMORY)
+
+    Signed-off-by: Markus Heidelberg <markus.heidelberg@web.de>
+
+commit 650632fe4ca09cfd0e5e6a593f2efc02ef87a58c
+Author: Markus Heidelberg <markus.heidelberg@web.de>
+Date:	Tue Sep 9 17:31:46 2008 +0200
+
+    gitignore: add tags files and Vim swap file
+
+    Signed-off-by: Markus Heidelberg <markus.heidelberg@web.de>
+
+commit 1d9b67b23fca6a25154333733204339802510720
+Author: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+Date:	Tue Sep 9 17:52:47 2008 +0900
+
+    add board_eth_init() for sh7785lcr board
+
+    Fix the problem that cannot work RTL8169 on sh7785lcr board.
+
+    Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+
+commit 7b7a869a8ba3bd6d9bffb748c91232141330f514
+Author: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Date:	Wed Aug 6 16:08:41 2008 -0500
+
+    mtd: SPI Flash: Support the STMicro Flash
+
+    Add MTD SPI Flash support for M25P16, M25P20, M25P32,
+    M25P40, M25P64, M25P80, M25P128.
+
+    Signed-off-by: Jason McMullan <mcmullan@netapp.com>
+    Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+
+commit 4bc07c368076560ed7fa4c9f987c71a8521488a9
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Tue Sep 9 17:55:31 2008 +0200
+
+    trab: fix build problem after change to use do_div()
+
+    We must link with libgeneric now.
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 3b20fd83c73c22acfcb0c6663be747bd5c8b7011
+Author: Ryan CHEN <ryan.chen@st.com>
+Date:	Wed Aug 20 13:00:17 2008 -0400
+
+    Correct drv_usb_kbd_init function
+
+    The patch is that check if usb_get_dev_index() function return valid
+    pointer. If valid, continue. Otherwise return -1.
+
+    Signed-off-by: Ryan Chen <ryan.chen@st.com>
+    Acked-by: Markus Klotzbuecher <mk@denx.de>
+
+commit eba1f2fc75f128a9a6c1328d786996a93fd7a707
+Author: Remy Bohmer <linux@bohmer.net>
+Date:	Wed Aug 20 11:22:02 2008 +0200
+
+    Make usb-stop() safe to call multiple times in a row.
+
+    A recent commit (936897d4d1365452bbbdf8430db5e7769ef08d38)
+    enabled the usb_stop() command in common/cmd_bootm.c which was
+    not enabled for some time, because no board did actually set the
+    CFG_CMD_USB flag. So, now the usb_stop() is executed before
+    loading the linux kernel.
+
+    However, the usb_ohci driver hangs up (at least on AT91SAM) if the
+    driver is stopped twice (e.g. the peripheral clock is stopped on AT91).
+    If some other piece of code calls usb_stop() before the bootm command,
+    this command will hangup the system during boot.
+    (usb start and stop is typically used while booting from usb memory stick)
+
+    But, stopping the usb stack twice is useless anyway, and a flag already
+    existed that kept track on the usb_init()/usb_stop() calls.
+    So, we now check if the usb stack is really started before we stop it.
+
+    This problem is now fixed in both the upper as low-level layer.
+
+    Signed-off-by: Remy Bohmer <linux@bohmer.net>
+    Acked-by: Markus Klotzbuecher <mk@denx.de>
+
+commit 2c8ccf2728f5e67d991cecf76c4057db75a87b67
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Tue Sep 9 16:55:47 2008 +0200
+
+    Makefile: fix bug introduced by commit 47ffd6c2
+
+commit 880f6a5d7596f42db5ff8803b797b78ec5b146e0
+Author: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es>
+Date:	Tue Sep 9 10:00:33 2008 -0400
+
+    ppc4xx: ppc440-generic-ALL: Fix out of tree build v2
+
+    This patch solves the problems compiling ml507, v5fx30teval and
+    ppc440-generic out of tree.
+
+    Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es>
+
+commit 47bebe34ca4e33bab0e822e4ceebbec2590ccbcb
+Author: Nícolas Carneiro Lebedenco <nicolas.lebedenco@tasksistemas.com.br>
+Date:	Thu Sep 4 15:35:46 2008 -0300
+
+    Fix dev_print when called from usb_stor_info (usb storage command)
+
+    Fix output of the usb storage command. It was printing "Device 0: not
+    available" because IF_TYPE_USB was not included into the switch
+    statement.
+
+    Signed-off-by: Nicolas Lebedenco <nicolas.lebedenco@tasksistemas.com.br>
+
+commit a4f243452cc8ce0c2c9b51a2520db4bde5f472de
+Author: Bartlomiej Sieka <tur@semihalf.com>
+Date:	Tue Sep 9 12:58:16 2008 +0200
+
+    FIT: make iminfo check hashes of all images in FIT, return 1 on failed check
+
+    Signed-off-by: Bartlomiej Sieka <tur@semihalf.com>
+
+commit 919f550dc11a13abf01c6bc713c968de790b8d7c
+Author: Bartlomiej Sieka <tur@semihalf.com>
+Date:	Tue Sep 9 12:58:15 2008 +0200
+
+    FIT: add ability to check hashes of all images in FIT, improve output
+
+    - add function fit_all_image_check_hashes() that verifies if all
+      hashes of all images in the FIT are valid
+    - improve output of fit_image_check_hashes() when the hash check fails
+
+    Signed-off-by: Bartlomiej Sieka <tur@semihalf.com>
+
+commit 1de1fa408967cef6804bb046b904114519bb36f0
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Mon Sep 8 20:54:39 2008 +0200
+
+    qemu_mips: Update linux bootm to support dynamic cmdline
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit f5ed9e39088ecfa5a5f3ef47b08e5bda7890d764
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date:	Mon Sep 8 14:56:49 2008 -0500
+
+    Add support for booting of INTEGRITY operating system uImages
+
+    Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+
+commit 72f1b65f1b68bc6ed0d182eda1f3d6cf51b6414a
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Mon Sep 8 21:01:29 2008 +0200
+
+    mips/bootm: Fix typo in commit c4f9419c, "initrd_start" replaced by "images->rd_start"
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 9ba2e2c8191353d75b2d535e672a125be7b84c03
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Mon Sep 8 13:57:12 2008 -0500
+
+    Remove support for booting ARTOS images
+
+    Pantelis Antoniou stated:
+	AFAIK, it is still used but the products using PPC are long gone.
+	Nuke it plz (from orbit).
+
+    So remove it since it cleans up a usage of env_get_char outside of
+    the environment code.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 47ffd6c2fc72b46daa9d5d59eedb894fab2b7ee1
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Tue Sep 9 15:45:18 2008 +0200
+
+    Makefile: compile and link each module just once
+
+    Several source files need to be compiled and linked when one or more
+    config options are selected. To allow for easy selection in the
+    Makefiles yet to avoild multiple compilation (which costs build time)
+    and especially multiple linking (which causes errors), we use
+    "COBJS = $(sort COBJS-y)" which eliminates duplicates.
+
+    By courtesy of Detlev Zundel who suggested this approach.
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 48d0192fe869948fef14b460b5f0c85bca933693
+Author: Andreas Engel <andreas.engel@ericsson.com>
+Date:	Mon Sep 8 14:30:53 2008 +0200
+
+    Moved conditional compile into Makefile
+
+    Signed-off-by: Andreas Engel <andreas.engel@ericsson.com>
+
+commit 20c9226cb8cab08a111ee73db04e62d943ee0c97
+Author: Andreas Engel <andreas.engel@ericsson.com>
+Date:	Mon Sep 8 10:17:31 2008 +0200
+
+    Merged serial_pl010.c and serial_pl011.c.
+
+    They only differ in the init function.
+    This also adds the missing watchdog support for the PL011.
+
+    Signed-off-by: Andreas Engel <andreas.engel@ericsson.com>
+
+commit 0817d688f307ee2c0598e79175c94a40ce90337b
+Author: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es>
+Date:	Sun Sep 7 17:10:27 2008 -0400
+
+    Remove gap fill in srec object v2
+
+    SREC files do not need gap fill: The load address is specified in the
+    file. On the other hand, it can't be avoided in a .bin object. It has
+    no information about memory location.
+
+    Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es>
+
+commit 1dc306931ca5ce87f13916fa7165b052d3aa714f
+Author: Markus Heidelberg <markus.heidelberg@web.de>
+Date:	Sun Sep 7 20:18:27 2008 +0200
+
+    README: fix missing subdirectory in the documentation
+
+    Signed-off-by: Markus Heidelberg <markus.heidelberg@web.de>
+
+commit 3ef96ded38a8d33b58b9fab9cd879d51ddac4cbd
+Author: Graeme Russ <graeme.russ@gmail.com>
+Date:	Sun Sep 7 07:08:42 2008 +1000
+
+    Update i386 code (sc520_cdp)
+
+    Attempt to bring i386 / sc520 inline with master
+
+    Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
+
+commit 5608692104efa8d56df803dc79ea41ac3607eee5
+Author: Guennadi Liakhovetski <lg@denx.de>
+Date:	Thu Sep 4 13:01:49 2008 +0200
+
+    fw_env: add NAND support
+
+    Add support for environment in NAND with automatic NOR / NAND recognition,
+    including unaligned environment, bad-block skipping, redundant environment
+    copy.
+
+    Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
+
+commit dd794323a2a1ed6a8a5df51785c31bcde60ad7ca
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Tue Sep 9 09:50:24 2008 +0200
+
+    ppc4xx: Fix out-of-tree building of CPCI405 variants
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+    Acked-by: Stefan Roese <sr@denx.de>
+
+commit 59f630588e3fdbd698a0a2798e52a8924e899563
+Author: Sergei Poselenov <sposelenov@emcraft.com>
+Date:	Fri Aug 15 15:42:11 2008 +0200
+
+    Removed hardcoded MxMR loop value from upmconfig() for MPC85xx.
+
+    Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
+
+commit e64987a892353f3d49eb242d997820ef8f538912
+Author: Anatolij Gustschin <agust@denx.de>
+Date:	Fri Aug 15 15:42:13 2008 +0200
+
+    85xx: socrates: Enable Lime support.
+
+    This patch adds Lime GDC support together with support for the PWM
+    backlight control through the w83782d chip.  The reset pin of the
+    latter is attached to GPIO, so we need to reset it in
+    early_board_init_r.
+
+    Signed-off-by: Anatolij Gustschin <agust@denx.de>
+
+commit 3e79b588b5199f35016f178fc0d5d1266382097f
+Author: Detlev Zundel <dzu@denx.de>
+Date:	Fri Aug 15 15:42:12 2008 +0200
+
+    85xx: Socrates: Major code update.
+
+    - Update the local bus ranges in the FDT for Linux for the various
+      devices connected to the local bus via chip-select.
+
+    - Set the LCRR_DBYP bit in the LCRR for local bus frequencies
+      lower than 66 MHz and uses I/O accessor functions consequently.
+
+    - UPM data update.
+
+    - Update of default environment and configuration.	Use I2C multibus
+      as we do have two I2C buses.  Also enable sdram and ext2 commands.
+
+    Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
+    Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
+    Signed-off-by: Detlev Zundel <dzu@denx.de>
+
+commit e8d18541c6ceab821f75faab031740b33fdbfa4b
+Author: Timur Tabi <timur@freescale.com>
+Date:	Fri Jul 18 16:52:23 2008 +0200
+
+    Update Freescale 85xx boards to sys_eeprom.c
+
+    The new sys_eeprom.c supports both the old CCID EEPROM format and the new NXID
+    format, and so it obsoletes board/freescale/common/cds_eeprom.c.  Freescale
+    86xx boards already use sys_eeprom.c, so this patch migrates the remaining
+    Freescale 85xx boards to use it as well.  cds_eeprom.c is deleted.
+
+    Signed-off-by: Timur Tabi <timur@freescale.com>
+
+commit aab2bf0202c86227e3dcc8a5b58946087ebcc1af
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Tue Sep 9 10:08:02 2008 +0200
+
+    lib_ppc/interrupts.c: make board_show_activity() a weak function
+
+    This allows to use show_activity() without having to
+    define an empty board_show_activity() function.
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit fe876787f8743883ce58fed61525eaa2f34da4c5
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Tue Sep 9 10:06:44 2008 +0200
+
+    stxxtc: remove empty CONFIG_SHOW_ACTIVITY functions
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 965de106ba8900372c8b16dc60d5acab7f925e38
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Tue Sep 9 10:03:47 2008 +0200
+
+    NETTA2: remove empty CONFIG_SHOW_ACTIVITY functions
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 6cc64f9b5f69239c8b1969572b5a3a4aab7de5b9
+Author: Sergei Poselenov <sposelenov@emcraft.com>
+Date:	Fri Aug 15 15:42:11 2008 +0200
+
+    Removed hardcoded MxMR loop value from upmconfig() for MPC85xx.
+
+    Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
+
+commit 36241ca29d4804a1006fb3f26069effda5202581
+Author: Anatolij Gustschin <agust@denx.de>
+Date:	Fri Aug 15 15:42:13 2008 +0200
+
+    85xx: socrates: Enable Lime support.
+
+    This patch adds Lime GDC support together with support for the PWM
+    backlight control through the w83782d chip.  The reset pin of the
+    latter is attached to GPIO, so we need to reset it in
+    early_board_init_r.
+
+    Signed-off-by: Anatolij Gustschin <agust@denx.de>
+
+commit 7a47753ddcaebbf2142809842f70c5f723bd9ddb
+Author: Detlev Zundel <dzu@denx.de>
+Date:	Fri Aug 15 15:42:12 2008 +0200
+
+    85xx: Socrates: Major code update.
+
+    - Update the local bus ranges in the FDT for Linux for the various
+      devices connected to the local bus via chip-select.
+
+    - Set the LCRR_DBYP bit in the LCRR for local bus frequencies
+      lower than 66 MHz and uses I/O accessor functions consequently.
+
+    - UPM data update.
+
+    - Update of default environment and configuration.	Use I2C multibus
+      as we do have two I2C buses.  Also enable sdram and ext2 commands.
+
+    Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
+    Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
+    Signed-off-by: Detlev Zundel <dzu@denx.de>
+
+commit 4d2ae70e8c31c22e5710df5ff236b5565ea2cf2c
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Tue Sep 9 01:22:39 2008 +0200
+
+    disk-on-chip: remove duplicate doc_probe declaration
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 3221b074a0ab199f6ae47c19cc22f42ddf3ef819
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Tue Sep 9 00:59:40 2008 +0200
+
+    onenand_uboot: fix warning: 'struct mtd_oob_ops' declared inside parameter list
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 13b4db0e2107175a8622ebb48529fa3ad8e12c75
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Tue Sep 9 00:59:39 2008 +0200
+
+    rs5c372: fix rtc_set prototype
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 1bb8b2ef2722bbaea3cc5d46321ce1d99f9b56f7
+Author: Sergei Poselenov <sposelenov@emcraft.com>
+Date:	Thu Aug 14 14:08:28 2008 +0200
+
+    ARM: fix warning: target CPU does not support interworking
+
+    This patch fixes warnings like this:
+
+    start.S:0: warning: target CPU does not support interworking
+
+    which come from some ARM cross compilers and are caused by hard-coded
+    (with "--with-cpu=arm9" configuration option) ARM targets (which
+    support ARM Thumb instructions), while the ARM target selected from
+    the command line (with "-march=armv4") doesn't support Thumb
+    instructions.
+
+    This warning is issued by the compiler regardless of the real use of
+    the Thumb instructions in code.
+
+    To fix this problem, we use options according to compiler version
+    being used.
+
+    Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 4265c35fbcb248e58179007621d61d32d0b3b82a
+Author: Sergei Poselenov <sposelenov@emcraft.com>
+Date:	Thu Aug 14 14:08:28 2008 +0200
+
+    ARM: Use do_div() instead of division for "long long".
+
+    Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 8febd13c69cb68652577d1a9fcbde954bf784155
+Author: Timur Tabi <timur@freescale.com>
+Date:	Fri Jul 18 16:52:23 2008 +0200
+
+    Update Freescale 85xx boards to sys_eeprom.c
+
+    The new sys_eeprom.c supports both the old CCID EEPROM format and the new NXID
+    format, and so it obsoletes board/freescale/common/cds_eeprom.c.  Freescale
+    86xx boards already use sys_eeprom.c, so this patch migrates the remaining
+    Freescale 85xx boards to use it as well.  cds_eeprom.c is deleted.
+
+    Signed-off-by: Timur Tabi <timur@freescale.com>
+
+commit 1055171ed05b7c4885737463d52b8d6c013bcb5d
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Mon Sep 8 23:26:22 2008 +0200
+
+    lib_arm/bootm.c: fix compile warnings
+
+    bootm.c:128: warning: label 'error' defined but not used
+    bootm.c:65: warning: unused variable 'ret'
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 2e3c867d0a63c563a51e65b776973b008f16cec5
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Mon Sep 8 22:46:42 2008 +0200
+
+    ml507: fix out of tree build problem
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 9863a15a98f23b79f34a0e4f9e465bc6df5d504d
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Mon Sep 8 22:10:28 2008 +0200
+
+    common/cmd_bootm.c: fix printf() format warnings
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 4394f9a8c42bb1b0abc4fc04bd582d4db5f8b726
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Mon Sep 8 22:37:45 2008 +0200
+
+    BMW, PCIPPC2, PCIPPC6, RBC82: fix compile warnings
+
+    missing doc_probe() prototype.
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 2c5e3cc4994897d364b148942ff23e47783198f6
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Mon Sep 8 21:28:14 2008 +0200
+
+    mk48t59: fix compile problem introduced by commit d1e23194
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 5ff889349d2ace13f10c9335e09365fcec8247cc
+Author: Stefan Roese <sr@denx.de>
+Date:	Mon Sep 8 14:11:12 2008 +0200
+
+    ppc4xx: Move ppc4xx specific prototypes to ppc4xx header
+
+    This patch moves some 4xx specific prototypes out of include common.h
+    to a ppc4xx specific header.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit ac53ee8318678190bf3c68da477a84a657d86fb0
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Fri Sep 5 15:34:04 2008 +0200
+
+    ppc4xx: Update CPCI405(AB) configuration
+
+    This patch add FDT support and command line editing capabilities
+    for CPCI405 and CPCI405AB boards.
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 7b1fbcadf73a83b3beb94abccda1c35e2c075a94
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Fri Sep 5 15:34:03 2008 +0200
+
+    ppc4xx: Cleanup CPCI405 linker script
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 767f9159c5c94cd0cb3135b5b82814ad12816ddf
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Fri Sep 5 15:34:02 2008 +0200
+
+    ppc4xx: Update CPCI405 variants handling
+
+    This patch replaces the BOARD_REVISION variable in include/config.mk
+    by a using a temporary include file in the platform directory.
+
+    The former way does not work anymore and the latter is also used by
+    some other boards.
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit f071f01fd09e9bf1cf09de37a7416aacce71bae1
+Author: Stefan Roese <sr@denx.de>
+Date:	Mon Sep 8 10:01:48 2008 +0200
+
+    ppc4xx: Remove CONFIG_CS8952_PHY define
+
+    Since this define is only used on one board that was never really in
+    production, removing this compile time option doesn't hurt and makes
+    the code more readable.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 6ca8646c1860bba74326bf916a5a3389a5c0d3b5
+Author: Stefan Roese <sr@denx.de>
+Date:	Fri Sep 5 14:11:40 2008 +0200
+
+    ppc4xx: Fix compilation warning for PIP405
+
+    This patch fixes a compilation warning for the PIP405 board. It moves the
+    #ifndef CONFIG_CS8952_PHY define a little so that the warning doesn't
+    occur anymore. I am a little unsure if this #ifdef is at the correct
+    place now or if it could be removed completely. This needs to get
+    tested on the PIP405 board.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 725b53ac61f4df3026b8f6489ef0080fd27d3816
+Author: Stefan Roese <sr@denx.de>
+Date:	Fri Sep 5 14:09:09 2008 +0200
+
+    ppc4xx: Fix compilation warning for canyonlands & glacier
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 302e52e0b1d4c7f994991709d0cb6c3ea612cdb5
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Fri Sep 5 14:40:29 2008 -0500
+
+    Fix compiler warning in mpc8xxx ddr code
+
+    ctrl_regs.c: In function 'compute_fsl_memctl_config_regs':
+    ctrl_regs.c:523: warning: 'caslat' may be used uninitialized in this function
+    ctrl_regs.c:523: note: 'caslat' was declared here
+
+    Add a warning in DDR1 case if cas_latency isn't a value we know about.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+    Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit d1e2319414ea5218ba801163e4530ecf2dfcbf36
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Mon Sep 1 23:06:23 2008 +0200
+
+    rtc: allow rtc_set to return an error and use it in cmd_date
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit ee9536a28cb149bcb6c5dee9d08c62c91f4c72d2
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Mon Sep 1 01:16:33 2008 +0200
+
+    ap325rxa/favr-32-ezkit: Use CONFIG_FLASH_CFI_DRIVER
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 6b971c73f182248ce103503d74fbc0100bb8c8b7
+Author: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
+Date:	Sun Aug 31 05:37:04 2008 +0900
+
+    config.mk: Move arch-specific condition to $(ARCH)_config.mk
+
+    Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
+
+commit ea86b9e64b811753d9eabe0f560ee189fbe5d0c1
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Fri Aug 29 19:08:29 2008 -0500
+
+    Prevent crash if random/invalid ramdisks are passed to bootm
+
+    Adds returning an error from the ramdisk detection code if
+    its not a real ramdisk (invalid).  There is no reason we can't
+    just return back to the console if we detect an invalid
+    ramdisk or CRC error.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 8e02494e8f86c8f2d7324b5eb9e75271104a01ef
+Author: Anatolij Gustschin <agust@denx.de>
+Date:	Fri Aug 29 21:04:45 2008 +0200
+
+    Prevent crash if random DTB address is passed to bootm
+
+    This patch adds bootm_start() return value check. If
+    error status is returned, we do not proceed further to
+    prevent board reset or crash as we still can recover
+    at this point.
+
+    Signed-off-by: Anatolij Gustschin <agust@denx.de>
+
+commit cc347801add2689b1ee54d21f62bc14ecf6e1dd8
+Author: Andrew Dyer <adyer@righthandtech.com>
+Date:	Fri Aug 29 12:30:39 2008 -0500
+
+    clean up some #if !defined() in drivers/video/cfb_console.c
+
+    rearrange some #if !defined() / #else / #endif statements to remove
+    the negative logic.
+
+    Signed-off-by: Andrew Dyer <adyer@righthandtech.com>
+
+commit c83f4c2d77f07174dcd6bef7e87a0f7017be7c33
+Author: Kyungmin Park <kmpark@infradead.org>
+Date:	Fri Aug 29 09:02:20 2008 +0900
+
+    apollon: use the last memory area for u-boot
+
+    Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
+
+commit a6f2e455b774d0c5d56e44e5661df9adb69b6e07
+Author: Heiko Schocher <hs@denx.de>
+Date:	Thu Aug 28 13:50:42 2008 +0200
+
+    TQM8272: move NAND part in seperate File
+
+    I didn't try to use drivers/mtd/nand/fsl_upm.c for the NAND driver,
+    because I have no longer access to the hardware.
+
+    Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit 584f979f7ee914e32d408739cbdd2c4457ec18b8
+Author: Heiko Schocher <hs@denx.de>
+Date:	Thu Aug 28 13:48:36 2008 +0200
+
+    TQM8272: Fix compiling error for the TQM8272 board.
+
+    Fix compile problems caused by
+    commit  cfa460adfdefcc30d104e1a9ee44994ee349bb7b
+
+    Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit 1a7f8ccec981648ccd38fca2535490582eee08e6
+Author: Kyungmin Park <kmpark@infradead.org>
+Date:	Wed Aug 27 14:45:20 2008 +0900
+
+    Add JFFS2 command support on OneNAND
+
+    Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
+
+commit f5c3ba79788b0e39baab7026d374fe375dd1a43f
+Author: Mark Jackson <mpfj@mimc.co.uk>
+Date:	Mon Aug 25 19:21:30 2008 +0100
+
+    Allow console input to be disabled
+
+    Added new CONFIG_DISABLE_CONSOLE define and GD_FLG_DISABLE_CONSOLE.
+
+    When CONFIG_DISABLE_CONSOLE is defined, setting
+    GD_FLG_DISABLE_CONSOLE disables all console input and output.
+
+    Signed-off-by: Mark Jackson <mpfj@mimc.co.uk>
+
+commit 2b22d608f370565c87f55928b524207031419c11
+Author: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es>
+Date:	Wed Jul 30 12:39:29 2008 +0200
+
+    loads: allow negative offsets
+
+    Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es>
+
+commit e90fb6afab2c0c074dfb67bacb4de179eb188a24
+Author: Yuri Tikhonov <yur@emcraft.com>
+Date:	Thu Sep 4 11:19:05 2008 +0200
+
+    USB EHCI: reset root hub
+
+    Some of multi-function USB controllers (e.g. ISP1562) allow root hub
+    resetting only via EHCI registers. So, this patch adds the
+    corresponding kind of reset to OHCI's hc_reset() if the newly
+    introduced CONFIG_PCI_EHCI_DEVNO option is set (e.g. for Socrates
+    board).
+
+    Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
+    Acked-by: Markus Klotzbuecher <mk@denx.de>
+
+commit 5875d358f025c1b042d8a0f08384b756de7256c9
+Author: Yuri Tikhonov <yur@emcraft.com>
+Date:	Fri Aug 15 15:42:09 2008 +0200
+
+    RX 8025 RTC: analyze 12/24-hour mode flag in rtc_get().
+
+    Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
+
+commit 3e3c026ed746a284c6f0ef139b26d859939de7e9
+Author: Stefan Roese <sr@denx.de>
+Date:	Fri Sep 5 10:47:46 2008 +0200
+
+    devices: Use list_add_tail() instead of list_add() to register a device
+
+    This patch fixes a problem spotted on Glacier/Canyonlands (and most
+    likely lots of other board ports), that no serial output was seen
+    after console initialization in console_init_r(). This is because the
+    last added console device was used instead of the first added.
+
+    This patch fixes this problem by using list_add_tail() instead of
+    list_add() to register a device. This way the first added console
+    is used again.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 78d78236896d62bb8ca7302af38d8f1493eb2651
+Author: Victor Gallardo <vgallardo@amcc.com>
+Date:	Thu Sep 4 23:49:36 2008 -0700
+
+    ppc4xx: Add support for GPCS, SGMII and M88E1112 PHY
+
+    This patch adds GPCS, SGMII and M88E1112 PHY support
+    for the AMCC PPC460GT/EX processors.
+
+    Signed-off-by: Victor Gallardo <vgallardo@amcc.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit f6b6c45840f9b4671d2d97243a12a1f3ffb64765
+Author: Adam Graham <agraham@amcc.com>
+Date:	Wed Sep 3 12:26:59 2008 -0700
+
+    ppc4xx: Update Kilauea to use PPC4xx DDR autocalibration routines
+
+    Signed-off-by: Adam Graham <agraham@amcc.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 075d0b81e896e8735ae26372cd384f87cbd24e41
+Author: Adam Graham <agraham@amcc.com>
+Date:	Wed Sep 3 12:26:28 2008 -0700
+
+    ppc4xx: IBM Memory Controller DDR autocalibration routines
+
+    Alternate SDRAM DDR autocalibration routine that can be generically used
+    for any PPC4xx chips that have the IBM SDRAM Controller core allowing for
+    support of more DIMM/memory chip vendors and gets the DDR autocalibration
+    values which give the best read latency performance (SDRAM0_RDCC.[RDSS]).
+
+    Two alternate SDRAM DDR autocalibration algoritm are provided in this patch,
+    "Method_A" and "Method_B".	DDR autocalibration Method_A scans the full range
+    of possible PPC4xx	SDRAM Controller DDR autocalibration values and takes a
+    lot longer to run than Method_B.  Method_B executes in the same amount of time
+    as the currently existing DDR autocalibration routine, i.e. 1 second or so.
+    Normally Method_B is used and it is set as the default method.
+
+    The current U-Boot PPC4xx DDR autocalibration code calibrates the IBM SDRAM
+    Controller registers.[bit-field]:
+    1)	SDRAM0_RQDC.[RQFD]
+    2)	SDRAM0_RFDC.[RFFD]
+
+    This alternate PPC4xx DDR autocalibration code calibrates the following
+    IBM SDRAM Controller registers.[bit-field]:
+
+    1)	SDRAM0_WRDTR.[WDTR]
+    2)	SDRAM0_CLKTR.[CKTR]
+    3)	SDRAM0_RQDC.[RQFD]
+    4)	SDRAM0_RFDC.[RFFD]
+
+    and will also use the calibrated settings of the above four registers that
+    produce the best "Read Sample Cycle Select" value in the SDRAM0_RDCC.[RDSS]
+    register.[bit-field].
+
+    Signed-off-by: Adam Graham <agraham@amcc.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit e07f4a8033b6270b8103049adb6456f660ff4a89
+Author: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es>
+Date:	Mon Sep 1 13:09:39 2008 -0400
+
+    ppc44x: Unification of virtex5 pp440 boards
+
+    This patch provides an unificated way of handling xilinx v5 ppc440 boards.
+
+    It unificates 3 different things:
+
+    1) Source code
+    A new board called ppc440-generic has been created. This board includes
+    a generic tlb initialization (Maps the whole memory into virtual) and
+    defines board_pre_init, checkboard, initdram and get_sys_info weakly,
+    so, they can be replaced by specific functions.
+
+    If a new board needs to redefine any of the previous functions
+    (specific initialization) it can create a new directory with the
+    specific initializations needed. (see the example ml507 board).
+
+    2) Configuration file
+    Common configurations are located under configs/xilinx-ppc440.h, this
+    header file interpretes the xparameters file generated by EDK and
+    configurates u-boot in correspondence. Example: if there is a Temac,
+    allows CMD_CONFIG_NET
+    Specific configuration are located under specific configuration file.
+    (see the example ml507 board)
+
+    3) Makefile
+    Some work has been done in order to not duplicate work in the Main
+    Makefile. Please see the attached code.
+
+    In order to support new boards they can be implemented in the next way:
+
+    a) Simple Generic Board  (90% of the time)
+    Using EDK generates a new xparameters.h file, replace
+    ppc440-generic/xparameters.h  and run make xilinx-ppc440-generic_config
+    && make
+
+    b) Simple Boards with special u-boot parameters (9 % of the time)
+    Create a new file under configs for it (use ml507.h as example) and
+    change your paramaters. Create a new Makefile paragraph and compile
+
+    c) Complex boards (1% of the time)
+    Create a new folder for the board, like the ml507
+
+    Finally, it adds support for the Avnet FX30T Evaluation board, following
+    the new generic structure:
+
+    Cheap board by Avnet for evaluating the Virtex5 FX technology.
+
+    This patch adds support for:
+     - UartLite
+     - 16MB Flash
+     - 64MB RAM
+
+    Prior using U-boot in this board, read carefully the ERRATA by Avnet
+    to solve some memory initialization issues.
+
+    Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 64ac1eb5afafced49b327425ad1814b2dc422d6e
+Author: Nick Spence <nick.spence@freescale.com>
+Date:	Tue Sep 2 15:21:16 2008 -0500
+
+    mpc83xx: fix mpc8313 in-tree building with NAND
+
+    and add mpc8313 NAND build to MAKEALL
+
+    Signed-off-by: Nick Spence <nick.spence@freescale.com>
+    Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit 6eb2a44e27919fdc601e0c05404b298a7602c0e3
+Author: Nick Spence <nick.spence@freescale.com>
+Date:	Thu Aug 28 14:09:25 2008 -0700
+
+    mpc83xx: clean up cache operations and unlock_ram_in_cache() functions
+
+    Cleans up some latent issues with the data cache control so that
+    dcache_enable() and dcache_disable() will work reliably (after
+    unlock_ram_in_cache() has been called)
+
+    Signed-off-by: Nick Spence <nick.spence@freescale.com>
+    Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit 46497056ae3b1e81e736e9cf3a170472c5d9719f
+Author: Nick Spence <nick.spence@freescale.com>
+Date:	Thu Aug 28 14:09:19 2008 -0700
+
+    mpc83xx: Store and display Arbiter Event Register values
+
+    Record the Arbiter Event Register values and optionally display them.
+
+    The Arbiter Event Register can record the type and effective address of
+    an arbiter error, even through an HRESET. This patch stores the values in
+    the global data structure.
+
+    Display of the Arbiter Event registers immediately after the RSR value
+    can be enabled with defines. The Arbiter values will only be displayed
+    if an arbiter event has occured since the last Power On Reset, and either
+    of the following defines exist:
+     #define CONFIG_DISPLAY_AER_BRIEF - display only the arbiter address and
+					and type register values
+     #define CONFIG_DISPLAY_AER_FULL  - display and interpret the arbiter
+					event register values
+
+    Address Only transactions are one of the trapped events that can register
+    as an arbiter event. They occur with some cache manipulation instructions
+    if the HID0_ABE (Address Broadcast Enable) is set and the memory region
+    has the MEMORY_COHERENCE WIMG bit set. Setting:
+     #define CONFIG_MASK_AER_AO - prevents the arbiter from recording address
+				  only events, so that it can still capture
+				  other real problems.
+
+    Signed-off-by: Nick Spence <nick.spence@freescale.com>
+    Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit ade50c7fa1b16ef98be17e9c3ae286aecf4f5605
+Author: Nick Spence <nick.spence@freescale.com>
+Date:	Thu Aug 28 14:09:11 2008 -0700
+
+    mpc83xx: use r4 instead of r2 in lock_ram_in_cache and unlock_ram_in_cache
+
+    This is needed in unlock_ram_in_cache() because it is called from C and
+    will corrupt the small data area anchor that is kept in R2.
+
+    lock_ram_in_cache() is modified similarly as good coding practice, but
+    is not called from C.
+
+    Signed-off-by: Nick Spence <nick.spence@freescale.com>
+    Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit d9fe88173cb4f7d293796ffe10c7a0d3d426d8f9
+Author: Nick Spence <nick.spence@freescale.com>
+Date:	Fri Aug 22 23:52:50 2008 -0700
+
+    MPC83XX: Fix GPIO configuration - set gpio level before direction
+
+    Set DAT value before DIR values to avoid creating glitches on the
+    GPIO signals.
+
+    Set gpio level register before direction register to inhibit
+    glitches on high level output pins.
+
+    Dir and data gets cleared at powerup, so high level output lines see
+    a short low pulse between setting the direction and level registers.
+
+    Issue was seen on a new board with the nReset line of the NOR flash
+    connected to a GPIO. Setting the direction register puts the NOR flash
+    in reset so the next instruction to set the level cannot get executed.
+
+    Signed-off-by: Nick Spence <nick.spence@freescale.com>
+    Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
+    Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit 7007c5975ee900ad70983b0681d3251e221f8321
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Tue Sep 2 02:58:32 2008 +0200
+
+    doc/qemu_mips: add doc howto debug u-boot with gdb
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 7deb3b3ecd0e81ef09bb68aa0ec2346f4ae0a405
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Wed Sep 3 17:15:45 2008 +0200
+
+    ppx4xx: Fix broken DASA_SIM board
+
+    This patch adds initdram() to DASA_SIM boards that has been
+    removed accidentally by a previous commit.
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 7e410aa30fbcb1d19a26bbf1e84a9ca6102d534b
+Author: Stefan Roese <sr@denx.de>
+Date:	Mon Sep 1 08:35:37 2008 +0200
+
+    ppc4xx: Remove reference to common/lists.o from some esd linker scripts
+
+    This patch removes some direct references to common/lists.o from some
+    esd linker scripts. This is necessary because the lists source was moved
+    and is not in the "common" directory anymore.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 97b0734d65f8a0b03df0a335a2addc759da56107
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Tue Sep 2 16:33:05 2008 +0200
+
+    ppc4xx: Remove obsolete or unused functions from some esd boards
+
+    This patch removes initdram() and testdram() from most esd 405 platforms.
+    Some boards also have an empty dummy implementation of
+    misc_init_f(). This is also removed.
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 1092ce218c514e5ccb18450ac5af501d96d6e3e9
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Tue Sep 2 15:07:54 2008 +0200
+
+    ppc4xx: Update VOM405 board configuration
+
+    - remove PCI code
+    - add command line editing
+    - minor cleanup
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 830c800e28e96ec7c3c6936a0bd1b9461f3e77d4
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Tue Sep 2 15:07:53 2008 +0200
+
+    ppc4xx: Remove obsolete initdram() function from VOM405 board
+
+    This patch removed the obsolete initdram() function from
+    VOM405 platform file.
+
+    Some minor cleanup.
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 3d4dd7a941b2327b8c2fc535b782ca307ff8b6c8
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Tue Sep 2 15:07:52 2008 +0200
+
+    ppc4xx: Cleanup VOM405 linker script
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit fcaffd597f6f5191b12ca66c2a4789bbdeea85c2
+Author: Matthias Fuchs <mf@esd.eu>
+Date:	Tue Sep 2 15:07:51 2008 +0200
+
+    ppc4xx: Add fdt support for VOM405 boards
+
+    Signed-off-by: Matthias Fuchs <mf@esd.eu>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 9ec367aa2c5dcf79558aa2b209b45d7686654c14
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Tue Sep 2 11:36:14 2008 +0200
+
+    ppc4xx: Coding style cleanup
+
+    Wrap long lines etc.
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 17e65c21adfb63980e6aff80bfbd2df0eeb12060
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Tue Sep 2 11:35:56 2008 +0200
+
+    ppc4xx: Enable USB on PLU405 boards
+
+    This patch enables the PCI-OHCI controller on PLU405 board.
+
+    Also the default CPU frequency is updated to 266 MHz and
+    command line editing is enabled.
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 40e43e3b87d57b2ac786e27f6e25a7df9940d93b
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Tue Sep 2 11:35:35 2008 +0200
+
+    ppc4xx: Cleanup PLU405 platform file
+
+    This patch
+    - wraps some long lines
+    - removes unused/obsolete functions: misc_init_f() and initdram()
+
+    Signed-off-by: Matthias Fuchs <mf@esd.eu>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit d74cdb1d0614ab78128e0735a51e7988a7b7ea33
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Tue Sep 2 11:35:04 2008 +0200
+
+    ppc4xx: Cleanup PLU405 linker script
+
+    Signed-off-by: Matthias Fuchs <mf@esd.eu>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 3bc1054cec2f6b25822f301ea922a16233baa4c7
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Tue Sep 2 11:34:36 2008 +0200
+
+    ppc4xx: Add fdt support for PLU405 boards
+
+    Signed-off-by: Matthias Fuchs <mf@esd.eu>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 5a3e480b783bfbc139586293a54fb875d7c5c5d4
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Tue Sep 2 11:34:08 2008 +0200
+
+    ppc4xx: Increase U-Boot size to 384kB for PLU405 boards
+
+    Signed-off-by: Matthias Fuchs <mf@esd.eu>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit be1b0d2777e179191a57b138b660547a17e55aad
+Author: Jochen Friedrich <jochen@scram.de>
+Date:	Tue Sep 2 11:24:59 2008 +0200
+
+    Don't tftp to unknown flash
+
+    If a board has a variable number of flash banks, there are empty entries
+    in flash_info[] and CFG_DIRECT_FLASH_TFTP is set, tftp boot fails with
+    "Outside available Flash". This patch skips flash banks with unknown
+    flash ids.
+
+    Signed-off-by: Jochen Friedrich <jochen@scram.de>
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 33314470ab32a3f5412bb61b5f3d6c216c88bf9b
+Author: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+Date:	Thu Aug 28 13:40:44 2008 +0900
+
+    net: smc911x: Add pkt_data_pull and pkt_data_push function
+
+    The RSK7203 board has the SMSC9118 wired up 'incorrectly'.
+    Byte-swapping is necessary, and so poor performance is inevitable.
+    This problem cannot evade by the swap function of CHIP, this can
+    evade by software Byte-swapping.
+    And this has problem by FIFO access only. pkt_data_pull/pkt_data_push
+    functions necessary to solve this problem.
+
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 10efa024b8ffd9e6aaca63da8bddfdffdc672274
+Author: Ben Warren <biggerbadderben@gmail.com>
+Date:	Sun Aug 31 20:37:00 2008 -0700
+
+    Moved initialization of EEPRO100 Ethernet controller to board_eth_init()
+
+    Affected boards:
+	db64360
+	db64460
+	katmai
+	taihu
+	taishan
+	yucca
+	cpc45
+	cpu87
+	eXalion
+	elppc
+	debris
+	kvme080
+	mpc8315erdb
+	integratorap
+	ixdp425
+	oxc
+	pm826
+	pm828
+	pm854
+	pm856
+	ppmc7xx
+	sc3
+	sc520_spunk
+	sorcery
+	tqm8272
+	tqm85xx
+	utx8245
+
+    Removed initialization of the driver from net/eth.c
+    Also, wrapped contents of pci_eth_init() by CONFIG_PCI.
+
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 8ca0b3f99c4fce7a599dcaf92ae095496dc8c8e0
+Author: Ben Warren <biggerbadderben@gmail.com>
+Date:	Sun Aug 31 10:45:44 2008 -0700
+
+    Moved initialization of TULIP Ethernet controller to board_eth_init()
+
+    Affected boards:
+	cu824
+	bab7xx
+	adciop
+	dasa_sim
+	mousse
+	mpc8540eval
+	musenki
+	mvblue
+	pcippc2/pcippc6
+	sbc8240
+	stxssa
+
+    Removed initialization of the driver from net/eth.c
+
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit ad3381cf4167120db5c7b88e4970245e1d5c0a32
+Author: Ben Warren <biggerbadderben@gmail.com>
+Date:	Sun Aug 31 10:44:19 2008 -0700
+
+    Moved initialization of E1000 Ethernet controller to board_eth_init()
+
+    Affected boards:
+	ap1000
+	mvbc_p
+	PM854
+
+    Removed initialization of the driver from net/eth.c
+
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 4fce2aceaf8afd31a252bc782c9dbc497bf40487
+Author: Ben Warren <biggerbadderben@gmail.com>
+Date:	Sun Aug 31 10:40:51 2008 -0700
+
+    Moved initialization of plb2800 Ethernet driver to board_eth_init
+
+    Affected boards:
+	purple
+
+    Removed initialization of controller from net/eth.c
+
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit e1d7480b5de1fd4830bf7cf5e2237d3b0846d08d
+Author: Ben Warren <biggerbadderben@gmail.com>
+Date:	Sun Aug 31 10:39:12 2008 -0700
+
+    Moved initialization of MPC5xxx_FEC Ethernet driver to CPU directory
+
+    Modified board_eth_init() functions of boards that have this FEC in addition
+    to other Ethernet controllers.
+
+    Affected boards:
+	bc3450
+	icecube
+	mvbc_p
+	o2dnt
+	pm520
+	total5200
+	tq5200
+
+    Removed initialization of controller from net/eth.c
+
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit a0aad08f9427ac00218bdb2cb649833ce6ec9b8d
+Author: Ben Warren <biggerbadderben@gmail.com>
+Date:	Sun Aug 31 10:36:38 2008 -0700
+
+    Moved initialization of MPC512x_FEC Ethernet driver to CPU directory
+
+    Added a cpu_eth_init() function to MPC512x CPU directory and
+    removed code from net/eth.c
+
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 8218bd2aa68820b878a8413493ae17fd8d21f944
+Author: Ben Warren <biggerbadderben@gmail.com>
+Date:	Sun Aug 31 10:16:59 2008 -0700
+
+    Moved initialization of IncaIP Ethernet controller to board_eth_init
+
+    Affected boards:
+	IncaIP
+
+    Removed initialization of the driver from net/eth.c
+
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 164846eeb25cb2a5ede7ab9371fdca7f4831a055
+Author: Ben Warren <biggerbadderben@gmail.com>
+Date:	Sun Aug 31 10:15:26 2008 -0700
+
+    Moved initialization of 3COM Ethernet controller (AmigaOne) to board_eth_init()
+
+	Affected boards:
+	    AmigaOneG3SE
+
+	Removed initialization of the driver from net/eth.c
+
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 6aca145e067efe75398e9fac97822bd3700de0b2
+Author: Ben Warren <biggerbadderben@gmail.com>
+Date:	Sun Aug 31 10:13:34 2008 -0700
+
+    Moved initialization of GT6426x Ethernet controller to board_eth_init()
+
+    Affected boards:
+	EVB64260
+	P3G4
+	ZUMA
+
+    Removed initialization of the driver from net/eth.c
+
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit e3090534d62045dcb73f5392bacc64a4e8e443dc
+Author: Ben Warren <biggerbadderben@gmail.com>
+Date:	Sun Aug 31 10:08:43 2008 -0700
+
+    Moved initialization of PCNET Ethernet controller to board_eth_init()
+
+    Affected boards:
+	PN62
+	sc520_cdp
+
+    Removed initialization of the driver from net/eth.c
+
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit b902b8dda5e1fd4d5fe2f202c71ee3521d2c40ed
+Author: Ben Warren <biggerbadderben@gmail.com>
+Date:	Sun Aug 31 10:07:16 2008 -0700
+
+    Moved initialization of NATSEMI Ethernet controller to board_eth_init()
+
+    Affected boards:
+	a3000
+
+    Removed initialization of the driver from net/eth.c
+
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 19403633dd70333893c2da7926a1d0dcd6dab7d8
+Author: Ben Warren <biggerbadderben@gmail.com>
+Date:	Sun Aug 31 10:03:22 2008 -0700
+
+    Moved initialization of NS8382X Ethernet controller to board_eth_init()
+
+    Affected boards:
+	bc3450
+	cpci5200
+	mecp5200
+	pf2000
+	icecube
+	o2dnt
+	pm520
+	sandpoint8245
+	total5200
+	tqm5200
+
+    Removed initialization of the driver from net/eth.c
+
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit ccdd12f83ef93719fbe85f642aa4dc648b9498f0
+Author: Ben Warren <biggerbadderben@gmail.com>
+Date:	Sun Aug 31 09:59:33 2008 -0700
+
+    Moved initialization of TSI108 Ethernet controller to board_eth_init()
+
+    Affected boards:
+	mpc7448hpc2
+
+    Removed initialization of the driver from net/eth.c
+
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 0b252f50ae218ae15bfb63af44227972686ebc56
+Author: Ben Warren <biggerbadderben@gmail.com>
+Date:	Sun Aug 31 21:41:08 2008 -0700
+
+    Moved initialization of RTL8139 Ethernet controller to board_eth_init()
+
+    Affected boards:
+	hidden_dragon
+	MPC8544DS
+	MPC8610HPCN
+	R2DPLUS
+	TB0229
+
+    Removed initialization of the driver from net/eth.c
+
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 02d69891d95ee76b0e86e1715a4dc0b964a57cb7
+Author: Ben Warren <biggerbadderben@gmail.com>
+Date:	Sun Aug 31 09:49:42 2008 -0700
+
+    Moved initialization of RTL8169 Ethernet controller to board_eth_init()
+
+    Affected boards:
+	linkstation
+	r7780mp
+
+    Removed initialization of the driver from net/eth.c
+
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 3ae071e44256144d6c1e3febb65f6c56bd433769
+Author: Ben Warren <biggerbadderben@gmail.com>
+Date:	Tue Aug 12 22:11:53 2008 -0700
+
+    Moved initialization of Ethernet controllers on Atmel AT91 to board_eth_init()
+
+    Removed at91sam9_eth_initialize() from net/eth.c
+
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 89973f8a82c28ad893c4c3cc56839a8e10fe5f13
+Author: Ben Warren <biggerbadderben@gmail.com>
+Date:	Sun Aug 31 22:22:04 2008 -0700
+
+    Introduce netdev.h header file and remove externs
+
+    This addresses all drivers whose initializers have already
+    been moved to board_eth_init()/cpu_eth_init().
+
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 5a8a163ac394d9f4f7ff57f415d82bd673b0068c
+Author: Andy Fleming <afleming@freescale.com>
+Date:	Sun Aug 31 16:33:30 2008 -0500
+
+    Add pixis_set_sgmii command
+
+    The 8544DS and 8572DS platforms support an optional SGMII riser card to
+    expose ethernet over an SGMII interface.  Once the card is in, it is also
+    necessary to configure the board such that it uses the card, rather than
+    the on-board ethernet ports.  This can either be done by flipping dip switches
+    on the motherboard, or by modifying registers in the pixis.  Either way
+    requires a reboot.
+
+    This adds a command to allow users to choose which ports are routed through
+    the SGMII card, and which through the onboard ports.  It also allows users
+    to revert to the current switch settings.
+
+    This code does not work on the 8572, as the PIXIS is different.
+
+    Signed-off-by: Andy Fleming <afleming@freescale.com>
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 216f2a7156a5fde7b47adc40ad553c888a9cbaa7
+Author: Andy Fleming <afleming@freescale.com>
+Date:	Sun Aug 31 16:33:29 2008 -0500
+
+    Add SGMII support for the 8544 DS
+
+    The 8544 DS has an optional SGMII Riser card, which uses different PHY
+    addresses.	Check if we are in SGMII mode, and invoke the SGMII Riser
+    setup code if so.
+
+    Signed-off-by: Andy Fleming <afleming@freescale.com>
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 652f7c2eef76a1340928bd660845441e932d86a2
+Author: Andy Fleming <afleming@freescale.com>
+Date:	Sun Aug 31 16:33:28 2008 -0500
+
+    Add support for Freescale SGMII Riser Card
+
+    The 8544DS and 8572DS systems have an optional SGMII riser card which
+    exposes new ethernet ports which are connected to the eTSECs via an
+    SGMII interface.  The SGMII PHYs for this board are offset from the standard
+    PHY addresses, so this code modifies the passed in tsec_info structure to
+    use the SGMII PHYs on the card, instead.
+
+    Signed-off-by: Andy Fleming <afleming@freescale.com>
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 2abe361c03b43e6dcf68f54e96b5c05156c49284
+Author: Andy Fleming <afleming@freescale.com>
+Date:	Sun Aug 31 16:33:27 2008 -0500
+
+    Add SGMII support to the tsec
+
+    Adds support for configuring the TBI to talk properly with the SerDes.
+
+    Signed-off-by: Andy Fleming <afleming@freescale.com>
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 75b9d4ae0d69f214eab641caf12ce8af83a39a42
+Author: Andy Fleming <afleming@freescale.com>
+Date:	Sun Aug 31 16:33:26 2008 -0500
+
+    Pass in tsec_info struct through tsec_initialize
+
+    The tsec driver contains a hard-coded array of configuration information
+    for the tsec ethernet controllers.	We create a default function that works
+    for most tsecs, and allow that to be overridden by board code.  It creates
+    an array of tsec_info structures, which are then parsed by the corresponding
+    driver instance to determine configuration.  Also, add regs, miiregs, and
+    devname fields to the tsec_info structure, so that we don't need the kludgy
+    "index" parameter.
+
+    Signed-off-by: Andy Fleming <afleming@freescale.com>
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit dd3d1f56a01f460d560766126ee7dfed2ea9bc10
+Author: Andy Fleming <afleming@freescale.com>
+Date:	Sun Aug 31 16:33:25 2008 -0500
+
+    tsec: Move tsec.h to include/
+
+    This is to prepare the way for board code passing in the tsec_info structure
+
+    Signed-off-by: Andy Fleming <afleming@freescale.com>
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit d23dc394aa69093b6326ad917db04dc0d1aff3f8
+Author: Sergei Poselenov <sposelenov@emcraft.com>
+Date:	Fri Jun 6 15:52:44 2008 +0200
+
+    PHY: Add support for the M88E1121R Marvell chip.
+
+    Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
+    Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 1711f3bd16d1c5e9d17b4c0198b426d86999781b
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Tue Sep 2 21:17:36 2008 +0200
+
+    fw_env.c: fix build problems with MTD_VERSION=old
+
+    (as needed to support old 2.4 Linux kernel based releases)
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 628ffd73bcff0c9f3bc5a8eeb2c7455fe9d28a51
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Mon Sep 1 17:11:26 2008 +0200
+
+    device: make device_register() clone the device
+
+    This is expected by the callers, but this fact was hidden well within
+    the old list implementation.
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit c75e772a2f061a508bba28ded1b5bea91f0442b0
+Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Date:	Sun Aug 31 23:28:15 2008 +0900
+
+    sh: Remove CC line from board's Makefile
+
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit 468eae0660de6fdfd9999944c536ecc4797bd944
+Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Date:	Sun Aug 31 23:25:57 2008 +0900
+
+    sh: Replaced "@./mkconfig" for @$(MKCONFIG)
+
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit 3aeb1ff7482a732503186c742d3a5ded4b7a0d34
+Author: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+Date:	Thu Aug 28 14:50:52 2008 +0900
+
+    sh: Add support sh2 to MAKEALL
+
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit 6f3d8bb5faa12dbf3031382286784c978df038ee
+Author: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+Date:	Thu Aug 28 14:52:23 2008 +0900
+
+    sh: Fix compile error rsk7203 board
+
+    This boards used old type preprocessor.
+    This patch fix compile error.
+
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit 1c98172e025018552e9bb4c43b0aaee76f79b1aa
+Author: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+Date:	Thu Aug 28 14:53:31 2008 +0900
+
+    sh: Fix compile error sh7785lcr board
+
+    This boards used old type preprocessor.
+    This patch fix compile error.
+
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit 6f0da4972e48f99d37bc522814940a6022cd3084
+Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Date:	Fri Aug 22 17:39:09 2008 +0900
+
+    sh: Renesas Solutions AP325RXA board support
+
+    AP325RXA is SH7723's reference board.
+    This has SCIF, NOR Flash, Ethernet, USB host, LCDC, SD Host, Camera and other.
+    In this patch, support SCIF, NOR Flash, and Ethernet.
+
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit ab09f433b50bb83b5e440c335bc3839ee069e534
+Author: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+Date:	Fri Aug 22 17:48:51 2008 +0900
+
+    sh: add support Renesas SH7723
+
+    Renesas SH7723 has 5 SCIF, SD, Camera, LCDC and other.
+    This patch supports CPU register's header file and SCIF serial driver.
+
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit c655fad06ba3fb042dbc667724a40e1a9a091248
+Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Date:	Sun Aug 31 23:02:04 2008 +0900
+
+    sh: Renesas RSK+ 7203 board support
+
+    This adds initial support for the RTE RSK+ SH7203 board.
+
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit 6ede753ddf52a7b0f992d9bccbe5e4a0968ca475
+Author: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+Date:	Thu Jul 3 23:11:02 2008 +0900
+
+    sh: Add support Renesas SH7203 processor
+
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit 6ad43d0dd86b612895ddc7f480eb6cdfe793adf9
+Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Date:	Sun Aug 31 22:48:33 2008 +0900
+
+    sh: Add support SH2/SH2A which is CPU of Renesas Technology
+
+    Add support SH2/SH2A basic function.
+
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit 0d53a47dc0737b6aa3a39caee21410c169441ae5
+Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Date:	Sun Aug 31 22:45:08 2008 +0900
+
+    sh: Renesas R0P7785LC0011RL board support
+
+    This board has SH7785, 512MB DDR2-SDRAM, NOR Flash,
+    Graphic, Ethernet, USB, SD, RTC, and I2C controller.
+
+    This patch supports the following functions:
+     - 128MB DDR2-SDRAM (29-bit address mode only)
+     - NOR Flash
+     - USB host
+     - Ethernet
+
+    Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit b0b6218929bc7de9a6bdb8e564fa8ec2efa71b4e
+Author: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+Date:	Thu Jul 10 19:32:53 2008 +0900
+
+    sh: add support for SH7785
+
+    Renesas SH7785 has DDR2-SDRAM controller, PCI, and other.
+    This patch supports CPU register's header file.
+
+    Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+    Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit d6e04258be8f2408845468d3cf722a4cf0433445
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Sun Aug 31 04:45:42 2008 +0200
+
+    davinci: fix remaining dm644x_eth
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 08ab4e1780fa63c88dd5a5ab52f4ff4ed1ee1878
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Sun Aug 31 04:24:56 2008 +0200
+
+    fs: Move conditional compilation to Makefile
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit c1de7a6daf9c657484e1c6d433f01fccd49a7f48
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Sun Aug 31 04:24:55 2008 +0200
+
+    devices: merge to list_head
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit ef0255fc75f28655f9681422079287d68a14dbaa
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Sun Aug 31 04:24:51 2008 +0200
+
+    update linux/list
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 71cb31227bee741b274f6c0279b2aac1ab8e28e3
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Sun Aug 31 00:39:48 2008 +0200
+
+    smdk6400: add gitignore
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit f9f692e2b146d4e306b777e6d5f69f1d725b9eb9
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Sun Aug 31 00:39:48 2008 +0200
+
+    smdk6400: Use CONFIG_FLASH_CFI_DRIVER
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 7c0e5a8db3d1358b0ce3cc85ada0de6341ca4a15
+Author: Guennadi Liakhovetski <lg@denx.de>
+Date:	Sun Aug 31 00:39:47 2008 +0200
+
+    smdk6400: remove redundant bootargs definition
+
+    Double bootargs setting leads to a duplicated environmant entry.
+
+    Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
+
+commit 11edcfe260f20dcea79284a3e95270989d433854
+Author: Guennadi Liakhovetski <lg@denx.de>
+Date:	Sun Aug 31 00:39:47 2008 +0200
+
+    ARM: Add support for S3C6400 based SMDK6400 board
+
+    SMDK6400 can only boot U-Boot from NAND-flash. This patch adds a nand_spl
+    driver for it too. The board can also boot from the NOR flash, but due to
+    hardware limitations it can only address 64KiB on it, which is not enough
+    for U-Boot. Based on the original sources by Samsung for U-Boot 1.1.6.
+
+    Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
+
+commit e0056b341069796eaea11eae0fc8eb93a3dceaac
+Author: Guennadi Liakhovetski <lg@denx.de>
+Date:	Sun Aug 31 00:39:47 2008 +0200
+
+    NAND: add NAND driver for S3C64XX
+
+    Based on the original S3C64XX NAND driver by Samsung for U-Boot 1.1.6.
+
+    Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
+
+commit 3fe7b589f9c7463df39056f8872006a67f56a91c
+Author: Guennadi Liakhovetski <lg@denx.de>
+Date:	Sun Aug 31 00:39:47 2008 +0200
+
+    S3C64XX: remove broken HWFLOW support from the serial driver
+
+    As noted by Harald Welte, HWFLOW support in the S3C64XX serial driver is
+    broken and currently unused. Remove it.
+
+    Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
+
+commit 2fb28dcf82048045e1bf5014e938e486fa6c2383
+Author: Guennadi Liakhovetski <lg@denx.de>
+Date:	Sun Aug 31 00:39:47 2008 +0200
+
+    serial: add S3C64XX serial driver
+
+    Based on the original S3C64XX UART driver by Samsung for U-Boot 1.1.6.
+
+    Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
+
+commit 8262813ca04fc57f5d8856e1828085c136e0f1eb
+Author: Guennadi Liakhovetski <lg@denx.de>
+Date:	Sun Aug 31 00:39:46 2008 +0200
+
+    USB: Add support for OHCI controller on S3C6400
+
+    Notice: USB on S3C6400 currently works _only_ with switched off MMU. One could
+    try to enable the MMU, but map addresses 1-to-1, and disable data cache, then
+    it should work too and we could still profit from instruction cache.
+
+    Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
+
+commit 9b07773f8883665b002500c190507e9fd99b7181
+Author: Guennadi Liakhovetski <lg@denx.de>
+Date:	Sun Aug 31 00:39:46 2008 +0200
+
+    ARM: Add arm1176 core with S3C6400 SoC
+
+    Based on the original S3C64XX port by Samsung for U-Boot 1.1.6.
+
+    Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
+
+commit fcaac589a68115819ddadcf5c18ded9a5f9e2c75
+Author: Sandeep Paulraj <s-paulraj@ti.com>
+Date:	Sun Aug 31 00:39:46 2008 +0200
+
+    ARM DaVinci: Changing function names for EMAC driver
+
+    DM644x is just one of a series of DaVinci chips that use the EMAC driver.
+    By replacing all the function names that start with dm644x_* to davinci_*
+    we make these function more portable. I have tested this change on my EVM.
+    DM6467 is another DaVinci SOC which uses the EMAC driver and i will
+    be sending patches that add DaVinci DM6467 support to the list soon.
+
+    Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
+
+commit fbbb1de369ca7d5ace6f7b0ce9d0aee24a6f457b
+Author: Gururaja Hebbar K R <gururajakr@sanyo.co.in>
+Date:	Sat Aug 30 23:21:30 2008 +0200
+
+    Integrator[AP/CP] - Remove unused file memsetup.S
+
+    - memsetup.s is changed/merged to lowlevel_init.S
+      memsetup.S has a global label memsetup that just returns back to caller
+    - memsetup global label is changed/merged to lowlevel_init
+      This label is not called from anywhere.
+
+    Signed-off-by: Gururaja Hebbar <gururajakr@sanyo.co.in>
+
+commit 89d51d022a63be1a851eda983c8cbce1a044f65f
+Author: Hugo Villeneuve <hugo.villeneuve@lyrtech.com>
+Date:	Wed Aug 27 21:35:52 2008 +0200
+
+    ARM DaVinci: Standardize names of directories/files
+
+    ARM DaVinci: Standardize names of directories/files.
+
+    Signed-off-by: Hugo Villeneuve <hugo.villeneuve@lyrtech.com>
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 264bbdd11d01f14f5ea4629556ae63b00b13402d
+Author: Hugo Villeneuve <hugo.villeneuve@lyrtech.com>
+Date:	Fri Jul 11 15:10:13 2008 -0400
+
+    ARM DaVinci: Move common functions to board/davinci/common
+
+    ARM DaVinci: Move common functions to board/davinci/common.
+
+    Signed-off-by: Hugo Villeneuve <hugo.villeneuve@lyrtech.com>
+
+commit c2b4b2e4814f4ace9015fdb64132894327400bf0
+Author: Stefan Roese <sr@denx.de>
+Date:	Fri Aug 29 11:56:49 2008 +0200
+
+    ppc4xx/NAND: Add select_chip function to 4xx NDFC driver
+
+    This function is needed for the new NAND infrastructure. We only need
+    a dummy implementation though for the NDFC.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 3d4a746e2fb4545f07d871049805fb34ae97cc94
+Author: Stefan Roese <sr@denx.de>
+Date:	Fri Aug 29 12:06:27 2008 +0200
+
+    ppc4xx: Increase image size for NAND boot target
+
+    This is needed since now with HUSH enabled (amcc-common.h) the image
+    read from NAND exceeds the previous limit.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 6b5049d056cd8ef72d1f2f461ceb2d033d93f759
+Author: Ben Warren <biggerbadderben@gmail.com>
+Date:	Thu Aug 28 23:58:30 2008 -0700
+
+    Move MPC512x_FEC driver to drivers/net
+
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 80b00af01b3c9154774de2936f05a051e92f6a03
+Author: Ben Warren <biggerbadderben@gmail.com>
+Date:	Thu Aug 28 23:58:29 2008 -0700
+
+    Move MPC5xxx_FEC driver to drivers/net
+
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 3de7bf0e6b1ad2608014096c8192f13229b2e9d7
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Fri Aug 29 21:53:57 2008 +0200
+
+    cmd_terminal: remove no need ifdef
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 578118bdf122877ae769776be002255be447b4fa
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Fri Aug 29 21:53:57 2008 +0200
+
+    common/Makefile: order by functionality
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit ba7b5b2348b684cf8ec424b2e38e267dc1cfd2fb
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Fri Aug 29 21:53:56 2008 +0200
+
+    miiphyutil: Move conditional compilation to Makefile
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 81789c39db3f0f6b621df8c0ec66014d701f368e
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Fri Aug 29 21:53:37 2008 +0200
+
+    autoscript: Move conditional compilation to Makefile
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit bbf52df9aa94ffb115b8b1ebeb00d01374bb0a1d
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Fri Aug 29 01:18:11 2008 +0200
+
+    crc16: move to lib_generic
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 55195773eacefb22dd483a3c560ea30a14263ce1
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Fri Aug 29 01:18:01 2008 +0200
+
+    miiphybb: move to drivers/net/phy
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit e8314035996a9118ac5948df2ff8a2f2161ed67a
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Thu Aug 28 12:31:51 2008 +0200
+
+    soft_spi: move to drivers/spi
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 4d75e0aa9caca64d4a1d55d95cd1ca5f30d9fc56
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Thu Aug 28 12:31:51 2008 +0200
+
+    soft_i2c: move to drivers/i2c
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 717a222229fdb77703e9174d0eb08a4b41febf49
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Thu Aug 28 12:31:48 2008 +0200
+
+    gunzip: move to lib_generic
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 52aef8f9ba28b747973bf76741c23db658d5773c
+Author: Wolfgang Ocker <weo@reccoware.de>
+Date:	Tue Aug 26 19:55:23 2008 +0200
+
+    ppc4xx: NAND configuration
+
+    Made NAND bank configuration setting a config variable.
+
+    Signed-off-by: Wolfgang Ocker <weo@reccoware.de>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 5bc542a593abc9e974fbd34704af85c37c366c60
+Author: Victor Gallardo <vgallardo@amcc.com>
+Date:	Thu Aug 28 16:03:28 2008 -0700
+
+    ppc4xx: fix UIC external_interrupt hang on UIC0
+
+    This patch fixes a UIC external_interrupt hang if critical or non-critical
+    interrupt is set at the same time as a normal interrupt is set on UIC0.
+
+    Signed-off-by: Victor Gallardo <vgallardo@amcc.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 04737d5ffd16248cb80ab3dd4f3765057a803f18
+Author: Prodyut  Hazarika <phazarika@amcc.com>
+Date:	Wed Aug 27 16:39:00 2008 -0700
+
+    ppc4xx: Optimizations/Cleanups for IBM DDR2 Memory Controller
+
+    Removed Magic numbers from Initialization preload registers
+    Tested with Kilauea, Glacier, Canyonlands and Katmai boards
+    About 5-7% improvement seen for LMBench memtests
+
+    Signed-off-by: Prodyut Hazarika <phazarika@amcc.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 8a490422bed685c9491274ec997f62061d88620b
+Author: John Rigby <jrigby@freescale.com>
+Date:	Thu Aug 28 13:17:07 2008 -0600
+
+    ADS5121: Fix NOR and CPLD ALE timing for rev 2 silicon
+
+    MPC5121 rev 2 silicon has a new register for controlling how long
+    CS is asserted after deassertion of ALE in multiplexed mode.
+
+    The default is to assert CS together with ALE.  The alternative
+    is to assert CS (ALEN+1)*LPC_CLK clocks after deassertion of ALE.
+
+    The default is wrong for the NOR flash and CPLD on the ADS5121.
+
+    This patch turns on the alternative for CS0 (NOR) and CS2 (CPLD)
+    it does so conditionally based on silicon rev 2.0 or greater.
+
+    Signed-off-by: Martha J Marx <mmarx@silicontkx.com>
+    Signed-off-by: John Rigby <jrigby@freescale.com>
+
+commit 5d9a5efa4b332f442b54a755d49969123c3a8742
+Author: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Date:	Tue Aug 19 00:56:46 2008 +0600
+
+    Add I2C frequency dividers for ColdFire
+
+    The existing I2C freqency dividers for FDR does not apply
+    to ColdFire platforms; thus, a seperate table is added
+    based on MCF5xxx Reference Manual
+
+    Signed-off-by: Luigi 'Comio' Mantellini <luigi.mantellini@idf-hit.com>
+    Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+    Acked-by: Tabi Timur <timur@freescale.com>
+
+commit eec567a67e00d1ed8d941e9098b7d421f4091abf
+Author: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Date:	Tue Aug 19 03:01:19 2008 +0600
+
+    ColdFire: I2C fix for multiple platforms
+
+    Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+
+commit d53cf6a9c7423cba668b867978648645f71c3090
+Author: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Date:	Tue Aug 19 00:37:13 2008 +0600
+
+    ColdFire: Add CONFIG_MII_INIT for M5272C3
+
+    Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+
+commit f78ced3028d4130b24a318943a70cf5584ab16f4
+Author: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Date:	Tue Aug 19 00:26:25 2008 +0600
+
+    ColdFire: Multiple fixes for MCF5445x platforms
+
+    Add FEC pin set and mii reset in __mii_init(). Change
+    legacy flash vendor from 2 to AMD LEGACY (0xFFF0),
+    change cfi_offset to 0, and change CFG_FLASH_CFI to
+    CONFIG_FLASH_CFI_LEGACY. Correct M54451EVB and
+    M54455EVB env settings in configuration file.
+
+    Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+
+commit 454e725b3a9537b7f273bbd0cbca180f23a7a6e8
+Author: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Date:	Fri Aug 15 18:24:25 2008 +0000
+
+    ColdFire: Change the SDRAM BRD2WT timing from 3 to 7
+
+    The user manuals recommend 7.
+
+    Signed-off-by: Kurt Mahan <kmahan@freescale.com>
+    Acked-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+
+commit 79e0799cf6e88d98d77b216a55234bf674b59a4e
+Author: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Date:	Fri Aug 15 16:50:07 2008 +0000
+
+    ColdFire: Raise uart baudrate to 115200 bps
+
+    M5249EVB, M5271EVB, M5272C3, M5275EVB and M5282EVB platforms
+    uart baudrate increase from 19200 to 115200 bps
+
+    Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+
+commit ab6ba842682552ccf071d0034da0a20633d1d1ac
+Author: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Date:	Wed Aug 13 12:07:03 2008 +0000
+
+    ColdFire: Fix board.c warning message
+
+    Implicit declaration of nand_init() warning message
+
+    Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+
+commit 5798b1c4650e9a8713c95b25c1e669a2bc80a97b
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Wed Aug 27 01:10:34 2008 -0500
+
+    FSL DDR: Remove duplicate setting of cs0_bnds register on 86xx.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 258c37b147353bc522ffc33dfbd7d0d9cd7c32d7
+Author: Heiko Schocher <hs@denx.de>
+Date:	Thu Aug 21 20:44:49 2008 +0200
+
+    mpc52xx: added support for the MPC5200 based MUC.MC52 board from MAN.
+
+    Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit 9cff4448a9cb882defe6c8bde73b77fc0c636799
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Tue Aug 19 14:46:36 2008 -0500
+
+    mpc85xx: remove redudant code with lib_ppc/interrupts.c
+
+    For some reason we duplicated the majority of code in lib_ppc/interrupts.c
+    not show how that happened, but there is no good reason for it.
+
+    Use the interrupt_init_cpu() and timer_interrupt_cpu() since its why
+    they exist.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 9490a7f1a9484617bad75c60807ce02c8a3a6d56
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Fri Jul 25 13:31:05 2008 -0500
+
+    mpc85xx: Add support for the MPC8536DS reference board
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+    Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
+    Signed-off-by: Dejan Minic <minic@freescale.com>
+    Signed-off-by: Jason Jin <Jason.jin@freescale.com>
+    Signed-off-by: Dave Liu <daveliu@freescale.com>
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit ef50d6c06ece74fb17e8d7510e62cad9df8b810d
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Tue Aug 12 11:14:19 2008 -0500
+
+    mpc85xx: Add support for the MPC8536
+
+    The MPC8536 Adds SDHC and SATA controllers to the PQ3 family.  We
+    also have SERDES init code for the 8536.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+    Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
+    Signed-off-by: Dejan Minic <minic@freescale.com>
+    Signed-off-by: Jason Jin <Jason.jin@freescale.com>
+    Signed-off-by: Dave Liu <daveliu@freescale.com>
+
+commit 129ba616b3813dde861f25f3d8a3c47c5c36ad5f
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Tue Aug 12 11:13:08 2008 -0500
+
+    mpc85xx: Add support for the MPC8572DS reference board
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 457caecdbca3df21a93abff19eab12dbc61b7897
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Wed Aug 27 01:05:35 2008 -0500
+
+    FSL DDR: Remove old SPD support from cpu/mpc85xx
+
+    All 85xx boards have been converted to the new code so we can
+    remove the old SPD DDR setup code.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 0e7927db138976469e7257e29c1338050a50fcd9
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Wed Aug 27 01:04:07 2008 -0500
+
+    FSL DDR: Convert STXSSA to new DDR code.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit c360d9b970fbb9c13744c355879671165bbb9b9e
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Wed Aug 27 01:03:42 2008 -0500
+
+    FSL DDR: Convert STXGP3 to new DDR code.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 8e55313b7ae12352a343f9b9962e662dbd897187
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Tue Aug 26 23:52:58 2008 -0500
+
+    FSL DDR: Convert SBC8560 to new DDR code.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 9658bec2e8f55d56ca1be70090ce5a348be4980f
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Tue Aug 26 23:52:32 2008 -0500
+
+    FSL DDR: Convert MPC8540EVAL to new DDR code.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 6bfa8f723cfd82c55e3ef5620ade396916470a70
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Tue Aug 26 23:52:07 2008 -0500
+
+    FSL DDR: Convert PM856 to new DDR code.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit d53bd3e17bd4f460257c19255569ea6dcfaae817
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Tue Aug 26 23:51:49 2008 -0500
+
+    FSL DDR: Convert PM854 to new DDR code.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 33b9079ba20926f14238fff863b68a98e938948e
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Tue Aug 26 23:15:28 2008 -0500
+
+    FSL DDR: Convert sbc8548 to new DDR code.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit a947e4c7eb15cea1d9fb633955c516aab5ad35dd
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Tue Aug 26 23:14:14 2008 -0500
+
+    FSL DDR: Convert atum8548 to new DDR code.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit be0bd8234b9777ecd63c4c686f72af070d886517
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Tue Aug 26 22:56:56 2008 -0500
+
+    FSL DDR: Convert socrates to new DDR code.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 1167a2fd56138b716e01370c4267f3b70bf9ffa0
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Tue Aug 26 08:02:30 2008 -0500
+
+    FSL DDR: Convert MPC8544DS to new DDR code.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit e6f5b35b41ddbd637bb9ca4ad985b1e0b07dae0e
+Author: Jon Loeliger <jdl@freescale.com>
+Date:	Tue Mar 18 13:51:05 2008 -0500
+
+    FSL DDR: Convert MPC8568MDS to new DDR code.
+
+    Signed-off-by: Jon Loeliger <jdl@freescale.com>
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit e31d2c1e2bc954dc32e33bb2076139f85b95f8e6
+Author: Jon Loeliger <jdl@freescale.com>
+Date:	Tue Mar 18 13:51:06 2008 -0500
+
+    FSL DDR: Convert MPC8548CDS to new DDR code.
+
+    Signed-off-by: Jon Loeliger <jdl@freescale.com>
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit aa11d85cf318b961e029fe50d68ca47d004bce93
+Author: Jon Loeliger <jdl@freescale.com>
+Date:	Mon Mar 17 15:48:18 2008 -0500
+
+    FSL DDR: Convert MPC8541CDS to new DDR code.
+
+    Signed-off-by: Jon Loeliger <jdl@freescale.com>
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 2b40edb10d81da7bba724edbccd7f53777112579
+Author: Jon Loeliger <jdl@freescale.com>
+Date:	Tue Mar 18 11:12:42 2008 -0500
+
+    FSL DDR: Convert MPC8555ADS to new DDR code.
+
+    Signed-off-by: Jon Loeliger <jdl@freescale.com>
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 8b625114e8bc5a6b436181167a6e7fcd3303dd2c
+Author: Jon Loeliger <jdl@freescale.com>
+Date:	Tue Mar 18 11:12:44 2008 -0500
+
+    FSL DDR: Convert MPC8560ADS to new DDR code.
+
+    Signed-off-by: Jon Loeliger <jdl@freescale.com>
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 9617c8d49a21703eaf13a4033ab1a56eecc033cc
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Fri Jun 6 13:12:18 2008 -0500
+
+    FSL DDR: Convert MPC8540ADS to new DDR code.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 2a6c2d7ab2a66660f40a6cd3de2eb29ee29d9693
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Tue Aug 26 21:34:55 2008 -0500
+
+    FSL DDR: Add 85xx specific register setting
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 6fb1b7346849ccd0c20306143e334f5b76143070
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Mon Jun 9 11:07:46 2008 -0500
+
+    FSL DDR: Add e500 TLB helper for DDR code
+
+    Provide a helper function that board code can call to map TLBs when
+    setting up DDR.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit d26b739afe5a6760bd345743188759cd9d0f3b47
+Author: Andrew Dyer <adyer@righthandtech.com>
+Date:	Tue Aug 26 17:03:38 2008 -0500
+
+    dm9000 remove dead external phy support, gpio fix
+
+    dm9000 has code to detect and initialize external phy parts, but later
+    on in the code the part is forced to use the internal phy
+    unconditionally.  Remove the unused/untested code.
+
+    change the GPIO initialization so that only the GPIO used as an
+    internal phy reset (hardwired in the chip) is set as an output.  The
+    remaining GPIO need to be handled by board specific code to prevent
+    possible drive conflicts.  Set as inputs for safety.
+
+    replace a few magic numbers with defines
+
+    Signed-off-by: Andrew Dyer <adyer@righthandtech.com>
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit a1573db0c07c8ba99e9c373bb07ecd6f59da672c
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date:	Tue Aug 26 11:17:48 2008 -0500
+
+    Standardize bootp, tftpboot, rarpboot, dhcp, and nfs command descriptions
+
+    cmd_net.c command descriptions were updated to describe the optional
+    hostIPaddr argument.  The dhcp command help message was also updated
+    to more closely reflect the other commands in cmd_net.c
+
+    Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 51dfe1382ebaf691485badfa0ea5e75b0710531b
+Author: Remy Bohmer <linux@bohmer.net>
+Date:	Wed Aug 20 11:30:28 2008 +0200
+
+    Fix bogus error message in the DHCP handler
+
+    The DHCP handler has 1 state that is not listed in this case, causing a
+    failure message when there is actually no failure.
+
+    Signed-off-by: Remy Bohmer <linux@bohmer.net>
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 61365501a0e2cae9c1df2818b7b5b3f52c450d18
+Author: Remy Bohmer <linux@bohmer.net>
+Date:	Wed Aug 20 11:30:27 2008 +0200
+
+    Fix compile error when CONFIG_BOOTP_RANDOM_DELAY is set.
+
+    The option CONFIG_BOOTP_RANDOM_DELAY does not compile, because of a
+    missing extern inside the net/bootp.h header
+
+    Signed-off-by: Remy Bohmer <linux@bohmer.net>
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 1803f7f91ff35ca402259065df7557107dcf28a2
+Author: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Date:	Tue Aug 19 21:26:32 2008 +0000
+
+    ColdFire: Add FEC Buffer descriptors in SRAM
+
+    Add FEC Buffer descriptors and data buffer in SRAM for
+    faster execution and access.
+
+    Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 429be27ce195210d4b9decf9e867b9ca6155a87d
+Author: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Date:	Thu Aug 21 23:55:11 2008 +0000
+
+    Fix ColdFire FEC warning messages
+
+    Types mismatch and implicit declaration of icache_invalid()
+    warning messages
+
+    Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 6a002171098e968bd5b362347d2831224fab6048
+Author: Ben Warren <biggerbadderben@gmail.com>
+Date:	Sat Jul 12 00:17:50 2008 -0700
+
+    Moved initialization of SKGE Ethernet driver to board code.
+
+    The only board using this driver is the SL8245 board.
+    Removed initialization for the driver from net/eth.c
+
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 8379f42bc745eb9e4ca551a30fd2d0a63f740d75
+Author: Ben Warren <biggerbadderben@gmail.com>
+Date:	Sat Jul 12 00:08:45 2008 -0700
+
+    Moved conditional compilation to Makefile for SK98 Ethernet driver
+
+    Brute-force removal of #ifdefs.  Didn't touch the code.
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 65d3d99c28dc363d15eaee78225ff643df499b97
+Author: Ben Warren <biggerbadderben@gmail.com>
+Date:	Fri Jul 11 23:42:19 2008 -0700
+
+    Moved initialization of ULI526X Ethernet driver to board code.
+
+    The only board using this driver is the Freescale MPC8610HPCD board.
+    Removed initialization for the driver from net/eth.c
+
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 914947313a710f5dcf06beaf7f2aa24f1ebcce4f
+Author: Ben Warren <biggerbadderben@gmail.com>
+Date:	Fri Jul 11 23:15:28 2008 -0700
+
+    Moved initialization of Blackfin EMAC Ethernet controller to board_eth_init()
+
+    Added board_eth_init() function to bf537-stamp board.
+    Removed initialization for the Blackin EMAC driver from net/eth.c
+
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit fc363ce35408f348cacced68505f3747a53e3d7c
+Author: Ben Warren <biggerbadderben@gmail.com>
+Date:	Wed Jul 9 01:04:19 2008 -0700
+
+    Moved initialization of GRETH Ethernet driver to CPU directory
+
+    Added a cpu_eth_init() function to leon2/leon3 CPU directories and
+    removed code from net/eth.c
+
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 86882b80771309bceb11c6accfd7f6f90ade8bfc
+Author: Ben Warren <biggerbadderben@gmail.com>
+Date:	Tue Aug 26 22:16:25 2008 -0700
+
+    Moved initialization of MCFFEC Ethernet driver to CPU directory
+
+    Added a cpu_eth_init() function to coldfire CPU directories and
+    removed code from net/eth.c
+
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit b31da88b9c160d80d42a59cbbb31e24f27184d5c
+Author: Ben Warren <biggerbadderben@gmail.com>
+Date:	Tue Aug 26 22:12:36 2008 -0700
+
+    Moved initialization of FSL_MCDMAFEC Ethernet driver to CPU directory
+
+    Added a cpu_eth_init() function to cpu/mcf547x_8x directory and
+    removed code from net/eth.c
+
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit b5710d9974f6f0f3ddb4e67d6cccc262ab37049e
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Tue Aug 26 15:01:38 2008 -0500
+
+    FSL DDR: Remove old SPD support from cpu/mpc86xx
+
+    All 86xx boards have been converted to the new code so we can
+    remove the old SPD DDR setup code.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 9bd4e5911b750837515466bc7449087698b88e0e
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Tue Aug 26 15:01:37 2008 -0500
+
+    FSL DDR: Convert SBC8641D to new DDR code.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 39aa1a73483e1ac2bd56d5523abfc3970ee82c77
+Author: Jon Loeliger <jdl@freescale.com>
+Date:	Tue Aug 26 15:01:36 2008 -0500
+
+    FSL DDR: Convert MPC8610HPCD to new DDR code.
+
+    Signed-off-by: Jon Loeliger <jdl@freescale.com>
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 6a8e5692933e8e6d6e5ba7e594f49dd6d4c3a263
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Tue Aug 26 15:01:35 2008 -0500
+
+    FSL DDR: Convert MPC8641HPCN to new DDR code.
+
+    Signed-off-by: Jon Loeliger <jdl@freescale.com>
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 46ff4f1100ea64a01d21cc008ce85ac15eb1821f
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Tue Aug 26 15:01:34 2008 -0500
+
+    FSL DDR: Add 86xx specific register setting
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 233fdd502a6c227f476212b3097653ad48d7e254
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Tue Aug 26 15:01:32 2008 -0500
+
+    FSL DDR: Add DDR2 DIMM paramter support
+
+    Compute DIMM parameters based upon the SPD information.
+
+    Signed-off-by: James Yang <James.Yang@freescale.com>
+    Signed-off-by: Jon Loeliger <jdl@freescale.com>
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 05c05a2363a6ac11e0e405926034546ffad71fad
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Tue Aug 26 15:01:30 2008 -0500
+
+    FSL DDR: Add DDR1 DIMM paramter support
+
+    Compute DIMM parameters based upon the SPD information in spd.
+
+    Signed-off-by: James Yang <James.Yang@freescale.com>
+    Signed-off-by: Jon Loeliger <jdl@freescale.com>
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 58e5e9aff147e8c7e2bc1406bf9384f65f020ffa
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Tue Aug 26 15:01:29 2008 -0500
+
+    FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code.
+
+    The main purpose of this rewrite it to be able to share the same
+    initialization code on all FSL PowerPC products that have DDR
+    controllers.  (83xx, 85xx, 86xx).
+
+    The code is broken up into the following steps:
+	GET_SPD
+	COMPUTE_DIMM_PARMS
+	COMPUTE_COMMON_PARMS
+	GATHER_OPTS
+	ASSIGN_ADDRESSES
+	COMPUTE_REGS
+	PROGRAM_REGS
+
+    This allows us to share more code an easily allow for board specific code
+    overrides.
+
+    Additionally this code base adds support for >4G of DDR and provides a
+    foundation for supporting interleaving on processors with more than one
+    controller.
+
+    Signed-off-by: James Yang <James.Yang@freescale.com>
+    Signed-off-by: Jon Loeliger <jdl@freescale.com>
+    Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
+    Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit f784e32b4bce0013983506b11af4b85b8ca3d36e
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Tue Aug 26 15:01:28 2008 -0500
+
+    FSL DDR: Provide a generic set_ddr_laws()
+
+    Provide a helper function that will setup the last available
+    LAWs (upto 2) for DDR.  Useful for SPD/dyanmic DDR setting code.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 0f2cbe3f5eddbdf3848265f35e4f714434929cff
+Author: James Yang <James.Yang@freescale.com>
+Date:	Tue Aug 26 15:01:27 2008 -0500
+
+    Add proper SPD definitions for DDR1/2/3
+
+    Also adds helper functions for DDR1/2 to verify the checksum.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 285db74716c724ae8a0ff177878fd09a74428c7b
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Wed Aug 27 01:02:48 2008 +0200
+
+    Update CHANGELOG
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
 commit adf22b66d8bf05bd46e098cf71e6dca29b30aa7b
 Author: Heiko Schocher <hs@denx.de>
 Date:	Tue Aug 19 10:08:49 2008 +0200

CREDITS

@@ -405,7 +405,9 @@ D: Atmel AT91CAP9ADK support
 
 N: Ricardo Ribalda Delgado
 E: ricardo.ribalda@uam.es
-D: PPC440x5 (Virtex5), ML507 Board, eeprom_simul, adt7460
+D: PPC440x5 (Virtex5), ML507 Board, eeprom_simul, adt7460, v5fx30teval
+D: Virtex ppc440 generic architecture
+D: Virtex ppc405 generic architecture
 W: http://www.ii.uam.es/~rribalda
 
 N: Stefan Roese

MAINTAINERS

@@ -4,7 +4,7 @@
 #									#
 # For any board without permanent maintainer, please contact		#
 #	Wolfgang Denk <wd@denx.de>					#
-# and Cc: the <U-Boot-Users@lists.sourceforge.net> mailing lists.	#
+# and Cc: the <u-boot@lists.denx.de> mailing list.			#
 #									#
 # Note: lists sorted by Maintainer Name					#
 #########################################################################
@@ -130,6 +130,10 @@ Jon Diekema <jon.diekema@smiths-aerospace.com>
 
 	sbc8260		MPC8260
 
+Dirk Eibach <eibach@gdsys.de>
+
+	neo		PPC405EP
+
 Dave Ellis <DGE@sixnetio.com>
 
 	SXNI855T	MPC8xx
@@ -314,6 +318,9 @@ Daniel Poirot <dan.poirot@windriver.com>
 Ricardo Ribalda <ricardo.ribalda@uam.es>
 
 	ml507 		PPC440x5
+	v5fx30teval	PPC440x5
+	xilinx-ppc405-generic	PPC405
+	xilinx-ppc440-generic	PPC440x5
 
 Stefan Roese <sr@denx.de>
 
@@ -359,6 +366,10 @@ Travis Sawyer (travis.sawyer@sandburst.com>
 	METROBOX	PPC440GX
 	XPEDITE1K	PPC440GX
 
+Georg Schardt <schardt@team-ctech.de>
+
+	fx12mm		PPC405
+
 Heiko Schocher <hs@denx.de>
 
 	ids8247		MPC8247
@@ -592,6 +603,10 @@ Greg Ungerer <greg.ungerer@opengear.com>
 	cm4116		ks8695p
 	cm4148		ks8695p
 
+Hugo Villeneuve <hugo.villeneuve@lyrtech.com>
+
+	SFFSDR		ARM926EJS
+
 Richard Woodruff <r-woodruff2@ti.com>
 
 	omap2420h4	ARM1136EJS
@@ -601,6 +616,10 @@ Alex Z
 	lart		SA1100
 	dnp1110		SA1110
 
+Sergey Lapin <slapin@ossfans.org>
+
+	afeb9260	ARM926EJS (AT91SAM9260 SoC)
+
 -------------------------------------------------------------------------
 
 Unknown / orphaned boards:
@@ -685,7 +704,6 @@ Yasushi Shoji <yashi@atmark-techno.com>
 Michal Simek <monstr@monstr.eu>
 
 	ML401		MicroBlaze
-	XUPV2P		MicroBlaze
 
 #########################################################################
 # Coldfire Systems:							#
@@ -707,6 +725,7 @@ TsiChung Liew <Tsi-Chung.Liew@freescale.com>
 	M52277EVB	mcf5227x
 	M5235EVB	mcf52x2
 	M5253DEMO	mcf52x2
+	M53017EVB	mcf532x
 	M5329EVB	mcf532x
 	M5373EVB	mcf532x
 	M54455EVB	mcf5445x

MAKEALL

@@ -1,6 +1,15 @@
 #!/bin/sh
 
-: ${JOBS:=}
+# Determine number of CPU cores if no default was set
+: ${BUILD_NCPUS:="`getconf _NPROCESSORS_ONLN`"}
+
+if [ "$BUILD_NCPUS" -gt 1 ]
+then
+	JOBS=-j`expr "$BUILD_NCPUS" + 1`
+else
+	JOBS=""
+fi
+
 
 if [ "${CROSS_COMPILE}" ] ; then
 	MAKE="make CROSS_COMPILE=${CROSS_COMPILE}"
@@ -161,6 +170,7 @@ LIST_4xx="		\
 	alpr		\
 	AP1000		\
 	AR405		\
+	arches		\
 	ASH405		\
 	bamboo		\
 	bamboo_nand	\
@@ -185,6 +195,7 @@ LIST_4xx="		\
 	ebony		\
 	ERIC		\
 	EXBITGEN	\
+	fx12mm		\
 	G2000		\
 	glacier		\
 	haleakala	\
@@ -210,6 +221,7 @@ LIST_4xx="		\
 	ml300		\
 	ml507		\
 	ml507_flash	\
+	neo		\
 	ocotea		\
 	OCRTC		\
 	ORSG		\
@@ -230,12 +242,16 @@ LIST_4xx="		\
 	sequoia_nand	\
 	taihu		\
 	taishan		\
+	v5fx30teval	\
+	v5fx30teval_flash \
 	VOH405		\
 	VOM405		\
 	W7OLMC		\
 	W7OLMG		\
 	walnut		\
 	WUH405		\
+	xilinx-ppc440-generic \
+	xilinx-ppc440-generic_flash \
 	XPEDITE1K	\
 	yellowstone	\
 	yosemite	\
@@ -320,7 +336,7 @@ LIST_8260="		\
 
 LIST_83xx="		\
 	MPC8313ERDB_33	\
-	MPC8313ERDB_66	\
+	MPC8313ERDB_NAND_66	\
 	MPC8315ERDB	\
 	MPC8323ERDB	\
 	MPC832XEMDS	\
@@ -527,6 +543,7 @@ LIST_ARM11="		\
 #########################################################################
 
 LIST_at91="		\
+	afeb9260	\
 	at91cap9adk	\
 	at91rm9200dk	\
 	at91sam9260ek	\
@@ -681,7 +698,6 @@ LIST_nios2="		\
 LIST_microblaze="	\
 	ml401		\
 	suzaku		\
-	xupv2p		\
 "
 
 #########################################################################
@@ -702,6 +718,7 @@ LIST_coldfire="			\
 	M5272C3			\
 	M5275EVB		\
 	M5282EVB		\
+	M53017EVB		\
 	M5329AFEE		\
 	M5373EVB		\
 	M54451EVB		\

Makefile

@@ -21,11 +21,16 @@
 # MA 02111-1307 USA
 #
 
-VERSION = 1
-PATCHLEVEL = 3
-SUBLEVEL = 4
-EXTRAVERSION =
+VERSION = 2009
+PATCHLEVEL = 01
+SUBLEVEL =
+EXTRAVERSION = -rc1
+ifneq "$(SUBLEVEL)" ""
 U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
+else
+U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL)$(EXTRAVERSION)
+endif
+TIMESTAMP_FILE = $(obj)include/timestamp_autogenerated.h
 VERSION_FILE = $(obj)include/version_autogenerated.h
 
 HOSTARCH := $(shell uname -m | \
@@ -40,7 +45,12 @@ HOSTARCH := $(shell uname -m | \
 HOSTOS := $(shell uname -s | tr '[:upper:]' '[:lower:]' | \
 	    sed -e 's/\(cygwin\).*/cygwin/')
 
-export	HOSTARCH HOSTOS
+# Set shell to bash if possible, otherwise fall back to sh
+SHELL := $(shell if [ -x "$$BASH" ]; then echo $$BASH; \
+	else if [ -x /bin/bash ]; then echo /bin/bash; \
+	else echo sh; fi; fi)
+
+export	HOSTARCH HOSTOS SHELL
 
 # Deal with colliding definitions from tcsh etc.
 VENDOR=
@@ -199,6 +209,7 @@ endif
 OBJS := $(addprefix $(obj),$(OBJS))
 
 LIBS  = lib_generic/libgeneric.a
+LIBS += lib_generic/lzma/liblzma.a
 LIBS += $(shell if [ -f board/$(VENDOR)/common/Makefile ]; then echo \
 	"board/$(VENDOR)/common/lib$(VENDOR).a"; fi)
 LIBS += cpu/$(CPU)/lib$(CPU).a
@@ -216,6 +227,7 @@ LIBS += disk/libdisk.a
 LIBS += drivers/bios_emulator/libatibiosemu.a
 LIBS += drivers/block/libblock.a
 LIBS += drivers/dma/libdma.a
+LIBS += drivers/fpga/libfpga.a
 LIBS += drivers/hwmon/libhwmon.a
 LIBS += drivers/i2c/libi2c.a
 LIBS += drivers/input/libinput.a
@@ -225,6 +237,7 @@ LIBS += drivers/mtd/libmtd.a
 LIBS += drivers/mtd/nand/libnand.a
 LIBS += drivers/mtd/nand_legacy/libnand_legacy.a
 LIBS += drivers/mtd/onenand/libonenand.a
+LIBS += drivers/mtd/ubi/libubi.a
 LIBS += drivers/mtd/spi/libspi_flash.a
 LIBS += drivers/net/libnet.a
 LIBS += drivers/net/phy/libphy.a
@@ -238,9 +251,11 @@ endif
 ifeq ($(CPU),mpc85xx)
 LIBS += drivers/qe/qe.a
 LIBS += cpu/mpc8xxx/ddr/libddr.a
+TAG_SUBDIRS += cpu/mpc8xxx
 endif
 ifeq ($(CPU),mpc86xx)
 LIBS += cpu/mpc8xxx/ddr/libddr.a
+TAG_SUBDIRS += cpu/mpc8xxx
 endif
 LIBS += drivers/rtc/librtc.a
 LIBS += drivers/serial/libserial.a
@@ -252,7 +267,7 @@ LIBS += api/libapi.a
 LIBS += post/libpost.a
 
 LIBS := $(addprefix $(obj),$(LIBS))
-.PHONY : $(LIBS) $(VERSION_FILE)
+.PHONY : $(LIBS) $(TIMESTAMP_FILE) $(VERSION_FILE)
 
 LIBBOARD = board/$(BOARDDIR)/lib$(BOARD).a
 LIBBOARD := $(addprefix $(obj),$(LIBBOARD))
@@ -295,7 +310,7 @@ $(obj)u-boot.hex:	$(obj)u-boot
 		$(OBJCOPY) ${OBJCFLAGS} -O ihex $< $@
 
 $(obj)u-boot.srec:	$(obj)u-boot
-		$(OBJCOPY) ${OBJCFLAGS} -O srec $< $@
+		$(OBJCOPY) -O srec $< $@
 
 $(obj)u-boot.bin:	$(obj)u-boot
 		$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
@@ -344,13 +359,13 @@ $(SUBDIRS):	depend $(obj)include/autoconf.mk
 $(LDSCRIPT):	depend $(obj)include/autoconf.mk
 		$(MAKE) -C $(dir $@) $(notdir $@)
 
-$(NAND_SPL):	$(VERSION_FILE)	$(obj)include/autoconf.mk
+$(NAND_SPL):	$(TIMESTAMP_FILE) $(VERSION_FILE) $(obj)include/autoconf.mk
 		$(MAKE) -C nand_spl/board/$(BOARDDIR) all
 
 $(U_BOOT_NAND):	$(NAND_SPL) $(obj)u-boot.bin $(obj)include/autoconf.mk
 		cat $(obj)nand_spl/u-boot-spl-16k.bin $(obj)u-boot.bin > $(obj)u-boot-nand.bin
 
-$(ONENAND_IPL):	$(VERSION_FILE)	$(obj)include/autoconf.mk
+$(ONENAND_IPL):	$(TIMESTAMP_FILE) $(VERSION_FILE) $(obj)include/autoconf.mk
 		$(MAKE) -C onenand_ipl/board/$(BOARDDIR) all
 
 $(U_BOOT_ONENAND):	$(ONENAND_IPL) $(obj)u-boot.bin $(obj)include/autoconf.mk
@@ -359,10 +374,13 @@ $(U_BOOT_ONENAND):	$(ONENAND_IPL) $(obj)u-boot.bin $(obj)include/autoconf.mk
 
 $(VERSION_FILE):
 		@( printf '#define U_BOOT_VERSION "U-Boot %s%s"\n' "$(U_BOOT_VERSION)" \
-		 '$(shell $(CONFIG_SHELL) $(TOPDIR)/tools/setlocalversion $(TOPDIR))' \
-		 ) > $@.tmp
+		 '$(shell $(TOPDIR)/tools/setlocalversion $(TOPDIR))' ) > $@.tmp
 		@cmp -s $@ $@.tmp && rm -f $@.tmp || mv -f $@.tmp $@
 
+$(TIMESTAMP_FILE):
+		@date +'#define U_BOOT_DATE "%b %d %C%y"' > $@
+		@date +'#define U_BOOT_TIME "%T"' >> $@
+
 gdbtools:
 		$(MAKE) -C tools/gdb all || exit 1
 
@@ -372,7 +390,7 @@ updater:
 env:
 		$(MAKE) -C tools/env all MTD_VERSION=${MTD_VERSION} || exit 1
 
-depend dep:	$(VERSION_FILE)
+depend dep:	$(TIMESTAMP_FILE) $(VERSION_FILE)
 		for dir in $(SUBDIRS) ; do $(MAKE) -C $$dir _depend ; done
 
 TAG_SUBDIRS += include
@@ -445,7 +463,8 @@ $(obj)include/autoconf.mk: $(obj)include/config.h
 	set -e ; \
 	: Extract the config macros ; \
 	$(CPP) $(CFLAGS) -DDO_DEPS_ONLY -dM include/common.h | \
-		sed -n -f tools/scripts/define2mk.sed > $@
+		sed -n -f tools/scripts/define2mk.sed > $@.tmp && \
+	mv $@.tmp $@
 
 sinclude $(obj)include/autoconf.mk.dep
 
@@ -453,7 +472,7 @@ sinclude $(obj)include/autoconf.mk.dep
 else	# !config.mk
 all $(obj)u-boot.hex $(obj)u-boot.srec $(obj)u-boot.bin \
 $(obj)u-boot.img $(obj)u-boot.dis $(obj)u-boot \
-$(SUBDIRS) $(VERSION_FILE) gdbtools updater env depend \
+$(SUBDIRS) $(TIMESTAMP_FILE) $(VERSION_FILE) gdbtools updater env depend \
 dep tags ctags etags cscope $(obj)System.map:
 	@echo "System not configured - see README" >&2
 	@ exit 1
@@ -917,7 +936,7 @@ MBX860T_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc mpc8xx mbx8xx
 
 mgsuvd_config:		unconfig
-	@$(MKCONFIG) $(@:_config=) ppc mpc8xx mgsuvd
+	@$(MKCONFIG) $(@:_config=) ppc mpc8xx mgsuvd keymile
 
 MHPC_config:		unconfig
 	@$(MKCONFIG) $(@:_config=) ppc mpc8xx mhpc eltec
@@ -1059,7 +1078,7 @@ RPXlite_DW_config:	unconfig
 		  $(XECHO) "... with LCD display ..."; \
 		}
 	@[ -z "$(findstring _NVRAM,$@)" ] || \
-		{ echo "#define  CFG_ENV_IS_IN_NVRAM"	>>$(obj)include/config.h ; \
+		{ echo "#define  CONFIG_ENV_IS_IN_NVRAM"	>>$(obj)include/config.h ; \
 		  $(XECHO) "... with ENV in NVRAM ..."; \
 		}
 	@$(MKCONFIG) -a RPXlite_DW ppc mpc8xx RPXlite_dw
@@ -1201,7 +1220,8 @@ bubinga_config:	unconfig
 CANBT_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx canbt esd
 
-# Canyonlands & Glacier use different U-Boot images
+# Arches, Canyonlands & Glacier use different U-Boot images
+arches_config \
 canyonlands_config \
 glacier_config:	unconfig
 	@mkdir -p $(obj)include
@@ -1242,12 +1262,12 @@ CMS700_config:	unconfig
 CPCI2DP_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx cpci2dp esd
 
-CPCI405_config	\
-CPCI4052_config	\
+CPCI405_config		\
+CPCI4052_config		\
 CPCI405DT_config	\
 CPCI405AB_config:	unconfig
+	@mkdir -p $(obj)board/esd/cpci405
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx cpci405 esd
-	@echo "BOARD_REVISION = $(@:_config=)"	>> $(obj)include/config.mk
 
 CPCIISER4_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx cpciiser4 esd
@@ -1282,6 +1302,24 @@ ERIC_config:	unconfig
 EXBITGEN_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx exbitgen
 
+fx12mm_flash_config: unconfig
+	@mkdir -p $(obj)include $(obj)board/xilinx/ppc405-generic
+	@mkdir -p $(obj)include $(obj)board/avnet/fx12mm
+	@echo "LDSCRIPT:=$(SRCTREE)/board/xilinx/ppc405-generic/u-boot-rom.lds"\
+		> $(obj)board/avnet/fx12mm/config.tmp
+	@echo "TEXT_BASE := 0xFFCB0000" \
+		>> $(obj)board/avnet/fx12mm/config.tmp
+	@$(MKCONFIG) fx12mm ppc ppc4xx fx12mm avnet
+
+fx12mm_config: unconfig
+	@mkdir -p $(obj)include $(obj)board/xilinx/ppc405-generic
+	@mkdir -p $(obj)include $(obj)board/avnet/fx12mm
+	@echo "LDSCRIPT:=$(SRCTREE)/board/xilinx/ppc405-generic/u-boot-ram.lds"\
+		> $(obj)board/avnet/fx12mm/config.tmp
+	@echo "TEXT_BASE := 0x03000000" \
+		>> $(obj)board/avnet/fx12mm/config.tmp
+	@$(MKCONFIG) fx12mm ppc ppc4xx fx12mm avnet
+
 G2000_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx g2000
 
@@ -1356,16 +1394,26 @@ ML2_config:	unconfig
 ml300_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx ml300 xilinx
 
-ml507_flash_config:	unconfig
+ml507_flash_config: unconfig
+	@mkdir -p $(obj)include $(obj)board/xilinx/ppc440-generic
 	@mkdir -p $(obj)include $(obj)board/xilinx/ml507
-	@cp $(obj)board/xilinx/ml507/u-boot-rom.lds  $(obj)board/xilinx/ml507/u-boot.lds
-	@echo "TEXT_BASE = 0xFE360000" > $(obj)board/xilinx/ml507/config.tmp
-	@$(MKCONFIG) $(@:_flash_config=) ppc ppc4xx ml507 xilinx
-
-ml507_config:	unconfig
+	@echo "LDSCRIPT:=$(SRCTREE)/board/xilinx/ppc440-generic/u-boot-rom.lds"\
+		> $(obj)board/xilinx/ml507/config.tmp
+	@echo "TEXT_BASE := 0xFE360000" \
+		>> $(obj)board/xilinx/ml507/config.tmp
+	@$(MKCONFIG) ml507 ppc ppc4xx ml507 xilinx
+
+ml507_config: unconfig
+	@mkdir -p $(obj)include $(obj)board/xilinx/ppc440-generic
 	@mkdir -p $(obj)include $(obj)board/xilinx/ml507
-	@cp $(obj)board/xilinx/ml507/u-boot-ram.lds  $(obj)board/xilinx/ml507/u-boot.lds
-	@$(MKCONFIG) $(@:_config=) ppc ppc4xx ml507 xilinx
+	@echo "LDSCRIPT:=$(SRCTREE)/board/xilinx/ppc440-generic/u-boot-ram.lds"\
+		> $(obj)board/xilinx/ml507/config.tmp
+	@echo "TEXT_BASE := 0x04000000"  \
+		>> $(obj)board/xilinx/ml507/config.tmp
+	@$(MKCONFIG) ml507 ppc ppc4xx ml507 xilinx
+
+neo_config:	unconfig
+	@$(MKCONFIG) $(@:_config=) ppc ppc4xx neo gdsys
 
 ocotea_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx ocotea amcc
@@ -1461,6 +1509,24 @@ taihu_config:	unconfig
 taishan_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx taishan amcc
 
+v5fx30teval_config: unconfig
+	@mkdir -p $(obj)include $(obj)board/xilinx/ppc440-generic
+	@mkdir -p $(obj)include $(obj)board/avnet/v5fx30teval
+	@echo "LDSCRIPT:=$(SRCTREE)/board/xilinx/ppc440-generic/u-boot-ram.lds"\
+		> $(obj)board/avnet/v5fx30teval/config.tmp
+	@echo "TEXT_BASE := 0x03000000" \
+		>> $(obj)board/avnet/v5fx30teval/config.tmp
+	@$(MKCONFIG) v5fx30teval ppc ppc4xx v5fx30teval avnet
+
+v5fx30teval_flash_config: unconfig
+	@mkdir -p $(obj)include $(obj)board/xilinx/ppc440-generic
+	@mkdir -p $(obj)include $(obj)board/avnet/v5fx30teval
+	@echo "LDSCRIPT:=$(SRCTREE)/board/xilinx/ppc440-generic/u-boot-rom.lds"\
+		> $(obj)board/avnet/v5fx30teval/config.tmp
+	@echo "TEXT_BASE := 0xFF1C0000" \
+		>> $(obj)board/avnet/v5fx30teval/config.tmp
+	@$(MKCONFIG) v5fx30teval ppc ppc4xx v5fx30teval avnet
+
 VOH405_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx voh405 esd
 
@@ -1479,6 +1545,38 @@ sycamore_config: unconfig
 WUH405_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx wuh405 esd
 
+xilinx-ppc405-generic_flash_config: unconfig
+	@mkdir -p $(obj)include $(obj)board/xilinx/ppc405-generic
+	@echo "LDSCRIPT:=$(SRCTREE)/board/xilinx/ppc405-generic/u-boot-rom.lds"\
+		> $(obj)board/xilinx/ppc405-generic/config.tmp
+	@echo "TEXT_BASE := 0xFE360000" \
+		>> $(obj)board/xilinx/ppc405-generic/config.tmp
+	@$(MKCONFIG) xilinx-ppc405-generic ppc ppc4xx ppc405-generic xilinx
+
+xilinx-ppc405-generic_config: unconfig
+	@mkdir -p $(obj)include $(obj)board/xilinx/ppc405-generic
+	@echo "LDSCRIPT:=$(SRCTREE)/board/xilinx/ppc405-generic/u-boot-ram.lds"\
+		> $(obj)board/xilinx/ppc405-generic/config.tmp
+	@echo "TEXT_BASE := 0x04000000" \
+		>> $(obj)board/xilinx/ppc405-generic/config.tmp
+	@$(MKCONFIG) xilinx-ppc405-generic ppc ppc4xx ppc405-generic xilinx
+
+xilinx-ppc440-generic_flash_config: unconfig
+	@mkdir -p $(obj)include $(obj)board/xilinx/ppc440-generic
+	@echo "LDSCRIPT:=$(SRCTREE)/board/xilinx/ppc440-generic/u-boot-rom.lds"\
+		> $(obj)board/xilinx/ppc440-generic/config.tmp
+	@echo "TEXT_BASE := 0xFE360000" \
+		>> $(obj)board/xilinx/ppc440-generic/config.tmp
+	@$(MKCONFIG) xilinx-ppc440-generic ppc ppc4xx ppc440-generic xilinx
+
+xilinx-ppc440-generic_config: unconfig
+	@mkdir -p $(obj)include $(obj)board/xilinx/ppc440-generic
+	@echo "LDSCRIPT:=$(SRCTREE)/board/xilinx/ppc440-generic/u-boot-ram.lds"\
+		> $(obj)board/xilinx/ppc440-generic/config.tmp
+	@echo "TEXT_BASE := 0x04000000" \
+		>> $(obj)board/xilinx/ppc440-generic/config.tmp
+	@$(MKCONFIG) xilinx-ppc440-generic ppc ppc4xx ppc440-generic xilinx
+
 XPEDITE1K_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx xpedite1k
 
@@ -1652,12 +1750,12 @@ ISPAN_config		\
 ISPAN_REVB_config:	unconfig
 	@mkdir -p $(obj)include
 	@if [ "$(findstring _REVB_,$@)" ] ; then \
-		echo "#define CFG_REV_B" > $(obj)include/config.h ; \
+		echo "#define CONFIG_SYS_REV_B" > $(obj)include/config.h ; \
 	fi
 	@$(MKCONFIG) -a ISPAN ppc mpc8260 ispan
 
 mgcoge_config	:	unconfig
-	@$(MKCONFIG) mgcoge ppc mpc8260 mgcoge
+	@$(MKCONFIG) mgcoge ppc mpc8260 mgcoge keymile
 
 MPC8260ADS_config	\
 MPC8260ADS_lowboot_config	\
@@ -1679,8 +1777,8 @@ PQ2FADS-ZU_66MHz_lowboot_config	\
 	@mkdir -p $(obj)include
 	@mkdir -p $(obj)board/freescale/mpc8260ads
 	$(if $(findstring PQ2FADS,$@), \
-	@echo "#define CONFIG_ADSTYPE CFG_PQ2FADS" > $(obj)include/config.h, \
-	@echo "#define CONFIG_ADSTYPE CFG_"$(subst MPC,,$(word 1,$(subst _, ,$@))) > $(obj)include/config.h)
+	@echo "#define CONFIG_ADSTYPE CONFIG_SYS_PQ2FADS" > $(obj)include/config.h, \
+	@echo "#define CONFIG_ADSTYPE CONFIG_SYS_"$(subst MPC,,$(word 1,$(subst _, ,$@))) > $(obj)include/config.h)
 	$(if $(findstring MHz,$@), \
 	@echo "#define CONFIG_8260_CLKIN" $(subst MHz,,$(word 2,$(subst _, ,$@)))"000000" >> $(obj)include/config.h, \
 	$(if $(findstring VR,$@), \
@@ -1843,7 +1941,27 @@ ZPC1900_config: unconfig
 ## Coldfire
 #########################################################################
 
-M52277EVB_config:	unconfig
+M52277EVB_config \
+M52277EVB_spansion_config \
+M52277EVB_stmicro_config :	unconfig
+	@case "$@" in \
+	M52277EVB_config)		FLASH=SPANSION;; \
+	M52277EVB_spansion_config)	FLASH=SPANSION;; \
+	M52277EVB_stmicro_config)	FLASH=STMICRO;; \
+	esac; \
+	if [ "$${FLASH}" = "SPANSION" ] ; then \
+		echo "#define CONFIG_SYS_SPANSION_BOOT"	>> $(obj)include/config.h ; \
+		echo "TEXT_BASE = 0x00000000" > $(obj)board/freescale/m52277evb/config.tmp ; \
+		cp $(obj)board/freescale/m52277evb/u-boot.spa $(obj)board/freescale/m52277evb/u-boot.lds ; \
+		$(XECHO) "... with SPANSION boot..." ; \
+	fi; \
+	if [ "$${FLASH}" = "STMICRO" ] ; then \
+		echo "#define CONFIG_CF_SBF"	>> $(obj)include/config.h ; \
+		echo "#define CONFIG_SYS_STMICRO_BOOT"	>> $(obj)include/config.h ; \
+		echo "TEXT_BASE = 0x43E00000" > $(obj)board/freescale/m52277evb/config.tmp ; \
+		cp $(obj)board/freescale/m52277evb/u-boot.stm $(obj)board/freescale/m52277evb/u-boot.lds ; \
+		$(XECHO) "... with ST Micro boot..." ; \
+	fi
 	@$(MKCONFIG) -a M52277EVB m68k mcf5227x m52277evb freescale
 
 M5235EVB_config \
@@ -1903,6 +2021,9 @@ M5275EVB_config :		unconfig
 M5282EVB_config :		unconfig
 	@$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5282evb freescale
 
+M53017EVB_config :		unconfig
+	@$(MKCONFIG) $(@:_config=) m68k mcf532x m53017evb freescale
+
 M5329AFEE_config \
 M5329BFEE_config :	unconfig
 	@case "$@" in \
@@ -1932,19 +2053,19 @@ M54451EVB_stmicro_config :	unconfig
 	M54451EVB_stmicro_config)	FLASH=STMICRO;; \
 	esac; \
 	if [ "$${FLASH}" = "SPANSION" ] ; then \
-		echo "#define CFG_SPANSION_BOOT"	>> $(obj)include/config.h ; \
+		echo "#define CONFIG_SYS_SPANSION_BOOT"	>> $(obj)include/config.h ; \
 		echo "TEXT_BASE = 0x00000000" > $(obj)board/freescale/m54451evb/config.tmp ; \
 		cp $(obj)board/freescale/m54451evb/u-boot.spa $(obj)board/freescale/m54451evb/u-boot.lds ; \
 		$(XECHO) "... with SPANSION boot..." ; \
 	fi; \
 	if [ "$${FLASH}" = "STMICRO" ] ; then \
 		echo "#define CONFIG_CF_SBF"	>> $(obj)include/config.h ; \
-		echo "#define CFG_STMICRO_BOOT"	>> $(obj)include/config.h ; \
+		echo "#define CONFIG_SYS_STMICRO_BOOT"	>> $(obj)include/config.h ; \
 		echo "TEXT_BASE = 0x47E00000" > $(obj)board/freescale/m54451evb/config.tmp ; \
 		cp $(obj)board/freescale/m54451evb/u-boot.stm $(obj)board/freescale/m54451evb/u-boot.lds ; \
 		$(XECHO) "... with ST Micro boot..." ; \
 	fi; \
-	echo "#define CFG_INPUT_CLKSRC 24000000" >> $(obj)include/config.h ;
+	echo "#define CONFIG_SYS_INPUT_CLKSRC 24000000" >> $(obj)include/config.h ;
 	@$(MKCONFIG) -a M54451EVB m68k mcf5445x m54451evb freescale
 
 M54455EVB_config \
@@ -1966,25 +2087,25 @@ M54455EVB_stm33_config :	unconfig
 	M54455EVB_stm33_config)		FLASH=STMICRO; FREQ=33333333;; \
 	esac; \
 	if [ "$${FLASH}" = "INTEL" ] ; then \
-		echo "#define CFG_INTEL_BOOT" >> $(obj)include/config.h ; \
+		echo "#define CONFIG_SYS_INTEL_BOOT" >> $(obj)include/config.h ; \
 		echo "TEXT_BASE = 0x00000000" > $(obj)board/freescale/m54455evb/config.tmp ; \
 		cp $(obj)board/freescale/m54455evb/u-boot.int $(obj)board/freescale/m54455evb/u-boot.lds ; \
 		$(XECHO) "... with INTEL boot..." ; \
 	fi; \
 	if [ "$${FLASH}" = "ATMEL" ] ; then \
-		echo "#define CFG_ATMEL_BOOT"	>> $(obj)include/config.h ; \
+		echo "#define CONFIG_SYS_ATMEL_BOOT"	>> $(obj)include/config.h ; \
 		echo "TEXT_BASE = 0x04000000" > $(obj)board/freescale/m54455evb/config.tmp ; \
 		cp $(obj)board/freescale/m54455evb/u-boot.atm $(obj)board/freescale/m54455evb/u-boot.lds ; \
 		$(XECHO) "... with ATMEL boot..." ; \
 	fi; \
 	if [ "$${FLASH}" = "STMICRO" ] ; then \
 		echo "#define CONFIG_CF_SBF"	>> $(obj)include/config.h ; \
-		echo "#define CFG_STMICRO_BOOT"	>> $(obj)include/config.h ; \
+		echo "#define CONFIG_SYS_STMICRO_BOOT"	>> $(obj)include/config.h ; \
 		echo "TEXT_BASE = 0x4FE00000" > $(obj)board/freescale/m54455evb/config.tmp ; \
 		cp $(obj)board/freescale/m54455evb/u-boot.stm $(obj)board/freescale/m54455evb/u-boot.lds ; \
 		$(XECHO) "... with ST Micro boot..." ; \
 	fi; \
-	echo "#define CFG_INPUT_CLKSRC $${FREQ}" >> $(obj)include/config.h ; \
+	echo "#define CONFIG_SYS_INPUT_CLKSRC $${FREQ}" >> $(obj)include/config.h ; \
 	$(XECHO) "... with $${FREQ}Hz input clock"
 	@$(MKCONFIG) -a M54455EVB m68k mcf5445x m54455evb freescale
 
@@ -2004,20 +2125,20 @@ M5475GFE_config :	unconfig
 	M5475FFE_config)	BOOT=2;CODE=32;VID=1;USB=1;RAM=64;RAM1=64;; \
 	M5475GFE_config)	BOOT=4;CODE=0;VID=0;USB=0;RAM=64;RAM1=0;; \
 	esac; \
-	echo "#define CFG_BUSCLK	133333333" > $(obj)include/config.h ; \
-	echo "#define CFG_BOOTSZ	$${BOOT}" >> $(obj)include/config.h ; \
-	echo "#define CFG_DRAMSZ	$${RAM}" >> $(obj)include/config.h ; \
+	echo "#define CONFIG_SYS_BUSCLK	133333333" > $(obj)include/config.h ; \
+	echo "#define CONFIG_SYS_BOOTSZ	$${BOOT}" >> $(obj)include/config.h ; \
+	echo "#define CONFIG_SYS_DRAMSZ	$${RAM}" >> $(obj)include/config.h ; \
 	if [ "$${RAM1}" != "0" ] ; then \
-		echo "#define CFG_DRAMSZ1	$${RAM1}" >> $(obj)include/config.h ; \
+		echo "#define CONFIG_SYS_DRAMSZ1	$${RAM1}" >> $(obj)include/config.h ; \
 	fi; \
 	if [ "$${CODE}" != "0" ] ; then \
-		echo "#define CFG_NOR1SZ	$${CODE}" >> $(obj)include/config.h ; \
+		echo "#define CONFIG_SYS_NOR1SZ	$${CODE}" >> $(obj)include/config.h ; \
 	fi; \
 	if [ "$${VID}" == "1" ] ; then \
-		echo "#define CFG_VIDEO" >> $(obj)include/config.h ; \
+		echo "#define CONFIG_SYS_VIDEO" >> $(obj)include/config.h ; \
 	fi; \
 	if [ "$${USB}" == "1" ] ; then \
-		echo "#define CFG_USBCTRL" >> $(obj)include/config.h ; \
+		echo "#define CONFIG_SYS_USBCTRL" >> $(obj)include/config.h ; \
 	fi
 	@$(MKCONFIG) -a M5475EVB m68k mcf547x_8x m547xevb freescale
 
@@ -2039,20 +2160,20 @@ M5485HFE_config :	unconfig
 	M5485GFE_config)	BOOT=4;CODE=0;VID=0;USB=0;RAM=64;RAM1=0;; \
 	M5485HFE_config)	BOOT=2;CODE=16;VID=1;USB=0;RAM=64;RAM1=0;; \
 	esac; \
-	echo "#define CFG_BUSCLK	100000000" > $(obj)include/config.h ; \
-	echo "#define CFG_BOOTSZ	$${BOOT}" >> $(obj)include/config.h ; \
-	echo "#define CFG_DRAMSZ	$${RAM}" >> $(obj)include/config.h ; \
+	echo "#define CONFIG_SYS_BUSCLK	100000000" > $(obj)include/config.h ; \
+	echo "#define CONFIG_SYS_BOOTSZ	$${BOOT}" >> $(obj)include/config.h ; \
+	echo "#define CONFIG_SYS_DRAMSZ	$${RAM}" >> $(obj)include/config.h ; \
 	if [ "$${RAM1}" != "0" ] ; then \
-		echo "#define CFG_DRAMSZ1	$${RAM1}" >> $(obj)include/config.h ; \
+		echo "#define CONFIG_SYS_DRAMSZ1	$${RAM1}" >> $(obj)include/config.h ; \
 	fi; \
 	if [ "$${CODE}" != "0" ] ; then \
-		echo "#define CFG_NOR1SZ	$${CODE}" >> $(obj)include/config.h ; \
+		echo "#define CONFIG_SYS_NOR1SZ	$${CODE}" >> $(obj)include/config.h ; \
 	fi; \
 	if [ "$${VID}" == "1" ] ; then \
-		echo "#define CFG_VIDEO" >> $(obj)include/config.h ; \
+		echo "#define CONFIG_SYS_VIDEO" >> $(obj)include/config.h ; \
 	fi; \
 	if [ "$${USB}" == "1" ] ; then \
-		echo "#define CFG_USBCTRL" >> $(obj)include/config.h ; \
+		echo "#define CONFIG_SYS_USBCTRL" >> $(obj)include/config.h ; \
 	fi
 	@$(MKCONFIG) -a M5485EVB m68k mcf547x_8x m548xevb freescale
 
@@ -2071,11 +2192,11 @@ MPC8313ERDB_NAND_66_config: unconfig
 	@mkdir -p $(obj)board/freescale/mpc8313erdb
 	@if [ "$(findstring _33_,$@)" ] ; then \
 		$(XECHO) -n "...33M ..." ; \
-		echo "#define CFG_33MHZ" >>$(obj)include/config.h ; \
+		echo "#define CONFIG_SYS_33MHZ" >>$(obj)include/config.h ; \
 	fi ; \
 	if [ "$(findstring _66_,$@)" ] ; then \
 		$(XECHO) -n "...66M..." ; \
-		echo "#define CFG_66MHZ" >>$(obj)include/config.h ; \
+		echo "#define CONFIG_SYS_66MHZ" >>$(obj)include/config.h ; \
 	fi ; \
 	if [ "$(findstring _NAND_,$@)" ] ; then \
 		$(XECHO) -n "...NAND..." ; \
@@ -2083,6 +2204,9 @@ MPC8313ERDB_NAND_66_config: unconfig
 		echo "#define CONFIG_NAND_U_BOOT" >>$(obj)include/config.h ; \
 	fi ;
 	@$(MKCONFIG) -a MPC8313ERDB ppc mpc83xx mpc8313erdb freescale
+	@if [ "$(findstring _NAND_,$@)" ] ; then \
+		echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk ; \
+	fi ;
 
 MPC8315ERDB_config: unconfig
 	@$(MKCONFIG) -a MPC8315ERDB ppc mpc83xx mpc8315erdb freescale
@@ -2344,8 +2468,14 @@ TQM8560_config:		unconfig
 MPC8610HPCD_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc mpc86xx mpc8610hpcd freescale
 
+MPC8641HPCN_36BIT_config \
 MPC8641HPCN_config:    unconfig
-	@$(MKCONFIG) $(@:_config=) ppc mpc86xx mpc8641hpcn freescale
+	@mkdir -p $(obj)include
+	@if [ "$(findstring _36BIT_,$@)" ] ; then \
+		echo "#define CONFIG_PHYS_64BIT" >>$(obj)include/config.h ; \
+		$(XECHO) "... enabling 36-bit physical addressing." ; \
+	fi
+	@$(MKCONFIG) -a MPC8641HPCN ppc mpc86xx mpc8641hpcn freescale
 
 sbc8641d_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc mpc86xx sbc8641d
@@ -2435,15 +2565,6 @@ shannon_config	:	unconfig
 at91rm9200dk_config	:	unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm920t at91rm9200dk atmel at91rm9200
 
-at91sam9261ek_config	:	unconfig
-	@$(MKCONFIG) $(@:_config=) arm arm926ejs at91sam9261ek atmel at91
-
-at91sam9263ek_config	:	unconfig
-	@$(MKCONFIG) $(@:_config=) arm arm926ejs at91sam9263ek atmel at91
-
-at91sam9rlek_config	:	unconfig
-	@$(MKCONFIG) $(@:_config=) arm arm926ejs at91sam9rlek atmel at91
-
 cmc_pu2_config	:	unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm920t cmc_pu2 NULL at91rm9200
 
@@ -2463,11 +2584,69 @@ mp2usb_config	:	unconfig
 ## Atmel ARM926EJ-S Systems
 #########################################################################
 
+afeb9260_config:	unconfig
+	@$(MKCONFIG) $(@:_config=) arm arm926ejs afeb9260 NULL at91
+
 at91cap9adk_config	:	unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm926ejs at91cap9adk atmel at91
 
+at91sam9260ek_nandflash_config \
+at91sam9260ek_dataflash_cs0_config \
+at91sam9260ek_dataflash_cs1_config \
 at91sam9260ek_config	:	unconfig
-	@$(MKCONFIG) $(@:_config=) arm arm926ejs at91sam9260ek atmel at91
+	@if [ "$(findstring _nandflash,$@)" ] ; then \
+		echo "#define CONFIG_SYS_USE_NANDFLASH 1"	>>$(obj)include/config.h ; \
+		$(XECHO) "... with environment variable in NAND FLASH" ; \
+	elif [ "$(findstring dataflash_cs0,$@)" ] ; then \
+		echo "#define CONFIG_SYS_USE_DATAFLASH_CS0 1"	>>$(obj)include/config.h ; \
+		$(XECHO) "... with environment variable in SPI DATAFLASH CS0" ; \
+	else \
+		echo "#define CONFIG_SYS_USE_DATAFLASH_CS1 1"	>>$(obj)include/config.h ; \
+		$(XECHO) "... with environment variable in SPI DATAFLASH CS1" ; \
+	fi;
+	@$(MKCONFIG) -a at91sam9260ek arm arm926ejs at91sam9260ek atmel at91
+
+at91sam9261ek_nandflash_config \
+at91sam9261ek_dataflash_cs0_config \
+at91sam9261ek_dataflash_cs3_config \
+at91sam9261ek_config	:	unconfig
+	@if [ "$(findstring _nandflash,$@)" ] ; then \
+		echo "#define CONFIG_SYS_USE_NANDFLASH 1"	>>$(obj)include/config.h ; \
+		$(XECHO) "... with environment variable in NAND FLASH" ; \
+	elif [ "$(findstring dataflash_cs3,$@)" ] ; then \
+		echo "#define CONFIG_SYS_USE_DATAFLASH_CS3 1"	>>$(obj)include/config.h ; \
+		$(XECHO) "... with environment variable in SPI DATAFLASH CS3" ; \
+	else \
+		echo "#define CONFIG_SYS_USE_DATAFLASH_CS0 1"	>>$(obj)include/config.h ; \
+		$(XECHO) "... with environment variable in SPI DATAFLASH CS0" ; \
+	fi;
+	@$(MKCONFIG) -a at91sam9261ek arm arm926ejs at91sam9261ek atmel at91
+
+at91sam9263ek_nandflash_config \
+at91sam9263ek_dataflash_config \
+at91sam9263ek_dataflash_cs0_config \
+at91sam9263ek_config	:	unconfig
+	@if [ "$(findstring _nandflash,$@)" ] ; then \
+		echo "#define CONFIG_SYS_USE_NANDFLASH 1"	>>$(obj)include/config.h ; \
+		$(XECHO) "... with environment variable in NAND FLASH" ; \
+	else \
+		echo "#define CONFIG_SYS_USE_DATAFLASH 1"	>>$(obj)include/config.h ; \
+		$(XECHO) "... with environment variable in SPI DATAFLASH CS0" ; \
+	fi;
+	@$(MKCONFIG) -a at91sam9263ek arm arm926ejs at91sam9263ek atmel at91
+
+at91sam9rlek_nandflash_config \
+at91sam9rlek_dataflash_config \
+at91sam9rlek_dataflash_cs0_config \
+at91sam9rlek_config	:	unconfig
+	@if [ "$(findstring _nandflash,$@)" ] ; then \
+		echo "#define CONFIG_SYS_USE_NANDFLASH 1"	>>$(obj)include/config.h ; \
+		$(XECHO) "... with environment variable in NAND FLASH" ; \
+	else \
+		echo "#define CONFIG_SYS_USE_DATAFLASH 1"	>>$(obj)include/config.h ; \
+		$(XECHO) "... with environment variable in SPI DATAFLASH CS0" ; \
+	fi;
+	@$(MKCONFIG) -a at91sam9rlek arm arm926ejs at91sam9rlek atmel at91
 
 ########################################################################
 ## ARM Integrator boards - see doc/README-integrator for more info.
@@ -2972,11 +3151,6 @@ suzaku_config:	unconfig
 	@echo "#define CONFIG_SUZAKU 1" > $(obj)include/config.h
 	@$(MKCONFIG) -a $(@:_config=) microblaze microblaze suzaku AtmarkTechno
 
-xupv2p_config:	unconfig
-	@mkdir -p $(obj)include
-	@echo "#define CONFIG_XUPV2P 1" > $(obj)include/config.h
-	@$(MKCONFIG) -a $(@:_config=) microblaze microblaze xupv2p xilinx
-
 #========================================================================
 # Blackfin
 #========================================================================
@@ -3029,7 +3203,7 @@ mimc200_config		:	unconfig
 rsk7203_config: unconfig
 	@ >include/config.h
 	@echo "#define CONFIG_RSK7203 1" >> include/config.h
-	@./mkconfig -a $(@:_config=) sh sh2 rsk7203
+	@$(MKCONFIG) -a $(@:_config=) sh sh2 rsk7203 renesas
 
 #########################################################################
 ## sh3 (Renesas SuperH)
@@ -3052,7 +3226,7 @@ ms7720se_config: unconfig
 MigoR_config :       unconfig
 	@mkdir -p $(obj)include
 	@echo "#define CONFIG_MIGO_R 1" > $(obj)include/config.h
-	@./mkconfig -a $(@:_config=) sh sh4 MigoR
+	@$(MKCONFIG) -a $(@:_config=) sh sh4 MigoR renesas
 
 ms7750se_config: unconfig
 	@mkdir -p $(obj)include
@@ -3067,27 +3241,27 @@ ms7722se_config :	unconfig
 r2dplus_config  :   unconfig
 	@mkdir -p $(obj)include
 	@echo "#define CONFIG_R2DPLUS 1" > $(obj)include/config.h
-	@$(MKCONFIG) -a $(@:_config=) sh sh4 r2dplus
+	@$(MKCONFIG) -a $(@:_config=) sh sh4 r2dplus renesas
 
 r7780mp_config: unconfig
 	@mkdir -p $(obj)include
 	@echo "#define CONFIG_R7780MP 1" > $(obj)include/config.h
-	@$(MKCONFIG) -a $(@:_config=) sh sh4 r7780mp
+	@$(MKCONFIG) -a $(@:_config=) sh sh4 r7780mp renesas
 
 sh7763rdp_config  :   unconfig
 	@mkdir -p $(obj)include
 	@echo "#define CONFIG_SH7763RDP 1" > $(obj)include/config.h
-	@$(MKCONFIG) -a $(@:_config=) sh sh4 sh7763rdp
+	@$(MKCONFIG) -a $(@:_config=) sh sh4 sh7763rdp renesas
 
 sh7785lcr_config  :   unconfig
 	@ >include/config.h
 	@echo "#define CONFIG_SH7785LCR 1" >> include/config.h
-	@$(MKCONFIG) -a $(@:_config=) sh sh4 sh7785lcr
+	@$(MKCONFIG) -a $(@:_config=) sh sh4 sh7785lcr renesas
 
 ap325rxa_config  :   unconfig
 	@mkdir -p $(obj)include
 	@echo "#define CONFIG_AP325RXA 1" > $(obj)include/config.h
-	@$(MKCONFIG) -a $(@:_config=) sh sh4 ap325rxa
+	@$(MKCONFIG) -a $(@:_config=) sh sh4 ap325rxa renesas
 
 #========================================================================
 # SPARC
@@ -3148,7 +3322,7 @@ clean:
 	@rm -f $(obj)include/bmp_logo.h
 	@rm -f $(obj)nand_spl/{u-boot-spl,u-boot-spl.map,System.map}
 	@rm -f $(obj)onenand_ipl/onenand-{ipl,ipl.bin,ipl-2k.bin,ipl-4k.bin,ipl.map}
-	@rm -f $(obj)api_examples/demo $(VERSION_FILE)
+	@rm -f $(obj)api_examples/demo $(TIMESTAMP_FILE) $(VERSION_FILE)
 	@find $(OBJTREE) -type f \
 		\( -name 'core' -o -name '*.bak' -o -name '*~' \
 		-o -name '*.o'	-o -name '*.a'	\) -print \
@@ -3162,7 +3336,7 @@ clobber:	clean
 	@rm -f $(OBJS) $(obj)*.bak $(obj)ctags $(obj)etags $(obj)TAGS \
 		$(obj)cscope.* $(obj)*.*~
 	@rm -f $(obj)u-boot $(obj)u-boot.map $(obj)u-boot.hex $(ALL)
-	@rm -f $(obj)tools/{crc32.c,environment.c,env/crc32.c,md5.c,sha1.c,inca-swap-bytes}
+	@rm -f $(obj)tools/{crc32.c,env_embedded.c,env/crc32.c,md5.c,sha1.c,inca-swap-bytes}
 	@rm -f $(obj)tools/{image.c,fdt.c,fdt_ro.c,fdt_rw.c,fdt_strerror.c,zlib.h}
 	@rm -f $(obj)tools/{fdt_wip.c,libfdt_internal.h}
 	@rm -f $(obj)cpu/mpc824x/bedbug_603e.c

README.nios_CONFIG_SYS_NIOS_CPU

@@ -0,0 +1,140 @@
+
+===============================================================================
+	C F G _ N I O S _ C P U _ *   v s .   N I O S	S D K
+===============================================================================
+
+When ever you have to make a new NIOS CPU configuration you can use this table
+as a reference list to the original NIOS SDK symbols made by Alteras SOPC
+Builder. Look into excalibur.h and excalibur.s in your SDK path cpu_sdk/inc.
+Symbols beginning with a '[ptf]:' are coming from your SOPC sytem description
+(PTF file) in sections WIZARD_SCRIPT_ARGUMENTS or SYSTEM_BUILDER_INFO.
+
+C O R E					N I O S	  S D K			[1],[7]
+-------------------------------------------------------------------------------
+CONFIG_SYS_NIOS_CPU_CLK					nasys_clock_freq
+CONFIG_SYS_NIOS_CPU_ICACHE					nasys_icache_size
+CONFIG_SYS_NIOS_CPU_DCACHE					nasys_dcache_size
+CONFIG_SYS_NIOS_CPU_REG_NUMS					nasys_nios_num_regs
+CONFIG_SYS_NIOS_CPU_MUL					__nios_use_multiply__
+CONFIG_SYS_NIOS_CPU_MSTEP					__nios_use_mstep__
+CONFIG_SYS_NIOS_CPU_STACK					nasys_stack_top
+CONFIG_SYS_NIOS_CPU_VEC_BASE					nasys_vector_table
+CONFIG_SYS_NIOS_CPU_VEC_SIZE					nasys_vector_table_size
+CONFIG_SYS_NIOS_CPU_VEC_NUMS
+CONFIG_SYS_NIOS_CPU_RST_VECT					nasys_reset_address
+CONFIG_SYS_NIOS_CPU_DBG_CORE					nasys_debug_core
+CONFIG_SYS_NIOS_CPU_RAM_BASE		na_onchip_ram_64_kbytes
+CONFIG_SYS_NIOS_CPU_RAM_SIZE		na_onchip_ram_64_kbytes_size
+CONFIG_SYS_NIOS_CPU_ROM_BASE		na_boot_monitor_rom
+CONFIG_SYS_NIOS_CPU_ROM_SIZE		na_boot_monitor_rom_size
+CONFIG_SYS_NIOS_CPU_OCI_BASE					nasys_oci_core
+CONFIG_SYS_NIOS_CPU_OCI_SIZE
+CONFIG_SYS_NIOS_CPU_SRAM_BASE		na_ext_ram		nasys_program_mem
+							nasys_data_mem
+CONFIG_SYS_NIOS_CPU_SRAM_SIZE		na_ext_ram_size		nasys_program_mem_size
+							nasys_data_mem_size
+CONFIG_SYS_NIOS_CPU_SDRAM_BASE		 na_sdram
+CONFIG_SYS_NIOS_CPU_SDRAM_SIZE		 na_sdram_size
+CONFIG_SYS_NIOS_CPU_FLASH_BASE		 na_ext_flash		nasys_main_flash
+							nasys_am29lv065d_flash_0
+							nasys_flash_0
+CONFIG_SYS_NIOS_CPU_FLASH_SIZE	    na_ext_flash_size		nasys_main_flash_size
+
+T I M E R				N I O S	  S D K			    [3]
+-------------------------------------------------------------------------------
+CONFIG_SYS_NIOS_CPU_TIMER_NUMS					nasys_timer_count
+CONFIG_SYS_NIOS_CPU_TIMER[0-9]					nasys_timer_[0-9]
+CONFIG_SYS_NIOS_CPU_TIMER[0-9]_IRQ				nasys_timer_[0-9]_irq
+CONFIG_SYS_NIOS_CPU_TIMER[0-9]_PER				[ptf]:period
+							[ptf]:period_units
+							[ptf]:mult
+CONFIG_SYS_NIOS_CPU_TIMER[0-9]_AR				[ptf]:always_run
+CONFIG_SYS_NIOS_CPU_TIMER[0-9]_FP				[ptf]:fixed_period
+CONFIG_SYS_NIOS_CPU_TIMER[0-9]_SS				[ptf]:snapshot
+
+U A R T					N I O S	  S D K			    [2]
+-------------------------------------------------------------------------------
+CONFIG_SYS_NIOS_CPU_UART_NUMS					nasys_uart_count
+CONFIG_SYS_NIOS_CPU_UART[0-9]					nasys_uart_[0-9]
+CONFIG_SYS_NIOS_CPU_UART[0-9]_IRQ				nasys_uart_[0-9]_irq
+CONFIG_SYS_NIOS_CPU_UART[0-9]_BR				[ptf]:baud
+CONFIG_SYS_NIOS_CPU_UART[0-9]_DB				[ptf]:data_bits
+CONFIG_SYS_NIOS_CPU_UART[0-9]_SB				[ptf]:stop_bits
+CONFIG_SYS_NIOS_CPU_UART[0-9]_PA				[ptf]:parity
+CONFIG_SYS_NIOS_CPU_UART[0-9]_HS				[ptf]:use_cts_rts
+CONFIG_SYS_NIOS_CPU_UART[0-9]_EOP				[ptf]:use_eop_register
+
+P I O					N I O S	  S D K			    [4]
+-------------------------------------------------------------------------------
+CONFIG_SYS_NIOS_CPU_PIO_NUMS					nasys_pio_count
+CONFIG_SYS_NIOS_CPU_PIO[0-9]					nasys_pio_[0-9]
+CONFIG_SYS_NIOS_CPU_PIO[0-9]_IRQ				nasys_pio_[0-9]_irq
+CONFIG_SYS_NIOS_CPU_PIO[0-9]_BITS				[ptf]:Data_Width
+CONFIG_SYS_NIOS_CPU_PIO[0-9]_TYPE				[ptf]:has_tri
+							[ptf]:has_out
+							[ptf]:has_in
+CONFIG_SYS_NIOS_CPU_PIO[0-9]_CAP				[ptf]:capture
+CONFIG_SYS_NIOS_CPU_PIO[0-9]_EDGE				[ptf]:edge_type
+CONFIG_SYS_NIOS_CPU_PIO[0-9]_ITYPE				[ptf]:irq_type
+
+S P I					N I O S	  S D K			    [6]
+-------------------------------------------------------------------------------
+CONFIG_SYS_NIOS_CPU_SPI_NUMS					nasys_spi_count
+CONFIG_SYS_NIOS_CPU_SPI[0-9]					nasys_spi_[0-9]
+CONFIG_SYS_NIOS_CPU_SPI[0-9]_IRQ				nasys_spi_[0-9]_irq
+CONFIG_SYS_NIOS_CPU_SPI[0-9]_BITS				[ptf]:databits
+CONFIG_SYS_NIOS_CPU_SPI[0-9]_MA				[ptf]:ismaster
+CONFIG_SYS_NIOS_CPU_SPI[0-9]_SLN				[ptf]:numslaves
+CONFIG_SYS_NIOS_CPU_SPI[0-9]_TCLK				[ptf]:targetclock
+CONFIG_SYS_NIOS_CPU_SPI[0-9]_TDELAY				[ptf]:targetdelay
+CONFIG_SYS_NIOS_CPU_SPI[0-9]_*					[ptf]:*
+
+I D E					N I O S	  S D K
+-------------------------------------------------------------------------------
+CONFIG_SYS_NIOS_CPU_IDE_NUMS					nasys_usersocket_count
+CONFIG_SYS_NIOS_CPU_IDE[0-9]					nasys_usersocket_[0-9]
+
+A S M I					N I O S	  S D K			    [5]
+-------------------------------------------------------------------------------
+CONFIG_SYS_NIOS_CPU_ASMI_NUMS					nasys_asmi_count
+CONFIG_SYS_NIOS_CPU_ASMI[0-9]					nasys_asmi_[0-9]
+CONFIG_SYS_NIOS_CPU_ASMI[0-9]_IRQ				nasys_asmi_[0-9]_irq
+
+E t h e r n e t	  ( L A N )		N I O S	  S D K
+-------------------------------------------------------------------------------
+CONFIG_SYS_NIOS_CPU_LAN_NUMS
+CONFIG_SYS_NIOS_CPU_LAN[0-9]_BASE	na_lan91c111
+CONFIG_SYS_NIOS_CPU_LAN[0-9]_OFFS				LAN91C111_REGISTERS_OFFSET
+CONFIG_SYS_NIOS_CPU_LAN[0-9]_IRQ	na_lan91c111_irq
+CONFIG_SYS_NIOS_CPU_LAN[0-9]_BUSW				LAN91C111_DATA_BUS_WIDTH
+CONFIG_SYS_NIOS_CPU_LAN[0-9]_TYPE
+
+s y s t e m   c o m p o s i n g		N I O S	  S D K
+-------------------------------------------------------------------------------
+CONFIG_SYS_NIOS_CPU_TICK_TIMER		(na_low_priority_timer2)
+CONFIG_SYS_NIOS_CPU_USER_TIMER		(na_timer1)
+CONFIG_SYS_NIOS_CPU_BUTTON_PIO		(na_button_pio)
+CONFIG_SYS_NIOS_CPU_LCD_PIO		(na_lcd_pio)
+CONFIG_SYS_NIOS_CPU_LED_PIO		(na_led_pio)
+CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO	(na_seven_seg_pio)
+CONFIG_SYS_NIOS_CPU_RECONF_PIO		(na_reconfig_request_pio)
+CONFIG_SYS_NIOS_CPU_CFPRESENT_PIO	(na_cf_present_pio)
+CONFIG_SYS_NIOS_CPU_CFPOWER_PIO	(na_cf_power_pio)
+CONFIG_SYS_NIOS_CPU_CFATASEL_PIO	(na_cf_ata_select_pio)
+CONFIG_SYS_NIOS_CPU_USER_SPI		(na_spi)
+
+
+===============================================================================
+	R E F E R E N C E S
+===============================================================================
+[1]	http://www.altera.com/literature/ds/ds_nioscpu.pdf
+[2]	http://www.altera.com/literature/ds/ds_nios_uart.pdf
+[3]	http://www.altera.com/literature/ds/ds_nios_timer.pdf
+[4]	http://www.altera.com/literature/ds/ds_nios_pio.pdf
+[5]	http://www.altera.com/literature/ds/ds_nios_asmi.pdf
+[6]	http://www.altera.com/literature/ds/ds_nios_spi.pdf
+[7]	http://www.altera.com/literature/ds/ds_legacy_sdram_ctrl.pdf
+
+
+===============================================================================
+Stephan Linz <linz@li-pro.net>

api/api.c

@@ -534,7 +534,7 @@ static int API_env_enum(va_list ap)
 
 		for (i = 0; env_get_char(i) != '\0'; i = n + 1) {
 			for (n = i; env_get_char(n) != '\0'; ++n) {
-				if (n >= CFG_ENV_SIZE) {
+				if (n >= CONFIG_ENV_SIZE) {
 					/* XXX shouldn't we set *next = NULL?? */
 					return 0;
 				}

api/api_platform-ppc.c

@@ -66,7 +66,7 @@ int platform_sys_info(struct sys_info *si)
 	si->bar = gd->bd->bi_bar;
 #undef bi_bar
 #else
-	si->bar = NULL;
+	si->bar = 0;
 #endif
 
 	platform_set_mr(si, gd->bd->bi_memstart, gd->bd->bi_memsize, MR_ATTR_DRAM);

api/api_storage.c

@@ -30,6 +30,10 @@
 #include <common.h>
 #include <api_public.h>
 
+#if defined(CONFIG_CMD_USB) && defined(CONFIG_USB_STORAGE)
+#include <usb.h>
+#endif
+
 #define DEBUG
 #undef DEBUG
 
@@ -63,28 +67,28 @@ static struct stor_spec specs[ENUM_MAX] = { { 0, 0, 0, 0, "" }, };
 void dev_stor_init(void)
 {
 #if defined(CONFIG_CMD_IDE)
-	specs[ENUM_IDE].max_dev = CFG_IDE_MAXDEVICE;
+	specs[ENUM_IDE].max_dev = CONFIG_SYS_IDE_MAXDEVICE;
 	specs[ENUM_IDE].enum_started = 0;
 	specs[ENUM_IDE].enum_ended = 0;
 	specs[ENUM_IDE].type = DEV_TYP_STOR | DT_STOR_IDE;
 	specs[ENUM_IDE].name = "ide";
 #endif
 #if defined(CONFIG_CMD_MMC)
-	specs[ENUM_MMC].max_dev = CFG_MMC_MAX_DEVICE;
+	specs[ENUM_MMC].max_dev = CONFIG_SYS_MMC_MAX_DEVICE;
 	specs[ENUM_MMC].enum_started = 0;
 	specs[ENUM_MMC].enum_ended = 0;
 	specs[ENUM_MMC].type = DEV_TYP_STOR | DT_STOR_MMC;
 	specs[ENUM_MMC].name = "mmc";
 #endif
 #if defined(CONFIG_CMD_SATA)
-	specs[ENUM_SATA].max_dev = CFG_SATA_MAX_DEVICE;
+	specs[ENUM_SATA].max_dev = CONFIG_SYS_SATA_MAX_DEVICE;
 	specs[ENUM_SATA].enum_started = 0;
 	specs[ENUM_SATA].enum_ended = 0;
 	specs[ENUM_SATA].type = DEV_TYP_STOR | DT_STOR_SATA;
 	specs[ENUM_SATA].name = "sata";
 #endif
 #if defined(CONFIG_CMD_SCSI)
-	specs[ENUM_SCSI].max_dev = CFG_SCSI_MAX_DEVICE;
+	specs[ENUM_SCSI].max_dev = CONFIG_SYS_SCSI_MAX_DEVICE;
 	specs[ENUM_SCSI].enum_started = 0;
 	specs[ENUM_SCSI].enum_ended = 0;
 	specs[ENUM_SCSI].type = DEV_TYP_STOR | DT_STOR_SCSI;

blackfin_config.mk

@@ -24,7 +24,7 @@
 CONFIG_BFIN_CPU := $(strip $(subst ",,$(CONFIG_BFIN_CPU)))
 CONFIG_BFIN_BOOT_MODE := $(strip $(subst ",,$(CONFIG_BFIN_BOOT_MODE)))
 
-PLATFORM_RELFLAGS += -ffixed-P5
+PLATFORM_RELFLAGS += -ffixed-P5 -fomit-frame-pointer
 PLATFORM_CPPFLAGS += -DCONFIG_BLACKFIN
 
 ifneq (,$(CONFIG_BFIN_CPU))

board/AtmarkTechno/suzaku/flash.c

@@ -24,7 +24,7 @@
 
 #include <common.h>
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
 
 unsigned long flash_init(void)
 {

board/AtmarkTechno/suzaku/u-boot.lds

@@ -61,6 +61,7 @@ SECTIONS
 	{
 		__bss_start = .;
 		*(.bss)
+		. = ALIGN(4);
 		__bss_end = .;
 	}
 	__end = . ;

board/BuS/EB+MCF-EV123/EB+MCF-EV123.c

@@ -32,7 +32,7 @@
 int checkboard (void)
 {
 	puts ("Board: MCF-EV1 + MCF-EV23 (BuS Elektronik GmbH & Co. KG)\n");
-#if (TEXT_BASE ==  CFG_INT_FLASH_BASE)
+#if (TEXT_BASE ==  CONFIG_SYS_INT_FLASH_BASE)
 	puts ("       Boot from Internal FLASH\n");
 #endif
 
@@ -45,10 +45,10 @@ phys_size_t initdram (int board_type)
 
 	size = 0;
 	MCFSDRAMC_DCR = MCFSDRAMC_DCR_RTIM_6
-			| MCFSDRAMC_DCR_RC ((15 * CFG_CLK) >> 4);
-#ifdef CFG_SDRAM_BASE0
+			| MCFSDRAMC_DCR_RC ((15 * CONFIG_SYS_CLK) >> 4);
+#ifdef CONFIG_SYS_SDRAM_BASE0
 
-	MCFSDRAMC_DACR0 = MCFSDRAMC_DACR_BASE (CFG_SDRAM_BASE0)
+	MCFSDRAMC_DACR0 = MCFSDRAMC_DACR_BASE (CONFIG_SYS_SDRAM_BASE0)
 			| MCFSDRAMC_DACR_CASL (1)
 			| MCFSDRAMC_DACR_CBM (3)
 			| MCFSDRAMC_DACR_PS_16;
@@ -57,17 +57,17 @@ phys_size_t initdram (int board_type)
 
 	MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IP;
 
-	*(unsigned short *) (CFG_SDRAM_BASE0) = 0xA5A5;
+	*(unsigned short *) (CONFIG_SYS_SDRAM_BASE0) = 0xA5A5;
 	MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_RE;
 	for (i = 0; i < 2000; i++)
 		asm (" nop");
 	mbar_writeLong (MCFSDRAMC_DACR0,
 			mbar_readLong (MCFSDRAMC_DACR0) | MCFSDRAMC_DACR_IMRS);
-	*(unsigned int *) (CFG_SDRAM_BASE0 + 0x220) = 0xA5A5;
-	size += CFG_SDRAM_SIZE * 1024 * 1024;
+	*(unsigned int *) (CONFIG_SYS_SDRAM_BASE0 + 0x220) = 0xA5A5;
+	size += CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 #endif
-#ifdef CFG_SDRAM_BASE1
-	MCFSDRAMC_DACR1 = MCFSDRAMC_DACR_BASE (CFG_SDRAM_BASE1)
+#ifdef CONFIG_SYS_SDRAM_BASE1
+	MCFSDRAMC_DACR1 = MCFSDRAMC_DACR_BASE (CONFIG_SYS_SDRAM_BASE1)
 			| MCFSDRAMC_DACR_CASL (1)
 			| MCFSDRAMC_DACR_CBM (3)
 			| MCFSDRAMC_DACR_PS_16;
@@ -76,25 +76,25 @@ phys_size_t initdram (int board_type)
 
 	MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_IP;
 
-	*(unsigned short *) (CFG_SDRAM_BASE1) = 0xA5A5;
+	*(unsigned short *) (CONFIG_SYS_SDRAM_BASE1) = 0xA5A5;
 	MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_RE;
 
 	for (i = 0; i < 2000; i++)
 		asm (" nop");
 
 	MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_IMRS;
-	*(unsigned int *) (CFG_SDRAM_BASE1 + 0x220) = 0xA5A5;
-	size += CFG_SDRAM_SIZE1 * 1024 * 1024;
+	*(unsigned int *) (CONFIG_SYS_SDRAM_BASE1 + 0x220) = 0xA5A5;
+	size += CONFIG_SYS_SDRAM_SIZE1 * 1024 * 1024;
 #endif
 	return size;
 }
 
 
-#if defined(CFG_DRAM_TEST)
+#if defined(CONFIG_SYS_DRAM_TEST)
 int testdram (void)
 {
-	uint *pstart = (uint *) CFG_MEMTEST_START;
-	uint *pend = (uint *) CFG_MEMTEST_END;
+	uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
+	uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
 	uint *p;
 
 	printf("SDRAM test phase 1:\n");

board/BuS/EB+MCF-EV123/Makefile

@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	= $(BOARD).o cfm_flash.o flash.o VCxK.o mii.o
+COBJS	= $(BOARD).o cfm_flash.o flash.o VCxK.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))

board/BuS/EB+MCF-EV123/VCxK.c

@@ -25,7 +25,7 @@
 #include <asm/m5282.h>
 #include "VCxK.h"
 
-vu_char *vcxk_bws = (vu_char *)(CFG_CS3_BASE);
+vu_char *vcxk_bws = (vu_char *)(CONFIG_SYS_CS3_BASE);
 #define VCXK_BWS vcxk_bws
 
 static ulong vcxk_driver;

board/BuS/EB+MCF-EV123/cfm_flash.c

@@ -28,14 +28,14 @@
 
 #if defined(CONFIG_M5281) || defined(CONFIG_M5282)
 
-#if (CFG_CLK>20000000)
-	#define CFM_CLK  (((long) CFG_CLK / (400000 * 8) + 1) | 0x40)
+#if (CONFIG_SYS_CLK>20000000)
+	#define CFM_CLK  (((long) CONFIG_SYS_CLK / (400000 * 8) + 1) | 0x40)
 #else
-	#define CFM_CLK  ((long) CFG_CLK / 400000 + 1)
+	#define CFM_CLK  ((long) CONFIG_SYS_CLK / 400000 + 1)
 #endif
 
 #define cmf_backdoor_address(addr)	(((addr) & 0x0007FFFF) | 0x04000000 | \
-					 (CFG_MBAR & 0xC0000000))
+					 (CONFIG_SYS_MBAR & 0xC0000000))
 
 void cfm_flash_print_info (flash_info_t * info)
 {
@@ -60,8 +60,8 @@ void cfm_flash_init (flash_info_t * info)
 	MCFCFM_MCR = 0;
 	MCFCFM_CLKD = CFM_CLK;
 	debug ("CFM Clock divider: %ld (%d Hz @ %ld Hz)\n",CFM_CLK,\
-		CFG_CLK / (2* ((CFM_CLK & 0x3F)+1) * (1+((CFM_CLK & 0x40)>>6)*7)),\
-		CFG_CLK);
+		CONFIG_SYS_CLK / (2* ((CFM_CLK & 0x3F)+1) * (1+((CFM_CLK & 0x40)>>6)*7)),\
+		CONFIG_SYS_CLK);
 	MCFCFM_SACC = 0;
 	MCFCFM_DACC = 0;
 
@@ -86,7 +86,7 @@ void cfm_flash_init (flash_info_t * info)
 	{
 		if (sector == 0)
 		{
-			info->start[sector] = CFG_INT_FLASH_BASE;
+			info->start[sector] = CONFIG_SYS_INT_FLASH_BASE;
 		}
 		else
 		{
@@ -187,7 +187,7 @@ int cfm_flash_write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cn
 	return rc;
 }
 
-#ifdef CFG_FLASH_PROTECTION
+#ifdef CONFIG_SYS_FLASH_PROTECTION
 
 int cfm_flash_protect(flash_info_t * info,long sector,int prot)
 {

board/BuS/EB+MCF-EV123/cfm_flash.h

@@ -33,7 +33,7 @@ extern void cfm_flash_print_info (flash_info_t * info);
 extern int cfm_flash_erase_sector (flash_info_t * info, int sector);
 extern void cfm_flash_init (flash_info_t * info);
 extern int cfm_flash_write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt);
-#ifdef CFG_FLASH_PROTECTION
+#ifdef CONFIG_SYS_FLASH_PROTECTION
 extern int cfm_flash_protect(flash_info_t * info,long sector,int prot);
 #endif
 

board/BuS/EB+MCF-EV123/flash.c

@@ -27,10 +27,10 @@
 #include <common.h>
 #include  "cfm_flash.h"
 
-#define PHYS_FLASH_1 CFG_FLASH_BASE
+#define PHYS_FLASH_1 CONFIG_SYS_FLASH_BASE
 #define FLASH_BANK_SIZE 0x200000
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
 
 void flash_print_info (flash_info_t * info)
 {
@@ -83,7 +83,7 @@ unsigned long flash_init (void)
 	int i, j;
 	ulong size = 0;
 
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
 		ulong flashbase = 0;
 
 		switch (i)
@@ -93,8 +93,8 @@ unsigned long flash_init (void)
 				(AMD_MANUFACT & FLASH_VENDMASK) |
 				(AMD_ID_LV160B & FLASH_TYPEMASK);
 			flash_info[i].size = FLASH_BANK_SIZE;
-			flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
-			memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+			flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+			memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
 			flashbase = PHYS_FLASH_1;
 			for (j = 0; j < flash_info[i].sector_count; j++) {
 				if (j == 0) {
@@ -128,8 +128,8 @@ unsigned long flash_init (void)
 	}
 
 	flash_protect (FLAG_PROTECT_SET,
-		       CFG_FLASH_BASE,
-		       CFG_FLASH_BASE + 0xffff, &flash_info[0]);
+		       CONFIG_SYS_FLASH_BASE,
+		       CONFIG_SYS_FLASH_BASE + 0xffff, &flash_info[0]);
 
 	return size;
 }
@@ -177,7 +177,7 @@ int amd_flash_erase_sector(flash_info_t * info, int sector)
 		result = *addr;
 
 		/* check timeout */
-		if (get_timer (0) > CFG_FLASH_ERASE_TOUT) {
+		if (get_timer (0) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
 			state = ERR_TIMOUT;
 		}
@@ -303,7 +303,7 @@ volatile static int amd_write_word (flash_info_t * info, ulong dest, u16 data)
 		result = *addr;
 
 		/* check timeout */
-		if (get_timer (0) > CFG_FLASH_ERASE_TOUT) {
+		if (get_timer (0) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 				state = ERR_TIMOUT;
 		}
 		if (!state && ((result & BIT_RDY_MASK) == (data & BIT_RDY_MASK)))
@@ -390,7 +390,7 @@ int amd_flash_protect(flash_info_t * info,long sector,int prot)
 	return rc;
 }
 
-#ifdef CFG_FLASH_PROTECTION
+#ifdef CONFIG_SYS_FLASH_PROTECTION
 
 int flash_real_protect(flash_info_t * info,long sector,int prot)
 {

board/BuS/EB+MCF-EV123/mii.c

@@ -1,304 +0,0 @@
-/*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/fec.h>
-#include <asm/immap.h>
-
-#include <config.h>
-#include <net.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
-#undef MII_DEBUG
-#undef ET_DEBUG
-
-int fecpin_setclear(struct eth_device *dev, int setclear)
-{
-	if (setclear) {
-		MCFGPIO_PASPAR |= 0x0F00;
-		MCFGPIO_PEHLPAR = CFG_PEHLPAR;
-	} else {
-		MCFGPIO_PASPAR &= 0xF0FF;
-		MCFGPIO_PEHLPAR &= ~CFG_PEHLPAR;
-	}
-	return 0;
-}
-
-#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
-#include <miiphy.h>
-
-/* Make MII read/write commands for the FEC. */
-#define mk_mii_read(ADDR, REG)	(0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
-
-#define mk_mii_write(ADDR, REG, VAL)	(0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
-
-/* PHY identification */
-#define PHY_ID_LXT970		0x78100000	/* LXT970 */
-#define PHY_ID_LXT971		0x001378e0	/* LXT971 and 972 */
-#define PHY_ID_82555		0x02a80150	/* Intel 82555 */
-#define PHY_ID_QS6612		0x01814400	/* QS6612 */
-#define PHY_ID_AMD79C784	0x00225610	/* AMD 79C784 */
-#define PHY_ID_AMD79C874VC	0x0022561B	/* AMD 79C874 */
-#define PHY_ID_LSI80225		0x0016f870	/* LSI 80225 */
-#define PHY_ID_LSI80225B	0x0016f880	/* LSI 80225/B */
-#define PHY_ID_DP83848VV	0x20005C90	/* National 83848 */
-#define PHY_ID_DP83849		0x20005CA2	/* National 82849 */
-
-#define STR_ID_LXT970		"LXT970"
-#define STR_ID_LXT971		"LXT971"
-#define STR_ID_82555		"Intel82555"
-#define STR_ID_QS6612		"QS6612"
-#define STR_ID_AMD79C784	"AMD79C784"
-#define STR_ID_AMD79C874VC	"AMD79C874VC"
-#define STR_ID_LSI80225		"LSI80225"
-#define STR_ID_LSI80225B	"LSI80225/B"
-#define STR_ID_DP83848VV	"N83848"
-#define STR_ID_DP83849		"N83849"
-
-/****************************************************************************
- * mii_init -- Initialize the MII for MII command without ethernet
- * This function is a subset of eth_init
- ****************************************************************************
- */
-void mii_reset(struct fec_info_s *info)
-{
-	volatile fec_t *fecp = (fec_t *) (info->miibase);
-	int i;
-
-	fecp->ecr = FEC_ECR_RESET;
-	for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
-		udelay(1);
-	}
-	if (i == FEC_RESET_DELAY) {
-		printf("FEC_RESET_DELAY timeout\n");
-	}
-}
-
-/* send command to phy using mii, wait for result */
-uint mii_send(uint mii_cmd)
-{
-	struct fec_info_s *info;
-	struct eth_device *dev;
-	volatile fec_t *ep;
-	uint mii_reply;
-	int j = 0;
-
-	/* retrieve from register structure */
-	dev = eth_get_dev();
-	info = dev->priv;
-
-	ep = (fec_t *) info->miibase;
-
-	ep->mmfr = mii_cmd;	/* command to phy */
-
-	/* wait for mii complete */
-	while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
-		udelay(1);
-		j++;
-	}
-	if (j >= MCFFEC_TOUT_LOOP) {
-		printf("MII not complete\n");
-		return -1;
-	}
-
-	mii_reply = ep->mmfr;	/* result from phy */
-	ep->eir = FEC_EIR_MII;	/* clear MII complete */
-#ifdef ET_DEBUG
-	printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
-	       __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
-#endif
-
-	return (mii_reply & 0xffff);	/* data read from phy */
-}
-#endif				/* CFG_DISCOVER_PHY || CONFIG_CMD_MII */
-
-#if defined(CFG_DISCOVER_PHY)
-int mii_discover_phy(struct eth_device *dev)
-{
-#define MAX_PHY_PASSES 11
-	struct fec_info_s *info = dev->priv;
-	int phyaddr, pass;
-	uint phyno, phytype;
-
-	if (info->phyname_init)
-		return info->phy_addr;
-
-	phyaddr = -1;		/* didn't find a PHY yet */
-	for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
-		if (pass > 1) {
-			/* PHY may need more time to recover from reset.
-			 * The LXT970 needs 50ms typical, no maximum is
-			 * specified, so wait 10ms before try again.
-			 * With 11 passes this gives it 100ms to wake up.
-			 */
-			udelay(10000);	/* wait 10ms */
-		}
-
-		for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
-
-			phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
-#ifdef ET_DEBUG
-			printf("PHY type 0x%x pass %d type\n", phytype, pass);
-#endif
-			if (phytype != 0xffff) {
-				phyaddr = phyno;
-				phytype <<= 16;
-				phytype |=
-				    mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
-
-				switch (phytype & 0xffffffff) {
-				case PHY_ID_AMD79C874VC:
-					strcpy(info->phy_name,
-					       STR_ID_AMD79C874VC);
-					info->phyname_init = 1;
-					break;
-				default:
-					strcpy(info->phy_name, "unknown");
-					info->phyname_init = 1;
-					break;
-				}
-
-#ifdef ET_DEBUG
-				printf("PHY @ 0x%x pass %d type ", phyno, pass);
-				switch (phytype & 0xffffffff) {
-				case PHY_ID_AMD79C874VC:
-					printf(STR_ID_AMD79C874VC);
-					break;
-				default:
-					printf("0x%08x\n", phytype);
-					break;
-				}
-#endif
-			}
-		}
-	}
-	if (phyaddr < 0)
-		printf("No PHY device found.\n");
-
-	return phyaddr;
-}
-#endif				/* CFG_DISCOVER_PHY */
-
-void mii_init(void) __attribute__((weak,alias("__mii_init")));
-
-void __mii_init(void)
-{
-	volatile fec_t *fecp;
-	struct fec_info_s *info;
-	struct eth_device *dev;
-	int miispd = 0, i = 0;
-	u16 autoneg = 0;
-
-	/* retrieve from register structure */
-	dev = eth_get_dev();
-	info = dev->priv;
-
-	fecp = (fec_t *) info->miibase;
-
-	fecpin_setclear(dev, 1);
-
-	mii_reset(info);
-
-	/* We use strictly polling mode only */
-	fecp->eimr = 0;
-
-	/* Clear any pending interrupt */
-	fecp->eir = 0xffffffff;
-
-	/* Set MII speed */
-	miispd = (gd->bus_clk / 1000000) / 5;
-	fecp->mscr = miispd << 1;
-
-	info->phy_addr = mii_discover_phy(dev);
-
-#define AUTONEGLINK		(PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
-	while (i < MCFFEC_TOUT_LOOP) {
-		autoneg = 0;
-		miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
-		i++;
-
-		if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
-			break;
-
-		udelay(500);
-	}
-	if (i >= MCFFEC_TOUT_LOOP) {
-		printf("Auto Negotiation not complete\n");
-	}
-
-	/* adapt to the half/full speed settings */
-	info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
-	info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
-}
-
-/*****************************************************************************
- * Read and write a MII PHY register, routines used by MII Utilities
- *
- * FIXME: These routines are expected to return 0 on success, but mii_send
- *	  does _not_ return an error code. Maybe 0xFFFF means error, i.e.
- *	  no PHY connected...
- *	  For now always return 0.
- * FIXME: These routines only work after calling eth_init() at least once!
- *	  Otherwise they hang in mii_send() !!! Sorry!
- *****************************************************************************/
-
-int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
-		       unsigned short *value)
-{
-	short rdreg;		/* register working value */
-
-#ifdef MII_DEBUG
-	printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
-#endif
-	rdreg = mii_send(mk_mii_read(addr, reg));
-
-	*value = rdreg;
-
-#ifdef MII_DEBUG
-	printf("0x%04x\n", *value);
-#endif
-
-	return 0;
-}
-
-int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
-			unsigned short value)
-{
-	short rdreg;		/* register working value */
-
-#ifdef MII_DEBUG
-	printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
-#endif
-
-	rdreg = mii_send(mk_mii_write(addr, reg, value));
-
-#ifdef MII_DEBUG
-	printf("0x%04x\n", value);
-#endif
-
-	return 0;
-}
-
-#endif				/* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */

board/BuS/EB+MCF-EV123/u-boot.lds

@@ -63,7 +63,7 @@ SECTIONS
     lib_generic/zlib.o	(.text)
 
 /*    . = env_offset; */
-    common/environment.o(.text)
+    common/env_embedded.o(.text)
 
     *(.text)
     *(.fixup)

board/LEOX/elpt860/README.LEOX

@@ -106,7 +106,7 @@ version - print monitor version
 ?       - alias for 'help'
 
 ##################################################
-# Environment Variables (CFG_ENV_IS_IN_NVRAM)
+# Environment Variables (CONFIG_ENV_IS_IN_NVRAM)
 ##############################
 
 LEOX_elpt860: printenv

board/LEOX/elpt860/elpt860.c

@@ -138,23 +138,23 @@ const uint sdram_table[] = {
 
 /* ------------------------------------------------------------------------- */
 
-#define CFG_PC4    0x0800
+#define CONFIG_SYS_PC4    0x0800
 
-#define CFG_DS1    CFG_PC4
+#define CONFIG_SYS_DS1    CONFIG_SYS_PC4
 
 /*
  * Very early board init code (fpga boot, etc.)
  */
 int board_early_init_f (void)
 {
-	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 
 	/*
 	 * Light up the red led on ELPT860 pcb (DS1) (PCDAT)
 	 */
-	immr->im_ioport.iop_pcdat &= ~CFG_DS1;	/* PCDAT (DS1 = 0)                */
-	immr->im_ioport.iop_pcpar &= ~CFG_DS1;	/* PCPAR (0=general purpose I/O)  */
-	immr->im_ioport.iop_pcdir |= CFG_DS1;	/* PCDIR (I/O: 0=input, 1=output) */
+	immr->im_ioport.iop_pcdat &= ~CONFIG_SYS_DS1;	/* PCDAT (DS1 = 0)                */
+	immr->im_ioport.iop_pcpar &= ~CONFIG_SYS_DS1;	/* PCPAR (0=general purpose I/O)  */
+	immr->im_ioport.iop_pcdir |= CONFIG_SYS_DS1;	/* PCDIR (I/O: 0=input, 1=output) */
 
 	return (0);		/* success */
 }
@@ -181,7 +181,7 @@ int checkboard (void)
 
 phys_size_t initdram (int board_type)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	long int size8, size9;
 	long int size_b0 = 0;
@@ -207,7 +207,7 @@ phys_size_t initdram (int board_type)
 	 * with two SDRAM banks or four cycles every 31.2 us with one
 	 * bank. It will be adjusted after memory sizing.
 	 */
-	memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K;
 
 	/*
 	 * The following value is used as an address (i.e. opcode) for
@@ -229,10 +229,10 @@ phys_size_t initdram (int board_type)
 	 * preliminary addresses - these have to be modified after the
 	 * SDRAM size has been determined.
 	 */
-	memctl->memc_or1 = CFG_OR1_PRELIM;
-	memctl->memc_br1 = CFG_BR1_PRELIM;
+	memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
+	memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
 
-	memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */
+	memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */
 
 	udelay (200);
 
@@ -252,7 +252,7 @@ phys_size_t initdram (int board_type)
 	 *
 	 * try 8 column mode
 	 */
-	size8 = dram_size (CFG_MAMR_8COL,
+	size8 = dram_size (CONFIG_SYS_MAMR_8COL,
 			   SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
 
 	udelay (1000);
@@ -260,7 +260,7 @@ phys_size_t initdram (int board_type)
 	/*
 	 * try 9 column mode
 	 */
-	size9 = dram_size (CFG_MAMR_9COL,
+	size9 = dram_size (CONFIG_SYS_MAMR_9COL,
 			   SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
 
 	if (size8 < size9) {	/* leave configuration at 9 columns       */
@@ -269,7 +269,7 @@ phys_size_t initdram (int board_type)
 	} else {		/* back to 8 columns                      */
 
 		size_b0 = size8;
-		memctl->memc_mamr = CFG_MAMR_8COL;
+		memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
 		udelay (500);
 		/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
 	}
@@ -282,22 +282,22 @@ phys_size_t initdram (int board_type)
 	 */
 	if (size_b0 < 0x02000000) {
 		/* reduce to 15.6 us (62.4 us / quad) */
-		memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
+		memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
 		udelay (1000);
 	}
 
 	/*
 	 * Final mapping: map bigger bank first
 	 */
-	memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
-	memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+	memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
+	memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
 
 	{
 		unsigned long reg;
 
 		/* adjust refresh rate depending on SDRAM type, one bank */
 		reg = memctl->memc_mptpr;
-		reg >>= 1;	/* reduce to CFG_MPTPR_1BK_8K / _4K */
+		reg >>= 1;	/* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
 		memctl->memc_mptpr = reg;
 	}
 
@@ -319,7 +319,7 @@ phys_size_t initdram (int board_type)
 static long int
 dram_size (long int mamr_value, long int *base, long int maxsize)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 
 	memctl->memc_mamr = mamr_value;
@@ -329,20 +329,20 @@ dram_size (long int mamr_value, long int *base, long int maxsize)
 
 /* ------------------------------------------------------------------------- */
 
-#define CFG_PA1     0x4000
-#define CFG_PA2     0x2000
+#define CONFIG_SYS_PA1     0x4000
+#define CONFIG_SYS_PA2     0x2000
 
-#define CFG_LBKs    (CFG_PA2 | CFG_PA1)
+#define CONFIG_SYS_LBKs    (CONFIG_SYS_PA2 | CONFIG_SYS_PA1)
 
 void reset_phy (void)
 {
-	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 
 	/*
 	 * Ensure LBK LXT901 ethernet 1 & 2 = 0 ... for normal loopback in effect
 	 *                                          and no AUI loopback
 	 */
-	immr->im_ioport.iop_padat &= ~CFG_LBKs;	/* PADAT (LBK eth 1&2 = 0)        */
-	immr->im_ioport.iop_papar &= ~CFG_LBKs;	/* PAPAR (0=general purpose I/O)  */
-	immr->im_ioport.iop_padir |= CFG_LBKs;	/* PADIR (I/O: 0=input, 1=output) */
+	immr->im_ioport.iop_padat &= ~CONFIG_SYS_LBKs;	/* PADAT (LBK eth 1&2 = 0)        */
+	immr->im_ioport.iop_papar &= ~CONFIG_SYS_LBKs;	/* PAPAR (0=general purpose I/O)  */
+	immr->im_ioport.iop_padir |= CONFIG_SYS_LBKs;	/* PADIR (I/O: 0=input, 1=output) */
 }

board/LEOX/elpt860/flash.c

@@ -33,7 +33,7 @@
 /*
 ** Note 1: In this file, you have to provide the following variable:
 ** ------
-**              flash_info_t    flash_info[CFG_MAX_FLASH_BANKS]
+**              flash_info_t    flash_info[CONFIG_SYS_MAX_FLASH_BANKS]
 ** 'flash_info_t' structure is defined into 'include/flash.h'
 ** and defined as extern into 'common/cmd_flash.c'
 **
@@ -61,11 +61,11 @@
 #include <mpc8xx.h>
 
 
-#ifndef	CFG_ENV_ADDR
-#  define CFG_ENV_ADDR	(CFG_FLASH_BASE + CFG_ENV_OFFSET)
+#ifndef	CONFIG_ENV_ADDR
+#  define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
 #endif
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
 
 /*-----------------------------------------------------------------------
  * Internal Functions
@@ -82,13 +82,13 @@ static int write_byte (flash_info_t *info, ulong dest, uchar data);
 unsigned long
 flash_init (void)
 {
-  volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+  volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
   volatile memctl8xx_t *memctl = &immap->im_memctl;
   unsigned long         size_b0;
   int i;
 
   /* Init: no FLASHes known */
-  for (i=0; i<CFG_MAX_FLASH_BANKS; ++i)
+  for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i)
     {
       flash_info[i].flash_id = FLASH_UNKNOWN;
     }
@@ -105,28 +105,28 @@ flash_init (void)
     }
 
   /* Remap FLASH according to real size */
-  memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK);
-  memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_PS_8 | BR_V;
+  memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK);
+  memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_PS_8 | BR_V;
 
   /* Re-do sizing to get full correct info */
-  size_b0 = flash_get_size ((volatile unsigned char *)CFG_FLASH_BASE,
+  size_b0 = flash_get_size ((volatile unsigned char *)CONFIG_SYS_FLASH_BASE,
 			    &flash_info[0]);
 
-  flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+  flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
   /* monitor protection ON by default */
   flash_protect (FLAG_PROTECT_SET,
-		 CFG_MONITOR_BASE,
-		 CFG_MONITOR_BASE + monitor_flash_len-1,
+		 CONFIG_SYS_MONITOR_BASE,
+		 CONFIG_SYS_MONITOR_BASE + monitor_flash_len-1,
 		 &flash_info[0]);
 #endif
 
-#ifdef	CFG_ENV_IS_IN_FLASH
+#ifdef	CONFIG_ENV_IS_IN_FLASH
   /* ENV protection ON by default */
   flash_protect(FLAG_PROTECT_SET,
-		CFG_ENV_ADDR,
-		CFG_ENV_ADDR + CFG_ENV_SIZE-1,
+		CONFIG_ENV_ADDR,
+		CONFIG_ENV_ADDR + CONFIG_ENV_SIZE-1,
 		&flash_info[0]);
 #endif
 
@@ -383,7 +383,7 @@ flash_erase (flash_info_t  *info,
   addr = (volatile unsigned char *)(info->start[l_sect]);
   while ( (addr[0] & 0x80) != 0x80 )
     {
-      if ( (now = get_timer(start)) > CFG_FLASH_ERASE_TOUT )
+      if ( (now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT )
 	{
 	  printf ("Timeout\n");
 	  return ( 1 );
@@ -556,7 +556,7 @@ write_word (flash_info_t  *info,
   start = get_timer (0);
   while ( (*((vu_long *)dest) & 0x00800080) != (data & 0x00800080) )
     {
-      if ( get_timer(start) > CFG_FLASH_WRITE_TOUT )
+      if ( get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT )
 	{
 	  return (1);
 	}
@@ -602,7 +602,7 @@ write_byte (flash_info_t  *info,
   start = get_timer (0);
   while ( (*((volatile unsigned char *)dest) & 0x80) != (data & 0x80) )
     {
-      if ( get_timer(start) > CFG_FLASH_WRITE_TOUT )
+      if ( get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT )
 	{
 	  return (1);
 	}

board/LEOX/elpt860/u-boot.lds

@@ -77,7 +77,7 @@ SECTIONS
     lib_ppc/ticks.o			(.text)
 
     . = env_offset;
-    common/environment.o		(.text)
+    common/env_embedded.o		(.text)
 
     *(.text)
     *(.fixup)
@@ -147,6 +147,7 @@ SECTIONS
    *(.dynbss)
    *(.bss)
    *(COMMON)
+   . = ALIGN(4);
   }
   _end = . ;
   PROVIDE (end = .);

board/LEOX/elpt860/u-boot.lds.debug

@@ -70,7 +70,7 @@ SECTIONS
     lib_generic/crc32.o		(.text)
 
     . = env_offset;
-    common/environment.o	(.text)
+    common/env_embedded.o	(.text)
 
     *(.text)
     *(.fixup)

board/MAI/AmigaOneG3SE/AmigaOneG3SE.c

@@ -26,6 +26,7 @@
 #include <common.h>
 #include <command.h>
 #include <pci.h>
+#include <netdev.h>
 #include "articiaS.h"
 #include "memio.h"
 #include "via686.h"
@@ -111,3 +112,11 @@ void pci_init_board (void)
 	articiaS_pci_init ();
 #endif
 }
+
+int board_eth_init(bd_t *bis)
+{
+#if defined(CONFIG_3COM)
+	eth_3com_initialize(bis);
+#endif
+	return 0;
+}

board/MAI/AmigaOneG3SE/cmd_boota.c

@@ -27,7 +27,7 @@ struct bootcode_block bblk;
 
 int do_boota (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 {
-	unsigned char *load_address = (unsigned char *) CFG_LOAD_ADDR;
+	unsigned char *load_address = (unsigned char *) CONFIG_SYS_LOAD_ADDR;
 	unsigned char *base_address;
 	unsigned long offset;
 

board/MAI/AmigaOneG3SE/enet.c

@@ -28,6 +28,7 @@
 #include <common.h>
 #include <malloc.h>
 #include <net.h>
+#include <netdev.h>
 #include <asm/io.h>
 #include <pci.h>
 

board/MAI/AmigaOneG3SE/flash.c

@@ -1,14 +1,14 @@
 #include <common.h>
 #include <flash.h>
 
-flash_info_t    flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t    flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
 
 
 unsigned long flash_init(void)
 {
     int i;
 
-    for (i = 0; i < CFG_MAX_FLASH_BANKS; i++)
+    for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
     {
 	flash_info[i].flash_id = FLASH_UNKNOWN;
 	flash_info[i].sector_count = 0;

board/MAI/AmigaOneG3SE/flash_new.c

@@ -39,7 +39,7 @@
 #endif
 /*---------------------------------------------------------------------*/
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
 
 static ulong flash_get_size (ulong addr, flash_info_t *info);
 static int flash_get_offsets (ulong base, flash_info_t *info);
@@ -80,7 +80,7 @@ unsigned long flash_init_old(void)
 {
     int i;
 
-    for (i = 0; i < CFG_MAX_FLASH_BANKS; i++)
+    for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
     {
 	flash_info[i].flash_id = FLASH_UNKNOWN;
 	flash_info[i].sector_count = 0;
@@ -101,33 +101,33 @@ unsigned long flash_init (void)
 	flash_to_xd();
 
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 		flash_info[i].sector_count = 0;
 		flash_info[i].size = 0;
 	}
 
-	DEBUGF("\n## Get flash size @ 0x%08x\n", CFG_FLASH_BASE);
+	DEBUGF("\n## Get flash size @ 0x%08x\n", CONFIG_SYS_FLASH_BASE);
 
-	flash_size = flash_get_size (CFG_FLASH_BASE, flash_info);
+	flash_size = flash_get_size (CONFIG_SYS_FLASH_BASE, flash_info);
 
 	DEBUGF("## Flash bank size: %08lx\n", flash_size);
 
 	if (flash_size) {
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE && \
-    CFG_MONITOR_BASE < CFG_FLASH_BASE + CFG_FLASH_MAX_SIZE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE && \
+    CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_MAX_SIZE
 		/* monitor protection ON by default */
 		flash_protect(FLAG_PROTECT_SET,
-			      CFG_MONITOR_BASE,
-			      CFG_MONITOR_BASE + monitor_flash_len - 1,
+			      CONFIG_SYS_MONITOR_BASE,
+			      CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
 			      &flash_info[0]);
 #endif
 
-#ifdef CFG_ENV_IS_IN_FLASH
+#ifdef CONFIG_ENV_IS_IN_FLASH
 		/* ENV protection ON by default */
 		flash_protect(FLAG_PROTECT_SET,
-			      CFG_ENV_ADDR,
-			      CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
+			      CONFIG_ENV_ADDR,
+			      CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
 			      &flash_info[0]);
 #endif
 
@@ -286,10 +286,10 @@ static ulong flash_get_size (ulong addr, flash_info_t *info)
 
 	}
 
-	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
 		printf ("** ERROR: sector count %d > max (%d) **\n",
-			info->sector_count, CFG_MAX_FLASH_SECT);
-		info->sector_count = CFG_MAX_FLASH_SECT;
+			info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
 	}
 
 	if (! flash_get_offsets (addr, info)) {
@@ -418,10 +418,10 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
 	last  = start;
 	addr = info->start[l_sect];
 
-	DEBUGF ("Start erase timeout: %d\n", CFG_FLASH_ERASE_TOUT);
+	DEBUGF ("Start erase timeout: %d\n", CONFIG_SYS_FLASH_ERASE_TOUT);
 
 	while ((in8(addr) & 0x80) != 0x80) {
-		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf ("Timeout\n");
 			flash_reset (info->start[0]);
 			flash_to_mem();
@@ -562,7 +562,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data)
 		/* data polling for D7 */
 		start = get_timer (0);
 		while ((in8(dest+i) & 0x80) != (data_ch[i] & 0x80)) {
-			if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 				flash_reset (addr);
 				flash_to_mem();
 				return (1);

board/MAI/AmigaOneG3SE/i8259.h

@@ -21,20 +21,20 @@
  * MA 02111-1307 USA
  */
 
-#define ICW1_1  CFG_ISA_IO_BASE_ADDRESS + ISA_INT1_ICW1
-#define ICW1_2  CFG_ISA_IO_BASE_ADDRESS + ISA_INT2_ICW1
-#define ICW2_1  CFG_ISA_IO_BASE_ADDRESS + ISA_INT1_ICW2
-#define ICW2_2  CFG_ISA_IO_BASE_ADDRESS + ISA_INT2_ICW2
-#define ICW3_1  CFG_ISA_IO_BASE_ADDRESS + ISA_INT1_ICW3
-#define ICW3_2  CFG_ISA_IO_BASE_ADDRESS + ISA_INT2_ICW3
-#define ICW4_1  CFG_ISA_IO_BASE_ADDRESS + ISA_INT1_ICW4
-#define ICW4_2  CFG_ISA_IO_BASE_ADDRESS + ISA_INT2_ICW4
-#define OCW1_1  CFG_ISA_IO_BASE_ADDRESS + ISA_INT1_OCW1
-#define OCW1_2  CFG_ISA_IO_BASE_ADDRESS + ISA_INT2_OCW1
-#define OCW2_1  CFG_ISA_IO_BASE_ADDRESS + ISA_INT1_OCW2
-#define OCW2_2  CFG_ISA_IO_BASE_ADDRESS + ISA_INT2_OCW2
-#define OCW3_1  CFG_ISA_IO_BASE_ADDRESS + ISA_INT1_OCW3
-#define OCW3_2  CFG_ISA_IO_BASE_ADDRESS + ISA_INT2_OCW3
+#define ICW1_1  CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT1_ICW1
+#define ICW1_2  CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT2_ICW1
+#define ICW2_1  CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT1_ICW2
+#define ICW2_2  CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT2_ICW2
+#define ICW3_1  CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT1_ICW3
+#define ICW3_2  CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT2_ICW3
+#define ICW4_1  CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT1_ICW4
+#define ICW4_2  CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT2_ICW4
+#define OCW1_1  CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT1_OCW1
+#define OCW1_2  CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT2_OCW1
+#define OCW2_1  CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT1_OCW2
+#define OCW2_2  CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT2_OCW2
+#define OCW3_1  CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT1_OCW3
+#define OCW3_2  CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT2_OCW3
 
 #define IMR_1   OCW1_1
 #define IMR_2   OCW1_2

board/MAI/AmigaOneG3SE/interrupts.c

@@ -119,12 +119,12 @@ int interrupt_init (void)
 #ifdef DEBUG
 	puts("interrupt_init: setting decrementer_count\n");
 #endif
-	decrementer_count = get_tbclk() / CFG_HZ;
+	decrementer_count = get_tbclk() / CONFIG_SYS_HZ;
 
 #ifdef DEBUG
 	puts("interrupt_init: setting actual decremter\n");
 #endif
-	set_dec (get_tbclk() / CFG_HZ);
+	set_dec (get_tbclk() / CONFIG_SYS_HZ);
 
 #ifdef DEBUG
 	puts("interrupt_init: clearing external interrupt table\n");

board/MAI/AmigaOneG3SE/ps2kbd.c

@@ -214,7 +214,7 @@ int isa_kbd_init (void)
 	}
 }
 
-#ifdef CFG_CONSOLE_OVERWRITE_ROUTINE
+#ifdef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
 extern int overwrite_console (void);
 #else
 int overwrite_console (void)
@@ -492,22 +492,22 @@ unsigned char handle_kbd_event (void)
  */
 unsigned char kbd_read_status(void)
 {
-	return(in8(CFG_ISA_IO_BASE_ADDRESS + KDB_COMMAND_PORT));
+	return(in8(CONFIG_SYS_ISA_IO_BASE_ADDRESS + KDB_COMMAND_PORT));
 }
 
 unsigned char kbd_read_input(void)
 {
-	return(in8(CFG_ISA_IO_BASE_ADDRESS + KDB_DATA_PORT));
+	return(in8(CONFIG_SYS_ISA_IO_BASE_ADDRESS + KDB_DATA_PORT));
 }
 
 void kbd_write_command(unsigned char cmd)
 {
-	out8(CFG_ISA_IO_BASE_ADDRESS + KDB_COMMAND_PORT,cmd);
+	out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS + KDB_COMMAND_PORT,cmd);
 }
 
 void kbd_write_output(unsigned char data)
 {
-	out8(CFG_ISA_IO_BASE_ADDRESS + KDB_DATA_PORT, data);
+	out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS + KDB_DATA_PORT, data);
 }
 
 int kbd_read_data(void)

board/MAI/AmigaOneG3SE/serial.c

@@ -6,7 +6,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#ifndef CFG_NS16550
+#ifndef CONFIG_SYS_NS16550
 static uint32 ComPort1;
 
 uint16 SerialEcho = 1;
@@ -147,8 +147,8 @@ void serial_debug_putc (int c)
 
 #else
 
-const NS16550_t Com0 = (NS16550_t) CFG_NS16550_COM1;
-const NS16550_t Com1 = (NS16550_t) CFG_NS16550_COM2;
+const NS16550_t Com0 = (NS16550_t) CONFIG_SYS_NS16550_COM1;
+const NS16550_t Com1 = (NS16550_t) CONFIG_SYS_NS16550_COM2;
 
 int serial_init (void)
 {

board/MAI/AmigaOneG3SE/u-boot.lds

@@ -62,7 +62,7 @@ SECTIONS
     cpu/74xx_7xx/start.o	(.text)
 /* store the environment in a seperate sector in the boot flash */
 /*    . = env_offset; */
-    common/environment.o(.text)
+    common/env_embedded.o(.text)
 
     *(.text)
     *(.fixup)

board/MAI/AmigaOneG3SE/usb_uhci.c

@@ -627,7 +627,7 @@ int usb_lowlevel_init(void)
 	pci_read_config_dword(busdevfunc,PCI_BASE_ADDRESS_4,&usb_base_addr);
 	USB_UHCI_PRINTF("IO Base Address = 0x%lx\n",usb_base_addr);
 	usb_base_addr&=0xFFFFFFF0;
-	usb_base_addr+=CFG_ISA_IO_BASE_ADDRESS;
+	usb_base_addr+=CONFIG_SYS_ISA_IO_BASE_ADDRESS;
 	rh.devnum = 0;
 	usb_init_skel();
 	reset_hc();
@@ -801,7 +801,7 @@ int uhci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
 	unsigned short wIndex;
 	unsigned short wLength;
 
-	if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) {
+	if (usb_pipeint(pipe)) {
 		printf("Root-Hub submit IRQ: NOT implemented\n");
 #if 0
 		uhci->rh.urb = urb;

board/Marvell/common/bootseq.txt

@@ -88,7 +88,7 @@ in_flash:
 		    nothing
 		mem_malloc_init
 		malloc_bin_reloc
-		spi_init (r or f)??? (CFG_ENV_IS_IN_EEPROM)
+		spi_init (r or f)??? (CONFIG_ENV_IS_IN_EEPROM)
 		env_relocated
 		misc_init_r(bd): (board/evb64260/evb64260.c)
 		    mpsc_init2

board/Marvell/common/flash.c

@@ -48,7 +48,7 @@
 int flash_erase_intel (flash_info_t * info, int s_first, int s_last);
 int write_word_intel (bank_addr_t addr, bank_word_t value);
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips */
 
 /*-----------------------------------------------------------------------
  * Functions
@@ -68,14 +68,14 @@ unsigned long flash_init (void)
 	unsigned long base, flash_size;
 
 	/* Init: no FLASHes known */
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
 	/* the boot flash */
-	base = CFG_FLASH_BASE;
+	base = CONFIG_SYS_FLASH_BASE;
 	size_b0 =
-		flash_get_size (CFG_BOOT_FLASH_WIDTH, (vu_long *) base,
+		flash_get_size (CONFIG_SYS_BOOT_FLASH_WIDTH, (vu_long *) base,
 				&flash_info[0]);
 
 	printf ("[%ldkB@%lx] ", size_b0 / 1024, base);
@@ -84,11 +84,11 @@ unsigned long flash_init (void)
 		printf ("## Unknown FLASH at %08lx: Size = 0x%08lx = %ld MB\n", base, size_b0, size_b0 << 20);
 	}
 
-	base = memoryGetDeviceBaseAddress (CFG_EXTRA_FLASH_DEVICE);
+	base = memoryGetDeviceBaseAddress (CONFIG_SYS_EXTRA_FLASH_DEVICE);
 /*	base = memoryGetDeviceBaseAddress(DEV_CS3_BASE_ADDR);*/
-	for (i = 1; i < CFG_MAX_FLASH_BANKS; i++) {
+	for (i = 1; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
 		unsigned long size =
-			flash_get_size (CFG_EXTRA_FLASH_WIDTH,
+			flash_get_size (CONFIG_SYS_EXTRA_FLASH_WIDTH,
 					(vu_long *) base, &flash_info[i]);
 
 		printf ("[%ldMB@%lx] ", size >> 20, base);
@@ -617,7 +617,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
 							/* has the timeout limit been reached? */
 							if (get_timer (start)
 							    >
-							    CFG_FLASH_ERASE_TOUT)
+							    CONFIG_SYS_FLASH_ERASE_TOUT)
 							{
 								/* timeout limit reached */
 								printf ("Time out limit reached erasing sector at address %08lx\n", info->start[sect]);
@@ -776,7 +776,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
 	addr = (volatile unsigned char *) (info->start[l_sect]);
 	/* broken for 2x16: TODO */
 	while ((addr[0] & 0x80) != 0x80) {
-		if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
+		if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf ("Timeout\n");
 			return 1;
 		}
@@ -956,7 +956,7 @@ static int write_word (flash_info_t * info, ulong dest, ulong data)
 				{
 					/* has the timeout limit been reached? */
 					if (get_timer (start) >
-					    CFG_FLASH_WRITE_TOUT) {
+					    CONFIG_SYS_FLASH_WRITE_TOUT) {
 						/* timeout limit reached */
 						printf ("Time out limit reached programming address %08lx with data %08lx\n", dest, data);
 						/* reset the flash */
@@ -1064,7 +1064,7 @@ static int write_word (flash_info_t * info, ulong dest, ulong data)
 	/* data polling for D7 */
 	start = get_timer (0);
 	while ((*((vu_long *) dest) & 0x00800080) != (data & 0x00800080)) {
-		if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			return (1);
 		}
 	}

board/Marvell/common/i2c.c

@@ -48,7 +48,7 @@ static void i2c_init (int speed, int slaveaddr)
 	unsigned int actualN = 0, actualM = 0;
 	unsigned int control, status;
 	unsigned int minMargin = 0xffffffff;
-	unsigned int tclk = CFG_TCLK;
+	unsigned int tclk = CONFIG_SYS_TCLK;
 	unsigned int i2cFreq = speed;	/* 100000 max. Fast mode not supported */
 
 	DP (puts ("i2c_init\n"));
@@ -372,7 +372,7 @@ i2c_read (uchar dev_addr, unsigned int offset, int alen, uchar * data,
 	  int len)
 {
 	uchar status = 0;
-	unsigned int i2cFreq = CFG_I2C_SPEED;
+	unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED;
 
 	DP (puts ("i2c_read\n"));
 
@@ -447,7 +447,7 @@ i2c_write (uchar dev_addr, unsigned int offset, int alen, uchar * data,
 	   int len)
 {
 	uchar status = 0;
-	unsigned int i2cFreq = CFG_I2C_SPEED;
+	unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED;
 
 	DP (puts ("i2c_write\n"));
 
@@ -500,7 +500,7 @@ int i2c_probe (uchar chip)
 	unsigned int i2c_status;
 #endif
 	uchar status = 0;
-	unsigned int i2cFreq = CFG_I2C_SPEED;
+	unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED;
 
 	DP (puts ("i2c_probe\n"));
 

board/Marvell/common/intel_flash.c

@@ -152,7 +152,7 @@ int write_word_intel (bank_addr_t addr, bank_word_t value)
 	/* data polling for D7 */
 	start = get_timer (0);
 	do {
-		if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			retval = 1;
 			goto done;
 		}
@@ -227,7 +227,7 @@ int flash_erase_intel (flash_info_t * info, int s_first, int s_last)
 			do {
 				now = get_timer (start);
 
-				if (now - estart > CFG_FLASH_ERASE_TOUT) {
+				if (now - estart > CONFIG_SYS_FLASH_ERASE_TOUT) {
 					printf ("Timeout (sect %d)\n", sect);
 					haderr = 1;
 					break;

board/Marvell/common/intel_flash.h

@@ -68,7 +68,7 @@
 /* ID and Lock Configuration */
 #define CHIP_RD_ID_LOCK		0x01		/* Bit 0 of each byte */
 #define CHIP_RD_ID_MAN		0x89		/* Manufacturer code = 0x89 */
-#define CHIP_RD_ID_DEV		CFG_FLASH_ID
+#define CHIP_RD_ID_DEV		CONFIG_SYS_FLASH_ID
 
 /* dimensions */
 #define CHIP_WIDTH		2		/* chips are in 16 bit mode */

board/Marvell/common/misc.S

@@ -16,7 +16,7 @@
 board_relocate_rom:
 	mflr	r7
 	/* update the location of the GT registers */
-	lis	r11, CFG_GT_REGS@h
+	lis	r11, CONFIG_SYS_GT_REGS@h
 	/* if we're using ECC, we must use the DMA engine to copy ourselves */
 	bl	start_idma_transfer_0
 	bl	wait_for_idma_0
@@ -29,12 +29,12 @@ board_relocate_rom:
 board_init_ecc:
 	mflr	r7
 	/* NOTE: r10 still contains the location we've been relocated to
-	 * which happens to be TOP_OF_RAM - CFG_MONITOR_LEN */
+	 * which happens to be TOP_OF_RAM - CONFIG_SYS_MONITOR_LEN */
 
 	/* now that we're running from ram, init the rest of main memory
 	 * for ECC use */
-	lis	r8, CFG_MONITOR_LEN@h
-	ori	r8, r8, CFG_MONITOR_LEN@l
+	lis	r8, CONFIG_SYS_MONITOR_LEN@h
+	ori	r8, r8, CONFIG_SYS_MONITOR_LEN@l
 
 	divw	r3, r10, r8
 
@@ -120,15 +120,15 @@ stop_idma_engine_0:
 	blr
 #endif
 
-#ifdef CFG_BOARD_ASM_INIT
+#ifdef CONFIG_SYS_BOARD_ASM_INIT
 	/* NOTE: trashes r3-r7 */
 	.globl board_asm_init
 board_asm_init:
 	/* just move the GT registers to where they belong */
-	lis	r3, CFG_DFL_GT_REGS@h
-	ori	r3, r3, CFG_DFL_GT_REGS@l
-	lis	r4, CFG_GT_REGS@h
-	ori	r4, r4, CFG_GT_REGS@l
+	lis	r3, CONFIG_SYS_DFL_GT_REGS@h
+	ori	r3, r3, CONFIG_SYS_DFL_GT_REGS@l
+	lis	r4, CONFIG_SYS_GT_REGS@h
+	ori	r4, r4, CONFIG_SYS_GT_REGS@l
 	li	r5, INTERNAL_SPACE_DECODE
 
 	/* test to see if we've already moved */

board/Marvell/common/ns16550.c

@@ -1,7 +1,7 @@
 /*
  * COM1 NS16550 support
  * originally from linux source (arch/ppc/boot/ns16550.c)
- * modified to use CFG_ISA_MEM and new defines
+ * modified to use CONFIG_SYS_ISA_MEM and new defines
  *
  * further modified by Josh Huber <huber@mclx.com> to support
  * the DUART on the Galileo Eval board. (db64360)
@@ -13,8 +13,8 @@
 #ifdef ZUMA_NTL
 /* no 16550 device */
 #else
-const NS16550_t COM_PORTS[] = { (NS16550_t) (CFG_DUART_IO + 0),
-	(NS16550_t) (CFG_DUART_IO + 0x20)
+const NS16550_t COM_PORTS[] = { (NS16550_t) (CONFIG_SYS_DUART_IO + 0),
+	(NS16550_t) (CONFIG_SYS_DUART_IO + 0x20)
 };
 
 volatile struct NS16550 *NS16550_init (int chan, int baud_divisor)

board/Marvell/common/ns16550.h

@@ -2,7 +2,7 @@
  * NS16550 Serial Port
  * originally from linux source (arch/ppc/boot/ns16550.h)
  * modified slightly to
- * have addresses as offsets from CFG_ISA_BASE
+ * have addresses as offsets from CONFIG_SYS_ISA_BASE
  * added a few more definitions
  * added prototypes for ns16550.c
  * reduced no of com ports to 2

board/Marvell/common/serial.c

@@ -52,17 +52,17 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int serial_init (void)
 {
-#if (defined CFG_INIT_CHAN1) || (defined CFG_INIT_CHAN2)
+#if (defined CONFIG_SYS_INIT_CHAN1) || (defined CONFIG_SYS_INIT_CHAN2)
 	int clock_divisor = 230400 / gd->baudrate;
 #endif
 
 	mpsc_init (gd->baudrate);
 
 	/* init the DUART chans so that KGDB in the kernel can use them */
-#ifdef CFG_INIT_CHAN1
+#ifdef CONFIG_SYS_INIT_CHAN1
 	NS16550_reinit (COM_PORTS[0], clock_divisor);
 #endif
-#ifdef CFG_INIT_CHAN2
+#ifdef CONFIG_SYS_INIT_CHAN2
 	NS16550_reinit (COM_PORTS[1], clock_divisor);
 #endif
 	return (0);
@@ -97,10 +97,10 @@ int serial_init (void)
 {
 	int clock_divisor = 230400 / gd->baudrate;
 
-#ifdef CFG_INIT_CHAN1
+#ifdef CONFIG_SYS_INIT_CHAN1
 	(void) NS16550_init (0, clock_divisor);
 #endif
-#ifdef CFG_INIT_CHAN2
+#ifdef CONFIG_SYS_INIT_CHAN2
 	(void) NS16550_init (1, clock_divisor);
 #endif
 	return (0);
@@ -109,29 +109,29 @@ int serial_init (void)
 void serial_putc (const char c)
 {
 	if (c == '\n')
-		NS16550_putc (COM_PORTS[CFG_DUART_CHAN], '\r');
+		NS16550_putc (COM_PORTS[CONFIG_SYS_DUART_CHAN], '\r');
 
-	NS16550_putc (COM_PORTS[CFG_DUART_CHAN], c);
+	NS16550_putc (COM_PORTS[CONFIG_SYS_DUART_CHAN], c);
 }
 
 int serial_getc (void)
 {
-	return NS16550_getc (COM_PORTS[CFG_DUART_CHAN]);
+	return NS16550_getc (COM_PORTS[CONFIG_SYS_DUART_CHAN]);
 }
 
 int serial_tstc (void)
 {
-	return NS16550_tstc (COM_PORTS[CFG_DUART_CHAN]);
+	return NS16550_tstc (COM_PORTS[CONFIG_SYS_DUART_CHAN]);
 }
 
 void serial_setbrg (void)
 {
 	int clock_divisor = 230400 / gd->baudrate;
 
-#ifdef CFG_INIT_CHAN1
+#ifdef CONFIG_SYS_INIT_CHAN1
 	NS16550_reinit (COM_PORTS[0], clock_divisor);
 #endif
-#ifdef CFG_INIT_CHAN2
+#ifdef CONFIG_SYS_INIT_CHAN2
 	NS16550_reinit (COM_PORTS[1], clock_divisor);
 #endif
 }

board/Marvell/db64360/db64360.c

@@ -33,6 +33,7 @@
 #include "../include/pci.h"
 #include "../include/mv_gen_reg.h"
 #include <net.h>
+#include <netdev.h>
 
 #include "eth.h"
 #include "mpsc.h"
@@ -54,7 +55,7 @@
 /* ------------------------------------------------------------------------- */
 
 /* this is the current GT register space location */
-/* it starts at CFG_DFL_GT_REGS but moves later to CFG_GT_REGS */
+/* it starts at CONFIG_SYS_DFL_GT_REGS but moves later to CONFIG_SYS_GT_REGS */
 
 /* Unfortunately, we cant change it while we are in flash, so we initialize it
  * to the "final" value. This means that any debug_led calls before
@@ -63,7 +64,7 @@
  */
 
 void board_prebootm_init (void);
-unsigned int INTERNAL_REG_BASE_ADDR = CFG_GT_REGS;
+unsigned int INTERNAL_REG_BASE_ADDR = CONFIG_SYS_GT_REGS;
 int display_mem_map (void);
 
 /* ------------------------------------------------------------------------- */
@@ -126,7 +127,7 @@ static void gt_pci_config (void)
 
 		GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
 		GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG,
-			      (stat & 0xffff0000) | CFG_PCI_IDSEL);
+			      (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
 
 	}
 	if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) {	/*if  PCI-X */
@@ -135,7 +136,7 @@ static void gt_pci_config (void)
 
 		GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
 		GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG,
-			      (stat & 0xffff0000) | CFG_PCI_IDSEL);
+			      (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
 	}
 
 	/* Enable master */
@@ -153,21 +154,21 @@ static void gt_pci_config (void)
 	/* ronen- add write to pci remap registers for 64460.
 	   in 64360 when writing to pci base go and overide remap automaticaly,
 	   in 64460 it doesn't */
-	GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CFG_PCI0_IO_BASE >> 16);
-	GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CFG_PCI0_IO_BASE >> 16);
-	GT_REG_WRITE (PCI_0_IO_SIZE, (CFG_PCI0_IO_SIZE - 1) >> 16);
+	GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CONFIG_SYS_PCI0_IO_BASE >> 16);
+	GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CONFIG_SYS_PCI0_IO_BASE >> 16);
+	GT_REG_WRITE (PCI_0_IO_SIZE, (CONFIG_SYS_PCI0_IO_SIZE - 1) >> 16);
 
-	GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CFG_PCI0_MEM_BASE >> 16);
-	GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CFG_PCI0_MEM_BASE >> 16);
-	GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CFG_PCI0_MEM_SIZE - 1) >> 16);
+	GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI0_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI0_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CONFIG_SYS_PCI0_MEM_SIZE - 1) >> 16);
 
-	GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CFG_PCI1_IO_BASE >> 16);
-	GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CFG_PCI1_IO_BASE >> 16);
-	GT_REG_WRITE (PCI_1_IO_SIZE, (CFG_PCI1_IO_SIZE - 1) >> 16);
+	GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CONFIG_SYS_PCI1_IO_BASE >> 16);
+	GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CONFIG_SYS_PCI1_IO_BASE >> 16);
+	GT_REG_WRITE (PCI_1_IO_SIZE, (CONFIG_SYS_PCI1_IO_SIZE - 1) >> 16);
 
-	GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CFG_PCI1_MEM_BASE >> 16);
-	GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CFG_PCI1_MEM_BASE >> 16);
-	GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CFG_PCI1_MEM_SIZE - 1) >> 16);
+	GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI1_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI1_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CONFIG_SYS_PCI1_MEM_SIZE - 1) >> 16);
 
 	/* PCI interface settings */
 	/* Timeout set to retry forever */
@@ -183,7 +184,7 @@ static void gt_pci_config (void)
 	for (stat = 0; stat <= PCI_HOST1; stat++)
 		pciWriteConfigReg (stat,
 				   PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,
-				   SELF, CFG_GT_REGS);
+				   SELF, CONFIG_SYS_GT_REGS);
 #endif
 
 }
@@ -199,7 +200,7 @@ static void gt_cpu_config (void)
 	tmp = GTREGREAD (CPU_CONFIGURATION);
 
 	/* set the SINGLE_CPU bit  see MV64360 P.399 */
-#ifndef CFG_GT_DUAL_CPU		/* SINGLE_CPU seems to cause JTAG problems */
+#ifndef CONFIG_SYS_GT_DUAL_CPU		/* SINGLE_CPU seems to cause JTAG problems */
 	tmp |= CPU_CONF_SINGLE_CPU;
 #endif
 
@@ -250,7 +251,7 @@ int board_early_init_f (void)
 	 * it last time. (huber)
 	 */
 
-	my_remap_gt_regs (CFG_DFL_GT_REGS, CFG_GT_REGS);
+	my_remap_gt_regs (CONFIG_SYS_DFL_GT_REGS, CONFIG_SYS_GT_REGS);
 
 	/* No PCI in first release of Port To_do: enable it. */
 #ifdef CONFIG_PCI
@@ -296,56 +297,56 @@ int board_early_init_f (void)
 	 * on-board sram on the eval board, and updates the correct
 	 * registers to boot from the sram. (device0)
 	 */
-	if (memoryGetDeviceBaseAddress (DEVICE0) == CFG_DFL_BOOTCS_BASE)
+	if (memoryGetDeviceBaseAddress (DEVICE0) == CONFIG_SYS_DFL_BOOTCS_BASE)
 		sram_boot = 1;
 	if (!sram_boot)
-		memoryMapDeviceSpace (DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE);
+		memoryMapDeviceSpace (DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE);
 
-	memoryMapDeviceSpace (DEVICE1, CFG_DEV1_SPACE, CFG_DEV1_SIZE);
-	memoryMapDeviceSpace (DEVICE2, CFG_DEV2_SPACE, CFG_DEV2_SIZE);
-	memoryMapDeviceSpace (DEVICE3, CFG_DEV3_SPACE, CFG_DEV3_SIZE);
+	memoryMapDeviceSpace (DEVICE1, CONFIG_SYS_DEV1_SPACE, CONFIG_SYS_DEV1_SIZE);
+	memoryMapDeviceSpace (DEVICE2, CONFIG_SYS_DEV2_SPACE, CONFIG_SYS_DEV2_SIZE);
+	memoryMapDeviceSpace (DEVICE3, CONFIG_SYS_DEV3_SPACE, CONFIG_SYS_DEV3_SIZE);
 
 
 	/* configure device timing */
-#ifdef CFG_DEV0_PAR		/* set port parameters for SRAM device module access */
+#ifdef CONFIG_SYS_DEV0_PAR		/* set port parameters for SRAM device module access */
 	if (!sram_boot)
-		GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CFG_DEV0_PAR);
+		GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CONFIG_SYS_DEV0_PAR);
 #endif
 
-#ifdef CFG_DEV1_PAR		/* set port parameters for RTC device module access */
-	GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CFG_DEV1_PAR);
+#ifdef CONFIG_SYS_DEV1_PAR		/* set port parameters for RTC device module access */
+	GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CONFIG_SYS_DEV1_PAR);
 #endif
-#ifdef CFG_DEV2_PAR		/* set port parameters for DUART device module access */
-	GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CFG_DEV2_PAR);
+#ifdef CONFIG_SYS_DEV2_PAR		/* set port parameters for DUART device module access */
+	GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CONFIG_SYS_DEV2_PAR);
 #endif
 
-#ifdef CFG_32BIT_BOOT_PAR	/* set port parameters for Flash device module access */
+#ifdef CONFIG_SYS_32BIT_BOOT_PAR	/* set port parameters for Flash device module access */
 	/* detect if we are booting from the 32 bit flash */
 	if (GTREGREAD (DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) {
 		/* 32 bit boot flash */
-		GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_8BIT_BOOT_PAR);
+		GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
 		GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS,
-			      CFG_32BIT_BOOT_PAR);
+			      CONFIG_SYS_32BIT_BOOT_PAR);
 	} else {
 		/* 8 bit boot flash */
-		GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_32BIT_BOOT_PAR);
-		GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);
+		GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_32BIT_BOOT_PAR);
+		GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
 	}
 #else
 	/* 8 bit boot flash only */
-/*	GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);*/
+/*	GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);*/
 #endif
 
 
 	gt_cpu_config ();
 
 	/* MPP setup */
-	GT_REG_WRITE (MPP_CONTROL0, CFG_MPP_CONTROL_0);
-	GT_REG_WRITE (MPP_CONTROL1, CFG_MPP_CONTROL_1);
-	GT_REG_WRITE (MPP_CONTROL2, CFG_MPP_CONTROL_2);
-	GT_REG_WRITE (MPP_CONTROL3, CFG_MPP_CONTROL_3);
+	GT_REG_WRITE (MPP_CONTROL0, CONFIG_SYS_MPP_CONTROL_0);
+	GT_REG_WRITE (MPP_CONTROL1, CONFIG_SYS_MPP_CONTROL_1);
+	GT_REG_WRITE (MPP_CONTROL2, CONFIG_SYS_MPP_CONTROL_2);
+	GT_REG_WRITE (MPP_CONTROL3, CONFIG_SYS_MPP_CONTROL_3);
 
-	GT_REG_WRITE (GPP_LEVEL_CONTROL, CFG_GPP_LEVEL_CONTROL);
+	GT_REG_WRITE (GPP_LEVEL_CONTROL, CONFIG_SYS_GPP_LEVEL_CONTROL);
 	DEBUG_LED0_ON ();
 	DEBUG_LED1_ON ();
 	DEBUG_LED2_ON ();
@@ -358,7 +359,7 @@ int board_early_init_f (void)
 int misc_init_r ()
 {
 	icache_enable ();
-#ifdef CFG_L2
+#ifdef CONFIG_SYS_L2
 	l2cache_enable ();
 #endif
 #ifdef CONFIG_MPSC
@@ -379,9 +380,9 @@ void after_reloc (ulong dest_addr, gd_t * gd)
 	/* check to see if we booted from the sram.  If so, move things
 	 * back to the way they should be. (we're running from main
 	 * memory at this point now */
-	if (memoryGetDeviceBaseAddress (DEVICE0) == CFG_DFL_BOOTCS_BASE) {
-		memoryMapDeviceSpace (DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE);
-		memoryMapDeviceSpace (BOOT_DEVICE, CFG_DFL_BOOTCS_BASE, _8M);
+	if (memoryGetDeviceBaseAddress (DEVICE0) == CONFIG_SYS_DFL_BOOTCS_BASE) {
+		memoryMapDeviceSpace (DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE);
+		memoryMapDeviceSpace (BOOT_DEVICE, CONFIG_SYS_DFL_BOOTCS_BASE, _8M);
 	}
 	display_mem_map ();
 	/* now, jump to the main ppcboot board init code */
@@ -401,7 +402,7 @@ int checkboard (void)
 {
 	int l_type = 0;
 
-	printf ("BOARD: %s\n", CFG_BOARD_NAME);
+	printf ("BOARD: %s\n", CONFIG_SYS_BOARD_NAME);
 	return (l_type);
 }
 
@@ -414,34 +415,34 @@ void debug_led (int led, int mode)
 	if (mode == 1) {
 		switch (led) {
 		case 0:
-			addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
+			addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
 					0x08000);
 			break;
 
 		case 1:
-			addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
+			addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
 					0x0c000);
 			break;
 
 		case 2:
-			addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
+			addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
 					0x10000);
 			break;
 		}
 	} else if (mode == 0) {
 		switch (led) {
 		case 0:
-			addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
+			addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
 					0x14000);
 			break;
 
 		case 1:
-			addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
+			addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
 					0x18000);
 			break;
 
 		case 2:
-			addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
+			addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
 					0x1c000);
 			break;
 		}
@@ -512,7 +513,7 @@ int display_mem_map (void)
 
 /* DRAM check routines copied from gw8260 */
 
-#if defined (CFG_DRAM_TEST)
+#if defined (CONFIG_SYS_DRAM_TEST)
 
 /*********************************************************************/
 /* NAME:  move64() -  moves a double word (64-bit)		     */
@@ -543,7 +544,7 @@ static void move64 (unsigned long long *src, unsigned long long *dest)
 }
 
 
-#if defined (CFG_DRAM_TEST_DATA)
+#if defined (CONFIG_SYS_DRAM_TEST_DATA)
 
 unsigned long long pattern[] = {
 	0xaaaaaaaaaaaaaaaaULL,
@@ -606,7 +607,7 @@ unsigned long long pattern[] = {
 /*********************************************************************/
 int mem_test_data (void)
 {
-	unsigned long long *pmem = (unsigned long long *) CFG_MEMTEST_START;
+	unsigned long long *pmem = (unsigned long long *) CONFIG_SYS_MEMTEST_START;
 	unsigned long long temp64 = 0;
 	int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
 	int i;
@@ -633,9 +634,9 @@ int mem_test_data (void)
 
 	return 0;
 }
-#endif /* CFG_DRAM_TEST_DATA */
+#endif /* CONFIG_SYS_DRAM_TEST_DATA */
 
-#if defined (CFG_DRAM_TEST_ADDRESS)
+#if defined (CONFIG_SYS_DRAM_TEST_ADDRESS)
 /*********************************************************************/
 /* NAME:  mem_test_address() -	test address lines		     */
 /*								     */
@@ -660,8 +661,8 @@ int mem_test_data (void)
 int mem_test_address (void)
 {
 	volatile unsigned int *pmem =
-		(volatile unsigned int *) CFG_MEMTEST_START;
-	const unsigned int size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 4;
+		(volatile unsigned int *) CONFIG_SYS_MEMTEST_START;
+	const unsigned int size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 4;
 	unsigned int i;
 
 	/* write address to each location */
@@ -678,9 +679,9 @@ int mem_test_address (void)
 	}
 	return 0;
 }
-#endif /* CFG_DRAM_TEST_ADDRESS */
+#endif /* CONFIG_SYS_DRAM_TEST_ADDRESS */
 
-#if defined (CFG_DRAM_TEST_WALK)
+#if defined (CONFIG_SYS_DRAM_TEST_WALK)
 /*********************************************************************/
 /* NAME:   mem_march() -  memory march				     */
 /*								     */
@@ -738,7 +739,7 @@ int mem_march (volatile unsigned long long *base,
 	}
 	return 0;
 }
-#endif /* CFG_DRAM_TEST_WALK */
+#endif /* CONFIG_SYS_DRAM_TEST_WALK */
 
 /*********************************************************************/
 /* NAME:   mem_test_walk() -  a simple walking ones test	     */
@@ -770,8 +771,8 @@ int mem_test_walk (void)
 {
 	unsigned long long mask;
 	volatile unsigned long long *pmem =
-		(volatile unsigned long long *) CFG_MEMTEST_START;
-	const unsigned long size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 8;
+		(volatile unsigned long long *) CONFIG_SYS_MEMTEST_START;
+	const unsigned long size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 8;
 
 	unsigned int i;
 
@@ -847,9 +848,9 @@ int testdram (void)
 /*    runwalk = 0; */
 
 	if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
-		printf ("Testing RAM from 0x%08x to 0x%08x ...  (don't panic... that will take a moment !!!!)\n", CFG_MEMTEST_START, CFG_MEMTEST_END);
+		printf ("Testing RAM from 0x%08x to 0x%08x ...  (don't panic... that will take a moment !!!!)\n", CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END);
 	}
-#ifdef CFG_DRAM_TEST_DATA
+#ifdef CONFIG_SYS_DRAM_TEST_DATA
 	if (rundata == 1) {
 		printf ("Test DATA ...  ");
 		if (mem_test_data () == 1) {
@@ -859,7 +860,7 @@ int testdram (void)
 			printf ("ok \n");
 	}
 #endif
-#ifdef CFG_DRAM_TEST_ADDRESS
+#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS
 	if (runaddress == 1) {
 		printf ("Test ADDRESS ...  ");
 		if (mem_test_address () == 1) {
@@ -869,7 +870,7 @@ int testdram (void)
 			printf ("ok \n");
 	}
 #endif
-#ifdef CFG_DRAM_TEST_WALK
+#ifdef CONFIG_SYS_DRAM_TEST_WALK
 	if (runwalk == 1) {
 		printf ("Test WALKING ONEs ...  ");
 		if (mem_test_walk () == 1) {
@@ -885,7 +886,7 @@ int testdram (void)
 	return 0;
 
 }
-#endif /* CFG_DRAM_TEST */
+#endif /* CONFIG_SYS_DRAM_TEST */
 
 /* ronen - the below functions are used by the bootm function           */
 /*  - we map the base register to fbe00000 (same mapping as in the LSP) */
@@ -924,8 +925,13 @@ void board_prebootm_init ()
 /* MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(2), 0x0000ff00); */
 
 /* Relocate MV64360 internal regs */
-	my_remap_gt_regs_bootm (CFG_GT_REGS, BRIDGE_REG_BASE_BOOTM);
+	my_remap_gt_regs_bootm (CONFIG_SYS_GT_REGS, BRIDGE_REG_BASE_BOOTM);
 
 	icache_disable ();
 	dcache_disable ();
 }
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}

board/Marvell/db64360/mpsc.c

@@ -426,7 +426,7 @@ void mpsc_sdma_init (void)
 			  (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT * 2)));
 
 /* Setup MPSC internal address space base address	*/
-	GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CFG_GT_REGS);
+	GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CONFIG_SYS_GT_REGS);
 
 /* no high address remap*/
 	GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG0, 0x00);
@@ -516,9 +516,9 @@ int galbrg_set_baudrate (int channel, int rate)
 
 #ifdef ZUMA_NTL
 	/* from tclk */
-	clock = (CFG_TCLK / (16 * rate)) - 1;
+	clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1;
 #else
-	clock = (CFG_TCLK / (16 * rate)) - 1;
+	clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1;
 #endif
 
 	galbrg_set_CDV (channel, clock);	/* set timer Reg. for BRG */

board/Marvell/db64360/pci.c

@@ -52,13 +52,13 @@ static void gt_pci_bus_mode_display (PCI_HOST host)
 		printf ("PCI %d bus mode: Conventional PCI\n", host);
 		break;
 	case 1:
-		printf ("PCI %d bus mode: 66 Mhz PCIX\n", host);
+		printf ("PCI %d bus mode: 66 MHz PCIX\n", host);
 		break;
 	case 2:
-		printf ("PCI %d bus mode: 100 Mhz PCIX\n", host);
+		printf ("PCI %d bus mode: 100 MHz PCIX\n", host);
 		break;
 	case 3:
-		printf ("PCI %d bus mode: 133 Mhz PCIX\n", host);
+		printf ("PCI %d bus mode: 133 MHz PCIX\n", host);
 		break;
 	default:
 		printf ("Unknown BUS %d\n", mode);
@@ -859,14 +859,14 @@ void pci_init_board (void)
 
 	/* PCI memory space */
 	pci_set_region (pci0_hose.regions + 0,
-			CFG_PCI0_0_MEM_SPACE,
-			CFG_PCI0_0_MEM_SPACE,
-			CFG_PCI0_MEM_SIZE, PCI_REGION_MEM);
+			CONFIG_SYS_PCI0_0_MEM_SPACE,
+			CONFIG_SYS_PCI0_0_MEM_SPACE,
+			CONFIG_SYS_PCI0_MEM_SIZE, PCI_REGION_MEM);
 
 	/* PCI I/O space */
 	pci_set_region (pci0_hose.regions + 1,
-			CFG_PCI0_IO_SPACE_PCI,
-			CFG_PCI0_IO_SPACE, CFG_PCI0_IO_SIZE, PCI_REGION_IO);
+			CONFIG_SYS_PCI0_IO_SPACE_PCI,
+			CONFIG_SYS_PCI0_IO_SPACE, CONFIG_SYS_PCI0_IO_SIZE, PCI_REGION_IO);
 
 	pci_set_ops (&pci0_hose,
 		     pci_hose_read_config_byte_via_dword,
@@ -901,14 +901,14 @@ void pci_init_board (void)
 
 	/* PCI memory space */
 	pci_set_region (pci1_hose.regions + 0,
-			CFG_PCI1_0_MEM_SPACE,
-			CFG_PCI1_0_MEM_SPACE,
-			CFG_PCI1_MEM_SIZE, PCI_REGION_MEM);
+			CONFIG_SYS_PCI1_0_MEM_SPACE,
+			CONFIG_SYS_PCI1_0_MEM_SPACE,
+			CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM);
 
 	/* PCI I/O space */
 	pci_set_region (pci1_hose.regions + 1,
-			CFG_PCI1_IO_SPACE_PCI,
-			CFG_PCI1_IO_SPACE, CFG_PCI1_IO_SIZE, PCI_REGION_IO);
+			CONFIG_SYS_PCI1_IO_SPACE_PCI,
+			CONFIG_SYS_PCI1_IO_SPACE, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO);
 
 	pci_set_ops (&pci1_hose,
 		     pci_hose_read_config_byte_via_dword,

board/Marvell/db64360/sdram_init.c

@@ -312,7 +312,7 @@ return 0;
 	} else
 		dimmInfo->slot = slot;	/* start to fill up dimminfo for this "slot" */
 
-#ifdef CFG_DISPLAY_DIMM_SPD_CONTENT
+#ifdef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT
 
 	for (i = 0; i <= 127; i++) {
 		printf ("SPD-EEPROM Byte %3d = %3x (%3d)\n", i, data[i],
@@ -690,16 +690,16 @@ return 0;
 						if ((dimmInfo->
 						     minimumCycleTimeAtMaxCasLatancy_LoP
 						     <
-						     CFG_DDR_SDRAM_CYCLE_COUNT_LOP)
+						     CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP)
 						    ||
 						    ((dimmInfo->
 						      minimumCycleTimeAtMaxCasLatancy_LoP
 						      ==
-						      CFG_DDR_SDRAM_CYCLE_COUNT_LOP)
+						      CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP)
 						     && (dimmInfo->
 							 minimumCycleTimeAtMaxCasLatancy_RoP
 							 <
-							 CFG_DDR_SDRAM_CYCLE_COUNT_ROP)))
+							 CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP)))
 						{
 							dimmInfo->
 								maxClSupported_DDR
@@ -714,16 +714,16 @@ return 0;
 						if ((dimmInfo->
 						     minimumCycleTimeAtMaxCasLatancy_LoP
 						     >
-						     CFG_DDR_SDRAM_CYCLE_COUNT_LOP)
+						     CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP)
 						    ||
 						    ((dimmInfo->
 						      minimumCycleTimeAtMaxCasLatancy_LoP
 						      ==
-						      CFG_DDR_SDRAM_CYCLE_COUNT_LOP)
+						      CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP)
 						     && (dimmInfo->
 							 minimumCycleTimeAtMaxCasLatancy_RoP
 							 >
-							 CFG_DDR_SDRAM_CYCLE_COUNT_ROP)))
+							 CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP)))
 						{
 							printf ("*********************************************************\n");
 							printf ("*** sysClock is higher than SDRAM's allowed frequency ***\n");
@@ -1290,37 +1290,37 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info)
 	case 0x0:
 	case 0x80:		/* refresh period is 15.625 usec */
 		sdram_config_reg =
-			(unsigned int) (((float) 15.625 * (float) CFG_BUS_HZ)
+			(unsigned int) (((float) 15.625 * (float) CONFIG_SYS_BUS_HZ)
 					/ (float) 1000000.0);
 		break;
 	case 0x1:
 	case 0x81:		/* refresh period is 3.9 usec */
 		sdram_config_reg =
-			(unsigned int) (((float) 3.9 * (float) CFG_BUS_HZ) /
+			(unsigned int) (((float) 3.9 * (float) CONFIG_SYS_BUS_HZ) /
 					(float) 1000000.0);
 		break;
 	case 0x2:
 	case 0x82:		/* refresh period is 7.8 usec */
 		sdram_config_reg =
-			(unsigned int) (((float) 7.8 * (float) CFG_BUS_HZ) /
+			(unsigned int) (((float) 7.8 * (float) CONFIG_SYS_BUS_HZ) /
 					(float) 1000000.0);
 		break;
 	case 0x3:
 	case 0x83:		/* refresh period is 31.3 usec */
 		sdram_config_reg =
-			(unsigned int) (((float) 31.3 * (float) CFG_BUS_HZ) /
+			(unsigned int) (((float) 31.3 * (float) CONFIG_SYS_BUS_HZ) /
 					(float) 1000000.0);
 		break;
 	case 0x4:
 	case 0x84:		/* refresh period is 62.5 usec */
 		sdram_config_reg =
-			(unsigned int) (((float) 62.5 * (float) CFG_BUS_HZ) /
+			(unsigned int) (((float) 62.5 * (float) CONFIG_SYS_BUS_HZ) /
 					(float) 1000000.0);
 		break;
 	case 0x5:
 	case 0x85:		/* refresh period is 125 usec */
 		sdram_config_reg =
-			(unsigned int) (((float) 125 * (float) CFG_BUS_HZ) /
+			(unsigned int) (((float) 125 * (float) CONFIG_SYS_BUS_HZ) /
 					(float) 1000000.0);
 		break;
 	default:		/* refresh period undefined */
@@ -1807,7 +1807,7 @@ phys_size_t initdram (int board_type)
 
 	printf ("-- DIMM2 has %d banks\n", dimmInfo2.numOfModuleBanks);
 
-	for (bank_no = 0; bank_no < CFG_DRAM_BANKS; bank_no++) {
+	for (bank_no = 0; bank_no < CONFIG_SYS_DRAM_BANKS; bank_no++) {
 		/* skip over banks that are not populated */
 		if (!checkbank[bank_no])
 			continue;

board/Marvell/db64360/u-boot.lds

@@ -60,7 +60,7 @@ SECTIONS
 
 /* store the environment in a seperate sector in the boot flash */
 /*    . = env_offset; */
-/*    common/environment.o(.text) */
+/*    common/env_embedded.o(.text) */
 
     *(.text)
     *(.fixup)
@@ -131,6 +131,7 @@ SECTIONS
    *(.dynbss)
    *(.bss)
    *(COMMON)
+   . = ALIGN(4);
   }
   _end = . ;
   PROVIDE (end = .);

board/Marvell/db64460/db64460.c

@@ -33,6 +33,7 @@
 #include "../include/pci.h"
 #include "../include/mv_gen_reg.h"
 #include <net.h>
+#include <netdev.h>
 
 #include "eth.h"
 #include "mpsc.h"
@@ -54,7 +55,7 @@
 /* ------------------------------------------------------------------------- */
 
 /* this is the current GT register space location */
-/* it starts at CFG_DFL_GT_REGS but moves later to CFG_GT_REGS */
+/* it starts at CONFIG_SYS_DFL_GT_REGS but moves later to CONFIG_SYS_GT_REGS */
 
 /* Unfortunately, we cant change it while we are in flash, so we initialize it
  * to the "final" value. This means that any debug_led calls before
@@ -63,7 +64,7 @@
  */
 
 void board_prebootm_init (void);
-unsigned int INTERNAL_REG_BASE_ADDR = CFG_GT_REGS;
+unsigned int INTERNAL_REG_BASE_ADDR = CONFIG_SYS_GT_REGS;
 int display_mem_map (void);
 
 /* ------------------------------------------------------------------------- */
@@ -126,7 +127,7 @@ static void gt_pci_config (void)
 
 		GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
 		GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG,
-			      (stat & 0xffff0000) | CFG_PCI_IDSEL);
+			      (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
 
 	}
 	if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) {	/*if  PCI-X */
@@ -135,7 +136,7 @@ static void gt_pci_config (void)
 
 		GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
 		GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG,
-			      (stat & 0xffff0000) | CFG_PCI_IDSEL);
+			      (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
 	}
 
 	/* Enable master */
@@ -153,21 +154,21 @@ static void gt_pci_config (void)
 	/* ronen- add write to pci remap registers for 64460.
 	   in 64360 when writing to pci base go and overide remap automaticaly,
 	   in 64460 it doesn't */
-	GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CFG_PCI0_IO_BASE >> 16);
-	GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CFG_PCI0_IO_BASE >> 16);
-	GT_REG_WRITE (PCI_0_IO_SIZE, (CFG_PCI0_IO_SIZE - 1) >> 16);
+	GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CONFIG_SYS_PCI0_IO_BASE >> 16);
+	GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CONFIG_SYS_PCI0_IO_BASE >> 16);
+	GT_REG_WRITE (PCI_0_IO_SIZE, (CONFIG_SYS_PCI0_IO_SIZE - 1) >> 16);
 
-	GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CFG_PCI0_MEM_BASE >> 16);
-	GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CFG_PCI0_MEM_BASE >> 16);
-	GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CFG_PCI0_MEM_SIZE - 1) >> 16);
+	GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI0_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI0_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CONFIG_SYS_PCI0_MEM_SIZE - 1) >> 16);
 
-	GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CFG_PCI1_IO_BASE >> 16);
-	GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CFG_PCI1_IO_BASE >> 16);
-	GT_REG_WRITE (PCI_1_IO_SIZE, (CFG_PCI1_IO_SIZE - 1) >> 16);
+	GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CONFIG_SYS_PCI1_IO_BASE >> 16);
+	GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CONFIG_SYS_PCI1_IO_BASE >> 16);
+	GT_REG_WRITE (PCI_1_IO_SIZE, (CONFIG_SYS_PCI1_IO_SIZE - 1) >> 16);
 
-	GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CFG_PCI1_MEM_BASE >> 16);
-	GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CFG_PCI1_MEM_BASE >> 16);
-	GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CFG_PCI1_MEM_SIZE - 1) >> 16);
+	GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI1_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI1_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CONFIG_SYS_PCI1_MEM_SIZE - 1) >> 16);
 
 	/* PCI interface settings */
 	/* Timeout set to retry forever */
@@ -183,7 +184,7 @@ static void gt_pci_config (void)
 	for (stat = 0; stat <= PCI_HOST1; stat++)
 		pciWriteConfigReg (stat,
 				   PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,
-				   SELF, CFG_GT_REGS);
+				   SELF, CONFIG_SYS_GT_REGS);
 #endif
 
 }
@@ -199,7 +200,7 @@ static void gt_cpu_config (void)
 	tmp = GTREGREAD (CPU_CONFIGURATION);
 
 	/* set the SINGLE_CPU bit  see MV64460 P.399 */
-#ifndef CFG_GT_DUAL_CPU		/* SINGLE_CPU seems to cause JTAG problems */
+#ifndef CONFIG_SYS_GT_DUAL_CPU		/* SINGLE_CPU seems to cause JTAG problems */
 	tmp |= CPU_CONF_SINGLE_CPU;
 #endif
 
@@ -250,7 +251,7 @@ int board_early_init_f (void)
 	 * it last time. (huber)
 	 */
 
-	my_remap_gt_regs (CFG_DFL_GT_REGS, CFG_GT_REGS);
+	my_remap_gt_regs (CONFIG_SYS_DFL_GT_REGS, CONFIG_SYS_GT_REGS);
 
 	/* No PCI in first release of Port To_do: enable it. */
 #ifdef CONFIG_PCI
@@ -296,56 +297,56 @@ int board_early_init_f (void)
 	 * on-board sram on the eval board, and updates the correct
 	 * registers to boot from the sram. (device0)
 	 */
-	if (memoryGetDeviceBaseAddress (DEVICE0) == CFG_DFL_BOOTCS_BASE)
+	if (memoryGetDeviceBaseAddress (DEVICE0) == CONFIG_SYS_DFL_BOOTCS_BASE)
 		sram_boot = 1;
 	if (!sram_boot)
-		memoryMapDeviceSpace (DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE);
+		memoryMapDeviceSpace (DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE);
 
-	memoryMapDeviceSpace (DEVICE1, CFG_DEV1_SPACE, CFG_DEV1_SIZE);
-	memoryMapDeviceSpace (DEVICE2, CFG_DEV2_SPACE, CFG_DEV2_SIZE);
-	memoryMapDeviceSpace (DEVICE3, CFG_DEV3_SPACE, CFG_DEV3_SIZE);
+	memoryMapDeviceSpace (DEVICE1, CONFIG_SYS_DEV1_SPACE, CONFIG_SYS_DEV1_SIZE);
+	memoryMapDeviceSpace (DEVICE2, CONFIG_SYS_DEV2_SPACE, CONFIG_SYS_DEV2_SIZE);
+	memoryMapDeviceSpace (DEVICE3, CONFIG_SYS_DEV3_SPACE, CONFIG_SYS_DEV3_SIZE);
 
 
 	/* configure device timing */
-#ifdef CFG_DEV0_PAR		/* set port parameters for SRAM device module access */
+#ifdef CONFIG_SYS_DEV0_PAR		/* set port parameters for SRAM device module access */
 	if (!sram_boot)
-		GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CFG_DEV0_PAR);
+		GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CONFIG_SYS_DEV0_PAR);
 #endif
 
-#ifdef CFG_DEV1_PAR		/* set port parameters for RTC device module access */
-	GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CFG_DEV1_PAR);
+#ifdef CONFIG_SYS_DEV1_PAR		/* set port parameters for RTC device module access */
+	GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CONFIG_SYS_DEV1_PAR);
 #endif
-#ifdef CFG_DEV2_PAR		/* set port parameters for DUART device module access */
-	GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CFG_DEV2_PAR);
+#ifdef CONFIG_SYS_DEV2_PAR		/* set port parameters for DUART device module access */
+	GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CONFIG_SYS_DEV2_PAR);
 #endif
 
-#ifdef CFG_32BIT_BOOT_PAR	/* set port parameters for Flash device module access */
+#ifdef CONFIG_SYS_32BIT_BOOT_PAR	/* set port parameters for Flash device module access */
 	/* detect if we are booting from the 32 bit flash */
 	if (GTREGREAD (DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) {
 		/* 32 bit boot flash */
-		GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_8BIT_BOOT_PAR);
+		GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
 		GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS,
-			      CFG_32BIT_BOOT_PAR);
+			      CONFIG_SYS_32BIT_BOOT_PAR);
 	} else {
 		/* 8 bit boot flash */
-		GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_32BIT_BOOT_PAR);
-		GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);
+		GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_32BIT_BOOT_PAR);
+		GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
 	}
 #else
 	/* 8 bit boot flash only */
-/*	GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);*/
+/*	GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);*/
 #endif
 
 
 	gt_cpu_config ();
 
 	/* MPP setup */
-	GT_REG_WRITE (MPP_CONTROL0, CFG_MPP_CONTROL_0);
-	GT_REG_WRITE (MPP_CONTROL1, CFG_MPP_CONTROL_1);
-	GT_REG_WRITE (MPP_CONTROL2, CFG_MPP_CONTROL_2);
-	GT_REG_WRITE (MPP_CONTROL3, CFG_MPP_CONTROL_3);
+	GT_REG_WRITE (MPP_CONTROL0, CONFIG_SYS_MPP_CONTROL_0);
+	GT_REG_WRITE (MPP_CONTROL1, CONFIG_SYS_MPP_CONTROL_1);
+	GT_REG_WRITE (MPP_CONTROL2, CONFIG_SYS_MPP_CONTROL_2);
+	GT_REG_WRITE (MPP_CONTROL3, CONFIG_SYS_MPP_CONTROL_3);
 
-	GT_REG_WRITE (GPP_LEVEL_CONTROL, CFG_GPP_LEVEL_CONTROL);
+	GT_REG_WRITE (GPP_LEVEL_CONTROL, CONFIG_SYS_GPP_LEVEL_CONTROL);
 	DEBUG_LED0_ON ();
 	DEBUG_LED1_ON ();
 	DEBUG_LED2_ON ();
@@ -358,7 +359,7 @@ int board_early_init_f (void)
 int misc_init_r ()
 {
 	icache_enable ();
-#ifdef CFG_L2
+#ifdef CONFIG_SYS_L2
 	l2cache_enable ();
 #endif
 #ifdef CONFIG_MPSC
@@ -379,9 +380,9 @@ void after_reloc (ulong dest_addr, gd_t * gd)
 	/* check to see if we booted from the sram.  If so, move things
 	 * back to the way they should be. (we're running from main
 	 * memory at this point now */
-	if (memoryGetDeviceBaseAddress (DEVICE0) == CFG_DFL_BOOTCS_BASE) {
-		memoryMapDeviceSpace (DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE);
-		memoryMapDeviceSpace (BOOT_DEVICE, CFG_DFL_BOOTCS_BASE, _8M);
+	if (memoryGetDeviceBaseAddress (DEVICE0) == CONFIG_SYS_DFL_BOOTCS_BASE) {
+		memoryMapDeviceSpace (DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE);
+		memoryMapDeviceSpace (BOOT_DEVICE, CONFIG_SYS_DFL_BOOTCS_BASE, _8M);
 	}
 	display_mem_map ();
 	/* now, jump to the main ppcboot board init code */
@@ -401,7 +402,7 @@ int checkboard (void)
 {
 	int l_type = 0;
 
-	printf ("BOARD: %s\n", CFG_BOARD_NAME);
+	printf ("BOARD: %s\n", CONFIG_SYS_BOARD_NAME);
 	return (l_type);
 }
 
@@ -414,34 +415,34 @@ void debug_led (int led, int mode)
 	if (mode == 1) {
 		switch (led) {
 		case 0:
-			addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
+			addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
 					0x08000);
 			break;
 
 		case 1:
-			addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
+			addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
 					0x0c000);
 			break;
 
 		case 2:
-			addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
+			addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
 					0x10000);
 			break;
 		}
 	} else if (mode == 0) {
 		switch (led) {
 		case 0:
-			addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
+			addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
 					0x14000);
 			break;
 
 		case 1:
-			addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
+			addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
 					0x18000);
 			break;
 
 		case 2:
-			addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
+			addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
 					0x1c000);
 			break;
 		}
@@ -512,7 +513,7 @@ int display_mem_map (void)
 
 /* DRAM check routines copied from gw8260 */
 
-#if defined (CFG_DRAM_TEST)
+#if defined (CONFIG_SYS_DRAM_TEST)
 
 /*********************************************************************/
 /* NAME:  move64() -  moves a double word (64-bit)		     */
@@ -543,7 +544,7 @@ static void move64 (unsigned long long *src, unsigned long long *dest)
 }
 
 
-#if defined (CFG_DRAM_TEST_DATA)
+#if defined (CONFIG_SYS_DRAM_TEST_DATA)
 
 unsigned long long pattern[] = {
 	0xaaaaaaaaaaaaaaaaULL,
@@ -606,7 +607,7 @@ unsigned long long pattern[] = {
 /*********************************************************************/
 int mem_test_data (void)
 {
-	unsigned long long *pmem = (unsigned long long *) CFG_MEMTEST_START;
+	unsigned long long *pmem = (unsigned long long *) CONFIG_SYS_MEMTEST_START;
 	unsigned long long temp64 = 0;
 	int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
 	int i;
@@ -633,9 +634,9 @@ int mem_test_data (void)
 
 	return 0;
 }
-#endif /* CFG_DRAM_TEST_DATA */
+#endif /* CONFIG_SYS_DRAM_TEST_DATA */
 
-#if defined (CFG_DRAM_TEST_ADDRESS)
+#if defined (CONFIG_SYS_DRAM_TEST_ADDRESS)
 /*********************************************************************/
 /* NAME:  mem_test_address() -	test address lines		     */
 /*								     */
@@ -660,8 +661,8 @@ int mem_test_data (void)
 int mem_test_address (void)
 {
 	volatile unsigned int *pmem =
-		(volatile unsigned int *) CFG_MEMTEST_START;
-	const unsigned int size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 4;
+		(volatile unsigned int *) CONFIG_SYS_MEMTEST_START;
+	const unsigned int size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 4;
 	unsigned int i;
 
 	/* write address to each location */
@@ -678,9 +679,9 @@ int mem_test_address (void)
 	}
 	return 0;
 }
-#endif /* CFG_DRAM_TEST_ADDRESS */
+#endif /* CONFIG_SYS_DRAM_TEST_ADDRESS */
 
-#if defined (CFG_DRAM_TEST_WALK)
+#if defined (CONFIG_SYS_DRAM_TEST_WALK)
 /*********************************************************************/
 /* NAME:   mem_march() -  memory march				     */
 /*								     */
@@ -738,7 +739,7 @@ int mem_march (volatile unsigned long long *base,
 	}
 	return 0;
 }
-#endif /* CFG_DRAM_TEST_WALK */
+#endif /* CONFIG_SYS_DRAM_TEST_WALK */
 
 /*********************************************************************/
 /* NAME:   mem_test_walk() -  a simple walking ones test	     */
@@ -770,8 +771,8 @@ int mem_test_walk (void)
 {
 	unsigned long long mask;
 	volatile unsigned long long *pmem =
-		(volatile unsigned long long *) CFG_MEMTEST_START;
-	const unsigned long size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 8;
+		(volatile unsigned long long *) CONFIG_SYS_MEMTEST_START;
+	const unsigned long size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 8;
 
 	unsigned int i;
 
@@ -847,9 +848,9 @@ int testdram (void)
 /*    runwalk = 0; */
 
 	if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
-		printf ("Testing RAM from 0x%08x to 0x%08x ...  (don't panic... that will take a moment !!!!)\n", CFG_MEMTEST_START, CFG_MEMTEST_END);
+		printf ("Testing RAM from 0x%08x to 0x%08x ...  (don't panic... that will take a moment !!!!)\n", CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END);
 	}
-#ifdef CFG_DRAM_TEST_DATA
+#ifdef CONFIG_SYS_DRAM_TEST_DATA
 	if (rundata == 1) {
 		printf ("Test DATA ...  ");
 		if (mem_test_data () == 1) {
@@ -859,7 +860,7 @@ int testdram (void)
 			printf ("ok \n");
 	}
 #endif
-#ifdef CFG_DRAM_TEST_ADDRESS
+#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS
 	if (runaddress == 1) {
 		printf ("Test ADDRESS ...  ");
 		if (mem_test_address () == 1) {
@@ -869,7 +870,7 @@ int testdram (void)
 			printf ("ok \n");
 	}
 #endif
-#ifdef CFG_DRAM_TEST_WALK
+#ifdef CONFIG_SYS_DRAM_TEST_WALK
 	if (runwalk == 1) {
 		printf ("Test WALKING ONEs ...  ");
 		if (mem_test_walk () == 1) {
@@ -885,7 +886,7 @@ int testdram (void)
 	return 0;
 
 }
-#endif /* CFG_DRAM_TEST */
+#endif /* CONFIG_SYS_DRAM_TEST */
 
 /* ronen - the below functions are used by the bootm function           */
 /*  - we map the base register to fbe00000 (same mapping as in the LSP) */
@@ -924,8 +925,13 @@ void board_prebootm_init ()
 	GT_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (2), 0x0000ff00);
 
 /* Relocate MV64460 internal regs */
-	my_remap_gt_regs_bootm (CFG_GT_REGS, BRIDGE_REG_BASE_BOOTM);
+	my_remap_gt_regs_bootm (CONFIG_SYS_GT_REGS, BRIDGE_REG_BASE_BOOTM);
 
 	icache_disable ();
 	dcache_disable ();
 }
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}

board/Marvell/db64460/mpsc.c

@@ -426,7 +426,7 @@ void mpsc_sdma_init (void)
 			  (MV64460_CUNIT_BASE_ADDR_WIN_0_BIT * 2)));
 
 /* Setup MPSC internal address space base address	*/
-	GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CFG_GT_REGS);
+	GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CONFIG_SYS_GT_REGS);
 
 /* no high address remap*/
 	GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG0, 0x00);
@@ -516,9 +516,9 @@ int galbrg_set_baudrate (int channel, int rate)
 
 #ifdef ZUMA_NTL
 	/* from tclk */
-	clock = (CFG_TCLK / (16 * rate)) - 1;
+	clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1;
 #else
-	clock = (CFG_TCLK / (16 * rate)) - 1;
+	clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1;
 #endif
 
 	galbrg_set_CDV (channel, clock);	/* set timer Reg. for BRG */

board/Marvell/db64460/pci.c

@@ -52,13 +52,13 @@ static void gt_pci_bus_mode_display (PCI_HOST host)
 		printf ("PCI %d bus mode: Conventional PCI\n", host);
 		break;
 	case 1:
-		printf ("PCI %d bus mode: 66 Mhz PCIX\n", host);
+		printf ("PCI %d bus mode: 66 MHz PCIX\n", host);
 		break;
 	case 2:
-		printf ("PCI %d bus mode: 100 Mhz PCIX\n", host);
+		printf ("PCI %d bus mode: 100 MHz PCIX\n", host);
 		break;
 	case 3:
-		printf ("PCI %d bus mode: 133 Mhz PCIX\n", host);
+		printf ("PCI %d bus mode: 133 MHz PCIX\n", host);
 		break;
 	default:
 		printf ("Unknown BUS %d\n", mode);
@@ -859,14 +859,14 @@ void pci_init_board (void)
 
 	/* PCI memory space */
 	pci_set_region (pci0_hose.regions + 0,
-			CFG_PCI0_0_MEM_SPACE,
-			CFG_PCI0_0_MEM_SPACE,
-			CFG_PCI0_MEM_SIZE, PCI_REGION_MEM);
+			CONFIG_SYS_PCI0_0_MEM_SPACE,
+			CONFIG_SYS_PCI0_0_MEM_SPACE,
+			CONFIG_SYS_PCI0_MEM_SIZE, PCI_REGION_MEM);
 
 	/* PCI I/O space */
 	pci_set_region (pci0_hose.regions + 1,
-			CFG_PCI0_IO_SPACE_PCI,
-			CFG_PCI0_IO_SPACE, CFG_PCI0_IO_SIZE, PCI_REGION_IO);
+			CONFIG_SYS_PCI0_IO_SPACE_PCI,
+			CONFIG_SYS_PCI0_IO_SPACE, CONFIG_SYS_PCI0_IO_SIZE, PCI_REGION_IO);
 
 	pci_set_ops (&pci0_hose,
 		     pci_hose_read_config_byte_via_dword,
@@ -901,14 +901,14 @@ void pci_init_board (void)
 
 	/* PCI memory space */
 	pci_set_region (pci1_hose.regions + 0,
-			CFG_PCI1_0_MEM_SPACE,
-			CFG_PCI1_0_MEM_SPACE,
-			CFG_PCI1_MEM_SIZE, PCI_REGION_MEM);
+			CONFIG_SYS_PCI1_0_MEM_SPACE,
+			CONFIG_SYS_PCI1_0_MEM_SPACE,
+			CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM);
 
 	/* PCI I/O space */
 	pci_set_region (pci1_hose.regions + 1,
-			CFG_PCI1_IO_SPACE_PCI,
-			CFG_PCI1_IO_SPACE, CFG_PCI1_IO_SIZE, PCI_REGION_IO);
+			CONFIG_SYS_PCI1_IO_SPACE_PCI,
+			CONFIG_SYS_PCI1_IO_SPACE, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO);
 
 	pci_set_ops (&pci1_hose,
 		     pci_hose_read_config_byte_via_dword,

board/Marvell/db64460/sdram_init.c

@@ -312,7 +312,7 @@ return 0;
 	} else
 		dimmInfo->slot = slot;	/* start to fill up dimminfo for this "slot" */
 
-#ifdef CFG_DISPLAY_DIMM_SPD_CONTENT
+#ifdef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT
 
 	for (i = 0; i <= 127; i++) {
 		printf ("SPD-EEPROM Byte %3d = %3x (%3d)\n", i, data[i],
@@ -690,16 +690,16 @@ return 0;
 						if ((dimmInfo->
 						     minimumCycleTimeAtMaxCasLatancy_LoP
 						     <
-						     CFG_DDR_SDRAM_CYCLE_COUNT_LOP)
+						     CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP)
 						    ||
 						    ((dimmInfo->
 						      minimumCycleTimeAtMaxCasLatancy_LoP
 						      ==
-						      CFG_DDR_SDRAM_CYCLE_COUNT_LOP)
+						      CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP)
 						     && (dimmInfo->
 							 minimumCycleTimeAtMaxCasLatancy_RoP
 							 <
-							 CFG_DDR_SDRAM_CYCLE_COUNT_ROP)))
+							 CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP)))
 						{
 							dimmInfo->
 								maxClSupported_DDR
@@ -714,16 +714,16 @@ return 0;
 						if ((dimmInfo->
 						     minimumCycleTimeAtMaxCasLatancy_LoP
 						     >
-						     CFG_DDR_SDRAM_CYCLE_COUNT_LOP)
+						     CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP)
 						    ||
 						    ((dimmInfo->
 						      minimumCycleTimeAtMaxCasLatancy_LoP
 						      ==
-						      CFG_DDR_SDRAM_CYCLE_COUNT_LOP)
+						      CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP)
 						     && (dimmInfo->
 							 minimumCycleTimeAtMaxCasLatancy_RoP
 							 >
-							 CFG_DDR_SDRAM_CYCLE_COUNT_ROP)))
+							 CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP)))
 						{
 							printf ("*********************************************************\n");
 							printf ("*** sysClock is higher than SDRAM's allowed frequency ***\n");
@@ -1289,37 +1289,37 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info)
 	case 0x0:
 	case 0x80:		/* refresh period is 15.625 usec */
 		sdram_config_reg =
-			(unsigned int) (((float) 15.625 * (float) CFG_BUS_HZ)
+			(unsigned int) (((float) 15.625 * (float) CONFIG_SYS_BUS_HZ)
 					/ (float) 1000000.0);
 		break;
 	case 0x1:
 	case 0x81:		/* refresh period is 3.9 usec */
 		sdram_config_reg =
-			(unsigned int) (((float) 3.9 * (float) CFG_BUS_HZ) /
+			(unsigned int) (((float) 3.9 * (float) CONFIG_SYS_BUS_HZ) /
 					(float) 1000000.0);
 		break;
 	case 0x2:
 	case 0x82:		/* refresh period is 7.8 usec */
 		sdram_config_reg =
-			(unsigned int) (((float) 7.8 * (float) CFG_BUS_HZ) /
+			(unsigned int) (((float) 7.8 * (float) CONFIG_SYS_BUS_HZ) /
 					(float) 1000000.0);
 		break;
 	case 0x3:
 	case 0x83:		/* refresh period is 31.3 usec */
 		sdram_config_reg =
-			(unsigned int) (((float) 31.3 * (float) CFG_BUS_HZ) /
+			(unsigned int) (((float) 31.3 * (float) CONFIG_SYS_BUS_HZ) /
 					(float) 1000000.0);
 		break;
 	case 0x4:
 	case 0x84:		/* refresh period is 62.5 usec */
 		sdram_config_reg =
-			(unsigned int) (((float) 62.5 * (float) CFG_BUS_HZ) /
+			(unsigned int) (((float) 62.5 * (float) CONFIG_SYS_BUS_HZ) /
 					(float) 1000000.0);
 		break;
 	case 0x5:
 	case 0x85:		/* refresh period is 125 usec */
 		sdram_config_reg =
-			(unsigned int) (((float) 125 * (float) CFG_BUS_HZ) /
+			(unsigned int) (((float) 125 * (float) CONFIG_SYS_BUS_HZ) /
 					(float) 1000000.0);
 		break;
 	default:		/* refresh period undefined */
@@ -1816,7 +1816,7 @@ phys_size_t initdram (int board_type)
 
 	printf ("-- DIMM2 has %d banks\n", dimmInfo2.numOfModuleBanks);
 
-	for (bank_no = 0; bank_no < CFG_DRAM_BANKS; bank_no++) {
+	for (bank_no = 0; bank_no < CONFIG_SYS_DRAM_BANKS; bank_no++) {
 		/* skip over banks that are not populated */
 		if (!checkbank[bank_no])
 			continue;

board/Marvell/db64460/u-boot.lds

@@ -60,7 +60,7 @@ SECTIONS
 
 /* store the environment in a seperate sector in the boot flash */
 /*    . = env_offset; */
-/*    common/environment.o(.text) */
+/*    common/env_embedded.o(.text) */
 
     *(.text)
     *(.fixup)
@@ -131,6 +131,7 @@ SECTIONS
    *(.dynbss)
    *(.bss)
    *(COMMON)
+   . = ALIGN(4);
   }
   _end = . ;
   PROVIDE (end = .);

board/RPXClassic/RPXClassic.c

@@ -111,7 +111,7 @@ void board_get_enetaddr (uchar * enet)
 	char buff[256], *cp;
 
 	/* Initialize I2C					*/
-	i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+	i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 
 	/* Read 256 bytes in EEPROM				*/
 	i2c_read (0x54, 0, 1, (uchar *)buff, 128);
@@ -167,7 +167,7 @@ void rpxclassic_init (void)
 
 phys_size_t initdram (int board_type)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	long int size10;
 
@@ -175,15 +175,15 @@ phys_size_t initdram (int board_type)
 			   sizeof (sdram_table) / sizeof (uint));
 
 	/* Refresh clock prescalar */
-	memctl->memc_mptpr = CFG_MPTPR;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
 
 	memctl->memc_mar = 0x00000000;
 
 	/* Map controller banks 1 to the SDRAM bank */
-	memctl->memc_or1 = CFG_OR1_PRELIM;
-	memctl->memc_br1 = CFG_BR1_PRELIM;
+	memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
+	memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
 
-	memctl->memc_mamr = CFG_MAMR_10COL & (~(MAMR_PTAE));	/* no refresh yet */
+	memctl->memc_mamr = CONFIG_SYS_MAMR_10COL & (~(MAMR_PTAE));	/* no refresh yet */
 
 	udelay (200);
 
@@ -200,7 +200,7 @@ phys_size_t initdram (int board_type)
 	 * try 10 column mode
 	 */
 
-	size10 = dram_size (CFG_MAMR_10COL, SDRAM_BASE_PRELIM,
+	size10 = dram_size (CONFIG_SYS_MAMR_10COL, SDRAM_BASE_PRELIM,
 						SDRAM_MAX_SIZE);
 
 	return (size10);
@@ -218,7 +218,7 @@ phys_size_t initdram (int board_type)
 
 static long int dram_size (long int mamr_value, long int *base, long int maxsize)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 
 	memctl->memc_mamr = mamr_value;

board/RPXClassic/eccx.c

@@ -299,7 +299,7 @@ void video_get_info_str (int line_number, char *info)
  */
 unsigned int board_video_init (void)
 {
-    volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+    volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
     volatile memctl8xx_t *memctl = &immap->im_memctl;
 
     /* Program ECCX registers                                                */

board/RPXClassic/flash.c

@@ -33,7 +33,7 @@
 #include <common.h>
 #include <mpc8xx.h>
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 /*-----------------------------------------------------------------------
  * Functions
@@ -51,20 +51,20 @@ unsigned long flash_init (void)
 	int i;
 
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
-	size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+	size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
 
-	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+	flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
-		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
 		      &flash_info[0]);
 #endif
 
@@ -313,7 +313,7 @@ int	flash_erase (flash_info_t *info, int s_first, int s_last)
 	last  = start;
 	addr = (vu_long *)(info->start[l_sect]);
 	while ((addr[0] & 0x80808080) != 0x80808080) {
-		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf ("Timeout\n");
 			return 1;
 		}
@@ -436,7 +436,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data)
 	/* data polling for D7 */
 	start = get_timer (0);
 	while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			return (1);
 		}
 	}

board/RPXClassic/u-boot.lds

@@ -64,7 +64,7 @@ SECTIONS
 /* XXX ?
     . = env_offset;
 */
-    common/environment.o(.text)
+    common/env_embedded.o(.text)
 
     *(.text)
     *(.fixup)
@@ -135,6 +135,7 @@ SECTIONS
    *(.dynbss)
    *(.bss)
    *(COMMON)
+   . = ALIGN(4);
   }
   _end = . ;
   PROVIDE (end = .);

board/RPXClassic/u-boot.lds.debug

@@ -61,7 +61,7 @@ SECTIONS
     lib_generic/crc32.o		(.text)
 
     . = env_offset;
-    common/environment.o(.text)
+    common/env_embedded.o(.text)
 
     *(.text)
     *(.fixup)

board/RPXlite/RPXlite.c

@@ -104,7 +104,7 @@ int checkboard (void)
 
 phys_size_t initdram (int board_type)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	long int size10;
 
@@ -112,15 +112,15 @@ phys_size_t initdram (int board_type)
 		   sizeof (sdram_table) / sizeof (uint));
 
 	/* Refresh clock prescalar */
-	memctl->memc_mptpr = CFG_MPTPR;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
 
 	memctl->memc_mar = 0x00000000;
 
 	/* Map controller banks 1 to the SDRAM bank */
-	memctl->memc_or1 = CFG_OR1_PRELIM;
-	memctl->memc_br1 = CFG_BR1_PRELIM;
+	memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
+	memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
 
-	memctl->memc_mamr = CFG_MAMR_10COL & (~(MAMR_PTAE));	/* no refresh yet */
+	memctl->memc_mamr = CONFIG_SYS_MAMR_10COL & (~(MAMR_PTAE));	/* no refresh yet */
 
 	udelay (200);
 
@@ -137,7 +137,7 @@ phys_size_t initdram (int board_type)
 	 * try 10 column mode
 	 */
 
-	size10 = dram_size (CFG_MAMR_10COL, SDRAM_BASE_PRELIM,
+	size10 = dram_size (CONFIG_SYS_MAMR_10COL, SDRAM_BASE_PRELIM,
 			    SDRAM_MAX_SIZE);
 
 	return (size10);
@@ -156,7 +156,7 @@ phys_size_t initdram (int board_type)
 static long int dram_size (long int mamr_value, long int *base,
 			   long int maxsize)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 
 	memctl->memc_mamr = mamr_value;

board/RPXlite/flash.c

@@ -38,7 +38,7 @@
 #include <common.h>
 #include <mpc8xx.h>
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 /*-----------------------------------------------------------------------
  * Functions
@@ -52,13 +52,13 @@ static void flash_get_offsets (ulong base, flash_info_t *info);
 
 unsigned long flash_init (void)
 {
-/*	volatile immap_t     *immap  = (immap_t *)CFG_IMMR; */
+/*	volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR; */
 /*	volatile memctl8xx_t *memctl = &immap->im_memctl; */
 	unsigned long size_b0 ;
 	int i;
 
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
@@ -73,19 +73,19 @@ unsigned long flash_init (void)
 */
 	/* Remap FLASH according to real size */
 /*%%%
-	memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
-	memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
+	memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
+	memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
 %%%*/
 	/* Re-do sizing to get full correct info */
 
-	size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
-	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+	size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+	flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
-		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
 		      &flash_info[0]);
 #endif
 
@@ -390,7 +390,7 @@ int	flash_erase (flash_info_t *info, int s_first, int s_last)
 	last  = start;
 	addr = (vu_long *)(info->start[l_sect]);
 	while ((addr[0] & 0x80808080) != 0x80808080) {
-		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf ("Timeout\n");
 			return 1;
 		}
@@ -513,7 +513,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data)
 	/* data polling for D7 */
 	start = get_timer (0);
 	while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			return (1);
 		}
 	}

board/RPXlite/u-boot.lds

@@ -64,7 +64,7 @@ SECTIONS
 /* XXX ?
     . = env_offset;
 */
-    common/environment.o(.text)
+    common/env_embedded.o(.text)
 
     *(.text)
     *(.fixup)
@@ -135,6 +135,7 @@ SECTIONS
    *(.dynbss)
    *(.bss)
    *(COMMON)
+   . = ALIGN(4);
   }
   _end = . ;
   PROVIDE (end = .);

board/RPXlite/u-boot.lds.debug

@@ -61,7 +61,7 @@ SECTIONS
     lib_generic/crc32.o		(.text)
 
     . = env_offset;
-    common/environment.o(.text)
+    common/env_embedded.o(.text)
 
     *(.text)
     *(.fixup)

board/RPXlite_dw/README

@@ -21,7 +21,7 @@ make distclean
 make RPXlite_DW_64_config
 make all
 
-2. CFG_ENV_IS_IN_FLASH/CFG_ENV_IS_IN_NVRAM
+2. CONFIG_ENV_IS_IN_FLASH/CONFIG_ENV_IS_IN_NVRAM
 
 The default environment parameter is stored in FLASH because it is a common choice for
 environment parameter.So I make NVRAM as backup parameter storeage.The reason why I

board/RPXlite_dw/RPXlite_dw.c

@@ -106,22 +106,22 @@ int checkboard (void)
 
 phys_size_t initdram (int board_type)
 {
-	volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+	volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	long int size9;
 
 	upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
 
 	/* Refresh clock prescalar */
-	memctl->memc_mptpr = CFG_MPTPR ;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR ;
 
 	memctl->memc_mar  = 0x00000088;
 
 	/* Map controller banks 1 to the SDRAM bank */
-	memctl->memc_or1 = CFG_OR1_PRELIM;
-	memctl->memc_br1 = CFG_BR1_PRELIM;
+	memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
+	memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
 
-	memctl->memc_mamr = CFG_MAMR_9COL & (~(MAMR_PTAE)); /* no refresh yet */
+	memctl->memc_mamr = CONFIG_SYS_MAMR_9COL & (~(MAMR_PTAE)); /* no refresh yet */
 	/*Disable Periodic timer A. */
 
 	udelay(200);
@@ -142,13 +142,13 @@ phys_size_t initdram (int board_type)
 	  * try 9 column mode
 	  */
 
-	size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE);
+	size9 = dram_size (CONFIG_SYS_MAMR_9COL, SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE);
 
 	/*
 	 * Final mapping:
 	 */
 
-	memctl->memc_or1 = ((-size9) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
+	memctl->memc_or1 = ((-size9) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
 
 	udelay (1000);
 
@@ -171,7 +171,7 @@ void rpxlite_init (void)
 static long int dram_size (long int mamr_value, long int *base,
 			   long int maxsize)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 
 	memctl->memc_mamr = mamr_value;

board/RPXlite_dw/flash.c

@@ -49,7 +49,7 @@
 #include <common.h>
 #include <mpc8xx.h>
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 /*-----------------------------------------------------------------------
  * Functions   vu_long : volatile unsigned long IN include/common.h
@@ -64,22 +64,22 @@ unsigned long flash_init (void)
 	int i;
 
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
-	size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
-	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+	size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+	flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 	/* If Monitor is in the cope of FLASH,then
 	 * protect this area by default in case for
 	 * other occupation. [SAM] */
 
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
-		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN-1,
 		      &flash_info[0]);
 #endif
 	flash_info[0].size = size_b0;
@@ -360,7 +360,7 @@ int	flash_erase (flash_info_t *info, int s_first, int s_last)
 	last  = start;
 	addr = (vu_long *)(info->start[l_sect]);
 	while ((addr[0] & 0x80808080) != 0x80808080) {
-		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf ("Timeout\n");
 			return 1;
 		}
@@ -482,7 +482,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data)
 	/* data polling for D7 */
 	start = get_timer (0);
 	while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			return (1);
 		}
 	}

board/RPXlite_dw/u-boot.lds

@@ -64,7 +64,7 @@ SECTIONS
 /* XXX ?
     . = env_offset;
 */
-    common/environment.o(.text)
+    common/env_embedded.o(.text)
 
     *(.text)
     *(.fixup)
@@ -135,6 +135,7 @@ SECTIONS
    *(.dynbss)
    *(.bss)
    *(COMMON)
+   . = ALIGN(4);
   }
   _end = . ;
   PROVIDE (end = .);

board/RPXlite_dw/u-boot.lds.debug

@@ -61,7 +61,7 @@ SECTIONS
     lib_generic/crc32.o		(.text)
 
     . = env_offset;
-    common/environment.o(.text)
+    common/env_embedded.o(.text)
 
     *(.text)
     *(.fixup)

board/RRvision/RRvision.c

@@ -112,7 +112,7 @@ int checkboard (void)
 
 phys_size_t initdram (int board_type)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	unsigned long reg;
 	long int size8, size9;
@@ -126,17 +126,17 @@ phys_size_t initdram (int board_type)
 	 * with two SDRAM banks or four cycles every 31.2 us with one
 	 * bank. It will be adjusted after memory sizing.
 	 */
-	memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K;
 
 	memctl->memc_mar = 0x00000088;
 
 	/*
 	 * Map controller bank 1 the SDRAM bank 2 at physical address 0.
 	 */
-	memctl->memc_or1 = CFG_OR2_PRELIM;
-	memctl->memc_br1 = CFG_BR2_PRELIM;
+	memctl->memc_or1 = CONFIG_SYS_OR2_PRELIM;
+	memctl->memc_br1 = CONFIG_SYS_BR2_PRELIM;
 
-	memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */
+	memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */
 
 	udelay (200);
 
@@ -156,7 +156,7 @@ phys_size_t initdram (int board_type)
 	 *
 	 * try 8 column mode
 	 */
-	size8 = dram_size (CFG_MAMR_8COL,
+	size8 = dram_size (CONFIG_SYS_MAMR_8COL,
 			   SDRAM_BASE2_PRELIM,
 			   SDRAM_MAX_SIZE);
 
@@ -165,7 +165,7 @@ phys_size_t initdram (int board_type)
 	/*
 	 * try 9 column mode
 	 */
-	size9 = dram_size (CFG_MAMR_9COL,
+	size9 = dram_size (CONFIG_SYS_MAMR_9COL,
 			   SDRAM_BASE2_PRELIM,
 			   SDRAM_MAX_SIZE);
 
@@ -174,7 +174,7 @@ phys_size_t initdram (int board_type)
 /*		debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20);	*/
 	} else {			/* back to 8 columns            */
 		size = size8;
-		memctl->memc_mamr = CFG_MAMR_8COL;
+		memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
 		udelay (500);
 /*		debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20);	*/
 	}
@@ -187,15 +187,15 @@ phys_size_t initdram (int board_type)
 	 */
 	if (size < 0x02000000) {
 		/* reduce to 15.6 us (62.4 us / quad) */
-		memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
+		memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
 		udelay (1000);
 	}
 
 	/*
 	 * Final mapping
 	 */
-	memctl->memc_or1 = ((-size) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
-	memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+	memctl->memc_or1 = ((-size) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
+	memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
 
 	/*
 	 * No bank 1
@@ -206,7 +206,7 @@ phys_size_t initdram (int board_type)
 
 	/* adjust refresh rate depending on SDRAM type, one bank */
 	reg = memctl->memc_mptpr;
-	reg >>= 1;			/* reduce to CFG_MPTPR_1BK_8K / _4K */
+	reg >>= 1;			/* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
 	memctl->memc_mptpr = reg;
 
 	udelay (10000);
@@ -227,7 +227,7 @@ phys_size_t initdram (int board_type)
 static long int dram_size (long int mamr_value, long int *base,
 						   long int maxsize)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 
 	memctl->memc_mamr = mamr_value;

board/RRvision/flash.c

@@ -26,11 +26,11 @@
 #include <common.h>
 #include <mpc8xx.h>
 
-#ifndef	CFG_ENV_ADDR
-#define CFG_ENV_ADDR	(CFG_FLASH_BASE + CFG_ENV_OFFSET)
+#ifndef	CONFIG_ENV_ADDR
+#define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
 #endif
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 /*-----------------------------------------------------------------------
  * Functions
@@ -43,13 +43,13 @@ static int write_word (flash_info_t *info, ulong dest, ulong data);
 
 unsigned long flash_init (void)
 {
-	volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+	volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	unsigned long size;
 	int i;
 
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
@@ -63,25 +63,25 @@ unsigned long flash_init (void)
 	}
 
 	/* Remap FLASH according to real size */
-	memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size & OR_AM_MSK);
-	memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
+	memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size & OR_AM_MSK);
+	memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
 
 	/* Re-do sizing to get full correct info */
-	size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+	size = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
-		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
 		      &flash_info[0]);
 #endif
 
-#ifdef	CFG_ENV_IS_IN_FLASH
+#ifdef	CONFIG_ENV_IS_IN_FLASH
 	/* ENV protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
-		      CFG_ENV_ADDR,
-		      CFG_ENV_ADDR+CFG_ENV_SIZE-1,
+		      CONFIG_ENV_ADDR,
+		      CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1,
 		      &flash_info[0]);
 #endif
 
@@ -388,7 +388,7 @@ int	flash_erase (flash_info_t *info, int s_first, int s_last)
 	last  = start;
 	addr = (vu_long*)(info->start[l_sect]);
 	while ((addr[0] & 0x00800080) != 0x00800080) {
-		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			puts ("Timeout\n");
 			return 1;
 		}
@@ -511,7 +511,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data)
 	/* data polling for D7 */
 	start = get_timer (0);
 	while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			return (1);
 		}
 	}

board/RRvision/u-boot.lds

@@ -66,7 +66,7 @@ SECTIONS
     lib_ppc/time.o		(.text)
 
     . = env_offset;
-    common/environment.o	(.ppcenv)
+    common/env_embedded.o	(.ppcenv)
 
     *(.text)
     *(.fixup)
@@ -137,6 +137,7 @@ SECTIONS
    *(.dynbss)
    *(.bss)
    *(COMMON)
+   . = ALIGN(4);
   }
   _end = . ;
   PROVIDE (end = .);

board/a3000/a3000.c

@@ -27,6 +27,7 @@
 #include <common.h>
 #include <mpc824x.h>
 #include <pci.h>
+#include <netdev.h>
 
 int checkboard (void)
 {
@@ -45,7 +46,7 @@ phys_size_t initdram (int board_type)
 	long mear1;
 	long emear1;
 
-	size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
+	size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE);
 
 	new_bank0_end = size - 1;
 	mear1 = mpc824x_mpc107_getreg(MEAR1);
@@ -109,3 +110,8 @@ void pci_init_board(void)
 {
 	pci_mpc824x_init(&hose);
 }
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}

board/a3000/flash.c

@@ -25,15 +25,15 @@
 #include <common.h>
 #include <mpc824x.h>
 
-#if defined(CFG_ENV_IS_IN_FLASH)
-# ifndef  CFG_ENV_ADDR
-#  define CFG_ENV_ADDR  (CFG_FLASH_BASE + CFG_ENV_OFFSET)
+#if defined(CONFIG_ENV_IS_IN_FLASH)
+# ifndef  CONFIG_ENV_ADDR
+#  define CONFIG_ENV_ADDR  (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
 # endif
-# ifndef  CFG_ENV_SIZE
-#  define CFG_ENV_SIZE  CFG_ENV_SECT_SIZE
+# ifndef  CONFIG_ENV_SIZE
+#  define CONFIG_ENV_SIZE  CONFIG_ENV_SECT_SIZE
 # endif
-# ifndef  CFG_ENV_SECT_SIZE
-#  define CFG_ENV_SECT_SIZE  CFG_ENV_SIZE
+# ifndef  CONFIG_ENV_SECT_SIZE
+#  define CONFIG_ENV_SECT_SIZE  CONFIG_ENV_SIZE
 # endif
 #endif
 
@@ -48,7 +48,7 @@
 #endif
 /*---------------------------------------------------------------------*/
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 /*-----------------------------------------------------------------------
  * Functions
@@ -65,13 +65,13 @@ static void flash_get_offsets (ulong base, flash_info_t *info);
 
 unsigned long flash_init (void)
 {
-	unsigned long flash_banks[CFG_MAX_FLASH_BANKS] = CFG_FLASH_BANKS;
-	unsigned long size, size_b[CFG_MAX_FLASH_BANKS];
+	unsigned long flash_banks[CONFIG_SYS_MAX_FLASH_BANKS] = CONFIG_SYS_FLASH_BANKS;
+	unsigned long size, size_b[CONFIG_SYS_MAX_FLASH_BANKS];
 
 	int i;
 
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i)
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i)
 	{
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 
@@ -99,27 +99,27 @@ unsigned long flash_init (void)
 	}
 
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
-	DEBUGF("protect monitor %x @ %x\n", CFG_MONITOR_BASE, CFG_MONITOR_LEN);
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+	DEBUGF("protect monitor %x @ %x\n", CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_LEN);
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
-		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN-1,
 		      &flash_info[0]);
 #endif
 
-#ifdef	CFG_ENV_IS_IN_FLASH
+#ifdef	CONFIG_ENV_IS_IN_FLASH
 	/* ENV protection ON by default */
-	DEBUGF("protect environtment %x @ %x\n", CFG_ENV_ADDR, CFG_ENV_SECT_SIZE);
+	DEBUGF("protect environtment %x @ %x\n", CONFIG_ENV_ADDR, CONFIG_ENV_SECT_SIZE);
 	flash_protect(FLAG_PROTECT_SET,
-		      CFG_ENV_ADDR,
-		      CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1,
+		      CONFIG_ENV_ADDR,
+		      CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1,
 		      &flash_info[0]);
 #endif
 
 	size = 0;
 	DEBUGF("## Final Flash bank sizes: ");
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i)
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i)
 	{
 		DEBUGF("%08lx ", size_b[i]);
 		size += size_b[i];
@@ -285,10 +285,10 @@ static ulong flash_get_size (vu_char *addr, flash_info_t *info)
 
 	}
 
-	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
 		printf ("** ERROR: sector count %d > max (%d) **\n",
-			info->sector_count, CFG_MAX_FLASH_SECT);
-		info->sector_count = CFG_MAX_FLASH_SECT;
+			info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
 	}
 
 	addr[0] = BS(0xFF);		/* restore read mode */
@@ -356,7 +356,7 @@ int	flash_erase (flash_info_t *info, int s_first, int s_last)
 			udelay (1000);
 
 			while (((status = BS(*addr)) & BYTEME(0x00800080)) != BYTEME(0x00800080)) {
-				if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+				if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 					printf ("Timeout\n");
 					*addr = BS(0xB0); /* suspend erase	  */
 					*addr = BS(0xFF); /* reset to read mode */
@@ -439,7 +439,7 @@ static int write_data (flash_info_t *info, uchar *dest, uchar data)
 	start = get_timer (0);
 
 	while (((status = BS(*addr)) & BYTEME(0x00800080)) != BYTEME(0x00800080)) {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			*addr = BS(0xFF);	/* restore read mode */
 			return 1;
 		}

board/actux1/actux1.c

@@ -49,16 +49,16 @@ int board_init (void)
 	/* adress of boot parameters */
 	gd->bd->bi_boot_params = 0x00000100;
 
-	GPIO_OUTPUT_CLEAR (CFG_GPIO_IORST);
-	GPIO_OUTPUT_ENABLE (CFG_GPIO_IORST);
+	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_IORST);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_IORST);
 
 	/* Setup GPIO's for PCI INTA */
-	GPIO_OUTPUT_DISABLE (CFG_GPIO_PCI1_INTA);
-	GPIO_INT_ACT_LOW_SET (CFG_GPIO_PCI1_INTA);
+	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_PCI1_INTA);
+	GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_PCI1_INTA);
 
 	/* Setup GPIO's for 33MHz clock output */
-	GPIO_OUTPUT_ENABLE (CFG_GPIO_PCI_CLK);
-	GPIO_OUTPUT_ENABLE (CFG_GPIO_EXTBUS_CLK);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_PCI_CLK);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_EXTBUS_CLK);
 	*IXP425_GPIO_GPCLKR = 0x011001FF;
 
 	/* CS5: Debug port */
@@ -69,7 +69,7 @@ int board_init (void)
 	*IXP425_EXP_CS7 = 0x80900003;
 
 	udelay (533);
-	GPIO_OUTPUT_SET (CFG_GPIO_IORST);
+	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_IORST);
 
 	ACTUX1_LED1 (2);
 	ACTUX1_LED2 (2);

board/actux1/actux1_hw.h

@@ -42,16 +42,16 @@
 #define ACTUX1_BOARDREL	(readb(IXP425_EXP_BUS_CS6_BASE_PHYS) & 0x0F)
 
 /* GPIO settings */
-#define CFG_GPIO_PCI1_INTA		2
-#define CFG_GPIO_PCI2_INTA		3
-#define CFG_GPIO_I2C_SDA		4
-#define CFG_GPIO_I2C_SCL		5
-#define CFG_GPIO_DBGJUMPER		9
-#define CFG_GPIO_BUTTON1		10
-#define CFG_GPIO_DBGSENSE		11
-#define CFG_GPIO_DTR			12
-#define CFG_GPIO_IORST			13	/* Out */
-#define CFG_GPIO_PCI_CLK		14	/* Out */
-#define CFG_GPIO_EXTBUS_CLK		15	/* Out */
+#define CONFIG_SYS_GPIO_PCI1_INTA		2
+#define CONFIG_SYS_GPIO_PCI2_INTA		3
+#define CONFIG_SYS_GPIO_I2C_SDA		4
+#define CONFIG_SYS_GPIO_I2C_SCL		5
+#define CONFIG_SYS_GPIO_DBGJUMPER		9
+#define CONFIG_SYS_GPIO_BUTTON1		10
+#define CONFIG_SYS_GPIO_DBGSENSE		11
+#define CONFIG_SYS_GPIO_DTR			12
+#define CONFIG_SYS_GPIO_IORST			13	/* Out */
+#define CONFIG_SYS_GPIO_PCI_CLK		14	/* Out */
+#define CONFIG_SYS_GPIO_EXTBUS_CLK		15	/* Out */
 
 #endif

board/actux1/u-boot.lds

@@ -37,7 +37,7 @@ SECTIONS
 		common/dlmalloc.o(.text)
 		cpu/ixp/cpu.o(.text)
 		. = env_offset;
-		common/environment.o(.ppcenv)
+		common/env_embedded.o(.ppcenv)
 		* (.text)
 	}
 
@@ -64,6 +64,7 @@ SECTIONS
 	__bss_start =.;
 	.bss (NOLOAD): {
 		*(.bss)
+		. = ALIGN(4);
 	}
 	_end =.;
 }

board/actux2/actux2.c

@@ -50,24 +50,24 @@ int board_init (void)
 	/* adress of boot parameters */
 	gd->bd->bi_boot_params = 0x00000100;
 
-	GPIO_OUTPUT_ENABLE (CFG_GPIO_IORST);
-	GPIO_OUTPUT_ENABLE (CFG_GPIO_ETHRST);
-	GPIO_OUTPUT_ENABLE (CFG_GPIO_DSR);
-	GPIO_OUTPUT_ENABLE (CFG_GPIO_DCD);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_IORST);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_ETHRST);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_DSR);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_DCD);
 
-	GPIO_OUTPUT_CLEAR (CFG_GPIO_IORST);
-	GPIO_OUTPUT_CLEAR (CFG_GPIO_ETHRST);
+	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_IORST);
+	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_ETHRST);
 
-	GPIO_OUTPUT_CLEAR (CFG_GPIO_DSR);
-	GPIO_OUTPUT_SET (CFG_GPIO_DCD);
+	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_DSR);
+	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_DCD);
 
 	/* Setup GPIO's for Interrupt inputs */
-	GPIO_OUTPUT_DISABLE (CFG_GPIO_DBGINT);
-	GPIO_OUTPUT_DISABLE (CFG_GPIO_ETHINT);
+	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_DBGINT);
+	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_ETHINT);
 
 	/* Setup GPIO's for 33MHz clock output */
-	GPIO_OUTPUT_ENABLE (CFG_GPIO_PCI_CLK);
-	GPIO_OUTPUT_ENABLE (CFG_GPIO_EXTBUS_CLK);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_PCI_CLK);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_EXTBUS_CLK);
 	*IXP425_GPIO_GPCLKR = 0x011001FF;
 
 	/* CS1: IPAC-X */
@@ -80,8 +80,8 @@ int board_init (void)
 	*IXP425_EXP_CS7 = 0x80900003;
 
 	udelay (533);
-	GPIO_OUTPUT_SET (CFG_GPIO_IORST);
-	GPIO_OUTPUT_SET (CFG_GPIO_ETHRST);
+	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_IORST);
+	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_ETHRST);
 
 	ACTUX2_LED1 (1);
 	ACTUX2_LED2 (0);

board/actux2/actux2_hw.h

@@ -39,21 +39,21 @@
 /*
  * GPIO settings
  */
-#define CFG_GPIO_DBGINT			0
-#define CFG_GPIO_ETHINT			1
-#define CFG_GPIO_ETHRST			2	/* Out */
-#define CFG_GPIO_LED5_GN		3	/* Out */
-#define CFG_GPIO_UNUSED4		4
-#define CFG_GPIO_UNUSED5		5
-#define CFG_GPIO_DSR			6	/* Out */
-#define CFG_GPIO_DCD			7	/* Out */
-#define CFG_GPIO_IPAC_INT		8
-#define CFG_GPIO_DBGJUMPER		9
-#define CFG_GPIO_BUTTON1		10
-#define CFG_GPIO_DBGSENSE		11
-#define CFG_GPIO_DTR			12
-#define CFG_GPIO_IORST			13	/* Out */
-#define CFG_GPIO_PCI_CLK		14	/* Out */
-#define CFG_GPIO_EXTBUS_CLK		15	/* Out */
+#define CONFIG_SYS_GPIO_DBGINT			0
+#define CONFIG_SYS_GPIO_ETHINT			1
+#define CONFIG_SYS_GPIO_ETHRST			2	/* Out */
+#define CONFIG_SYS_GPIO_LED5_GN		3	/* Out */
+#define CONFIG_SYS_GPIO_UNUSED4		4
+#define CONFIG_SYS_GPIO_UNUSED5		5
+#define CONFIG_SYS_GPIO_DSR			6	/* Out */
+#define CONFIG_SYS_GPIO_DCD			7	/* Out */
+#define CONFIG_SYS_GPIO_IPAC_INT		8
+#define CONFIG_SYS_GPIO_DBGJUMPER		9
+#define CONFIG_SYS_GPIO_BUTTON1		10
+#define CONFIG_SYS_GPIO_DBGSENSE		11
+#define CONFIG_SYS_GPIO_DTR			12
+#define CONFIG_SYS_GPIO_IORST			13	/* Out */
+#define CONFIG_SYS_GPIO_PCI_CLK		14	/* Out */
+#define CONFIG_SYS_GPIO_EXTBUS_CLK		15	/* Out */
 
 #endif

board/actux2/u-boot.lds

@@ -38,7 +38,7 @@ SECTIONS
 		cpu/ixp/cpu.o(.text)
 
 		. = env_offset;
-		common/environment.o (.ppcenv)
+		common/env_embedded.o (.ppcenv)
 
 		* (.text)
 	}
@@ -69,6 +69,7 @@ SECTIONS
 	__bss_start =.;
 	.bss (NOLOAD): {
 		*(.bss)
+		. = ALIGN(4);
 	}
 	_end =.;
 }

board/actux3/actux3.c

@@ -50,35 +50,35 @@ int board_init (void)
 	/* adress of boot parameters */
 	gd->bd->bi_boot_params = 0x00000100;
 
-	GPIO_OUTPUT_ENABLE (CFG_GPIO_IORST);
-	GPIO_OUTPUT_ENABLE (CFG_GPIO_ETHRST);
-	GPIO_OUTPUT_ENABLE (CFG_GPIO_DSR);
-	GPIO_OUTPUT_ENABLE (CFG_GPIO_DCD);
-	GPIO_OUTPUT_ENABLE (CFG_GPIO_LED5_GN);
-	GPIO_OUTPUT_ENABLE (CFG_GPIO_LED6_RT);
-	GPIO_OUTPUT_ENABLE (CFG_GPIO_LED6_GN);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_IORST);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_ETHRST);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_DSR);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_DCD);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_LED5_GN);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_LED6_RT);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_LED6_GN);
 
-	GPIO_OUTPUT_CLEAR (CFG_GPIO_IORST);
-	GPIO_OUTPUT_CLEAR (CFG_GPIO_ETHRST);
+	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_IORST);
+	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_ETHRST);
 
-	GPIO_OUTPUT_CLEAR (CFG_GPIO_DSR);
-	GPIO_OUTPUT_SET (CFG_GPIO_DCD);
+	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_DSR);
+	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_DCD);
 
-	GPIO_OUTPUT_CLEAR (CFG_GPIO_LED5_GN);
-	GPIO_OUTPUT_CLEAR (CFG_GPIO_LED6_RT);
-	GPIO_OUTPUT_CLEAR (CFG_GPIO_LED6_GN);
+	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_LED5_GN);
+	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_LED6_RT);
+	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_LED6_GN);
 
 	/*
 	 * Setup GPIO's for Interrupt inputs
 	 */
-	GPIO_OUTPUT_DISABLE (CFG_GPIO_DBGINT);
-	GPIO_OUTPUT_DISABLE (CFG_GPIO_ETHINT);
+	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_DBGINT);
+	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_ETHINT);
 
 	/*
 	 * Setup GPIO's for 33MHz clock output
 	 */
-	GPIO_OUTPUT_ENABLE (CFG_GPIO_PCI_CLK);
-	GPIO_OUTPUT_ENABLE (CFG_GPIO_EXTBUS_CLK);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_PCI_CLK);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_EXTBUS_CLK);
 	*IXP425_GPIO_GPCLKR = 0x011001FF;
 
 	/* CS1: IPAC-X */
@@ -91,8 +91,8 @@ int board_init (void)
 	*IXP425_EXP_CS7 = 0x80900003;
 
 	udelay (533);
-	GPIO_OUTPUT_SET (CFG_GPIO_IORST);
-	GPIO_OUTPUT_SET (CFG_GPIO_ETHRST);
+	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_IORST);
+	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_ETHRST);
 
 	ACTUX3_LED1_RT (1);
 	ACTUX3_LED1_GN (0);

board/actux3/actux3_hw.h

@@ -41,20 +41,20 @@
 #define ACTUX3_OPTION		(readb(IXP425_EXP_BUS_CS6_BASE_PHYS) & 0xF0)
 
 /* GPIO settings */
-#define CFG_GPIO_DBGINT			0
-#define CFG_GPIO_ETHINT			1
-#define CFG_GPIO_ETHRST			2	/* Out */
-#define CFG_GPIO_LED5_GN		3	/* Out */
-#define CFG_GPIO_LED6_RT		4	/* Out */
-#define CFG_GPIO_LED6_GN		5	/* Out */
-#define CFG_GPIO_DSR			6	/* Out */
-#define CFG_GPIO_DCD			7	/* Out */
-#define CFG_GPIO_DBGJUMPER		9
-#define CFG_GPIO_BUTTON1		10
-#define CFG_GPIO_DBGSENSE		11
-#define CFG_GPIO_DTR			12
-#define CFG_GPIO_IORST			13	/* Out */
-#define CFG_GPIO_PCI_CLK		14	/* Out */
-#define CFG_GPIO_EXTBUS_CLK		15	/* Out */
+#define CONFIG_SYS_GPIO_DBGINT			0
+#define CONFIG_SYS_GPIO_ETHINT			1
+#define CONFIG_SYS_GPIO_ETHRST			2	/* Out */
+#define CONFIG_SYS_GPIO_LED5_GN		3	/* Out */
+#define CONFIG_SYS_GPIO_LED6_RT		4	/* Out */
+#define CONFIG_SYS_GPIO_LED6_GN		5	/* Out */
+#define CONFIG_SYS_GPIO_DSR			6	/* Out */
+#define CONFIG_SYS_GPIO_DCD			7	/* Out */
+#define CONFIG_SYS_GPIO_DBGJUMPER		9
+#define CONFIG_SYS_GPIO_BUTTON1		10
+#define CONFIG_SYS_GPIO_DBGSENSE		11
+#define CONFIG_SYS_GPIO_DTR			12
+#define CONFIG_SYS_GPIO_IORST			13	/* Out */
+#define CONFIG_SYS_GPIO_PCI_CLK		14	/* Out */
+#define CONFIG_SYS_GPIO_EXTBUS_CLK		15	/* Out */
 
 #endif

board/actux3/u-boot.lds

@@ -38,7 +38,7 @@ SECTIONS
 		cpu/ixp/cpu.o (.text)
 
 		. = env_offset;
-		common/environment.o (.ppcenv)
+		common/env_embedded.o (.ppcenv)
 
 		* (.text)
 	}
@@ -69,6 +69,7 @@ SECTIONS
 	__bss_start =.;
 	.bss (NOLOAD): {
 		*(.bss)
+		. = ALIGN(4);
 	}
 	_end =.;
 }

board/actux4/actux4.c

@@ -49,53 +49,53 @@ int board_init (void)
 	/* adress of boot parameters */
 	gd->bd->bi_boot_params = 0x00000100;
 
-	GPIO_OUTPUT_CLEAR (CFG_GPIO_nPWRON);
-	GPIO_OUTPUT_ENABLE (CFG_GPIO_nPWRON);
+	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_nPWRON);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_nPWRON);
 
-	GPIO_OUTPUT_CLEAR (CFG_GPIO_IORST);
-	GPIO_OUTPUT_ENABLE (CFG_GPIO_IORST);
+	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_IORST);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_IORST);
 
 	/* led not populated on board*/
-	GPIO_OUTPUT_ENABLE (CFG_GPIO_LED3);
-	GPIO_OUTPUT_SET (CFG_GPIO_LED3);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_LED3);
+	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_LED3);
 
 	/* middle LED */
-	GPIO_OUTPUT_ENABLE (CFG_GPIO_LED2);
-	GPIO_OUTPUT_SET (CFG_GPIO_LED2);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_LED2);
+	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_LED2);
 
 	/* right LED */
 	/* weak pulldown = LED weak on */
-	GPIO_OUTPUT_DISABLE (CFG_GPIO_LED1);
-	GPIO_OUTPUT_SET (CFG_GPIO_LED1);
+	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_LED1);
+	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_LED1);
 
 	/* Setup GPIO's for Interrupt inputs */
-	GPIO_OUTPUT_DISABLE (CFG_GPIO_USBINTA);
-	GPIO_OUTPUT_DISABLE (CFG_GPIO_USBINTB);
-	GPIO_OUTPUT_DISABLE (CFG_GPIO_USBINTC);
-	GPIO_OUTPUT_DISABLE (CFG_GPIO_RTCINT);
-	GPIO_OUTPUT_DISABLE (CFG_GPIO_PCI_INTA);
-	GPIO_OUTPUT_DISABLE (CFG_GPIO_PCI_INTB);
-
-	GPIO_INT_ACT_LOW_SET (CFG_GPIO_USBINTA);
-	GPIO_INT_ACT_LOW_SET (CFG_GPIO_USBINTB);
-	GPIO_INT_ACT_LOW_SET (CFG_GPIO_USBINTC);
-	GPIO_INT_ACT_LOW_SET (CFG_GPIO_RTCINT);
-	GPIO_INT_ACT_LOW_SET (CFG_GPIO_PCI_INTA);
-	GPIO_INT_ACT_LOW_SET (CFG_GPIO_PCI_INTB);
+	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_USBINTA);
+	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_USBINTB);
+	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_USBINTC);
+	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_RTCINT);
+	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_PCI_INTA);
+	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_PCI_INTB);
+
+	GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_USBINTA);
+	GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_USBINTB);
+	GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_USBINTC);
+	GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_RTCINT);
+	GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_PCI_INTA);
+	GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_PCI_INTB);
 
 	/* Setup GPIO's for 33MHz clock output */
 	*IXP425_GPIO_GPCLKR = 0x011001FF;
-	GPIO_OUTPUT_ENABLE (CFG_GPIO_EXTBUS_CLK);
-	GPIO_OUTPUT_ENABLE (CFG_GPIO_PCI_CLK);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_EXTBUS_CLK);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_PCI_CLK);
 
 	*IXP425_EXP_CS1 = 0xbd113c42;
 
 	udelay (10000);
-	GPIO_OUTPUT_SET (CFG_GPIO_IORST);
+	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_IORST);
 	udelay (10000);
-	GPIO_OUTPUT_CLEAR (CFG_GPIO_IORST);
+	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_IORST);
 	udelay (10000);
-	GPIO_OUTPUT_SET (CFG_GPIO_IORST);
+	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_IORST);
 
 	return 0;
 }

board/actux4/actux4_hw.h

@@ -29,21 +29,21 @@
 /*
  * GPIO settings
  */
-#define CFG_GPIO_USBINTA		0
-#define CFG_GPIO_USBINTB		1
-#define CFG_GPIO_USBINTC		2
-#define CFG_GPIO_nPWRON			3	/* Out */
-#define CFG_GPIO_I2C_SCL		4
-#define CFG_GPIO_I2C_SDA		5
-#define CFG_GPIO_PCI_INTB		6
-#define CFG_GPIO_BUTTON1		7
-#define CFG_GPIO_LED1			8	/* Out */
-#define CFG_GPIO_RTCINT			9
-#define CFG_GPIO_LED2			10	/* Out */
-#define CFG_GPIO_PCI_INTA		11
-#define CFG_GPIO_IORST			12	/* Out */
-#define CFG_GPIO_LED3			13	/* Out */
-#define CFG_GPIO_PCI_CLK		14	/* Out */
-#define CFG_GPIO_EXTBUS_CLK		15	/* Out */
+#define CONFIG_SYS_GPIO_USBINTA		0
+#define CONFIG_SYS_GPIO_USBINTB		1
+#define CONFIG_SYS_GPIO_USBINTC		2
+#define CONFIG_SYS_GPIO_nPWRON			3	/* Out */
+#define CONFIG_SYS_GPIO_I2C_SCL		4
+#define CONFIG_SYS_GPIO_I2C_SDA		5
+#define CONFIG_SYS_GPIO_PCI_INTB		6
+#define CONFIG_SYS_GPIO_BUTTON1		7
+#define CONFIG_SYS_GPIO_LED1			8	/* Out */
+#define CONFIG_SYS_GPIO_RTCINT			9
+#define CONFIG_SYS_GPIO_LED2			10	/* Out */
+#define CONFIG_SYS_GPIO_PCI_INTA		11
+#define CONFIG_SYS_GPIO_IORST			12	/* Out */
+#define CONFIG_SYS_GPIO_LED3			13	/* Out */
+#define CONFIG_SYS_GPIO_PCI_CLK		14	/* Out */
+#define CONFIG_SYS_GPIO_EXTBUS_CLK		15	/* Out */
 
 #endif

board/actux4/u-boot.lds

@@ -60,6 +60,7 @@ SECTIONS
 	__bss_start =.;
 	.bss (NOLOAD): {
 		*(.bss)
+		. = ALIGN(4);
 	}
 	_end =.;
 }

board/adder/adder.c

@@ -68,7 +68,7 @@ static uint sdram_table[] = {
 phys_size_t initdram (int board_type)
 {
 	long int msize;
-	volatile immap_t     *immap  = (volatile immap_t *)CFG_IMMR;
+	volatile immap_t     *immap  = (volatile immap_t *)CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 
 	upmconfig(UPMA, sdram_table, sizeof(sdram_table) / sizeof(uint));
@@ -76,7 +76,7 @@ phys_size_t initdram (int board_type)
 	/* Configure SDRAM refresh */
 	memctl->memc_mptpr = MPTPR_PTP_DIV32; /* BRGCLK/32 */
 
-	memctl->memc_mamr = (94 << 24) | CFG_MAMR; /* No refresh */
+	memctl->memc_mamr = (94 << 24) | CONFIG_SYS_MAMR; /* No refresh */
 	udelay(200);
 
 	/* Run precharge from location 0x15 */
@@ -94,10 +94,10 @@ phys_size_t initdram (int board_type)
 	udelay(200);
 
 	memctl->memc_mamr |=  MAMR_PTAE; /* Enable refresh */
-	memctl->memc_or1   = ~(CFG_SDRAM_MAX_SIZE - 1) | OR_CSNT_SAM;
-	memctl->memc_br1   =  CFG_SDRAM_BASE | BR_PS_32 | BR_MS_UPMA | BR_V;
+	memctl->memc_or1   = ~(CONFIG_SYS_SDRAM_MAX_SIZE - 1) | OR_CSNT_SAM;
+	memctl->memc_br1   =  CONFIG_SYS_SDRAM_BASE | BR_PS_32 | BR_MS_UPMA | BR_V;
 
-	msize = get_ram_size(CFG_SDRAM_BASE, CFG_SDRAM_MAX_SIZE);
+	msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_MAX_SIZE);
 	memctl->memc_or1  |= ~(msize - 1);
 
 	return msize;

board/adder/u-boot.lds

@@ -118,6 +118,7 @@ SECTIONS
    *(.dynbss)
    *(.bss)
    *(COMMON)
+   . = ALIGN(4);
   }
   _end = . ;
   PROVIDE (end = .);

board/ads5121/ads5121.c

@@ -53,16 +53,16 @@ long int fixed_sdram(void);
 
 int board_early_init_f (void)
 {
-	volatile immap_t *im = (immap_t *) CFG_IMMR;
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 	u32 lpcaw;
 
 	/*
 	 * Initialize Local Window for the CPLD registers access (CS2 selects
 	 * the CPLD chip)
 	 */
-	im->sysconf.lpcs2aw = CSAW_START(CFG_CPLD_BASE) |
-			      CSAW_STOP(CFG_CPLD_BASE, CFG_CPLD_SIZE);
-	im->lpc.cs_cfg[2] = CFG_CS2_CFG;
+	im->sysconf.lpcs2aw = CSAW_START(CONFIG_SYS_CPLD_BASE) |
+			      CSAW_STOP(CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_SIZE);
+	im->lpc.cs_cfg[2] = CONFIG_SYS_CS2_CFG;
 
 	/*
 	 * According to MPC5121e RM, configuring local access windows should
@@ -80,21 +80,21 @@ int board_early_init_f (void)
 	 */
 
 #ifdef CONFIG_ADS5121_REV2
-	*((volatile u8 *)(CFG_CPLD_BASE + 0x08)) = 0xC1;
+	*((volatile u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) = 0xC1;
 #else
-	if (*((u8 *)(CFG_CPLD_BASE + 0x08)) & 0x04) {
-		*((volatile u8 *)(CFG_CPLD_BASE + 0x08)) = 0xC1;
+	if (*((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) & 0x04) {
+		*((volatile u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) = 0xC1;
 	} else {
 		/* running from Backup flash */
-		*((volatile u8 *)(CFG_CPLD_BASE + 0x08)) = 0x32;
+		*((volatile u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) = 0x32;
 	}
 #endif
 	/*
 	 * Configure Flash Speed
 	 */
-	*((volatile u32 *)(CFG_IMMR + LPC_OFFSET + CS0_CONFIG)) = CFG_CS0_CFG;
+	*((volatile u32 *)(CONFIG_SYS_IMMR + LPC_OFFSET + CS0_CONFIG)) = CONFIG_SYS_CS0_CFG;
 	if (SVR_MJREV (im->sysconf.spridr) >= 2) {
-		*((volatile u32 *)(CFG_IMMR + LPC_OFFSET + CS_ALE_TIMING_CONFIG)) = CFG_CS_ALETIMING;
+		*((volatile u32 *)(CONFIG_SYS_IMMR + LPC_OFFSET + CS_ALE_TIMING_CONFIG)) = CONFIG_SYS_CS_ALETIMING;
 	}
 	/*
 	 * Enable clocks
@@ -120,8 +120,8 @@ phys_size_t initdram (int board_type)
  */
 long int fixed_sdram (void)
 {
-	volatile immap_t *im = (immap_t *) CFG_IMMR;
-	u32 msize = CFG_DDR_SIZE * 1024 * 1024;
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
 	u32 msize_log2 = __ilog2 (msize);
 	u32 i;
 
@@ -129,7 +129,7 @@ long int fixed_sdram (void)
 	im->io_ctrl.regs[IOCTL_MEM/4] = IOCTRL_MUX_DDR;
 
 	/* Initialize DDR Local Window */
-	im->sysconf.ddrlaw.bar = CFG_DDR_BASE & 0xFFFFF000;
+	im->sysconf.ddrlaw.bar = CONFIG_SYS_DDR_BASE & 0xFFFFF000;
 	im->sysconf.ddrlaw.ar = msize_log2 - 1;
 
 	/*
@@ -141,68 +141,68 @@ long int fixed_sdram (void)
 	__asm__ __volatile__ ("isync");
 
 	/* Enable DDR */
-	im->mddrc.ddr_sys_config = CFG_MDDRC_SYS_CFG_EN;
+	im->mddrc.ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG_EN;
 
 	/* Initialize DDR Priority Manager */
-	im->mddrc.prioman_config1 = CFG_MDDRCGRP_PM_CFG1;
-	im->mddrc.prioman_config2 = CFG_MDDRCGRP_PM_CFG2;
-	im->mddrc.hiprio_config = CFG_MDDRCGRP_HIPRIO_CFG;
-	im->mddrc.lut_table0_main_upper = CFG_MDDRCGRP_LUT0_MU;
-	im->mddrc.lut_table0_main_lower = CFG_MDDRCGRP_LUT0_ML;
-	im->mddrc.lut_table1_main_upper = CFG_MDDRCGRP_LUT1_MU;
-	im->mddrc.lut_table1_main_lower = CFG_MDDRCGRP_LUT1_ML;
-	im->mddrc.lut_table2_main_upper = CFG_MDDRCGRP_LUT2_MU;
-	im->mddrc.lut_table2_main_lower = CFG_MDDRCGRP_LUT2_ML;
-	im->mddrc.lut_table3_main_upper = CFG_MDDRCGRP_LUT3_MU;
-	im->mddrc.lut_table3_main_lower = CFG_MDDRCGRP_LUT3_ML;
-	im->mddrc.lut_table4_main_upper = CFG_MDDRCGRP_LUT4_MU;
-	im->mddrc.lut_table4_main_lower = CFG_MDDRCGRP_LUT4_ML;
-	im->mddrc.lut_table0_alternate_upper = CFG_MDDRCGRP_LUT0_AU;
-	im->mddrc.lut_table0_alternate_lower = CFG_MDDRCGRP_LUT0_AL;
-	im->mddrc.lut_table1_alternate_upper = CFG_MDDRCGRP_LUT1_AU;
-	im->mddrc.lut_table1_alternate_lower = CFG_MDDRCGRP_LUT1_AL;
-	im->mddrc.lut_table2_alternate_upper = CFG_MDDRCGRP_LUT2_AU;
-	im->mddrc.lut_table2_alternate_lower = CFG_MDDRCGRP_LUT2_AL;
-	im->mddrc.lut_table3_alternate_upper = CFG_MDDRCGRP_LUT3_AU;
-	im->mddrc.lut_table3_alternate_lower = CFG_MDDRCGRP_LUT3_AL;
-	im->mddrc.lut_table4_alternate_upper = CFG_MDDRCGRP_LUT4_AU;
-	im->mddrc.lut_table4_alternate_lower = CFG_MDDRCGRP_LUT4_AL;
+	im->mddrc.prioman_config1 = CONFIG_SYS_MDDRCGRP_PM_CFG1;
+	im->mddrc.prioman_config2 = CONFIG_SYS_MDDRCGRP_PM_CFG2;
+	im->mddrc.hiprio_config = CONFIG_SYS_MDDRCGRP_HIPRIO_CFG;
+	im->mddrc.lut_table0_main_upper = CONFIG_SYS_MDDRCGRP_LUT0_MU;
+	im->mddrc.lut_table0_main_lower = CONFIG_SYS_MDDRCGRP_LUT0_ML;
+	im->mddrc.lut_table1_main_upper = CONFIG_SYS_MDDRCGRP_LUT1_MU;
+	im->mddrc.lut_table1_main_lower = CONFIG_SYS_MDDRCGRP_LUT1_ML;
+	im->mddrc.lut_table2_main_upper = CONFIG_SYS_MDDRCGRP_LUT2_MU;
+	im->mddrc.lut_table2_main_lower = CONFIG_SYS_MDDRCGRP_LUT2_ML;
+	im->mddrc.lut_table3_main_upper = CONFIG_SYS_MDDRCGRP_LUT3_MU;
+	im->mddrc.lut_table3_main_lower = CONFIG_SYS_MDDRCGRP_LUT3_ML;
+	im->mddrc.lut_table4_main_upper = CONFIG_SYS_MDDRCGRP_LUT4_MU;
+	im->mddrc.lut_table4_main_lower = CONFIG_SYS_MDDRCGRP_LUT4_ML;
+	im->mddrc.lut_table0_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT0_AU;
+	im->mddrc.lut_table0_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT0_AL;
+	im->mddrc.lut_table1_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT1_AU;
+	im->mddrc.lut_table1_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT1_AL;
+	im->mddrc.lut_table2_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT2_AU;
+	im->mddrc.lut_table2_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT2_AL;
+	im->mddrc.lut_table3_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT3_AU;
+	im->mddrc.lut_table3_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT3_AL;
+	im->mddrc.lut_table4_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT4_AU;
+	im->mddrc.lut_table4_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT4_AL;
 
 	/* Initialize MDDRC */
-	im->mddrc.ddr_sys_config = CFG_MDDRC_SYS_CFG;
-	im->mddrc.ddr_time_config0 = CFG_MDDRC_TIME_CFG0;
-	im->mddrc.ddr_time_config1 = CFG_MDDRC_TIME_CFG1;
-	im->mddrc.ddr_time_config2 = CFG_MDDRC_TIME_CFG2;
+	im->mddrc.ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG;
+	im->mddrc.ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0;
+	im->mddrc.ddr_time_config1 = CONFIG_SYS_MDDRC_TIME_CFG1;
+	im->mddrc.ddr_time_config2 = CONFIG_SYS_MDDRC_TIME_CFG2;
 
 	/* Initialize DDR */
 	for (i = 0; i < 10; i++)
-		im->mddrc.ddr_command = CFG_MICRON_NOP;
-
-	im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL;
-	im->mddrc.ddr_command = CFG_MICRON_NOP;
-	im->mddrc.ddr_command = CFG_MICRON_RFSH;
-	im->mddrc.ddr_command = CFG_MICRON_NOP;
-	im->mddrc.ddr_command = CFG_MICRON_RFSH;
-	im->mddrc.ddr_command = CFG_MICRON_NOP;
-	im->mddrc.ddr_command = CFG_MICRON_INIT_DEV_OP;
-	im->mddrc.ddr_command = CFG_MICRON_NOP;
-	im->mddrc.ddr_command = CFG_MICRON_EM2;
-	im->mddrc.ddr_command = CFG_MICRON_NOP;
-	im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL;
-	im->mddrc.ddr_command = CFG_MICRON_EM2;
-	im->mddrc.ddr_command = CFG_MICRON_EM3;
-	im->mddrc.ddr_command = CFG_MICRON_EN_DLL;
-	im->mddrc.ddr_command = CFG_MICRON_INIT_DEV_OP;
-	im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL;
-	im->mddrc.ddr_command = CFG_MICRON_RFSH;
-	im->mddrc.ddr_command = CFG_MICRON_INIT_DEV_OP;
-	im->mddrc.ddr_command = CFG_MICRON_OCD_DEFAULT;
-	im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL;
-	im->mddrc.ddr_command = CFG_MICRON_NOP;
+		im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
+
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_RFSH;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_RFSH;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_INIT_DEV_OP;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_EM2;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_EM2;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_EM3;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_EN_DLL;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_INIT_DEV_OP;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_RFSH;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_INIT_DEV_OP;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_OCD_DEFAULT;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
 
 	/* Start MDDRC */
-	im->mddrc.ddr_time_config0 = CFG_MDDRC_TIME_CFG0_RUN;
-	im->mddrc.ddr_sys_config = CFG_MDDRC_SYS_CFG_RUN;
+	im->mddrc.ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0_RUN;
+	im->mddrc.ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG_RUN;
 
 	return msize;
 }
@@ -292,8 +292,8 @@ static  iopin_t ioregs_init[] = {
 
 int checkboard (void)
 {
-	ushort brd_rev = *(vu_short *) (CFG_CPLD_BASE + 0x00);
-	uchar cpld_rev = *(vu_char *) (CFG_CPLD_BASE + 0x02);
+	ushort brd_rev = *(vu_short *) (CONFIG_SYS_CPLD_BASE + 0x00);
+	uchar cpld_rev = *(vu_char *) (CONFIG_SYS_CPLD_BASE + 0x02);
 
 	printf ("Board: ADS5121 rev. 0x%04x (CPLD rev. 0x%02x)\n",
 		brd_rev, cpld_rev);

board/ads5121/ads5121_diu.c

@@ -43,7 +43,7 @@ static int xres, yres;
 
 void diu_set_pixel_clock(unsigned int pixclock)
 {
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
 	volatile clk512x_t *clk = &immap->clk;
 	volatile unsigned int *clkdvdr = &clk->scfr[0];
 	unsigned long speed_ccb, temp, pixval;
@@ -100,7 +100,7 @@ int ads5121diu_init_show_bmp(cmd_tbl_t *cmdtp,
 }
 
 U_BOOT_CMD(
-	diufb, CFG_MAXARGS, 1, ads5121diu_init_show_bmp,
+	diufb, CONFIG_SYS_MAXARGS, 1, ads5121diu_init_show_bmp,
 	"diufb init | addr - Init or Display BMP file\n",
 	"init\n    - initialize DIU\n"
 	"addr\n    - display bmp at address 'addr'\n"

board/ads5121/pci.c

@@ -33,8 +33,8 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 /* System RAM mapped to PCI space */
-#define CONFIG_PCI_SYS_MEM_BUS	CFG_SDRAM_BASE
-#define CONFIG_PCI_SYS_MEM_PHYS	CFG_SDRAM_BASE
+#define CONFIG_PCI_SYS_MEM_BUS	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_PCI_SYS_MEM_PHYS	CONFIG_SYS_SDRAM_BASE
 
 static struct pci_controller pci_hose;
 
@@ -46,7 +46,7 @@ static struct pci_controller pci_hose;
 void
 pci_init_board(void)
 {
-	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 	volatile law512x_t *pci_law;
 	volatile pot512x_t *pci_pot;
 	volatile pcictrl512x_t *pci_ctrl;
@@ -87,10 +87,10 @@ pci_init_board(void)
 	/*
 	 * Configure PCI Local Access Windows
 	 */
-	pci_law[0].bar = CFG_PCI_MEM_PHYS & LAWBAR_BAR;
+	pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
 	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
 
-	pci_law[1].bar = CFG_PCI_IO_PHYS & LAWBAR_BAR;
+	pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
 	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_16M;
 
 	/*
@@ -98,18 +98,18 @@ pci_init_board(void)
 	 */
 
 	/* PCI mem space - prefetch */
-	pci_pot[0].potar = (CFG_PCI_MEM_BASE >> 12) & POTAR_TA_MASK;
-	pci_pot[0].pobar = (CFG_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK;
+	pci_pot[0].potar = (CONFIG_SYS_PCI_MEM_BASE >> 12) & POTAR_TA_MASK;
+	pci_pot[0].pobar = (CONFIG_SYS_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK;
 	pci_pot[0].pocmr = POCMR_EN | POCMR_PRE | POCMR_CM_256M;
 
 	/* PCI IO space */
-	pci_pot[1].potar = (CFG_PCI_IO_BASE >> 12) & POTAR_TA_MASK;
-	pci_pot[1].pobar = (CFG_PCI_IO_PHYS >> 12) & POBAR_BA_MASK;
+	pci_pot[1].potar = (CONFIG_SYS_PCI_IO_BASE >> 12) & POTAR_TA_MASK;
+	pci_pot[1].pobar = (CONFIG_SYS_PCI_IO_PHYS >> 12) & POBAR_BA_MASK;
 	pci_pot[1].pocmr = POCMR_EN | POCMR_IO | POCMR_CM_16M;
 
 	/* PCI mmio - non-prefetch mem space */
-	pci_pot[2].potar = (CFG_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK;
-	pci_pot[2].pobar = (CFG_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK;
+	pci_pot[2].potar = (CONFIG_SYS_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK;
+	pci_pot[2].pobar = (CONFIG_SYS_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK;
 	pci_pot[2].pocmr = POCMR_EN | POCMR_CM_256M;
 
 	/*
@@ -129,23 +129,23 @@ pci_init_board(void)
 
 	/* PCI memory prefetch space */
 	pci_set_region(hose->regions + 0,
-		       CFG_PCI_MEM_BASE,
-		       CFG_PCI_MEM_PHYS,
-		       CFG_PCI_MEM_SIZE,
+		       CONFIG_SYS_PCI_MEM_BASE,
+		       CONFIG_SYS_PCI_MEM_PHYS,
+		       CONFIG_SYS_PCI_MEM_SIZE,
 		       PCI_REGION_MEM|PCI_REGION_PREFETCH);
 
 	/* PCI memory space */
 	pci_set_region(hose->regions + 1,
-		       CFG_PCI_MMIO_BASE,
-		       CFG_PCI_MMIO_PHYS,
-		       CFG_PCI_MMIO_SIZE,
+		       CONFIG_SYS_PCI_MMIO_BASE,
+		       CONFIG_SYS_PCI_MMIO_PHYS,
+		       CONFIG_SYS_PCI_MMIO_SIZE,
 		       PCI_REGION_MEM);
 
 	/* PCI IO space */
 	pci_set_region(hose->regions + 2,
-		       CFG_PCI_IO_BASE,
-		       CFG_PCI_IO_PHYS,
-		       CFG_PCI_IO_SIZE,
+		       CONFIG_SYS_PCI_IO_BASE,
+		       CONFIG_SYS_PCI_IO_PHYS,
+		       CONFIG_SYS_PCI_IO_SIZE,
 		       PCI_REGION_IO);
 
 	/* System memory space */
@@ -158,8 +158,8 @@ pci_init_board(void)
 	hose->region_count = 4;
 
 	pci_setup_indirect(hose,
-			   (CFG_IMMR + 0x8300),
-			   (CFG_IMMR + 0x8304));
+			   (CONFIG_SYS_IMMR + 0x8300),
+			   (CONFIG_SYS_IMMR + 0x8304));
 
 	pci_register_hose(hose);
 

board/ads5121/u-boot.lds

@@ -115,6 +115,7 @@ SECTIONS
    *(.dynbss)
    *(.bss)
    *(COMMON)
+   . = ALIGN(4);
   }
   _end = . ;
   PROVIDE (end = .);

board/afeb9260/Makefile

@@ -0,0 +1,56 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian.pop@leadtechdesign.com>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS-y	+= afeb9260.o
+COBJS-y	+= partition.o
+COBJS-$(CONFIG_CMD_NAND) += nand.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

board/afeb9260/afeb9260.c

@@ -0,0 +1,243 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ * (C) Copyright 2008 Sergey Lapin <slapin@ossfans.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/at91sam9260.h>
+#include <asm/arch/at91sam9260_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/io.h>
+#include <asm/arch/hardware.h>
+#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
+#include <netdev.h>
+#include <net.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+static void afeb9260_serial_hw_init(void)
+{
+#ifdef CONFIG_USART0
+	at91_set_A_periph(AT91_PIN_PB4, 1);		/* TXD0 */
+	at91_set_A_periph(AT91_PIN_PB5, 0);		/* RXD0 */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US0);
+#endif
+
+#ifdef CONFIG_USART1
+	at91_set_A_periph(AT91_PIN_PB6, 1);		/* TXD1 */
+	at91_set_A_periph(AT91_PIN_PB7, 0);		/* RXD1 */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US1);
+#endif
+
+#ifdef CONFIG_USART2
+	at91_set_A_periph(AT91_PIN_PB8, 1);		/* TXD2 */
+	at91_set_A_periph(AT91_PIN_PB9, 0);		/* RXD2 */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US2);
+#endif
+
+#ifdef CONFIG_USART3	/* DBGU */
+	at91_set_A_periph(AT91_PIN_PB14, 0);		/* DRXD */
+	at91_set_A_periph(AT91_PIN_PB15, 1);		/* DTXD */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
+#endif
+}
+
+static void afeb9260_nand_hw_init(void)
+{
+	unsigned long csa;
+
+	/* Enable CS3 */
+	csa = at91_sys_read(AT91_MATRIX_EBICSA);
+	at91_sys_write(AT91_MATRIX_EBICSA,
+		       csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+	at91_sys_write(AT91_SMC_SETUP(3),
+		       AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) |
+		       AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
+	at91_sys_write(AT91_SMC_PULSE(3),
+		       AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
+		       AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
+	at91_sys_write(AT91_SMC_CYCLE(3),
+		       AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
+	at91_sys_write(AT91_SMC_MODE(3),
+		       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+		       AT91_SMC_EXNWMODE_DISABLE |
+		       AT91_SMC_DBW_8 |
+		       AT91_SMC_TDF_(2));
+
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC);
+
+	/* Configure RDY/BSY */
+	at91_set_gpio_input(AT91_PIN_PC13, 1);
+
+	/* Enable NandFlash */
+	at91_set_gpio_output(AT91_PIN_PC14, 1);
+}
+
+static void afeb9260_spi_hw_init(void)
+{
+	at91_set_A_periph(AT91_PIN_PA3, 0);	/* SPI0_NPCS0 */
+	at91_set_B_periph(AT91_PIN_PC11, 0);	/* SPI0_NPCS1 */
+
+	at91_set_A_periph(AT91_PIN_PA0, 0);	/* SPI0_MISO */
+	at91_set_A_periph(AT91_PIN_PA1, 0);	/* SPI0_MOSI */
+	at91_set_A_periph(AT91_PIN_PA2, 0);	/* SPI0_SPCK */
+
+	/* Enable clock */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_SPI0);
+}
+
+#ifdef CONFIG_MACB
+static void afeb9260_macb_hw_init(void)
+{
+	/* Enable clock */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC);
+
+	/*
+	 * Disable pull-up on:
+	 *	RXDV (PA17) => PHY normal mode (not Test mode)
+	 *	ERX0 (PA14) => PHY ADDR0
+	 *	ERX1 (PA15) => PHY ADDR1
+	 *	ERX2 (PA25) => PHY ADDR2
+	 *	ERX3 (PA26) => PHY ADDR3
+	 *	ECRS (PA28) => PHY ADDR4  => PHYADDR = 0x0
+	 *
+	 * PHY has internal pull-down
+	 */
+	writel(pin_to_mask(AT91_PIN_PA14) |
+	       pin_to_mask(AT91_PIN_PA15) |
+	       pin_to_mask(AT91_PIN_PA17) |
+	       pin_to_mask(AT91_PIN_PA25) |
+	       pin_to_mask(AT91_PIN_PA26) |
+	       pin_to_mask(AT91_PIN_PA28),
+	       pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
+
+	/* Need to reset PHY -> 500ms reset */
+	at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
+				     AT91_RSTC_ERSTL | (0x0D << 8) |
+				     AT91_RSTC_URSTEN);
+
+	at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
+
+	/* Wait for end hardware reset */
+	while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
+
+	/* Restore NRST value */
+	at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
+				     AT91_RSTC_ERSTL | (0x0 << 8) |
+				     AT91_RSTC_URSTEN);
+
+	/* Re-enable pull-up */
+	writel(pin_to_mask(AT91_PIN_PA14) |
+	       pin_to_mask(AT91_PIN_PA15) |
+	       pin_to_mask(AT91_PIN_PA17) |
+	       pin_to_mask(AT91_PIN_PA25) |
+	       pin_to_mask(AT91_PIN_PA26) |
+	       pin_to_mask(AT91_PIN_PA28),
+	       pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
+
+	at91_set_A_periph(AT91_PIN_PA19, 0);	/* ETXCK_EREFCK */
+	at91_set_A_periph(AT91_PIN_PA17, 0);	/* ERXDV */
+	at91_set_A_periph(AT91_PIN_PA14, 0);	/* ERX0 */
+	at91_set_A_periph(AT91_PIN_PA15, 0);	/* ERX1 */
+	at91_set_A_periph(AT91_PIN_PA18, 0);	/* ERXER */
+	at91_set_A_periph(AT91_PIN_PA16, 0);	/* ETXEN */
+	at91_set_A_periph(AT91_PIN_PA12, 0);	/* ETX0 */
+	at91_set_A_periph(AT91_PIN_PA13, 0);	/* ETX1 */
+	at91_set_A_periph(AT91_PIN_PA21, 0);	/* EMDIO */
+	at91_set_A_periph(AT91_PIN_PA20, 0);	/* EMDC */
+
+#ifndef CONFIG_RMII
+	at91_set_B_periph(AT91_PIN_PA28, 0);	/* ECRS */
+	at91_set_B_periph(AT91_PIN_PA29, 0);	/* ECOL */
+	at91_set_B_periph(AT91_PIN_PA25, 0);	/* ERX2 */
+	at91_set_B_periph(AT91_PIN_PA26, 0);	/* ERX3 */
+	at91_set_B_periph(AT91_PIN_PA27, 0);	/* ERXCK */
+	at91_set_B_periph(AT91_PIN_PA10, 0);	/* ETX2 */
+	at91_set_B_periph(AT91_PIN_PA11, 0);	/* ETX3 */
+	at91_set_B_periph(AT91_PIN_PA22, 0);	/* ETXER */
+#endif
+
+}
+#endif
+
+int board_init(void)
+{
+	/* Enable Ctrlc */
+	console_init_f();
+
+	/* arch number of AT91SAM9260EK-Board */
+	gd->bd->bi_arch_number = MACH_TYPE_AFEB9260;
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	afeb9260_serial_hw_init();
+#ifdef CONFIG_CMD_NAND
+	afeb9260_nand_hw_init();
+#endif
+	afeb9260_spi_hw_init();
+#ifdef CONFIG_MACB
+	afeb9260_macb_hw_init();
+#endif
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+	return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+#ifdef CONFIG_MACB
+	/*
+	 * Initialize ethernet HW addr prior to starting Linux,
+	 * needed for nfsroot
+	 */
+	eth_init(gd->bd);
+#endif
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_MACB
+	rc = macb_eth_initialize(0, (void *)AT91SAM9260_BASE_EMAC, 0x00);
+#endif
+	return rc;
+}

board/afeb9260/config.mk

@@ -0,0 +1 @@
+TEXT_BASE = 0x21f00000

board/afeb9260/nand.c

@@ -0,0 +1,78 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/at91sam9260.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/at91_pio.h>
+
+#include <nand.h>
+
+/*
+ *	hardware specific access to control-lines
+ */
+#define	MASK_ALE	(1 << 21)	/* our ALE is AD21 */
+#define	MASK_CLE	(1 << 22)	/* our CLE is AD22 */
+
+static void at91sam9260ek_nand_hwcontrol(struct mtd_info *mtd,
+					 int cmd, unsigned int ctrl)
+{
+	struct nand_chip *this = mtd->priv;
+
+	if (ctrl & NAND_CTRL_CHANGE) {
+		ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
+		IO_ADDR_W &= ~(MASK_ALE | MASK_CLE);
+
+		if (ctrl & NAND_CLE)
+			IO_ADDR_W |= MASK_CLE;
+		if (ctrl & NAND_ALE)
+			IO_ADDR_W |= MASK_ALE;
+
+		at91_set_gpio_value(AT91_PIN_PC14, !(ctrl & NAND_NCE));
+		this->IO_ADDR_W = (void *) IO_ADDR_W;
+	}
+
+	if (cmd != NAND_CMD_NONE)
+		writeb(cmd, this->IO_ADDR_W);
+}
+
+static int at91sam9260ek_nand_ready(struct mtd_info *mtd)
+{
+	return at91_get_gpio_value(AT91_PIN_PC13);
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+	nand->ecc.mode = NAND_ECC_SOFT;
+#ifdef CONFIG_SYS_NAND_DBW_16
+	nand->options = NAND_BUSWIDTH_16;
+#endif
+	nand->cmd_ctrl = at91sam9260ek_nand_hwcontrol;
+	nand->dev_ready = at91sam9260ek_nand_ready;
+	nand->chip_delay = 20;
+
+	return 0;
+}

board/afeb9260/partition.c

@@ -0,0 +1,36 @@
+/*
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#include <common.h>
+#include <config.h>
+#include <asm/hardware.h>
+#include <dataflash.h>
+
+AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
+
+struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
+	{CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0},	/* Logical adress, CS */
+	{CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1, 1}
+};
+
+/*define the area offsets*/
+dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
+	{0x00000000, 0x000041FF, FLAG_PROTECT_CLEAR, 0, "Bootstrap"},
+	{0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
+	{0x00008400, 0x00041FFF, FLAG_PROTECT_CLEAR, 0, "U-Boot"},
+};

board/alaska/alaska.c

@@ -32,48 +32,48 @@ void setupBat (ulong size)
 	int blocksize = 0;
 
 	/* Flash 0 */
-#if defined (CFG_AMD_BOOT)
-	batu = CFG_FLASH0_BASE | (BL_512K << 2) | BPP_RW | BPP_RX;
+#if defined (CONFIG_SYS_AMD_BOOT)
+	batu = CONFIG_SYS_FLASH0_BASE | (BL_512K << 2) | BPP_RW | BPP_RX;
 #else
-	batu = CFG_FLASH0_BASE | (BL_16M << 2) | BPP_RW | BPP_RX;
+	batu = CONFIG_SYS_FLASH0_BASE | (BL_16M << 2) | BPP_RW | BPP_RX;
 #endif
-	batl = CFG_FLASH0_BASE | 0x22;
+	batl = CONFIG_SYS_FLASH0_BASE | 0x22;
 	write_bat (IBAT0, batu, batl);
 	write_bat (DBAT0, batu, batl);
 
 	/* Flash 1 */
-#if defined (CFG_AMD_BOOT)
-	batu = CFG_FLASH1_BASE | (BL_16M << 2) | BPP_RW | BPP_RX;
+#if defined (CONFIG_SYS_AMD_BOOT)
+	batu = CONFIG_SYS_FLASH1_BASE | (BL_16M << 2) | BPP_RW | BPP_RX;
 #else
-	batu = CFG_FLASH1_BASE | (BL_512K << 2) | BPP_RW | BPP_RX;
+	batu = CONFIG_SYS_FLASH1_BASE | (BL_512K << 2) | BPP_RW | BPP_RX;
 #endif
-	batl = CFG_FLASH1_BASE | 0x22;
+	batl = CONFIG_SYS_FLASH1_BASE | 0x22;
 	write_bat (IBAT1, batu, batl);
 	write_bat (DBAT1, batu, batl);
 
 	/* CPLD */
-	batu = CFG_CPLD_BASE | (BL_512K << 2) | BPP_RW | BPP_RX;
-	batl = CFG_CPLD_BASE | 0x22;
+	batu = CONFIG_SYS_CPLD_BASE | (BL_512K << 2) | BPP_RW | BPP_RX;
+	batl = CONFIG_SYS_CPLD_BASE | 0x22;
 	write_bat (IBAT2, 0, 0);
 	write_bat (DBAT2, batu, batl);
 
 	/* FPGA */
-	batu = CFG_FPGA_BASE | (BL_512K << 2) | BPP_RW | BPP_RX;
-	batl = CFG_FPGA_BASE | 0x22;
+	batu = CONFIG_SYS_FPGA_BASE | (BL_512K << 2) | BPP_RW | BPP_RX;
+	batl = CONFIG_SYS_FPGA_BASE | 0x22;
 	write_bat (IBAT3, 0, 0);
 	write_bat (DBAT3, batu, batl);
 
 	/* MBAR - Data only */
-	batu = CFG_MBAR | BPP_RW | BPP_RX;
-	batl = CFG_MBAR | 0x22;
+	batu = CONFIG_SYS_MBAR | BPP_RW | BPP_RX;
+	batl = CONFIG_SYS_MBAR | 0x22;
 	mtspr (IBAT4L, 0);
 	mtspr (IBAT4U, 0);
 	mtspr (DBAT4L, batl);
 	mtspr (DBAT4U, batu);
 
 	/* MBAR - SRAM */
-	batu = CFG_SRAM_BASE | BPP_RW | BPP_RX;
-	batl = CFG_SRAM_BASE | 0x42;
+	batu = CONFIG_SYS_SRAM_BASE | BPP_RW | BPP_RX;
+	batl = CONFIG_SYS_SRAM_BASE | 0x42;
 	mtspr (IBAT5L, batl);
 	mtspr (IBAT5U, batu);
 	mtspr (DBAT5L, batl);
@@ -93,8 +93,8 @@ void setupBat (ulong size)
 		blocksize = BL_256M << 2;
 
 	/* Memory */
-	batu = CFG_SDRAM_BASE | blocksize | BPP_RW | BPP_RX;
-	batl = CFG_SDRAM_BASE | 0x42;
+	batu = CONFIG_SYS_SDRAM_BASE | blocksize | BPP_RW | BPP_RX;
+	batl = CONFIG_SYS_SDRAM_BASE | 0x42;
 	mtspr (IBAT6L, batl);
 	mtspr (IBAT6U, batu);
 	mtspr (DBAT6L, batl);
@@ -120,9 +120,9 @@ void setupBat (ulong size)
 		else if (size <= 0x10000000)	/* 256MB */
 			blocksize = BL_256M << 2;
 
-		batu = (CFG_SDRAM_BASE +
+		batu = (CONFIG_SYS_SDRAM_BASE +
 			0x10000000) | blocksize | BPP_RW | BPP_RX;
-		batl = (CFG_SDRAM_BASE + 0x10000000) | 0x42;
+		batl = (CONFIG_SYS_SDRAM_BASE + 0x10000000) | 0x42;
 	}
 
 	mtspr (IBAT7L, batl);