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@@ -60,7 +60,7 @@ void pciauto_config_init(struct pci_controller *hose);
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#define CONFIG_SYS_PCI64_MEMORY_BUS (64ull*1024*1024*1024)
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#define CONFIG_SYS_PCI64_MEMORY_BUS (64ull*1024*1024*1024)
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#endif
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#endif
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-int fsl_pci_setup_inbound_windows(struct pci_region *r)
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+static int fsl_pci_setup_inbound_windows(struct pci_region *r)
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{
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{
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struct pci_region *rgn_base = r;
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struct pci_region *rgn_base = r;
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u64 sz = min((u64)gd->ram_size, (1ull << 32) - 1);
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u64 sz = min((u64)gd->ram_size, (1ull << 32) - 1);
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@@ -145,6 +145,7 @@ void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data)
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int bridge;
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int bridge;
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int inbound = 0;
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int inbound = 0;
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volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)cfg_addr;
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volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)cfg_addr;
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+ struct pci_region *reg = hose->regions + hose->region_count;
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pci_dev_t dev = PCI_BDF(busno,0,0);
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pci_dev_t dev = PCI_BDF(busno,0,0);
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/* Initialize ATMU registers based on hose regions and flags */
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/* Initialize ATMU registers based on hose regions and flags */
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@@ -157,6 +158,11 @@ void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data)
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pci_setup_indirect(hose, cfg_addr, cfg_data);
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pci_setup_indirect(hose, cfg_addr, cfg_data);
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+ /* inbound */
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+ reg += fsl_pci_setup_inbound_windows(reg);
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+
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+ hose->region_count = reg - hose->regions;
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+
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for (r=0; r<hose->region_count; r++) {
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for (r=0; r<hose->region_count; r++) {
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u32 sz = (__ilog2_u64((u64)hose->regions[r].size) - 1);
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u32 sz = (__ilog2_u64((u64)hose->regions[r].size) - 1);
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if (hose->regions[r].flags & PCI_REGION_SYS_MEMORY) { /* inbound */
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if (hose->regions[r].flags & PCI_REGION_SYS_MEMORY) { /* inbound */
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