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@@ -94,13 +94,23 @@ static inline void board_cpld_write(int offset, int data)
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out_8((void *)(CONFIG_SYS_CPLD_ADDR), offset);
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out_8((void *)(CONFIG_SYS_CPLD_DATA), data);
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}
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+#else
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+static int pvr_460ex(void)
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+{
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+ u32 pvr = get_pvr();
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+
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+ if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA) ||
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+ (pvr == PVR_460EX_RB))
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+ return 1;
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+
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+ return 0;
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+}
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#endif /* defined(CONFIG_ARCHES) */
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int board_early_init_f(void)
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{
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#if !defined(CONFIG_ARCHES)
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u32 sdr0_cust0;
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- u32 pvr = get_pvr();
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#endif
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/*
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@@ -175,7 +185,7 @@ int board_early_init_f(void)
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mtdcr(AHB_TOP, 0x8000004B);
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mtdcr(AHB_BOT, 0x8000004B);
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- if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA)) {
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+ if (pvr_460ex()) {
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/*
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* Configure USB-STP pins as alternate and not GPIO
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* It seems to be neccessary to configure the STP pins as GPIO
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@@ -234,17 +244,16 @@ int get_cpu_num(void)
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int checkboard(void)
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{
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char *s = getenv("serial#");
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- u32 pvr = get_pvr();
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- if ((pvr == PVR_460GT_RA) || (pvr == PVR_460GT_SE_RA)) {
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- printf("Board: Glacier - AMCC PPC460GT Evaluation Board");
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- gd->board_type = BOARD_GLACIER;
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- } else {
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+ if (pvr_460ex()) {
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printf("Board: Canyonlands - AMCC PPC460EX Evaluation Board");
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if (in_8((void *)(CONFIG_SYS_BCSR_BASE + 3)) & CONFIG_SYS_BCSR3_PCIE)
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gd->board_type = BOARD_CANYONLANDS_PCIE;
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else
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gd->board_type = BOARD_CANYONLANDS_SATA;
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+ } else {
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+ printf("Board: Glacier - AMCC PPC460GT Evaluation Board");
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+ gd->board_type = BOARD_GLACIER;
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}
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switch (gd->board_type) {
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@@ -498,7 +507,6 @@ int misc_init_r(void)
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{
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u32 sdr0_srst1 = 0;
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u32 eth_cfg;
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- u32 pvr = get_pvr();
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u8 val;
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/*
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@@ -513,7 +521,7 @@ int misc_init_r(void)
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/* Set the for 2 RGMII mode */
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/* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
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eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL;
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- if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA))
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+ if (pvr_460ex())
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eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
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else
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eth_cfg &= ~SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
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