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@@ -588,98 +588,8 @@ u32 ddr_clktr(u32 default_val) {
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return default_val;
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}
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-/*************************************************************************
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- * pci_pre_init
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- *
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- * This routine is called just prior to registering the hose and gives
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- * the board the opportunity to check things. Returning a value of zero
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- * indicates that things are bad & PCI initialization should be aborted.
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- *
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- * Different boards may wish to customize the pci controller structure
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- * (add regions, override default access routines, etc) or perform
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- * certain pre-initialization actions.
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- *
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- ************************************************************************/
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#if defined(CONFIG_PCI)
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-int pci_pre_init(struct pci_controller * hose )
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-{
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- unsigned long strap;
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-
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- /*-------------------------------------------------------------------+
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- * The yucca board is always configured as the host & requires the
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- * PCI arbiter to be enabled.
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- *-------------------------------------------------------------------*/
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- mfsdr(SDR0_SDSTP1, strap);
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- if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ) {
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- printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
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- return 0;
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- }
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-
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- return 1;
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-}
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-#endif /* defined(CONFIG_PCI) */
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-
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-/*************************************************************************
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- * pci_target_init
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- *
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- * The bootstrap configuration provides default settings for the pci
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- * inbound map (PIM). But the bootstrap config choices are limited and
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- * may not be sufficient for a given board.
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- *
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- ************************************************************************/
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-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
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-void pci_target_init(struct pci_controller * hose )
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-{
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- /*-------------------------------------------------------------------+
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- * Disable everything
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- *-------------------------------------------------------------------*/
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- out32r( PCIL0_PIM0SA, 0 ); /* disable */
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- out32r( PCIL0_PIM1SA, 0 ); /* disable */
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- out32r( PCIL0_PIM2SA, 0 ); /* disable */
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- out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */
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-
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- /*-------------------------------------------------------------------+
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- * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
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- * strapping options to not support sizes such as 128/256 MB.
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- *-------------------------------------------------------------------*/
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- out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
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- out32r( PCIL0_PIM0LAH, 0 );
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- out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 );
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- out32r( PCIL0_BAR0, 0 );
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-
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- /*-------------------------------------------------------------------+
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- * Program the board's subsystem id/vendor id
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- *-------------------------------------------------------------------*/
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- out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
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- out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
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-
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- out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY );
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-}
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-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
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-
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-#if defined(CONFIG_PCI)
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-/*************************************************************************
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- * is_pci_host
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- *
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- * This routine is called to determine if a pci scan should be
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- * performed. With various hardware environments (especially cPCI and
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- * PPMC) it's insufficient to depend on the state of the arbiter enable
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- * bit in the strap register, or generic host/adapter assumptions.
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- *
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- * Rather than hard-code a bad assumption in the general 440 code, the
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- * 440 pci code requires the board to decide at runtime.
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- *
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- * Return 0 for adapter mode, non-zero for host (monarch) mode.
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- *
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- *
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- ************************************************************************/
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-int is_pci_host(struct pci_controller *hose)
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-{
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- /* The yucca board is always configured as host. */
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- return 1;
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-}
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-
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-static int yucca_pcie_card_present(int port)
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+int board_pcie_card_present(int port)
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{
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u16 reg;
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@@ -696,186 +606,55 @@ static int yucca_pcie_card_present(int port)
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}
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}
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-/*
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- * For the given slot, set rootpoint mode, send power to the slot,
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- * turn on the green LED and turn off the yellow LED, enable the clock
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- * and turn off reset.
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- */
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-void yucca_setup_pcie_fpga_rootpoint(int port)
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-{
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- u16 power, clock, green_led, yellow_led, reset_off, rootpoint, endpoint;
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-
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- switch(port) {
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- case 0:
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- rootpoint = FPGA_REG1C_PE0_ROOTPOINT;
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- endpoint = 0;
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- power = FPGA_REG1A_PE0_PWRON;
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- green_led = FPGA_REG1A_PE0_GLED;
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- clock = FPGA_REG1A_PE0_REFCLK_ENABLE;
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- yellow_led = FPGA_REG1A_PE0_YLED;
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- reset_off = FPGA_REG1C_PE0_PERST;
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- break;
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- case 1:
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- rootpoint = 0;
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- endpoint = FPGA_REG1C_PE1_ENDPOINT;
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- power = FPGA_REG1A_PE1_PWRON;
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- green_led = FPGA_REG1A_PE1_GLED;
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- clock = FPGA_REG1A_PE1_REFCLK_ENABLE;
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- yellow_led = FPGA_REG1A_PE1_YLED;
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- reset_off = FPGA_REG1C_PE1_PERST;
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- break;
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- case 2:
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- rootpoint = 0;
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- endpoint = FPGA_REG1C_PE2_ENDPOINT;
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- power = FPGA_REG1A_PE2_PWRON;
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- green_led = FPGA_REG1A_PE2_GLED;
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- clock = FPGA_REG1A_PE2_REFCLK_ENABLE;
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- yellow_led = FPGA_REG1A_PE2_YLED;
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- reset_off = FPGA_REG1C_PE2_PERST;
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- break;
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-
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- default:
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- return;
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- }
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-
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- out_be16((u16 *)FPGA_REG1A,
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- ~(power | clock | green_led) &
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- (yellow_led | in_be16((u16 *)FPGA_REG1A)));
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-
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- out_be16((u16 *)FPGA_REG1C,
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- ~(endpoint | reset_off) &
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- (rootpoint | in_be16((u16 *)FPGA_REG1C)));
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- /*
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- * Leave device in reset for a while after powering on the
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- * slot to give it a chance to initialize.
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- */
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- udelay(250 * 1000);
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-
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- out_be16((u16 *)FPGA_REG1C, reset_off | in_be16((u16 *)FPGA_REG1C));
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-}
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/*
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* For the given slot, set endpoint mode, send power to the slot,
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- * turn on the green LED and turn off the yellow LED, enable the clock
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- * .In end point mode reset bit is read only.
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+ * turn on the green LED and turn off the yellow LED, enable the
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+ * clock. In end point mode reset bit is read only.
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*/
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-void yucca_setup_pcie_fpga_endpoint(int port)
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+void board_pcie_setup_port(int port, int rootpoint)
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{
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- u16 power, clock, green_led, yellow_led, reset_off, rootpoint, endpoint;
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+ u16 power, clock, green_led, yellow_led,
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+ reset_off, rp, ep;
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- switch(port) {
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+ switch (port) {
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case 0:
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- rootpoint = FPGA_REG1C_PE0_ROOTPOINT;
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- endpoint = 0;
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- power = FPGA_REG1A_PE0_PWRON;
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- green_led = FPGA_REG1A_PE0_GLED;
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- clock = FPGA_REG1A_PE0_REFCLK_ENABLE;
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- yellow_led = FPGA_REG1A_PE0_YLED;
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- reset_off = FPGA_REG1C_PE0_PERST;
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+ rp = FPGA_REG1C_PE0_ROOTPOINT;
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+ ep = 0;
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break;
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case 1:
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- rootpoint = 0;
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- endpoint = FPGA_REG1C_PE1_ENDPOINT;
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- power = FPGA_REG1A_PE1_PWRON;
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- green_led = FPGA_REG1A_PE1_GLED;
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- clock = FPGA_REG1A_PE1_REFCLK_ENABLE;
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- yellow_led = FPGA_REG1A_PE1_YLED;
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- reset_off = FPGA_REG1C_PE1_PERST;
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+ rp = 0;
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+ ep = FPGA_REG1C_PE1_ENDPOINT;
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break;
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case 2:
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- rootpoint = 0;
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- endpoint = FPGA_REG1C_PE2_ENDPOINT;
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- power = FPGA_REG1A_PE2_PWRON;
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- green_led = FPGA_REG1A_PE2_GLED;
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- clock = FPGA_REG1A_PE2_REFCLK_ENABLE;
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- yellow_led = FPGA_REG1A_PE2_YLED;
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- reset_off = FPGA_REG1C_PE2_PERST;
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+ rp = 0;
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+ ep = FPGA_REG1C_PE2_ENDPOINT;
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break;
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default:
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return;
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}
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- out_be16((u16 *)FPGA_REG1A,
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- ~(power | clock | green_led) &
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- (yellow_led | in_be16((u16 *)FPGA_REG1A)));
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-
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- out_be16((u16 *)FPGA_REG1C,
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- ~(rootpoint | reset_off) &
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- (endpoint | in_be16((u16 *)FPGA_REG1C)));
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-}
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+ power = FPGA_REG1A_PWRON_ENCODE(port);
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+ green_led = FPGA_REG1A_GLED_ENCODE(port);
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+ clock = FPGA_REG1A_REFCLK_ENCODE(port);
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+ yellow_led = FPGA_REG1A_YLED_ENCODE(port);
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+ reset_off = FPGA_REG1C_PERST_ENCODE(port);
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-static struct pci_controller pcie_hose[3] = {{0},{0},{0}};
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+ out_be16((u16 *)FPGA_REG1A, ~(power | clock | green_led) &
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+ (yellow_led | in_be16((u16 *)FPGA_REG1A)));
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-void pcie_setup_hoses(int busno)
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-{
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- struct pci_controller *hose;
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- int i, bus;
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- int ret = 0;
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- char *env;
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- unsigned int delay;
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+ out_be16((u16 *)FPGA_REG1C, ~(ep | reset_off) &
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+ (rp | in_be16((u16 *)FPGA_REG1C)));
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- /*
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- * assume we're called after the PCIX hose is initialized, which takes
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- * bus ID 0 and therefore start numbering PCIe's from 1.
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- */
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- bus = busno;
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- for (i = 0; i <= 2; i++) {
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- /* Check for yucca card presence */
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- if (!yucca_pcie_card_present(i))
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- continue;
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-
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- if (is_end_point(i)) {
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- yucca_setup_pcie_fpga_endpoint(i);
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- ret = ppc4xx_init_pcie_endport(i);
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- } else {
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- yucca_setup_pcie_fpga_rootpoint(i);
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- ret = ppc4xx_init_pcie_rootport(i);
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- }
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- if (ret == -ENODEV)
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- continue;
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- if (ret) {
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- printf("PCIE%d: initialization as %s failed\n", i,
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- is_end_point(i) ? "endpoint" : "root-complex");
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- continue;
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- }
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-
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- hose = &pcie_hose[i];
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- hose->first_busno = bus;
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- hose->last_busno = bus;
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- hose->current_busno = bus;
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-
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- /* setup mem resource */
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- pci_set_region(hose->regions + 0,
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- CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
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- CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
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- CONFIG_SYS_PCIE_MEMSIZE,
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- PCI_REGION_MEM);
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- hose->region_count = 1;
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- pci_register_hose(hose);
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-
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- if (is_end_point(i)) {
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- ppc4xx_setup_pcie_endpoint(hose, i);
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- /*
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- * Reson for no scanning is endpoint can not generate
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- * upstream configuration accesses.
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- */
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- } else {
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- ppc4xx_setup_pcie_rootpoint(hose, i);
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- env = getenv("pciscandelay");
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- if (env != NULL) {
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- delay = simple_strtoul(env, NULL, 10);
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- if (delay > 5)
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- printf("Warning, expect noticable delay before "
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- "PCIe scan due to 'pciscandelay' value!\n");
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- mdelay(delay * 1000);
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- }
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+ if (rootpoint) {
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+ /*
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+ * Leave device in reset for a while after powering on the
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+ * slot to give it a chance to initialize.
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+ */
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+ udelay(250 * 1000);
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- /*
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- * Config access can only go down stream
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- */
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- hose->last_busno = pci_hose_scan(hose);
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- bus = hose->last_busno + 1;
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- }
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+ out_be16((u16 *)FPGA_REG1C,
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+ reset_off | in_be16((u16 *)FPGA_REG1C));
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}
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}
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#endif /* defined(CONFIG_PCI) */
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@@ -929,17 +708,6 @@ void fpga_init(void)
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return;
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}
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-#ifdef CONFIG_POST
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-/*
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- * Returns 1 if keys pressed to start the power-on long-running tests
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- * Called from board_init_f().
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- */
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-int post_hotkeys_pressed(void)
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-{
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- return (ctrlc());
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-}
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-#endif
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-
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/*---------------------------------------------------------------------------+
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| onboard_pci_arbiter_selected => from EPLD
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+---------------------------------------------------------------------------*/
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