Merge branch 'master' of rsync://rsync.denx.de/git/u-boot

CHANGELOG

@@ -2,6 +2,114 @@
 Changes since U-Boot 1.1.4:
 ======================================================================
 
+* Update for NC650 board:
+  - Support rev1 and rev2 hardware
+  - adapt to new NAND layer
+  - add CP850 configuration based on NC650
+
+* MPC5200: enable snooping of DMA transactions on XLB even if no PCI
+  is configured; othrwise DMA accesses aren't cache coherent which
+  causes for example USB to fail.
+
+* Some code cleanup
+
+* Fix dbau1x00 boards broken by dbau1550 patch
+  PLL:s were not set for boards other than 1550.
+  Flash CFI caused card to hang due to undefined CFG_FLASH_BANKS_LIST.
+  Default boot is now bootp for cards other than 1550.
+  Patch by Thomas Lange, 10 Aug 2005
+
+* Fixes common/cmd_flash.c:
+  - fix some compiler/parser error, if using m68k tool chain
+  - optical fix for protect on/off all messages, if using more
+    then one bank
+  Patch by Jens Scharsig, 28 Jul 2005
+
+* Fix Quad UART mapping on MCC200 board due to new HW revision
+
+* Fix JFFS2 support for legacy NAND driver.
+
+* Remove dependencies between DoC code and old legacy NAND driver.
+
+* Fix PM828_PCI target, for which PCI was *not* configured in.
+
+* Fix Lite5200B support: initialize SDelay register
+  See Freescale's AN3221 "MPC5200B SDRAM Initialization and
+  Configuration", 3.3.1 SDelay--MBAR + 0x0190
+
+* Changes/fixes for drivers/cfi_flash.c:
+
+  - Add Intel legacy lock/unlock support to common CFI driver
+
+    On some Intel flash's (e.g. Intel J3) legacy unlocking is
+    supported, meaning that unlocking of one sector will unlock
+    all sectors of this bank. Using this feature, unlocking
+    of all sectors upon startup (via env var "unlock=yes") will
+    get much faster.
+
+  - Fixed problem with multiple reads of envronment variable
+    "unlock" as pointed out by Reinhard Arlt & Anders Larsen.
+
+  - Removed unwanted linefeeds from "protect" command when
+    CFG_FLASH_PROTECTION is enabled.
+
+  - Changed p3p400 board to use CFG_FLASH_PROTECTION
+
+  Patch by Stefan Roese, 01 Apr 2006
+
+* Changes/fixes for drivers/cfi_flash.c:
+  - Correctly handle the cases where CFG_HZ != 1000 (several
+    XScale-based boards)
+  - Fix the timeout calculation of buffered writes (off by a
+    factor of 1000)
+  Patch by Anders Larsen, 31 Mar 2006
+
+* Updates to common PPC4xx onboard (DDR)SDRAM init code (405 and 440)
+
+  405 SDRAM: - The SDRAM parameters can now be defined in the board
+	       config file and the 405 SDRAM controller values will
+	       be calculated upon bootup (see PPChameleonEVB).
+	       When those settings are not defined in the board
+	       config file, the register setup will be as it is now,
+	       so this implementation should not break any current
+	       design using this code.
+
+	       Thanks to Andrea Marson from DAVE for this patch.
+
+  440 DDR:   - Added function sdram_tr1_set to auto calculate the
+	       TR1 value for the DDR.
+	     - Added ECC support (see p3p440).
+
+  Patch by Stefan Roese, 17 Mar 2006
+
+* Fix CONFIG_SKIP_LOWLEVEL_INIT dependency in cpu/arm920t/start.S
+  Patch by Peter Menzebach, 13 Oct 2005 [DNX#2006040142000473]
+
+* Add support for ymodem protocol download
+  Patch by Stefano Babic, 29 Mar 2006
+
+* Memory Map Update for Delta board: U-Boot is at 0x80000000-0x84000000
+  Merge from Markus Klotzbücher's repo, 01 Apr 2006
+
+* GCC-4.x fixes: clean up global data pointer initialization for all
+  boards
+
+* Update for Delta board:
+  - redundant NAND environment
+  - misc Monahans cleanups (remove dead code etc.)
+  - DA9030 Initialization; some minimal changes to PXA I2C driver to
+    make it work with the Monahans.
+  - Make Monahans clock frequency configurable using
+    CFG_MONAHANS_RUN_MODE_OSC_RATIO and
+    CFG_MONAHANS_TURBO_RUN_MODE_RATIO.
+  Merge from Markus Klotzbücher's repo, 25 Mar 2006
+
+* Enable Quad UART om MCC200 board.
+
+* Cleanup MCC200 board configuration; omit non-existent stuff.
+
+* Add support for MPC859/866 Rev. A.0
+
 * Add command for handling DDR ECC registers on MPC8349EE MDS board.
 
 * Fix DDR ECC bit definitions for MPC83xx.
@@ -344,7 +452,7 @@ Changes since U-Boot 1.1.4:
   are removed from the default U-Boot build.
   Enable DEBUG for lib_arm/board.c to enable debug messages.
   New CONFIG_DISPLAY_CPUINFO and CONFIG_DISPLAY_BOARDINFO options.
-  Patch  by Stefan Roese, 24 Jan 2006
+  Patch	 by Stefan Roese, 24 Jan 2006
 
 * Fix various compiler warnings on ppc4xx builds (ELDK 4.0)
   Patch by Stefan Roese, 18 Jan 2006
@@ -490,11 +598,11 @@ Changes for U-Boot 1.1.4:
 
 * Add support for multiple PHYs.
   Tested on the following boards:
-	cmcpu2      (at91rm9200/ether.c)
+	cmcpu2	    (at91rm9200/ether.c)
 	PPChameleon (ppc4xx/4xx_enet.c)
-	yukon       (mpc8220/fec.c)
-	uc100       (mpc8xx/fec.c)
-	tqm834x     (mpc834x/tsec.c) with EEPRO100
+	yukon	    (mpc8220/fec.c)
+	uc100	    (mpc8xx/fec.c)
+	tqm834x	    (mpc834x/tsec.c) with EEPRO100
 	lite5200    (mpc5xxx/fec.c) with EEPRO100 card (drivers/eepro100.c)
   Main changes include:
   common/miiphyutil.c
@@ -1034,18 +1142,18 @@ Changes for U-Boot 1.1.3:
   The first one is to define a single, static partition:
 
   #undef CONFIG_JFFS2_CMDLINE
-  #define CONFIG_JFFS2_DEV               "nor0"
-  #define CONFIG_JFFS2_PART_SIZE         0xFFFFFFFF	/* use whole device */
-  #define CONFIG_JFFS2_PART_SIZE         0x00100000	/* use 1MB */
-  #define CONFIG_JFFS2_PART_OFFSET       0x00000000
+  #define CONFIG_JFFS2_DEV		 "nor0"
+  #define CONFIG_JFFS2_PART_SIZE	 0xFFFFFFFF	/* use whole device */
+  #define CONFIG_JFFS2_PART_SIZE	 0x00100000	/* use 1MB */
+  #define CONFIG_JFFS2_PART_OFFSET	 0x00000000
 
   The second method uses the mtdparts command line option and dynamic
   partitioning:
 
   /* mtdparts command line support */
   #define CONFIG_JFFS2_CMDLINE
-  #define MTDIDS_DEFAULT         "nor1=zuma-1,nor2=zuma-2"
-  #define MTDPARTS_DEFAULT       "mtdparts=zuma-1:-(jffs2),zuma-2:-(user)"
+  #define MTDIDS_DEFAULT	 "nor1=zuma-1,nor2=zuma-2"
+  #define MTDPARTS_DEFAULT	 "mtdparts=zuma-1:-(jffs2),zuma-2:-(user)"
 
   Command line of course produces bigger images, and may be inappropriate
   for some targets, so by default it's off.
@@ -3358,7 +3466,7 @@ Changes for U-Boot 1.0.1:
   Bring ARM memory layout in sync with the documentation:
   stack and malloc-heap are now located _below_ the U-Boot code
 
-* Accelerate booting on TRAB board: read and check  autoupdate  image
+* Accelerate booting on TRAB board: read and check  autoupdate	image
   headers first instead of always reading the whole images.
 
 * Fix type in MPC5XXX code (pointed out by Victor Wren)
@@ -3478,7 +3586,7 @@ Changes for U-Boot 1.0.0:
 * Make 5200 reset command _really_ reset the board, without running
   any other code after it
 
-* Fix errors with flash erase when range spans  across banks
+* Fix errors with flash erase when range spans	across banks
   that are mapped in reverse order
 
 * Fix flash mapping and display on P3G4 board
@@ -3722,7 +3830,7 @@ Changes for U-Boot 0.4.8:
   or 1 x AM29LV652 (two LV065 in one chip = 16 MB);
   Run IPB at 133 Mhz; adjust the MII clock frequency accordingly
 
-* Set BRG_CLK on PM825/826 to 64MHz (VCO_OUT / 4, instead of 16  MHz)
+* Set BRG_CLK on PM825/826 to 64MHz (VCO_OUT / 4, instead of 16	 MHz)
   to allow for more accurate baudrate settings
   (error now 0.7% at 115 kbps, instead of 3.5% before)
 
@@ -4209,7 +4317,7 @@ Changes for U-Boot 0.4.0:
   Update for MPC8266ADS board
 
 * Get (mostly) rid of CFG_MONITOR_LEN definition; compute real length
-  instead CFG_MONITOR_LEN is now only used to determine  _at_compile_
+  instead CFG_MONITOR_LEN is now only used to determine	 _at_compile_
   _time_  (!) if the environment is embedded within the U-Boot image,
   or in a separate flash sector.
 
@@ -4259,7 +4367,7 @@ Changes for U-Boot 0.4.0:
 * Patch by Thomas Schäfer, 28 Apr 2003:
   Fix SPD handling for 256 ECC DIMM on Walnut
 
-* Add support for arbitrary bitmaps for TRAB's  VFD command;
+* Add support for arbitrary bitmaps for TRAB's	VFD command;
   allow to pass boot bitmap addresses in environment variables;
   allow for zero boot delay
 
@@ -4602,7 +4710,7 @@ Changes for U-Boot 0.3.0:
 
 * Add VFD type detection to trab board
 
-* extend drivers/cs8900.c driver to synchronize  ethaddr  environment
+* extend drivers/cs8900.c driver to synchronize	 ethaddr  environment
   variable with value in the EEPROM
 
 * Patch by Stefan Roese, 10 Feb 2003:
@@ -4762,7 +4870,7 @@ Changes for U-Boot 0.2.0:
 * Patch by Pierre Aubert, 05 Nov 2002
   Add support for slave serial Spartan 2 FPGAs
 
-* Fix uninitialized memory (MAC  address)  in  8xx  SCC/FEC  ethernet
+* Fix uninitialized memory (MAC	 address)  in  8xx  SCC/FEC  ethernet
   drivers
 
 * Add support for log buffer which can be passed to Linux kernel's

Makefile

@@ -133,6 +133,8 @@ LIBS += disk/libdisk.a
 LIBS += rtc/librtc.a
 LIBS += dtt/libdtt.a
 LIBS += drivers/libdrivers.a
+LIBS += drivers/nand/libnand.a
+LIBS += drivers/nand_legacy/libnand_legacy.a
 LIBS += drivers/sk98lin/libsk98lin.a
 LIBS += post/libpost.a post/cpu/libcpu.a
 LIBS += common/libcommon.a
@@ -631,8 +633,21 @@ NETTA2_config:		unconfig
 		 }
 	@./mkconfig -a $(call xtract_NETTA2,$@) ppc mpc8xx netta2
 
-NC650_config:	unconfig
-	@./mkconfig $(@:_config=) ppc mpc8xx nc650
+NC650_Rev1_config \
+NC650_Rev2_config \
+CP850_config:	unconfig
+	@ >include/config.h
+	@[ -z "$(findstring CP850,$@)" ] || \
+		 { echo "#define CONFIG_CP850 1" >>include/config.h ; \
+		   echo "#define CONFIG_IDS852_REV2 1" >>include/config.h ; \
+		 }
+	@[ -z "$(findstring Rev1,$@)" ] || \
+		 { echo "#define CONFIG_IDS852_REV1 1" >>include/config.h ; \
+		 }
+	@[ -z "$(findstring Rev2,$@)" ] || \
+		 { echo "#define CONFIG_IDS852_REV2 1" >>include/config.h ; \
+		 }
+	@./mkconfig -a NC650 ppc mpc8xx nc650
 
 NX823_config:		unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx nx823
@@ -1187,7 +1202,7 @@ PM828_config	\
 PM828_PCI_config	\
 PM828_ROMBOOT_config	\
 PM828_ROMBOOT_PCI_config:	unconfig
-	@if [ -z "$(findstring _PCI_,$@)" ] ; then \
+	@if [ "$(findstring _PCI_,$@)" ] ; then \
 		echo "#define CONFIG_PCI"  >>include/config.h ; \
 		echo "... with PCI enabled" ; \
 	else \

README

@@ -246,6 +246,7 @@ The following options need to be configured:
 		CONFIG_SA1110
 		CONFIG_ARM7
 		CONFIG_PXA250
+		CONFIG_CPU_MONAHANS
 
 		MicroBlaze based CPUs:
 		----------------------
@@ -304,13 +305,13 @@ The following options need to be configured:
 		-----------------
 
 		CONFIG_ARMADILLO,	CONFIG_AT91RM9200DK,	CONFIG_CERF250,
-		CONFIG_CSB637,		CONFIG_DNP1110, 	CONFIG_EP7312,
-		CONFIG_H2_OMAP1610,	CONFIG_HHP_CRADLE,	CONFIG_IMPA7,
-		CONFIG_INNOVATOROMAP1510, CONFIG_INNOVATOROMAP1610, CONFIG_KB9202,
-		CONFIG_LART,		CONFIG_LPD7A400,	CONFIG_LUBBOCK,
-		CONFIG_OSK_OMAP5912,	CONFIG_OMAP2420H4,	CONFIG_SHANNON,
-		CONFIG_P2_OMAP730,	CONFIG_SMDK2400,	CONFIG_SMDK2410,
-		CONFIG_TRAB,		CONFIG_VCMA9
+		CONFIG_CSB637,		CONFIG_DELTA,		CONFIG_DNP1110,
+	 	CONFIG_EP7312,		CONFIG_H2_OMAP1610,	CONFIG_HHP_CRADLE,
+		CONFIG_IMPA7,	    CONFIG_INNOVATOROMAP1510,	CONFIG_INNOVATOROMAP1610,
+		CONFIG_KB9202,		CONFIG_LART,		CONFIG_LPD7A400,
+		CONFIG_LUBBOCK,		CONFIG_OSK_OMAP5912,	CONFIG_OMAP2420H4,
+		CONFIG_SHANNON,		CONFIG_P2_OMAP730,	CONFIG_SMDK2400,
+		CONFIG_SMDK2410,	CONFIG_TRAB,		CONFIG_VCMA9
 
 		MicroBlaze based boards:
 		------------------------
@@ -379,6 +380,20 @@ The following options need to be configured:
 		that this requires a (stable) reference clock (32 kHz
 		RTC clock or CFG_8XX_XIN)
 
+- Intel Monahans options:
+		CFG_MONAHANS_RUN_MODE_OSC_RATIO
+
+		Defines the Monahans run mode to oscillator
+		ratio. Valid values are 8, 16, 24, 31. The core
+		frequency is this value multiplied by 13 MHz.
+
+		CFG_MONAHANS_TURBO_RUN_MODE_RATIO
+
+		Defines the Monahans turbo mode to oscillator
+		ratio. Valid values are 1 (default if undefined) and
+		2. The core frequency as calculated above is multiplied
+		by this value.
+
 - Linux Kernel Interface:
 		CONFIG_CLOCKS_IN_MHZ
 
@@ -1969,6 +1984,17 @@ to save the current settings.
 	  These two #defines specify the offset and size of the environment
 	  area within the first NAND device.
 
+	- CFG_ENV_OFFSET_REDUND
+
+	  This setting describes a second storage area of CFG_ENV_SIZE
+	  size used to hold a redundant copy of the environment data,
+	  so that there is a valid backup copy in case there is a
+	  power failure during a "saveenv" operation.
+
+	Note: CFG_ENV_OFFSET and CFG_ENV_OFFSET_REDUND must be aligned
+	to a block boundary, and CFG_ENV_SIZE must be a multiple of
+	the NAND devices block size.
+
 - CFG_SPI_INIT_OFFSET
 
 	Defines offset to the initial SPI buffer area in DPRAM. The
@@ -3283,6 +3309,8 @@ On ARM, the following registers are used:
 
     ==> U-Boot will use R8 to hold a pointer to the global data
 
+NOTE: DECLARE_GLOBAL_DATA_PTR must be used with file-global scope,
+or current versions of GCC may "optimize" the code too much.
 
 Memory Management:
 ------------------

board/MAI/AmigaOneG3SE/AmigaOneG3SE.c

@@ -1,6 +1,7 @@
 /*
  * (C) Copyright 2002
  * Hyperion Entertainment, ThomasF@hyperion-entertainment.com
+ * (C) Copyright 2006
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -88,8 +89,6 @@ long initdram (int board_type)
 
 void after_reloc (ulong dest_addr, gd_t *gd)
 {
-/* HJF:	DECLARE_GLOBAL_DATA_PTR; */
-
 	board_init_r (gd, dest_addr);
 }
 

board/MAI/AmigaOneG3SE/articiaS.c

@@ -29,6 +29,8 @@
 #include "smbus.h"
 #include "via686.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #undef DEBUG
 
 struct dimm_bank {
@@ -82,7 +84,6 @@ static inline unsigned short NSto10PS (unsigned char spd_byte)
 
 long detect_sdram (uint8 * rom, int dimmNum, struct dimm_bank *banks)
 {
-    DECLARE_GLOBAL_DATA_PTR;
 	int dimm_address = (dimmNum == 0) ? SM_DIMM0_ADDR : SM_DIMM1_ADDR;
 	uint32 busclock = gd->bus_clk;
 	uint32 memclock = busclock;
@@ -394,8 +395,6 @@ uint32 burst_to_len (uint32 support)
 
 long articiaS_ram_init (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	register uint32 i;
 	register uint32 value1;
 	register uint32 value2;

board/MAI/AmigaOneG3SE/articiaS_pci.c

@@ -26,6 +26,8 @@
 #include "memio.h"
 #include "articiaS.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #undef ARTICIA_PCI_DEBUG
 
 #ifdef  ARTICIA_PCI_DEBUG
@@ -493,8 +495,6 @@ pci_dev_t video_dev;
 
 int articiaS_init_vga (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
     extern void shutdown_bios(void);
     pci_dev_t dev = ~0;
     int busnr = 0;

board/MAI/AmigaOneG3SE/cmd_boota.c

@@ -3,6 +3,7 @@
 #include "../disk/part_amiga.h"
 #include <asm/cache.h>
 
+DECLARE_GLOBAL_DATA_PTR;
 
 #undef BOOTA_DEBUG
 
@@ -108,8 +109,6 @@ int do_boota (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 
 	s = getenv ("autostart");
 	if (s && strcmp (s, "yes") == 0) {
-		DECLARE_GLOBAL_DATA_PTR;
-
 		void (*boot) (bd_t *, char *, block_dev_desc_t *);
 		char *args;
 

board/MAI/AmigaOneG3SE/serial.c

@@ -4,6 +4,8 @@
 #include "memio.h"
 #include "articiaS.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #ifndef CFG_NS16550
 static uint32 ComPort1;
 
@@ -150,8 +152,6 @@ const NS16550_t Com1 = (NS16550_t) CFG_NS16550_COM2;
 
 int serial_init (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	uint32 clock_divisor = 115200 / gd->baudrate;
 
 	NS16550_init (Com0, clock_divisor);
@@ -239,8 +239,6 @@ void serial_puts (const char *string)
 
 void serial_setbrg (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	uint32 clock_divisor = 115200 / gd->baudrate;
 
 	NS16550_init (Com0, clock_divisor);

board/MAI/AmigaOneG3SE/via686.c

@@ -28,6 +28,8 @@
 #include "via686.h"
 #include "i8259.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #undef VIA_DEBUG
 
 #ifdef  VIA_DEBUG
@@ -226,33 +228,31 @@ __asm         ("    .globl via_calibrate_time_base \n"
 
 extern unsigned long via_calibrate_time_base(void);
 
-void via_calibrate_bus_freq(void)
+void via_calibrate_bus_freq (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
-    unsigned long tb;
+	unsigned long tb;
 
-    /* This is 20 microseconds */
-    #define CALIBRATE_TIME 28636
+	/* This is 20 microseconds */
+#define CALIBRATE_TIME 28636
 
+	/* Enable the timer (and disable speaker) */
+	unsigned char c;
 
-    /* Enable the timer (and disable speaker) */
-    unsigned char c;
-    c = in_byte(0x61);
-    out_byte(0x61, ((c & ~0x02) | 0x01));
+	c = in_byte (0x61);
+	out_byte (0x61, ((c & ~0x02) | 0x01));
 
-    /* Set timer 2 to low/high writing */
-    out_byte(0x43, 0xb0);
-    out_byte(0x42, CALIBRATE_TIME & 0xff);
-    out_byte(0x42, CALIBRATE_TIME >>8);
+	/* Set timer 2 to low/high writing */
+	out_byte (0x43, 0xb0);
+	out_byte (0x42, CALIBRATE_TIME & 0xff);
+	out_byte (0x42, CALIBRATE_TIME >> 8);
 
-    /* Read the time base */
-    tb = via_calibrate_time_base();
+	/* Read the time base */
+	tb = via_calibrate_time_base ();
 
-    if (tb >= 700000)
-	gd->bus_clk = 133333333;
-    else
-	gd->bus_clk = 100000000;
+	if (tb >= 700000)
+		gd->bus_clk = 133333333;
+	else
+		gd->bus_clk = 100000000;
 
 }
 

board/MAI/AmigaOneG3SE/video.c

@@ -26,6 +26,8 @@
 #include "memio.h"
 #include <part.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 unsigned char *cursor_position;
 unsigned int cursor_row;
 unsigned int cursor_col;
@@ -480,7 +482,6 @@ extern char version_string[];
 void video_banner(void)
 {
     block_dev_desc_t *ide;
-    DECLARE_GLOBAL_DATA_PTR;
     int i;
     char *s;
     int maxdev;

board/Marvell/common/serial.c

@@ -45,13 +45,13 @@
 
 #include "ns16550.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #ifdef CONFIG_MPSC
 
 
 int serial_init (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 #if (defined CFG_INIT_CHAN1) || (defined CFG_INIT_CHAN2)
 	int clock_divisor = 230400 / gd->baudrate;
 #endif
@@ -88,8 +88,6 @@ int serial_tstc (void)
 
 void serial_setbrg (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	galbrg_set_baudrate (CONFIG_MPSC_PORT, gd->baudrate);
 }
 
@@ -97,8 +95,6 @@ void serial_setbrg (void)
 
 int serial_init (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	int clock_divisor = 230400 / gd->baudrate;
 
 #ifdef CFG_INIT_CHAN1
@@ -130,8 +126,6 @@ int serial_tstc (void)
 
 void serial_setbrg (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	int clock_divisor = 230400 / gd->baudrate;
 
 #ifdef CFG_INIT_CHAN1

board/Marvell/db64360/mpsc.c

@@ -42,6 +42,8 @@
 
 #include "../include/memory.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* Define this if you wish to use the MPSC as a register based UART.
  * This will force the serial port to not use the SDMA engine at all.
  */
@@ -114,9 +116,7 @@ static void mpsc_debug_init (void)
 
 	/* Clear the CFR  (CHR4) */
 	/* Write random 'Z' bit (bit 29) of CHR4 to enable debug uart *UNDOCUMENTED FEATURE* */
-	temp = GTREGREAD (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_indent: Standard input:229: Warning:old style assignment ambiguity in "=&".  Assuming "= &"
-
-REG_GAP));
+	temp = GTREGREAD (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP));
 	temp &= 0xffffff00;
 	temp |= BIT29;
 	GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP),
@@ -158,7 +158,6 @@ char mpsc_getchar_debug (void)
  * global variables [josh] */
 int mpsc_putchar_early (char ch)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 	int mpsc = CHANNEL;
 	int temp =
 		GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
@@ -511,7 +510,6 @@ void mpsc_init2 (void)
 
 int galbrg_set_baudrate (int channel, int rate)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 	int clock;
 
 	galbrg_disable (channel);	/*ok */

board/Marvell/db64360/mv_eth.c

@@ -732,6 +732,7 @@ int mv64360_eth_xmit (struct eth_device *dev, volatile void *dataPtr,
 	pkt_info.cmd_sts = ETH_TX_FIRST_DESC | ETH_TX_LAST_DESC;	/* DMA owned, first last */
 	pkt_info.byte_cnt = dataSize;
 	pkt_info.buf_ptr = (unsigned int) dataPtr;
+	pkt_info.return_info = 0;
 
 	status = eth_port_send (ethernet_private, ETH_Q0, &pkt_info);
 	if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL)) {

board/Marvell/db64360/sdram_init.c

@@ -42,6 +42,8 @@
 #include "64360.h"
 #include "mv_regs.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #undef	DEBUG
 #define MAP_PCI
 
@@ -246,8 +248,6 @@ static inline unsigned short NSto10PS (unsigned char spd_byte)
 /* static int check_dimm(uchar slot, AUX_MEM_DIMM_INFO *info) */
 static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	unsigned long spd_checksum;
 
 #ifdef ZUMA_NTL

board/Marvell/db64460/mpsc.c

@@ -42,6 +42,8 @@
 
 #include "../include/memory.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* Define this if you wish to use the MPSC as a register based UART.
  * This will force the serial port to not use the SDMA engine at all.
  */
@@ -114,9 +116,7 @@ static void mpsc_debug_init (void)
 
 	/* Clear the CFR  (CHR4) */
 	/* Write random 'Z' bit (bit 29) of CHR4 to enable debug uart *UNDOCUMENTED FEATURE* */
-	temp = GTREGREAD (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_indent: Standard input:229: Warning:old style assignment ambiguity in "=&".  Assuming "= &"
-
-REG_GAP));
+	temp = GTREGREAD (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP));
 	temp &= 0xffffff00;
 	temp |= BIT29;
 	GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP),
@@ -158,7 +158,6 @@ char mpsc_getchar_debug (void)
  * global variables [josh] */
 int mpsc_putchar_early (char ch)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 	int mpsc = CHANNEL;
 	int temp =
 		GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
@@ -511,7 +510,6 @@ void mpsc_init2 (void)
 
 int galbrg_set_baudrate (int channel, int rate)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 	int clock;
 
 	galbrg_disable (channel);	/*ok */

board/Marvell/db64460/mv_eth.c

@@ -731,6 +731,7 @@ int mv64460_eth_xmit (struct eth_device *dev, volatile void *dataPtr,
 	pkt_info.cmd_sts = ETH_TX_FIRST_DESC | ETH_TX_LAST_DESC;	/* DMA owned, first last */
 	pkt_info.byte_cnt = dataSize;
 	pkt_info.buf_ptr = (unsigned int) dataPtr;
+	pkt_info.return_info = 0;
 
 	status = eth_port_send (ethernet_private, ETH_Q0, &pkt_info);
 	if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL)) {

board/Marvell/db64460/sdram_init.c

@@ -42,6 +42,8 @@
 #include "64460.h"
 #include "mv_regs.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #undef	DEBUG
 #define	MAP_PCI
 
@@ -246,8 +248,6 @@ static inline unsigned short NSto10PS (unsigned char spd_byte)
 /* static int check_dimm(uchar slot, AUX_MEM_DIMM_INFO *info) */
 static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	unsigned long spd_checksum;
 
 #ifdef ZUMA_NTL

board/adsvix/adsvix.c

@@ -30,6 +30,8 @@
 
 #include <common.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* ------------------------------------------------------------------------- */
 
 /*
@@ -38,8 +40,6 @@
 
 int board_init (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	/* memory and cpu-speed are setup before relocation */
 	/* so we do _nothing_ here */
 
@@ -62,8 +62,6 @@ int board_late_init(void)
 
 int dram_init (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;

board/amcc/bamboo/config.mk

@@ -32,6 +32,3 @@ endif
 ifeq ($(dbcr),1)
 PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
 endif
-
-# legacy nand support
-BOARDLIBS = drivers/nand_legacy/libnand_legacy.a

board/amcc/ebony/ebony.c

@@ -28,6 +28,8 @@
 #define FLASH_ONBD_N		2	/* 00000010 */
 #define FLASH_SRAM_SEL		1	/* 00000001 */
 
+DECLARE_GLOBAL_DATA_PTR;
+
 long int fixed_sdram(void);
 
 int board_early_init_f(void)
@@ -107,7 +109,7 @@ long int initdram(int board_type)
 	long dram_size = 0;
 
 #if defined(CONFIG_SPD_EEPROM)
-	dram_size = spd_sdram(0);
+	dram_size = spd_sdram();
 #else
 	dram_size = fixed_sdram();
 #endif
@@ -235,8 +237,6 @@ int pci_pre_init(struct pci_controller *hose)
 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
 void pci_target_init(struct pci_controller *hose)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	/*--------------------------------------------------------------------------+
 	 * Disable everything
 	 *--------------------------------------------------------------------------*/

board/amcc/luan/luan.c

@@ -28,6 +28,7 @@
 #include <spd_sdram.h>
 #include "epld.h"
 
+DECLARE_GLOBAL_DATA_PTR;
 
 extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
 
@@ -291,8 +292,6 @@ int pci_pre_init( struct pci_controller *hose )
 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
 void pci_target_init(struct pci_controller *hose)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	/*--------------------------------------------------------------------------+
 	 * Disable everything
 	 *--------------------------------------------------------------------------*/

board/amcc/ocotea/ocotea.c

@@ -30,6 +30,8 @@
 #include <spd_sdram.h>
 #include <ppc4xx_enet.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #define BOOT_SMALL_FLASH	32	/* 00100000 */
 #define FLASH_ONBD_N		2	/* 00000010 */
 #define FLASH_SRAM_SEL		1	/* 00000001 */
@@ -204,7 +206,7 @@ long int initdram (int board_type)
 	long dram_size = 0;
 
 #if defined(CONFIG_SPD_EEPROM)
-	dram_size = spd_sdram (0);
+	dram_size = spd_sdram ();
 #else
 	dram_size = fixed_sdram ();
 #endif
@@ -334,8 +336,6 @@ int pci_pre_init(struct pci_controller * hose )
 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
 void pci_target_init(struct pci_controller * hose )
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	/*--------------------------------------------------------------------------+
 	 * Disable everything
 	 *--------------------------------------------------------------------------*/

board/amcc/walnut/walnut.c

@@ -99,7 +99,7 @@ void sdram_init(void)
  */
 long int initdram(int board_type)
 {
-	return spd_sdram(0);
+	return spd_sdram();
 }
 
 int testdram(void)

board/amcc/yellowstone/yellowstone.c

@@ -24,6 +24,8 @@
 #include <asm/processor.h>
 #include <spd_sdram.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 int board_early_init_f(void)
@@ -136,7 +138,6 @@ int board_early_init_f(void)
 
 int misc_init_r (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 	uint pbcr;
 	int size_val = 0;
 

board/amcc/yosemite/yosemite.c

@@ -24,6 +24,8 @@
 #include <asm/processor.h>
 #include <spd_sdram.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 int board_early_init_f(void)
@@ -132,7 +134,6 @@ int board_early_init_f(void)
 
 int misc_init_r (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 	uint pbcr;
 	int size_val = 0;
 

board/amirix/ap1000/serial.c

@@ -27,9 +27,7 @@
 
 #include <ns16550.h>
 
-#if 0
-#include "serial.h"
-#endif
+DECLARE_GLOBAL_DATA_PTR;
 
 const NS16550_t COM_PORTS[] =
 	{ (NS16550_t) CFG_NS16550_COM1, (NS16550_t) CFG_NS16550_COM2 };
@@ -40,8 +38,6 @@ static int gComPort = 0;
 
 int serial_init (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate;
 
 	(void) NS16550_init (COM_PORTS[0], clock_divisor);
@@ -71,8 +67,6 @@ int serial_tstc (void)
 
 void serial_setbrg (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate;
 
 #ifdef CFG_INIT_CHAN1

board/armadillo/armadillo.c

@@ -28,6 +28,8 @@
 #include <common.h>
 #include <clps7111.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* ------------------------------------------------------------------------- */
 
 
@@ -37,8 +39,6 @@
 
 int board_init (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	/* Activate LED flasher */
 	IO_LEDFLSH = 0x40;
 
@@ -53,8 +53,6 @@ int board_init (void)
 
 int dram_init (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 

board/assabet/assabet.c

@@ -27,6 +27,8 @@
 #include <common.h>
 #include <SA-1100.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* ------------------------------------------------------------------------- */
 
 /*
@@ -99,8 +101,6 @@ neponset_init(void)
 int
 board_init(void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	gd->bd->bi_arch_number = MACH_TYPE_ASSABET;
 	gd->bd->bi_boot_params = 0xc0000100;
 
@@ -112,8 +112,6 @@ board_init(void)
 int
 dram_init(void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 

board/at91rm9200dk/at91rm9200dk.c

@@ -27,6 +27,8 @@
 #include <at91rm9200_net.h>
 #include <dm9161.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* ------------------------------------------------------------------------- */
 /*
  * Miscelaneous platform dependent initialisations
@@ -34,8 +36,6 @@
 
 int board_init (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	/* Enable Ctrlc */
 	console_init_f ();
 
@@ -56,8 +56,6 @@ int board_init (void)
 
 int dram_init (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	gd->bd->bi_dram[0].start = PHYS_SDRAM;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
 	return 0;

board/bmw/serial.c

@@ -24,6 +24,8 @@
 #include <common.h>
 #include "ns16550.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #if CONFIG_CONS_INDEX == 1
 static struct NS16550 *console =
 		(struct NS16550 *) (CFG_EUMB_ADDR + 0x4500);
@@ -38,8 +40,6 @@ extern ulong get_bus_freq (ulong);
 
 int serial_init (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	int clock_divisor = gd->bus_clk / 16 / gd->baudrate;
 
 	NS16550_init (CONFIG_CONS_INDEX - 1, clock_divisor);
@@ -75,8 +75,6 @@ int serial_tstc (void)
 
 void serial_setbrg (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	int clock_divisor = get_bus_freq (0) / 16 / gd->baudrate;
 
 	NS16550_reinit (console, clock_divisor);

board/cerf250/cerf250.c

@@ -27,6 +27,8 @@
 
 #include <common.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* ------------------------------------------------------------------------- */
 
 
@@ -36,8 +38,6 @@
 
 int board_init (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	/* memory and cpu-speed are setup before relocation */
 	/* so we do _nothing_ here */
 
@@ -60,8 +60,6 @@ int board_late_init(void)
 
 int dram_init (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;

board/cm4008/cm4008.c

@@ -31,6 +31,8 @@
 #include <common.h>
 #include <asm/arch/platform.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* ------------------------------------------------------------------------- */
 
 #define	ks8695_read(a)	  *((volatile unsigned int *) (KS8695_IO_BASE+(a)))
@@ -75,8 +77,6 @@ int board_late_init (void)
 
 int board_init (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	/* arch number of CM4008 */
 	gd->bd->bi_arch_number = 624;
 
@@ -92,8 +92,6 @@ int board_init (void)
 
 int dram_init (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size  = PHYS_SDRAM_1_SIZE;
 

board/cm41xx/cm41xx.c

@@ -31,6 +31,8 @@
 #include <common.h>
 #include <asm/arch/platform.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* ------------------------------------------------------------------------- */
 
 #define	ks8695_read(a)	  *((volatile unsigned int *) (KS8695_IO_BASE+(a)))
@@ -75,8 +77,6 @@ int board_late_init (void)
 
 int board_init (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	/* arch number of CM41xx */
 	gd->bd->bi_arch_number = 672;
 
@@ -92,8 +92,6 @@ int board_init (void)
 
 int dram_init (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size  = PHYS_SDRAM_1_SIZE;
 

board/cmc_pu2/cmc_pu2.c

@@ -33,6 +33,8 @@
 #include <at91rm9200_net.h>
 #include <dm9161.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* ------------------------------------------------------------------------- */
 /*
  * Miscelaneous platform dependent initialisations
@@ -45,7 +47,6 @@ int hw_detect (void);
 
 int board_init (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 	AT91PS_PIO piob = AT91C_BASE_PIOB;
 	AT91PS_PIO pioc = AT91C_BASE_PIOC;
 
@@ -109,8 +110,6 @@ int board_init (void)
 
 int dram_init (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	gd->bd->bi_dram[0].start = PHYS_SDRAM;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
 	return 0;

board/cogent/serial.c

@@ -6,6 +6,8 @@
 #include <common.h>
 #include <board/cogent/serial.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #if (CMA_MB_CAPS & CMA_MB_CAP_SERPAR)
 
 #if (defined(CONFIG_8xx) && defined(CONFIG_8xx_CONS_NONE)) || \
@@ -25,76 +27,65 @@
 
 int serial_init (void)
 {
-/*  DECLARE_GLOBAL_DATA_PTR; */
-
-    cma_mb_serial *mbsp = (cma_mb_serial *)CMA_MB_SERIAL_BASE;
+	cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_SERIAL_BASE;
 
-    cma_mb_reg_write(&mbsp->ser_ier, 0x00);	/* turn off interrupts */
-    serial_setbrg ();
-    cma_mb_reg_write(&mbsp->ser_lcr, 0x03);	/* 8 data, 1 stop, no parity */
-    cma_mb_reg_write(&mbsp->ser_mcr, 0x03);	/* RTS/DTR */
-    cma_mb_reg_write(&mbsp->ser_fcr, 0x07);	/* Clear & enable FIFOs */
+	cma_mb_reg_write (&mbsp->ser_ier, 0x00);	/* turn off interrupts */
+	serial_setbrg ();
+	cma_mb_reg_write (&mbsp->ser_lcr, 0x03);	/* 8 data, 1 stop, no parity */
+	cma_mb_reg_write (&mbsp->ser_mcr, 0x03);	/* RTS/DTR */
+	cma_mb_reg_write (&mbsp->ser_fcr, 0x07);	/* Clear & enable FIFOs */
 
-    return (0);
+	return (0);
 }
 
-void
-serial_setbrg (void)
+void serial_setbrg (void)
 {
-    DECLARE_GLOBAL_DATA_PTR;
-
-    cma_mb_serial *mbsp = (cma_mb_serial *)CMA_MB_SERIAL_BASE;
-    unsigned int divisor;
-    unsigned char lcr;
-
-    if ((divisor = br_to_div(gd->baudrate)) == 0)
-	divisor = DEFDIV;
-
-    lcr = cma_mb_reg_read(&mbsp->ser_lcr);
-    cma_mb_reg_write(&mbsp->ser_lcr, lcr|0x80);/* Access baud rate(set DLAB)*/
-    cma_mb_reg_write(&mbsp->ser_brl, divisor & 0xff);
-    cma_mb_reg_write(&mbsp->ser_brh, (divisor >> 8) & 0xff);
-    cma_mb_reg_write(&mbsp->ser_lcr, lcr);	/* unset DLAB */
+	cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_SERIAL_BASE;
+	unsigned int divisor;
+	unsigned char lcr;
+
+	if ((divisor = br_to_div (gd->baudrate)) == 0)
+		divisor = DEFDIV;
+
+	lcr = cma_mb_reg_read (&mbsp->ser_lcr);
+	cma_mb_reg_write (&mbsp->ser_lcr, lcr | 0x80);	/* Access baud rate(set DLAB) */
+	cma_mb_reg_write (&mbsp->ser_brl, divisor & 0xff);
+	cma_mb_reg_write (&mbsp->ser_brh, (divisor >> 8) & 0xff);
+	cma_mb_reg_write (&mbsp->ser_lcr, lcr);	/* unset DLAB */
 }
 
-void
-serial_putc(const char c)
+void serial_putc (const char c)
 {
-    cma_mb_serial *mbsp = (cma_mb_serial *)CMA_MB_SERIAL_BASE;
+	cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_SERIAL_BASE;
 
-    if (c == '\n')
-	serial_putc('\r');
+	if (c == '\n')
+		serial_putc ('\r');
 
-    while ((cma_mb_reg_read(&mbsp->ser_lsr) & LSR_THRE) == 0)
-	;
+	while ((cma_mb_reg_read (&mbsp->ser_lsr) & LSR_THRE) == 0);
 
-    cma_mb_reg_write(&mbsp->ser_thr, c);
+	cma_mb_reg_write (&mbsp->ser_thr, c);
 }
 
-void
-serial_puts(const char *s)
+void serial_puts (const char *s)
 {
-    while (*s != '\0')
-	serial_putc(*s++);
+	while (*s != '\0')
+		serial_putc (*s++);
 }
 
-int
-serial_getc(void)
+int serial_getc (void)
 {
-    cma_mb_serial *mbsp = (cma_mb_serial *)CMA_MB_SERIAL_BASE;
+	cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_SERIAL_BASE;
 
-    while ((cma_mb_reg_read(&mbsp->ser_lsr) & LSR_DR) == 0)
-	;
+	while ((cma_mb_reg_read (&mbsp->ser_lsr) & LSR_DR) == 0);
 
-    return ((int)cma_mb_reg_read(&mbsp->ser_rhr) & 0x7f);
+	return ((int) cma_mb_reg_read (&mbsp->ser_rhr) & 0x7f);
 }
 
-int
-serial_tstc(void)
+int serial_tstc (void)
 {
-    cma_mb_serial *mbsp = (cma_mb_serial *)CMA_MB_SERIAL_BASE;
+	cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_SERIAL_BASE;
 
-    return ((cma_mb_reg_read(&mbsp->ser_lsr) & LSR_DR) != 0);
+	return ((cma_mb_reg_read (&mbsp->ser_lsr) & LSR_DR) != 0);
 }
 
 #endif /* CONS_NONE */
@@ -118,71 +109,63 @@ serial_tstc(void)
 #error CONFIG_KGDB_INDEX must be configured for Cogent motherboard serial
 #endif
 
-void
-kgdb_serial_init(void)
+void kgdb_serial_init (void)
 {
-    cma_mb_serial *mbsp = (cma_mb_serial *)CMA_MB_KGDB_SER_BASE;
-    unsigned int divisor;
+	cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_KGDB_SER_BASE;
+	unsigned int divisor;
 
-    if ((divisor = br_to_div(CONFIG_KGDB_BAUDRATE)) == 0)
-	divisor = DEFDIV;
+	if ((divisor = br_to_div (CONFIG_KGDB_BAUDRATE)) == 0)
+		divisor = DEFDIV;
 
-    cma_mb_reg_write(&mbsp->ser_ier, 0x00);	/* turn off interrupts */
-    cma_mb_reg_write(&mbsp->ser_lcr, 0x80);	/* Access baud rate(set DLAB)*/
-    cma_mb_reg_write(&mbsp->ser_brl, divisor & 0xff);
-    cma_mb_reg_write(&mbsp->ser_brh, (divisor >> 8) & 0xff);
-    cma_mb_reg_write(&mbsp->ser_lcr, 0x03);	/* 8 data, 1 stop, no parity */
-    cma_mb_reg_write(&mbsp->ser_mcr, 0x03);	/* RTS/DTR */
-    cma_mb_reg_write(&mbsp->ser_fcr, 0x07);	/* Clear & enable FIFOs */
+	cma_mb_reg_write (&mbsp->ser_ier, 0x00);	/* turn off interrupts */
+	cma_mb_reg_write (&mbsp->ser_lcr, 0x80);	/* Access baud rate(set DLAB) */
+	cma_mb_reg_write (&mbsp->ser_brl, divisor & 0xff);
+	cma_mb_reg_write (&mbsp->ser_brh, (divisor >> 8) & 0xff);
+	cma_mb_reg_write (&mbsp->ser_lcr, 0x03);	/* 8 data, 1 stop, no parity */
+	cma_mb_reg_write (&mbsp->ser_mcr, 0x03);	/* RTS/DTR */
+	cma_mb_reg_write (&mbsp->ser_fcr, 0x07);	/* Clear & enable FIFOs */
 
-    printf("[on cma10x serial port B] ");
+	printf ("[on cma10x serial port B] ");
 }
 
-void
-putDebugChar(int c)
+void putDebugChar (int c)
 {
-    cma_mb_serial *mbsp = (cma_mb_serial *)CMA_MB_KGDB_SER_BASE;
+	cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_KGDB_SER_BASE;
 
-    while ((cma_mb_reg_read(&mbsp->ser_lsr) & LSR_THRE) == 0)
-	;
+	while ((cma_mb_reg_read (&mbsp->ser_lsr) & LSR_THRE) == 0);
 
-    cma_mb_reg_write(&mbsp->ser_thr, c & 0xff);
+	cma_mb_reg_write (&mbsp->ser_thr, c & 0xff);
 }
 
-void
-putDebugStr(const char *str)
+void putDebugStr (const char *str)
 {
-    while (*str != '\0') {
-	if (*str == '\n')
-	    putDebugChar('\r');
-	putDebugChar(*str++);
-    }
+	while (*str != '\0') {
+		if (*str == '\n')
+			putDebugChar ('\r');
+		putDebugChar (*str++);
+	}
 }
 
-int
-getDebugChar(void)
+int getDebugChar (void)
 {
-    cma_mb_serial *mbsp = (cma_mb_serial *)CMA_MB_KGDB_SER_BASE;
+	cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_KGDB_SER_BASE;
 
-    while ((cma_mb_reg_read(&mbsp->ser_lsr) & LSR_DR) == 0)
-	;
+	while ((cma_mb_reg_read (&mbsp->ser_lsr) & LSR_DR) == 0);
 
-    return ((int)cma_mb_reg_read(&mbsp->ser_rhr) & 0x7f);
+	return ((int) cma_mb_reg_read (&mbsp->ser_rhr) & 0x7f);
 }
 
-void
-kgdb_interruptible(int yes)
+void kgdb_interruptible (int yes)
 {
-    cma_mb_serial *mbsp = (cma_mb_serial *)CMA_MB_KGDB_SER_BASE;
-
-    if (yes == 1) {
-	printf("kgdb: turning serial ints on\n");
-	cma_mb_reg_write(&mbsp->ser_ier, 0xf);
-    }
-    else {
-	printf("kgdb: turning serial ints off\n");
-	cma_mb_reg_write(&mbsp->ser_ier, 0x0);
-    }
+	cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_KGDB_SER_BASE;
+
+	if (yes == 1) {
+		printf ("kgdb: turning serial ints on\n");
+		cma_mb_reg_write (&mbsp->ser_ier, 0xf);
+	} else {
+		printf ("kgdb: turning serial ints off\n");
+		cma_mb_reg_write (&mbsp->ser_ier, 0x0);
+	}
 }
 
 #endif /* KGDB && KGDB_NONE */

board/cradle/cradle.c

@@ -28,6 +28,8 @@
 #include <asm/arch/pxa-regs.h>
 #include <common.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* ------------------------------------------------------------------------- */
 
 
@@ -181,8 +183,6 @@ int
 board_init (void)
 /**********************************************************/
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	led_code (0xf, YELLOW);
 
 	/* arch number of HHP Cradle */
@@ -209,8 +209,6 @@ int
 dram_init (void)
 /**********************************************************/
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size  = PHYS_SDRAM_1_SIZE;
 	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;

board/csb226/csb226.c

@@ -26,6 +26,8 @@
 #include <common.h>
 #include <asm/arch/pxa-regs.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #ifdef CONFIG_SHOW_BOOT_PROGRESS
 # define SHOW_BOOT_PROGRESS(arg)        show_boot_progress(arg)
 #else
@@ -65,8 +67,6 @@ int misc_init_r(void)
 
 int board_init (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	/* memory and cpu-speed are setup before relocation */
 	/* so we do _nothing_ here */
 
@@ -88,8 +88,6 @@ int board_init (void)
 
 int dram_init (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 

board/csb637/csb637.c

@@ -26,6 +26,8 @@
 #include <at91rm9200_net.h>
 #include <bcm5221.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* ------------------------------------------------------------------------- */
 /*
  * Miscelaneous platform dependent initialisations
@@ -33,8 +35,6 @@
 
 int board_init (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	/* Enable Ctrlc */
 	console_init_f ();
 
@@ -51,8 +51,6 @@ int board_init (void)
 
 int dram_init (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	gd->bd->bi_dram[0].start = PHYS_SDRAM;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
 	return 0;

board/cu824/cu824.c

@@ -2,7 +2,7 @@
  * (C) Copyright 2001
  * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
  *
- * (C) Copyright 2001, 2002
+ * (C) Copyright 2001-2006
  * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
 
  * See file CREDITS for list of people who contributed to this
@@ -29,12 +29,12 @@
 #include <asm/processor.h>
 #include <pci.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #define BOARD_REV_REG 0xFE80002B
 
 int checkboard (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	char  revision = *(volatile char *)(BOARD_REV_REG);
 	char  buf[32];
 

board/dave/B2/B2.c

@@ -27,13 +27,14 @@
 #include <common.h>
 #include <asm/hardware.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /*
  * Miscelaneous platform dependent initialization
  */
 
 int board_init (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 	u32 temp;
 
 	/* Configuration Port Control Register*/
@@ -119,8 +120,6 @@ int board_init (void)
 
 int dram_init (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 

board/dave/PPChameleonEVB/PPChameleonEVB.c

@@ -29,6 +29,8 @@
 #include <command.h>
 #include <malloc.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* ------------------------------------------------------------------------- */
 
 /* Prototypes */
@@ -81,8 +83,6 @@ extern flash_info_t flash_info[];	/* info for FLASH chips */
 
 int misc_init_r (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	/* adjust flash start and size as well as the offset */
 	gd->bd->bi_flashstart = 0 - flash_info[0].size;
 	gd->bd->bi_flashoffset= flash_info[0].size - CFG_MONITOR_LEN;

board/dave/PPChameleonEVB/config.mk

@@ -26,9 +26,3 @@
 
 # Reserve 320 kB for Monitor
 TEXT_BASE = 0xFFFB0000
-
-# Compile the new NAND code (CFG_NAND_LEGACY mustn't be defined)
-BOARDLIBS = drivers/nand/libnand.a
-
-# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined)
-#BOARDLIBS = drivers/nand_legacy/libnand_legacy.a

board/dbau1x00/lowlevel_init.S

@@ -185,6 +185,8 @@ tlbloop:
 	bne	t0, t2, tlbloop
 	nop
 
+#endif /* CONFIG_DBAU1550 */
+
 	/* First setup pll:s to make serial work ok */
 	/* We have a 12 MHz crystal */
 	li	t0, SYS_CPUPLL
@@ -205,6 +207,7 @@ tlbloop:
 	sw	t1, 0(t0) /* aux pll */
 	sync
 
+#ifdef CONFIG_DBAU1550
 	/*  Static memory controller */
 	/* RCE0 - can not change while fetching, do so from icache */
 	move		t2, ra /* Store return address */
@@ -237,7 +240,7 @@ noCacheJump:
 	sw	t1, 0(t0)
 #else /* CONFIG_DBAU1550 */
 	li	t0, MEM_STTIME0
-	li	t1, 0x00014C0F
+	li	t1, 0x040181D7
 	sw	t1, 0(t0)
 
 	/* RCE0 AMD 29LV640M MirrorBit Flash */

board/delta/config.mk

@@ -1,8 +1 @@
-#TEXT_BASE = 0x0
-#TEXT_BASE = 0xa1700000
-#TEXT_BASE = 0xa3080000
-#TEXT_BASE = 0x9ffe0000
-TEXT_BASE = 0xa3008000
-
-# Compile the new NAND code (needed iff #ifdef CONFIG_NEW_NAND_CODE)
-BOARDLIBS = drivers/nand/libnand.a
+TEXT_BASE = 0x83008000

board/delta/delta.c

@@ -26,9 +26,15 @@
  */
 
 #include <common.h>
+#include <i2c.h>
+#include <da9030.h>
+#include <asm/arch/pxa-regs.h>
+
+DECLARE_GLOBAL_DATA_PTR;
 
 /* ------------------------------------------------------------------------- */
 
+static void init_DA9030(void);
 
 /*
  * Miscelaneous platform dependent initialisations
@@ -36,8 +42,6 @@
 
 int board_init (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	/* memory and cpu-speed are setup before relocation */
 	/* so we do _nothing_ here */
 
@@ -54,14 +58,13 @@ int board_late_init(void)
 {
 	setenv("stdout", "serial");
 	setenv("stderr", "serial");
+	init_DA9030();
 	return 0;
 }
 
 
 int dram_init (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
@@ -73,3 +76,81 @@ int dram_init (void)
 
 	return 0;
 }
+
+void i2c_init_board()
+{
+	CKENB |= (CKENB_4_I2C);
+
+	/* setup I2C GPIO's */
+	GPIO32 = 0x801;		/* SCL = Alt. Fkt. 1 */
+	GPIO33 = 0x801;		/* SDA = Alt. Fkt. 1 */
+}
+
+/* initialize the DA9030 Power Controller */
+static void init_DA9030()
+{
+	uchar addr = (uchar) DA9030_I2C_ADDR, val = 0;
+
+	CKENB |= CKENB_7_GPIO;
+	udelay(100);
+
+	/* Rising Edge on EXTON to reset DA9030 */
+	GPIO17 = 0x8800;	/* configure GPIO17, no pullup, -down */
+	GPDR0 |= (1<<17);	/* GPIO17 is output */
+	GSDR0 = (1<<17);
+	GPCR0 = (1<<17);	/* drive GPIO17 low */
+	GPSR0 = (1<<17);	/* drive GPIO17 high */
+
+#if CFG_DA9030_EXTON_DELAY
+	udelay((unsigned long) CFG_DA9030_EXTON_DELAY);	/* wait for DA9030 */
+#endif
+	GPCR0 = (1<<17);	/* drive GPIO17 low */
+
+	/* reset the watchdog and go active (0xec) */
+	val = (SYS_CONTROL_A_HWRES_ENABLE |
+	       (0x6<<4) |
+	       SYS_CONTROL_A_WDOG_ACTION |
+	       SYS_CONTROL_A_WATCHDOG);
+	if(i2c_write(addr, SYS_CONTROL_A, 1, &val, 1)) {
+		printf("Error accessing DA9030 via i2c.\n");
+		return;
+	}
+
+	i2c_reg_write(addr, REG_CONTROL_1_97, 0xfd); /* disable LDO1, enable LDO6 */
+	i2c_reg_write(addr, LDO2_3, 0xd1);	/* LDO2 =1,9V, LDO3=3,1V */
+	i2c_reg_write(addr, LDO4_5, 0xcc);	/* LDO2 =1,9V, LDO3=3,1V */
+	i2c_reg_write(addr, LDO6_SIMCP, 0x3e);	/* LDO6=3,2V, SIMCP = 5V support */
+	i2c_reg_write(addr, LDO7_8, 0xc9);	/* LDO7=2,7V, LDO8=3,0V */
+	i2c_reg_write(addr, LDO9_12, 0xec);	/* LDO9=3,0V, LDO12=3,2V */
+	i2c_reg_write(addr, BUCK, 0x0c);	/* Buck=1.2V */
+	i2c_reg_write(addr, REG_CONTROL_2_98, 0x7f); /* All LDO'S on 8,9,10,11,12,14 */
+	i2c_reg_write(addr, LDO_10_11, 0xcc);	/* LDO10=3.0V  LDO11=3.0V */
+	i2c_reg_write(addr, LDO_15, 0xae);	/* LDO15=1.8V, dislock first 3bit */
+	i2c_reg_write(addr, LDO_14_16, 0x05);	/* LDO14=2.8V, LDO16=NB */
+	i2c_reg_write(addr, LDO_18_19, 0x9c);	/* LDO18=3.0V, LDO19=2.7V */
+	i2c_reg_write(addr, LDO_17_SIMCP0, 0x2c); /* LDO17=3.0V, SIMCP=3V support */
+	i2c_reg_write(addr, BUCK2_DVC1, 0x9a);	/* Buck2=1.5V plus Update support of 520 MHz */
+	i2c_reg_write(addr, REG_CONTROL_2_18, 0x43); /* Ball on */
+	i2c_reg_write(addr, MISC_CONTROLB, 0x08); /* session valid enable */
+	i2c_reg_write(addr, USBPUMP, 0xc1);	/* start pump, ignore HW signals */
+
+	val = i2c_reg_read(addr, STATUS);
+	if(val & STATUS_CHDET)
+		printf("Charger detected, turning on LED.\n");
+	else {
+		printf("No charger detetected.\n");
+		/* undervoltage? print error and power down */
+	}
+}
+
+
+#if 0
+/* reset the DA9030 watchdog */
+void hw_watchdog_reset(void)
+{
+	uchar addr = (uchar) DA9030_I2C_ADDR, val = 0;
+	val = i2c_reg_read(addr, SYS_CONTROL_A);
+	val |= SYS_CONTROL_A_WATCHDOG;
+	i2c_reg_write(addr, SYS_CONTROL_A, val);
+}
+#endif

board/delta/lowlevel_init.S

@@ -1,10 +1,5 @@
 /*
- * Most of this taken from Redboot hal_platform_setup.h with cleanup
- *
- * NOTE: I haven't clean this up considerably, just enough to get it
- * running. See hal_platform_setup.h for the source. See
- * board/cradle/lowlevel_init.S for another PXA250 setup that is
- * much cleaner.
+ * (C) Copyright 2006 DENX Software Engineering
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -31,14 +26,6 @@
 
 DRAM_SIZE:  .long   CFG_DRAM_SIZE
 
-/* wait for coprocessor write complete */
-.macro CPWAIT reg
-	mrc	p15,0,\reg,c2,c0,0
-	mov	\reg,\reg
-	sub	pc,pc,#4
-.endm
-
-
 .macro wait time
 	ldr		r2, =OSCR
 	mov		r3, #0
@@ -49,13 +36,9 @@ DRAM_SIZE:  .long   CFG_DRAM_SIZE
 	bls		0b
 .endm
 
-/*
- *	Memory setup
- */
-
 .globl lowlevel_init
 lowlevel_init:
-	/* Set up GPIO pins first ----------------------------------------- */
+	/* Set up GPIO pins first */
 	mov	 r10, lr
 
 	/*  Configure GPIO  Pins 97, 98 UART1 / altern. Fkt. 1 */
@@ -73,22 +56,7 @@ lowlevel_init:
 	bic		r1, r1, #0x80000000
 	str		r1, [r0]
 
-	/* ---------------------------------------------------------------- */
-	/* Enable memory interface					    */
-	/* ---------------------------------------------------------------- */
-
-	/* ---------------------------------------------------------------- */
-	/* Step 1: Wait for at least 200 microsedonds to allow internal	    */
-	/*	   clocks to settle. Only necessary after hard reset...	    */
-	/*	   FIXME: can be optimized later			    */
-	/* ---------------------------------------------------------------- */
-;	wait #300
-
 mem_init:
-
-#define NEW_SDRAM_INIT 1
-#ifdef NEW_SDRAM_INIT
-
 	/* Configure ACCR Register - enable DMEMC Clock at 260 / 2 MHz */
 	ldr		r0, =ACCR
 	ldr		r1, [r0]
@@ -99,7 +67,7 @@ mem_init:
 	/* 2. Programm MDCNFG, leaving DMCEN de-asserted */
 	ldr		r0, =MDCNFG
 	ldr		r1, =(MDCNFG_DMAP | MDCNFG_DTYPE | MDCNFG_DTC_2 | MDCNFG_DCSE0 | MDCNFG_DRAC_13)
-	/*	ldr		r1, =0x80000403 */
+	/* ldr		r1, =0x80000403 */
 	str		r1, [r0]
 	ldr		r1, [r0]	/* delay until written */
 
@@ -140,121 +108,6 @@ mem_init:
 	orr		r1, r1, #MDCNFG_DMCEN
 	str		r1, [r0]
 
-
-#else /* NEW_SDRAM_INIT */
-
-	/* configure the MEMCLKCFG register */
-	ldr		r1, =MEMCLKCFG
-	ldr		r2, =0x00010001
-	str		r2, [r1]	     @ WRITE
-	ldr		r2, [r1]	     @ DELAY UNTIL WRITTEN
-
-	/* set CSADRCFG[0] to data flash SRAM mode */
-	ldr		r1, =CSADRCFG0
-	ldr		r2, =0x00320809
-	str		r2, [r1]	     @ WRITE
-	ldr		r2, [r1]	     @ DELAY UNTIL WRITTEN
-
-	/* set CSADRCFG[1] to data flash SRAM mode */
-	ldr		r1, =CSADRCFG1
-	ldr		r2, =0x00320809
-	str		r2, [r1]	     @ WRITE
-	ldr		r2, [r1]	     @ DELAY UNTIL WRITTEN
-
-	/* set MSC 0 register for SRAM memory */
-	ldr		r1, =MSC0
-	ldr		r2, =0x11191119
-	str		r2, [r1]	     @ WRITE
-	ldr		r2, [r1]	     @ DELAY UNTIL WRITTEN
-
-	/* set CSADRCFG[2] to data flash SRAM mode */
-	ldr		r1, =CSADRCFG2
-	ldr		r2, =0x00320809
-	str		r2, [r1]	     @ WRITE
-	ldr		r2, [r1]	     @ DELAY UNTIL WRITTEN
-
-	/* set CSADRCFG[3] to VLIO mode */
-	ldr		r1, =CSADRCFG3
-	ldr		r2, =0x0032080B
-	str		r2, [r1]	     @ WRITE
-	ldr		r2, [r1]	     @ DELAY UNTIL WRITTEN
-
-	/* set MSC 1 register for VLIO memory */
-	ldr		r1, =MSC1
-	ldr		r2, =0x123C1119
-	str		r2, [r1]	     @ WRITE
-	ldr		r2, [r1]	     @ DELAY UNTIL WRITTEN
-
-#if 0
-	/* This does not work in Zylonite. -SC */
-	ldr		r0, =0x15fffff0
-	ldr		r1, =0xb10b
-	str		r1, [r0]
-	str		r1, [r0, #4]
-#endif
-
-	/* Configure ACCR Register */
-	ldr		r0, =ACCR		@ ACCR
-	ldr		r1, =0x0180b108
-	str		r1, [r0]
-	ldr		r1, [r0]
-
-	/* Configure MDCNFG Register */
-	ldr		r0, =MDCNFG		@ MDCNFG
-	ldr		r1, =0x403
-	str		r1, [r0]
-	ldr		r1, [r0]
-
-	/* Perform Resistive Compensation by configuring RCOMP register */
-	ldr		r1, =RCOMP		@ RCOMP
-	ldr		r2, =0x000000ff
-	str		r2, [r1]
-	ldr		r2, [r1]
-
-	/* Configure MDMRS Register for SDCS0 */
-	ldr		r1, =MDMRS		@ MDMRS
-	ldr		r2, =0x60000023
-	ldr		r3, [r1]
-	orr		r2, r2, r3
-	str		r2, [r1]
-	ldr		r2, [r1]
-
-	/* Configure MDMRS Register for SDCS1 */
-	ldr		r1, =MDMRS		@ MDMRS
-	ldr		r2, =0xa0000023
-	ldr		r3, [r1]
-	orr		r2, r2, r3
-	str		r2, [r1]
-	ldr		r2, [r1]
-
-	/* Configure MDREFR */
-	ldr		r1, =MDREFR		@ MDREFR
-	ldr		r2, =0x00000006
-	str		r2, [r1]
-	ldr		r2, [r1]
-
-	/* Configure EMPI */
-	ldr		r1, =EMPI		@ EMPI
-	ldr		r2, =0x80000000
-	str		r2, [r1]
-	ldr		r2, [r1]
-
-	/* Hardware DDR Read-Strobe Delay Calibration */
-	ldr		r0, =DDR_HCAL		@ DDR_HCAL
-	ldr		r1, =0x803ffc07	    @ the offset is correct? -SC
-	str		r1, [r0]
-	wait		#5
-	ldr		r1, [r0]
-
-	/* Here we assume the hardware calibration alwasy be successful. -SC */
-	/* Set DMCEN bit in MDCNFG Register */
-	ldr		r0, =MDCNFG		@ MDCNFG
-	ldr		r1, [r0]
-	orr		r1, r1, #0x40000000	@ enable SDRAM for Normal Access
-	str		r1, [r0]
-
-#endif /* NEW_SDRAM_INIT */
-
 #ifndef CFG_SKIP_DRAM_SCRUB
 	/* scrub/init SDRAM if enabled/present */
 	ldr	r8, =CFG_DRAM_BASE	/* base address of SDRAM (CFG_DRAM_BASE) */
@@ -290,96 +143,4 @@ mem_init:
 	mcr	p14,0,r0,c10,c0,0  /* dcsr */
 
 endlowlevel_init:
-
 	mov	pc, lr
-
-
-/*
-@********************************************************************************
-@ DDR calibration
-@
-@  This function is used to calibrate DQS delay lines.
-@ Monahans supports three ways to do it. One is software
-@ calibration. Two is hardware calibration. Three is hybrid
-@ calibration.
-@
-@ TBD
-@ -SC
-ddr_calibration:
-
-	@ Case 1:	Write the correct delay value once
-	@ Configure DDR_SCAL Register
-	ldr		r0, =DDR_SCAL		@ DDR_SCAL
-q	ldr		r1, =0xaf2f2f2f
-	str		r1, [r0]
-	ldr		r1, [r0]
-*/
-/*	@ Case 2:	Software Calibration
-	@ Write test pattern to memory
-	ldr		r5, =0x0faf0faf		@ Data Pattern
-	ldr		r4, =0xa0000000		@ DDR ram
-	str		r5, [r4]
-
-	mov		r1, =0x0		@ delay count
-	mov		r6, =0x0
-	mov		r7, =0x0
-ddr_loop1:
-	add		r1, r1, =0x1
-	cmp		r1, =0xf
-	ble		end_loop
-	mov		r3, r1
-	mov		r0, r1, lsl #30
-	orr		r3, r3, r0
-	mov		r0, r1, lsl #22
-	orr		r3, r3, r0
-	mov		r0, r1, lsl #14
-	orr		r3, r3, r0
-	orr		r3, r3, =0x80000000
-	ldr		r2, =DDR_SCAL
-	str		r3, [r2]
-
-	ldr		r2, [r4]
-	cmp		r2, r5
-	bne		ddr_loop1
-	mov		r6, r1
-ddr_loop2:
-	add		r1, r1, =0x1
-	cmp		r1, =0xf
-	ble		end_loop
-	mov		r3, r1
-	mov		r0, r1, lsl #30
-	orr		r3, r3, r0
-	mov		r0, r1, lsl #22
-	orr		r3, r3, r0
-	mov		r0, r1, lsl #14
-	orr		r3, r3, r0
-	orr		r3, r3, =0x80000000
-	ldr		r2, =DDR_SCAL
-	str		r3, [r2]
-
-	ldr		r2, [r4]
-	cmp		r2, r5
-	be		ddr_loop2
-	mov		r7, r2
-
-	add		r3, r6, r7
-	lsr		r3, r3, =0x1
-	mov		r0, r1, lsl #30
-	orr		r3, r3, r0
-	mov		r0, r1, lsl #22
-	orr		r3, r3, r0
-	mov		r0, r1, lsl #14
-	orr		r3, r3, r0
-	orr		r3, r3, =0x80000000
-	ldr		r2, =DDR_SCAL
-
-end_loop:
-
-	@ Case 3:	Hardware Calibratoin
-	ldr		r0, =DDR_HCAL		@ DDR_HCAL
-	ldr		r1, =0x803ffc07	    @ the offset is correct? -SC
-	str		r1, [r0]
-	wait		#5
-	ldr		r1, [r0]
-	mov		pc, lr
-*/

board/delta/nand.c

@@ -23,7 +23,7 @@
 #include <common.h>
 
 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
-#ifdef CONFIG_NEW_NAND_CODE
+#if !defined(CFG_NAND_LEGACY)
 
 #include <nand.h>
 #include <asm/arch/pxa-regs.h>
@@ -293,11 +293,6 @@ static int dfc_wait(struct mtd_info *mtd, struct nand_chip *this, int state)
 {
 	unsigned long ndsr=0, event=0;
 
-	/* mk@tbd set appropriate timeouts */
-	/* 	if (state == FL_ERASING) */
-	/* 		timeo = CFG_HZ * 400; */
-	/* 	else */
-	/* 		timeo = CFG_HZ * 20; */
 	if(state == FL_WRITING) {
 		event = NDSR_CS0_CMDD | NDSR_CS0_BBD;
 	} else if(state == FL_ERASING) {
@@ -563,13 +558,12 @@ void board_nand_init(struct nand_chip *nand)
 
 
 	/* wait 10 us due to cmd buffer clear reset */
-	/* 	wait(10); */
+	/*	wait(10); */
 
 
 	nand->hwcontrol = dfc_hwcontrol;
-/* 	nand->dev_ready = dfc_device_ready; */
+/*	nand->dev_ready = dfc_device_ready; */
 	nand->eccmode = NAND_ECC_SOFT;
-	nand->chip_delay = NAND_DELAY_US;
 	nand->options = NAND_BUSWIDTH_16;
 	nand->waitfunc = dfc_wait;
 	nand->read_byte = dfc_read_byte;

board/dnp1110/dnp1110.c

@@ -24,8 +24,8 @@
 
 #include <common.h>
 #include <SA-1100.h>
-/* ------------------------------------------------------------------------- */
 
+DECLARE_GLOBAL_DATA_PTR;
 
 /*
  * Miscelaneous platform dependent initialisations
@@ -33,25 +33,21 @@
 
 int board_init (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	/* memory and cpu-speed are setup before relocation */
 	/* so we do _nothing_ here */
 
 	/* arch number of DNP1110-Board */
 	gd->bd->bi_arch_number = MACH_TYPE_DNP1110;
 
-    /* flash vpp on */
-    PPDR |= 0x80;	/* assumes LCD controller is off */
-    PPSR |= 0x80;
+	/* flash vpp on */
+	PPDR |= 0x80;	/* assumes LCD controller is off */
+	PPSR |= 0x80;
 
 	return 0;
 }
 
 int dram_init (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 

board/eltec/bab7xx/bab7xx.c

@@ -31,6 +31,8 @@
 #include <ns87308.h>
 #include <video_fb.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /*---------------------------------------------------------------------------*/
 /*
  * Get Bus clock frequency
@@ -169,8 +171,6 @@ long int initdram (int board_type)
 
 void after_reloc (ulong dest_addr)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	/*
 	 * Jump to the main U-Boot board init code
 	 */

board/eltec/elppc/elppc.c

@@ -26,6 +26,8 @@
 #include <mpc106.h>
 #include <video_fb.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* ------------------------------------------------------------------------- */
 
 int checkboard (void)
@@ -137,8 +139,6 @@ void watchdog_reset (void)
 
 void after_reloc (ulong dest_addr)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	/*
 	 * Jump to the main U-Boot board init code
 	 */

board/ep7312/ep7312.c

@@ -25,8 +25,7 @@
 #include <common.h>
 #include <clps7111.h>
 
-/* ------------------------------------------------------------------------- */
-
+DECLARE_GLOBAL_DATA_PTR;
 
 /*
  * Miscelaneous platform dependent initialisations
@@ -34,8 +33,6 @@
 
 int board_init (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	/* Activate LED flasher */
 	IO_LEDFLSH = 0x40;
 
@@ -50,8 +47,6 @@ int board_init (void)
 
 int dram_init (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 

board/esd/apc405/apc405.c

@@ -26,7 +26,7 @@
 #include <command.h>
 #include <malloc.h>
 
-/* ------------------------------------------------------------------------- */
+DECLARE_GLOBAL_DATA_PTR;
 
 #if 0
 #define FPGA_DEBUG
@@ -166,8 +166,6 @@ int misc_init_f (void)
 
 int misc_init_r (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	volatile unsigned short *fpga_mode =
 		(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
 	volatile unsigned short *fpga_ctrl2 =
@@ -301,8 +299,6 @@ int misc_init_r (void)
 
 int checkboard (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	unsigned char str[64];
 	int i = getenv_r ("serial#", str, sizeof(str));
 

board/esd/ar405/ar405.c

@@ -26,6 +26,8 @@
 #include <asm/processor.h>
 #include <command.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /*cmd_boot.c*/
 extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
 extern void lxt971_no_sleep(void);
@@ -53,8 +55,6 @@ const unsigned char fpgadata_xl30[] = {
 
 int board_early_init_f (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	int index, len, i;
 	int status;
 
@@ -151,8 +151,6 @@ int board_early_init_f (void)
 
 int checkboard (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	int index;
 	int len;
 	char str[64];

board/esd/ash405/config.mk

@@ -26,6 +26,3 @@
 #
 
 TEXT_BASE = 0xFFFC0000
-
-# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined)
-BOARDLIBS = drivers/nand_legacy/libnand_legacy.a

board/esd/canbt/canbt.c

@@ -26,6 +26,7 @@
 #include <asm/processor.h>
 #include <command.h>
 
+DECLARE_GLOBAL_DATA_PTR;
 
 /*cmd_boot.c*/
 extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
@@ -50,8 +51,6 @@ const unsigned char fpgadata[] = {
 
 int board_early_init_f (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	unsigned long cntrl0Reg;
 	int index, len, i;
 	int status;

board/esd/cms700/cms700.c

@@ -26,10 +26,10 @@
 #include <command.h>
 #include <malloc.h>
 
+DECLARE_GLOBAL_DATA_PTR;
 
 extern void lxt971_no_sleep(void);
 
-
 /* fpga configuration data - not compressed, generated by bin2c */
 const unsigned char fpgadata[] =
 {
@@ -87,8 +87,6 @@ int misc_init_f (void)
 
 int misc_init_r (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	/* adjust flash start and offset */
 	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
 	gd->bd->bi_flashoffset = 0;

board/esd/cms700/config.mk

@@ -26,6 +26,3 @@
 #
 
 TEXT_BASE = 0xFFFC0000
-
-# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined)
-BOARDLIBS = drivers/nand_legacy/libnand_legacy.a

board/esd/common/auto_update.c

@@ -24,8 +24,8 @@
 
 #include <common.h>
 
-#ifndef CFG_NAND_LEGACY
-#error CFG_NAND_LEGACY not defined in a file using the legacy NAND support!
+#if (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY)
+#warning CFG_NAND_LEGACY not defined in a file using the legacy NAND support!
 #endif
 
 #include <command.h>
@@ -74,7 +74,7 @@ extern int flash_write (char *, ulong, ulong);
 /* change char* to void* to shutup the compiler */
 extern block_dev_desc_t *get_dev (char*, int);
 
-#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#if (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY)
 /* references to names in cmd_nand.c */
 #define NANDRW_READ	0x01
 #define NANDRW_WRITE	0x00
@@ -84,7 +84,7 @@ extern struct nand_chip nand_dev_desc[];
 extern int nand_legacy_rw(struct nand_chip* nand, int cmd, size_t start, size_t len,
 		   size_t * retlen, u_char * buf);
 extern int nand_legacy_erase(struct nand_chip* nand, size_t ofs, size_t len, int clean);
-#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */
+#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY) */
 
 extern block_dev_desc_t ide_dev_desc[CFG_IDE_MAXDEVICE];
 
@@ -188,7 +188,7 @@ int au_do_update(int i, long sz)
 	int off, rc;
 	uint nbytes;
 	int k;
-#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#if (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY)
 	int total;
 #endif
 
@@ -262,7 +262,7 @@ int au_do_update(int i, long sz)
 			debug ("flash_sect_erase(%lx, %lx);\n", start, end);
 			flash_sect_erase(start, end);
 		} else {
-#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#if (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY)
 			printf("Updating NAND FLASH with image %s\n", au_image[i].name);
 			debug ("nand_legacy_erase(%lx, %lx);\n", start, end);
 			rc = nand_legacy_erase (nand_dev_desc, start, end - start + 1, 0);
@@ -290,7 +290,7 @@ int au_do_update(int i, long sz)
 			debug ("flash_write(%p, %lx %x)\n", addr, start, nbytes);
 			rc = flash_write((char *)addr, start, nbytes);
 		} else {
-#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#if (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY)
 			debug ("nand_legacy_rw(%p, %lx %x)\n", addr, start, nbytes);
 			rc = nand_legacy_rw(nand_dev_desc, NANDRW_WRITE | NANDRW_JFFS2,
 				     start, nbytes, (size_t *)&total, (uchar *)addr);
@@ -308,7 +308,7 @@ int au_do_update(int i, long sz)
 		if (au_image[i].type != AU_NAND) {
 			rc = crc32 (0, (uchar *)(start + off), ntohl(hdr->ih_size));
 		} else {
-#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#if (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY)
 			rc = nand_legacy_rw(nand_dev_desc, NANDRW_READ | NANDRW_JFFS2 | NANDRW_JFFS2_SKIP,
 				     start, nbytes, (size_t *)&total, (uchar *)addr);
 			rc = crc32 (0, (uchar *)(addr + off), ntohl(hdr->ih_size));

board/esd/cpci2dp/cpci2dp.c

@@ -26,6 +26,8 @@
 #include <command.h>
 #include <malloc.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 int board_early_init_f (void)
 {
 	unsigned long cntrl0Reg;
@@ -74,7 +76,6 @@ int misc_init_f (void)
 
 int misc_init_r (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 	unsigned long cntrl0Reg;
 
 	/* adjust flash start and offset */

board/esd/cpci405/config.mk

@@ -38,6 +38,3 @@ TEXT_BASE = 0xFFFD0000
 endif
 endif
 endif
-
-# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined)
-BOARDLIBS = drivers/nand_legacy/libnand_legacy.a

board/esd/cpci405/cpci405.c

@@ -27,7 +27,8 @@
 #include <malloc.h>
 #include <net.h>
 
-/* ------------------------------------------------------------------------- */
+DECLARE_GLOBAL_DATA_PTR;
+
 extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);       /*cmd_boot.c*/
 #if 0
 #define FPGA_DEBUG
@@ -100,8 +101,6 @@ int board_early_init_f (void)
 #endif
 
 #ifdef FPGA_DEBUG
-	DECLARE_GLOBAL_DATA_PTR;
-
 	/* set up serial port with default baudrate */
 	(void) get_clocks ();
 	gd->baudrate = CONFIG_BAUDRATE;
@@ -126,8 +125,6 @@ int board_early_init_f (void)
 		if (status != 0) {
 			/* booting FPGA failed */
 #ifndef FPGA_DEBUG
-			DECLARE_GLOBAL_DATA_PTR;
-
 			/* set up serial port with default baudrate */
 			(void) get_clocks ();
 			gd->baudrate = CONFIG_BAUDRATE;
@@ -268,7 +265,6 @@ int misc_init_f (void)
 
 int misc_init_r (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 	unsigned long cntrl0Reg;
 
 	/* adjust flash start and offset */
@@ -707,8 +703,6 @@ U_BOOT_CMD(
  */
 int do_get_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	bd_t *bd = gd->bd;
 	char *buf;
 	ulong crc;

board/esd/cpci750/mpsc.c

@@ -42,6 +42,8 @@
 
 #include "../../Marvell/include/memory.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* Define this if you wish to use the MPSC as a register based UART.
  * This will force the serial port to not use the SDMA engine at all.
  */
@@ -157,7 +159,6 @@ char mpsc_getchar_debug (void)
  * global variables [josh] */
 int mpsc_putchar_early (char ch)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 	int mpsc = CHANNEL;
 	int temp =
 		GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
@@ -510,7 +511,6 @@ void mpsc_init2 (void)
 
 int galbrg_set_baudrate (int channel, int rate)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 	int clock;
 
 	galbrg_disable (channel);	/*ok */

board/esd/cpci750/mv_eth.c

@@ -733,6 +733,7 @@ int mv64360_eth_xmit (struct eth_device *dev, volatile void *dataPtr,
 	pkt_info.cmd_sts = ETH_TX_FIRST_DESC | ETH_TX_LAST_DESC;	/* DMA owned, first last */
 	pkt_info.byte_cnt = dataSize;
 	pkt_info.buf_ptr = (unsigned int) dataPtr;
+	pkt_info.return_info = 0;
 
 	status = eth_port_send (ethernet_private, ETH_Q0, &pkt_info);
 	if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL)) {

board/esd/cpci750/sdram_init.c

@@ -45,6 +45,7 @@
 #include "64360.h"
 #include "mv_regs.h"
 
+DECLARE_GLOBAL_DATA_PTR;
 
 #undef	DEBUG
 /* #define DEBUG */
@@ -250,8 +251,6 @@ NSto10PS(unsigned char spd_byte)
 /* static int check_dimm(uchar slot, AUX_MEM_DIMM_INFO *info) */
 static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	unsigned long spd_checksum;
 
 	uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR;

board/esd/cpci750/serial.c

@@ -38,13 +38,12 @@
 #include "../../Marvell/include/memory.h"
 #include "serial.h"
 
-
 #include "mpsc.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 int serial_init (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	mpsc_init (gd->baudrate);
 
 	return (0);
@@ -70,8 +69,6 @@ int serial_tstc (void)
 
 void serial_setbrg (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	galbrg_set_baudrate (CONFIG_MPSC_PORT, gd->baudrate);
 }
 

board/esd/cpciiser4/cpciiser4.c

@@ -26,6 +26,8 @@
 #include <asm/processor.h>
 #include <command.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /*cmd_boot.c*/
 
 extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
@@ -55,8 +57,6 @@ const unsigned char fpgadata[] = {
 
 int board_early_init_f (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	int index, len, i;
 	volatile unsigned char dummy;
 	int status;

board/esd/dp405/dp405.c

@@ -26,6 +26,7 @@
 #include <command.h>
 #include <malloc.h>
 
+DECLARE_GLOBAL_DATA_PTR;
 
 /* fpga configuration data - not compressed, generated by bin2c */
 const unsigned char fpgadata[] =
@@ -84,8 +85,6 @@ int misc_init_f (void)
 
 int misc_init_r (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	/* adjust flash start and offset */
 	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
 	gd->bd->bi_flashoffset = 0;

board/esd/du405/du405.c

@@ -28,6 +28,8 @@
 #include <405gp_i2c.h>
 #include <command.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /*cmd_boot.c*/
 
 extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
@@ -55,8 +57,6 @@ const unsigned char fpgadata[] = {
 
 int board_early_init_f (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	int index, len, i;
 	int status;
 

board/esd/hh405/config.mk

@@ -29,6 +29,3 @@
 TEXT_BASE = 0xFFF80000
 #TEXT_BASE = 0xFFFC0000
 #TEXT_BASE = 0x00FC0000
-
-# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined)
-BOARDLIBS = drivers/nand_legacy/libnand_legacy.a

board/esd/hh405/hh405.c

@@ -34,6 +34,8 @@
 #include <pci.h>
 #include <sm501.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #ifdef CONFIG_VIDEO_SM501
 
 #define SWAP32(x)	 ((((x) & 0x000000ff) << 24) | (((x) & 0x0000ff00) << 8)|\
@@ -358,8 +360,6 @@ int board_early_init_f (void)
 
 int cf_enable(void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	int i;
 
 	volatile unsigned short *fpga_ctrl =
@@ -391,8 +391,6 @@ int cf_enable(void)
 
 int misc_init_r (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	volatile unsigned short *fpga_ctrl =
 		(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
 	volatile unsigned short *lcd_contrast =
@@ -628,8 +626,6 @@ int misc_init_r (void)
 
 int checkboard (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	char str[64];
 	int i = getenv_r ("serial#", str, sizeof(str));
 
@@ -673,8 +669,6 @@ long int initdram (int board_type)
 #ifdef CONFIG_IDE_RESET
 void ide_set_reset(int on)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	volatile unsigned short *fpga_mode =
 		(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
 	volatile unsigned short *fpga_status =
@@ -788,8 +782,6 @@ U_BOOT_CMD(eepwren,	2,	0,	do_eep_wren,
  */
 void video_get_info_str (int line_number, char *info)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	char str[64];
 	char str2[64];
 	int i = getenv_r("serial#", str2, sizeof(str));

board/esd/hub405/config.mk

@@ -26,6 +26,3 @@
 #
 
 TEXT_BASE = 0xFFFC0000
-
-# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined)
-BOARDLIBS = drivers/nand_legacy/libnand_legacy.a

board/esd/hub405/hub405.c

@@ -26,10 +26,10 @@
 #include <command.h>
 #include <malloc.h>
 
+DECLARE_GLOBAL_DATA_PTR;
 
 extern void lxt971_no_sleep(void);
 
-
 int board_revision(void)
 {
 	unsigned long osrl_reg;
@@ -110,8 +110,6 @@ int misc_init_f (void)
 
 int misc_init_r (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	volatile unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
 	volatile unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
 	volatile unsigned char *duart2_mcr = (unsigned char *)((ulong)DUART2_BA + 4);
@@ -208,8 +206,6 @@ int misc_init_r (void)
  */
 int checkboard (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	char str[64];
 	int i = getenv_r ("serial#", str, sizeof(str));
 

board/esd/pci405/pci405.c

@@ -30,6 +30,7 @@
 
 #include "pci405.h"
 
+DECLARE_GLOBAL_DATA_PTR;
 
 /* Prototypes */
 int gunzip(void *, int, unsigned char *, unsigned long *);
@@ -111,8 +112,6 @@ int board_revision(void)
 
 unsigned long fpga_done_state(void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	if (gd->board_type < 2) {
 		return FPGA_DONE_STATE_V11;
 	} else {
@@ -123,8 +122,6 @@ unsigned long fpga_done_state(void)
 
 unsigned long fpga_init_state(void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	if (gd->board_type < 2) {
 		return FPGA_INIT_STATE_V11;
 	} else {
@@ -320,8 +317,6 @@ int misc_init_r (void)
 
 int checkboard (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	char str[64];
 	int i = getenv_r ("serial#", str, sizeof(str));
 

board/esd/plu405/config.mk

@@ -27,6 +27,3 @@
 
 TEXT_BASE = 0xFFFC0000
 #TEXT_BASE = 0x00FC0000
-
-# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined)
-BOARDLIBS = drivers/nand_legacy/libnand_legacy.a

board/esd/pmc405/pmc405.c

@@ -29,10 +29,10 @@
 #include <command.h>
 #include <malloc.h>
 
+DECLARE_GLOBAL_DATA_PTR;
 
 extern void lxt971_no_sleep(void);
 
-
 /* fpga configuration data - not compressed, generated by bin2c */
 const unsigned char fpgadata[] =
 {
@@ -100,8 +100,6 @@ int board_early_init_f (void)
 
 int misc_init_r (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	/* adjust flash start and offset */
 	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
 	gd->bd->bi_flashoffset = 0;

board/esd/voh405/config.mk

@@ -26,6 +26,3 @@
 #
 
 TEXT_BASE = 0xFFF80000
-
-# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined)
-BOARDLIBS = drivers/nand_legacy/libnand_legacy.a

board/esd/vom405/vom405.c

@@ -26,10 +26,10 @@
 #include <command.h>
 #include <malloc.h>
 
+DECLARE_GLOBAL_DATA_PTR;
 
 extern void lxt971_no_sleep(void);
 
-
 /* fpga configuration data - not compressed, generated by bin2c */
 const unsigned char fpgadata[] =
 {
@@ -81,8 +81,6 @@ int board_early_init_f (void)
 
 int misc_init_r (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	/* adjust flash start and offset */
 	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
 	gd->bd->bi_flashoffset = 0;

board/esd/wuh405/config.mk

@@ -26,6 +26,3 @@
 #
 
 TEXT_BASE = 0xFFFC0000
-
-# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined)
-BOARDLIBS = drivers/nand_legacy/libnand_legacy.a

board/etin/debris/debris.c

@@ -26,6 +26,8 @@
 #include <pci.h>
 #include <i2c.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 int checkboard (void)
 {
 	/*TODO: Check processor type */
@@ -170,8 +172,6 @@ void nvram_write(long dest, const void *src, size_t count)
 
 int misc_init_r(void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	/* Write ethernet addr in NVRAM for VxWorks */
 	nvram_write(CFG_ENV_ADDR + CFG_NVRAM_VXWORKS_OFFS,
 			(char*)&gd->bd->bi_enetaddr[0], 6);

board/etx094/etx094.c

@@ -24,6 +24,8 @@
 #include <common.h>
 #include <mpc8xx.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* ------------------------------------------------------------------------- */
 
 static long int dram_size (long int, long int *, long int);
@@ -90,8 +92,6 @@ const uint sdram_table[] = {
 
 int checkboard (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	char *s = getenv ("serial#");
 	char *e;
 

board/evb4510/evb4510.c

@@ -25,6 +25,8 @@
 #include <asm/hardware.h>
 #include <command.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #ifdef CONFIG_EVB4510
 
 /* ------------------------------------------------------------------------- */
@@ -35,8 +37,6 @@
 
 int board_init (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	icache_enable();
 
 	/* address for the kernel command line */
@@ -52,7 +52,6 @@ int board_init (void)
 
 int dram_init (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size  = PHYS_SDRAM_1_SIZE;
 #if CONFIG_NR_DRAM_BANKS == 2

board/evb64260/evb64260.c

@@ -37,6 +37,9 @@
 #include "mpsc.h"
 #include "i2c.h"
 #include "64260.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
 #ifdef CONFIG_ZUMA_V2
 extern void zuma_mbox_init(void);
 #endif
@@ -323,8 +326,6 @@ int misc_init_r (void)
 void
 after_reloc(ulong dest_addr)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	/* check to see if we booted from the sram.  If so, move things
 	 * back to the way they should be. (we're running from main
 	 * memory at this point now */

board/evb64260/mpsc.c

@@ -32,6 +32,8 @@
 #include <malloc.h>
 #include "mpsc.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 int (*mpsc_putchar)(char ch) = mpsc_putchar_early;
 
 static volatile unsigned int *rx_desc_base=NULL;
@@ -115,7 +117,6 @@ struct _tag_mirror_hack {
 int
 mpsc_putchar_early(char ch)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 	int mpsc=CHANNEL;
 	int temp=GTREGREAD_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP);
 	galmpsc_set_tcschar(mpsc,ch);
@@ -177,79 +178,82 @@ mpsc_putchar_sdma(char ch)
 	return 0;
 }
 
-char
-mpsc_getchar(void)
+char mpsc_getchar (void)
 {
-    DECLARE_GLOBAL_DATA_PTR;
-    static unsigned int done = 0;
-    volatile char ch;
-    unsigned int len=0, idx=0, temp;
-
-    volatile unsigned int *p;
-
-
-    do {
-	p=&rx_desc_base[rx_desc_index*8];
-
-	INVALIDATE_DCACHE(&p[0], &p[1]);
-	/* Wait for character */
-	while (p[1] & DESC_OWNER){
-	    udelay(100);
-	    INVALIDATE_DCACHE(&p[0], &p[1]);
-	}
-
-	/* Handle error case */
-	if (p[1] & (1<<15)) {
-		printf("oops, error: %08x\n", p[1]);
-
-		temp = GTREGREAD_MIRROR(GALMPSC_CHANNELREG_2,CHANNEL,GALMPSC_REG_GAP);
-		temp |= (1 << 23);
-		GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_2, CHANNEL,GALMPSC_REG_GAP, temp);
-
-		/* Can't poll on abort bit, so we just wait. */
-		udelay(100);
+	static unsigned int done = 0;
+	volatile char ch;
+	unsigned int len = 0, idx = 0, temp;
 
-		galsdma_enable_rx();
-	}
-
-	/* Number of bytes left in this descriptor */
-	len = p[0] & 0xffff;
-
-	if (len) {
-	    /* Where to look */
-	    idx = 5;
-	    if (done > 3) idx = 4;
-	    if (done > 7) idx = 7;
-	    if (done > 11) idx = 6;
-
-	    INVALIDATE_DCACHE(&p[idx], &p[idx+1]);
-	    ch = p[idx] & 0xff;
-	    done++;
-	}
+	volatile unsigned int *p;
 
-	if (done < len) {
-		/* this descriptor has more bytes still
-		 * shift down the char we just read, and leave the
-		 * buffer in place for the next time around
-		 */
-		p[idx] =  p[idx] >> 8;
-		FLUSH_DCACHE(&p[idx], &p[idx+1]);
-	}
 
-	if (done == len) {
-		/* nothing left in this descriptor.
-		 * go to next one
-		 */
-		p[1] = DESC_OWNER | DESC_FIRST | DESC_LAST;
-		p[0] = 0x00100000;
-		FLUSH_DCACHE(&p[0], &p[1]);
-		/* Next descriptor */
-		rx_desc_index = (rx_desc_index + 1) % RX_DESC;
-		done = 0;
-	}
-    } while (len==0);	/* galileo bug.. len might be zero */
-
-    return ch;
+	do {
+		p = &rx_desc_base[rx_desc_index * 8];
+
+		INVALIDATE_DCACHE (&p[0], &p[1]);
+		/* Wait for character */
+		while (p[1] & DESC_OWNER) {
+			udelay (100);
+			INVALIDATE_DCACHE (&p[0], &p[1]);
+		}
+
+		/* Handle error case */
+		if (p[1] & (1 << 15)) {
+			printf ("oops, error: %08x\n", p[1]);
+
+			temp = GTREGREAD_MIRROR (GALMPSC_CHANNELREG_2,
+						 CHANNEL, GALMPSC_REG_GAP);
+			temp |= (1 << 23);
+			GT_REG_WRITE_MIRROR (GALMPSC_CHANNELREG_2, CHANNEL,
+					     GALMPSC_REG_GAP, temp);
+
+			/* Can't poll on abort bit, so we just wait. */
+			udelay (100);
+
+			galsdma_enable_rx ();
+		}
+
+		/* Number of bytes left in this descriptor */
+		len = p[0] & 0xffff;
+
+		if (len) {
+			/* Where to look */
+			idx = 5;
+			if (done > 3)
+				idx = 4;
+			if (done > 7)
+				idx = 7;
+			if (done > 11)
+				idx = 6;
+
+			INVALIDATE_DCACHE (&p[idx], &p[idx + 1]);
+			ch = p[idx] & 0xff;
+			done++;
+		}
+
+		if (done < len) {
+			/* this descriptor has more bytes still
+			 * shift down the char we just read, and leave the
+			 * buffer in place for the next time around
+			 */
+			p[idx] = p[idx] >> 8;
+			FLUSH_DCACHE (&p[idx], &p[idx + 1]);
+		}
+
+		if (done == len) {
+			/* nothing left in this descriptor.
+			 * go to next one
+			 */
+			p[1] = DESC_OWNER | DESC_FIRST | DESC_LAST;
+			p[0] = 0x00100000;
+			FLUSH_DCACHE (&p[0], &p[1]);
+			/* Next descriptor */
+			rx_desc_index = (rx_desc_index + 1) % RX_DESC;
+			done = 0;
+		}
+	} while (len == 0);	/* galileo bug.. len might be zero */
+
+	return ch;
 }
 
 int
@@ -266,8 +270,6 @@ mpsc_test_char(void)
 int
 mpsc_init(int baud)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	memset(MIRROR_HACK, 0, sizeof(struct _tag_mirror_hack));
 	MIRROR_HACK->GALMPSC_ROUTING_REGISTER_M=0x3fffffff;
 
@@ -382,7 +384,6 @@ mpsc_init2(void)
 int
 galbrg_set_baudrate(int channel, int rate)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 	int clock;
 
 	galbrg_disable(channel);
@@ -410,7 +411,6 @@ galbrg_set_baudrate(int channel, int rate)
 static int
 galbrg_set_CDV(int channel, int value)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 	unsigned int temp;
 
 	temp = GTREGREAD_MIRROR(GALBRG_0_CONFREG, channel, GALBRG_REG_GAP);
@@ -424,7 +424,6 @@ galbrg_set_CDV(int channel, int value)
 static int
 galbrg_enable(int channel)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 	unsigned int temp;
 
 	temp = GTREGREAD_MIRROR(GALBRG_0_CONFREG, channel, GALBRG_REG_GAP);
@@ -437,7 +436,6 @@ galbrg_enable(int channel)
 static int
 galbrg_disable(int channel)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 	unsigned int temp;
 
 	temp = GTREGREAD_MIRROR(GALBRG_0_CONFREG, channel, GALBRG_REG_GAP);
@@ -450,7 +448,6 @@ galbrg_disable(int channel)
 static int
 galbrg_set_clksrc(int channel, int value)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 	unsigned int temp;
 
 	temp = GTREGREAD_MIRROR(GALBRG_0_CONFREG,channel, GALBRG_REG_GAP);
@@ -583,7 +580,6 @@ galsdma_set_burstsize(int channel, unsigned int value)
 static int
 galmpsc_connect(int channel, int connect)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 	unsigned int temp;
 
 	temp = GTREGREAD_MIRROR_G(GALMPSC_ROUTING_REGISTER);
@@ -629,7 +625,6 @@ galmpsc_route_serial(int channel, int connect)
 static int
 galmpsc_route_rx_clock(int channel, int brg)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 	unsigned int temp;
 
 	temp = GTREGREAD_MIRROR_G(GALMPSC_RxC_ROUTE);
@@ -647,7 +642,6 @@ galmpsc_route_rx_clock(int channel, int brg)
 static int
 galmpsc_route_tx_clock(int channel, int brg)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 	unsigned int temp;
 
 	temp = GTREGREAD_MIRROR_G(GALMPSC_TxC_ROUTE);
@@ -688,7 +682,6 @@ galmpsc_write_config_regs(int mpsc, int mode)
 static int
 galmpsc_config_channel_regs(int mpsc)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 	GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_1,mpsc,GALMPSC_REG_GAP, 0);
 	GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP, 0);
 	GT_REG_WRITE(GALMPSC_CHANNELREG_3+(mpsc*GALMPSC_REG_GAP), 1);
@@ -709,7 +702,6 @@ galmpsc_config_channel_regs(int mpsc)
 static int
 galmpsc_set_brkcnt(int mpsc, int value)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 	unsigned int temp;
 
 	temp = GTREGREAD_MIRROR(GALMPSC_CHANNELREG_1,mpsc,GALMPSC_REG_GAP);
@@ -723,7 +715,6 @@ galmpsc_set_brkcnt(int mpsc, int value)
 static int
 galmpsc_set_tcschar(int mpsc, int value)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 	unsigned int temp;
 
 	temp = GTREGREAD_MIRROR(GALMPSC_CHANNELREG_1,mpsc,GALMPSC_REG_GAP);
@@ -737,7 +728,6 @@ galmpsc_set_tcschar(int mpsc, int value)
 static int
 galmpsc_set_char_length(int mpsc, int value)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 	unsigned int temp;
 
 	temp = GTREGREAD_MIRROR(GALMPSC_PROTOCONF_REG,mpsc,GALMPSC_REG_GAP);
@@ -751,7 +741,6 @@ galmpsc_set_char_length(int mpsc, int value)
 static int
 galmpsc_set_stop_bit_length(int mpsc, int value)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 	unsigned int temp;
 
 	temp = GTREGREAD_MIRROR(GALMPSC_PROTOCONF_REG,mpsc,GALMPSC_REG_GAP);
@@ -764,7 +753,6 @@ galmpsc_set_stop_bit_length(int mpsc, int value)
 static int
 galmpsc_set_parity(int mpsc, int value)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 	unsigned int temp;
 
 	temp = GTREGREAD_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP);
@@ -784,7 +772,6 @@ galmpsc_set_parity(int mpsc, int value)
 static int
 galmpsc_enter_hunt(int mpsc)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 	int temp;
 
 	temp = GTREGREAD_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP);
@@ -802,7 +789,6 @@ galmpsc_enter_hunt(int mpsc)
 static int
 galmpsc_shutdown(int mpsc)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 #if 0
 	unsigned int temp;
 

board/evb64260/sdram_init.c

@@ -35,6 +35,8 @@
 #include "i2c.h"
 #include "64260.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* #define	DEBUG */
 #define	MAP_PCI
 
@@ -199,7 +201,6 @@ static int check_dimm (uchar slot, sdram_info_t * info)
  * the array which is passed in with the relevant information */
 static int check_dimm (uchar slot, sdram_info_t * info)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 	uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR;
 	int ret;
 	uchar rows, cols, sdram_banks, supp_cal, width, cal_val;

board/evb64260/serial.c

@@ -39,6 +39,8 @@
 
 #include "mpsc.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #if (defined CFG_INIT_CHAN1) || (defined CFG_INIT_CHAN2)
 const NS16550_t COM_PORTS[] = { (NS16550_t) CFG_NS16550_COM1,
 				(NS16550_t) CFG_NS16550_COM2 };
@@ -48,8 +50,6 @@ const NS16550_t COM_PORTS[] = { (NS16550_t) CFG_NS16550_COM1,
 
 int serial_init (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 #if (defined CFG_INIT_CHAN1) || (defined CFG_INIT_CHAN2)
 	int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate;
 #endif
@@ -90,8 +90,6 @@ serial_tstc(void)
 void
 serial_setbrg (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	galbrg_set_baudrate(CONFIG_MPSC_PORT, gd->baudrate);
 }
 
@@ -99,8 +97,6 @@ serial_setbrg (void)
 
 int serial_init (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate;
 
 #ifdef CFG_INIT_CHAN1
@@ -137,8 +133,6 @@ serial_tstc(void)
 void
 serial_setbrg (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate;
 
 #ifdef CFG_INIT_CHAN1

board/ezkit533/ezkit533.c

@@ -30,6 +30,8 @@
 #include "psd4256.h"
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 int checkboard(void)
 {
 	printf("CPU:   ADSP BF533 Rev.: 0.%d\n", *pCHIPID >> 28);
@@ -41,7 +43,6 @@ int checkboard(void)
 
 long int initdram(int board_type)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 #ifdef DEBUG
 	int brate;
 	char *tmp = getenv("baudrate");

board/gcplus/gcplus.c

@@ -26,7 +26,8 @@
 
 #include <common.h>
 #include <SA-1100.h>
-/* ------------------------------------------------------------------------- */
+
+DECLARE_GLOBAL_DATA_PTR;
 
 /*
  * Miscelaneous platform dependent initialisations
@@ -35,8 +36,6 @@
 int
 board_init(void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	gd->bd->bi_arch_number = MACH_TYPE_GRAPHICSCLIENT;
 
 	gd->bd->bi_boot_params = 0xc000003c; /* Weird address? */
@@ -62,8 +61,6 @@ board_init(void)
 int
 dram_init(void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;

board/gen860t/fpga.c

@@ -32,6 +32,8 @@
 #include <command.h>
 #include "fpga.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #if (CONFIG_FPGA)
 
 #if 0
@@ -189,8 +191,6 @@ void fpga_selectmap_init (void)
  */
 int gen860t_init_fpga (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	int i;
 
 	PRINTF ("%s:%d: Initialize FPGA interface (relocation offset = 0x%.8lx)\n", __FUNCTION__, __LINE__, gd->reloc_off);

board/gen860t/gen860t.c

@@ -30,6 +30,8 @@
 #include "fpga.h"
 #include "ioport.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #ifdef CONFIG_STATUS_LED
 #include <status_led.h>
 #endif
@@ -126,8 +128,6 @@ const uint selectmap_upm_table[] = {
  */
 int checkboard (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	char *s;
 	char buf[64];
 	int i;
@@ -305,5 +305,3 @@ int post_hotkeys_pressed (void)
 	return 0;		/* No hotkeys supported */
 }
 #endif
-
-/* vim: set ts=4 sw=4 tw=78 : */

board/hermes/hermes.c

@@ -32,6 +32,8 @@
 # define SHOW_BOOT_PROGRESS(arg)
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* ------------------------------------------------------------------------- */
 
 static long int dram_size (long int, long int *, long int);
@@ -105,8 +107,6 @@ const uint sdram_table[] = {
 
 int checkboard (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	char *s = getenv ("serial#");
 	char *e;
 

board/hymod/bsp.c

@@ -28,6 +28,8 @@
 #include <net.h>
 #include <asm/iopin_8260.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /*-----------------------------------------------------------------------
  * Board Special Commands: FPGA load/store, EEPROM erase
  */
@@ -75,8 +77,6 @@
 int
 fpga_load (int mezz, uchar *addr, ulong size)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	hymod_conf_t *cp = &gd->bd->bi_hymod_conf;
 	xlx_info_t *fp;
 	xlx_iopins_t *fpgaio;

board/hymod/env.c

@@ -23,6 +23,8 @@
 
 #include <common.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* imports from fetch.c */
 extern int fetch_and_parse (char *, ulong, int (*)(uchar *, uchar *));
 
@@ -32,8 +34,6 @@ static char *def_global_env_path = "/hymod/global_env";
 static int
 env_callback (uchar *name, uchar *value)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	hymod_conf_t *cp = &gd->bd->bi_hymod_conf;
 	char ov[CFG_CBSIZE], nv[CFG_CBSIZE], *p, *q, *nn, c, *curver, *newver;
 	int override = 1, append = 0, remove = 0, nnl, ovl, nvl;

board/hymod/hymod.c

@@ -30,6 +30,8 @@
 #include <i2c.h>
 #include <asm/iopin_8260.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* ------------------------------------------------------------------------- */
 
 /* imports from eeprom.c */
@@ -424,8 +426,6 @@ initdram (int board_type)
 int
 last_stage_init (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	hymod_conf_t *cp = &gd->bd->bi_hymod_conf;
 	int rc;
 

board/icecube/icecube.c

@@ -27,6 +27,7 @@
 #include <common.h>
 #include <mpc5xxx.h>
 #include <pci.h>
+#include <asm/processor.h>
 
 #if defined(CONFIG_LITE5200B)
 #include "mt46v32m16.h"
@@ -89,6 +90,8 @@ long int initdram (int board_type)
 {
 	ulong dramsize = 0;
 	ulong dramsize2 = 0;
+	uint svr, pvr;
+
 #ifndef CFG_RAMBOOT
 	ulong test1, test2;
 
@@ -183,6 +186,24 @@ long int initdram (int board_type)
 
 #endif /* CFG_RAMBOOT */
 
+	/*
+	 * On MPC5200B we need to set the special configuration delay in the
+	 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
+	 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
+	 *
+	 * "The SDelay should be written to a value of 0x00000004. It is
+	 * required to account for changes caused by normal wafer processing
+	 * parameters."
+	 */
+	svr = get_svr();
+	pvr = get_pvr();
+	if ((SVR_MJREV(svr) >= 2) &&
+	    (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
+
+		*(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
+		__asm__ volatile ("sync");
+	}
+
 	return dramsize + dramsize2;
 }
 

board/ids8247/ids8247.c

@@ -25,6 +25,8 @@
 #include <ioports.h>
 #include <mpc8260.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /*
  * I/O Port configuration table
  *
@@ -295,8 +297,6 @@ long int initdram (int board_type)
 
 int misc_init_r (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	gd->bd->bi_flashstart = 0xff800000;
 }
 

board/impa7/impa7.c

@@ -25,6 +25,8 @@
 #include <common.h>
 #include <clps7111.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* ------------------------------------------------------------------------- */
 
 
@@ -34,8 +36,6 @@
 
 int board_init (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	/* Activate LED flasher */
 	IO_LEDFLSH = 0x40;
 
@@ -50,8 +50,6 @@ int board_init (void)
 
 int dram_init (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;

board/innokom/innokom.c

@@ -27,6 +27,8 @@
 #include <asm/arch/pxa-regs.h>
 #include <asm/mach-types.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #ifdef CONFIG_SHOW_BOOT_PROGRESS
 # define SHOW_BOOT_PROGRESS(arg)        show_boot_progress(arg)
 #else
@@ -95,8 +97,6 @@ int misc_init_r(void)
 
 int board_init (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	/* memory and cpu-speed are setup before relocation */
 	/* so we do _nothing_ here */
 
@@ -116,8 +116,6 @@ int board_init (void)
 
 int dram_init (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 

board/integratorap/integratorap.c

@@ -39,6 +39,8 @@
 #include <pci.h>
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 void flash__init (void);
 void ether__init (void);
 void peripheral_power_enable (void);
@@ -65,8 +67,6 @@ static inline void delay (unsigned long loops)
 
 int board_init (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	/* arch number of Integrator Board */
 	gd->bd->bi_arch_number = MACH_TYPE_INTEGRATOR;
 
@@ -480,8 +480,6 @@ void ether__init (void)
 ******************************/
 int dram_init (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size	 = PHYS_SDRAM_1_SIZE;
 

board/integratorcp/integratorcp.c

@@ -35,6 +35,8 @@
 
 #include <common.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 void flash__init (void);
 void ether__init (void);
 void peripheral_power_enable (void);
@@ -54,8 +56,6 @@ void show_boot_progress(int progress)
 
 int board_init (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	/* arch number of Integrator Board */
 	gd->bd->bi_arch_number = MACH_TYPE_CINTEGRATOR;
 
@@ -105,8 +105,6 @@ void ether__init (void)
 ******************************/
 int dram_init (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size	 = PHYS_SDRAM_1_SIZE;
 

board/ixdp425/ixdp425.c

@@ -28,11 +28,7 @@
 #include <asm/arch/ixp425.h>
 #include <common.h>
 
-/* ------------------------------------------------------------------------- */
-
-
-/* local prototypes */
-
+DECLARE_GLOBAL_DATA_PTR;
 
 /*
  * Miscelaneous platform dependent initialisations
@@ -49,8 +45,6 @@ int board_post_init (void)
 
 int board_init (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	/* arch number of IXDP */
 	gd->bd->bi_arch_number = MACH_TYPE_IXDP425;
 
@@ -64,8 +58,6 @@ int board_init (void)
 
 int dram_init (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size  = PHYS_SDRAM_1_SIZE;