keymile: Fix Coding style issues for keymile boards.

- use I/O accessors
  -> For accessing the FPGA therefore a struct km_bec_fpga
     is introduced.
- no longer externs needed
- to defines, that only select functions, don;t assign a
  numeric value
- Codingstyle changes to prevent checkpatch errors/warnings

Signed-off-by: Heiko Schocher <hs@denx.de>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
cc: Kim Phillips <kim.phillips@freescale.com>
cc: Holger Brunck <holger.brunck@keymile.com>
cc: Wolfgang Denk <wd@denx.de>
cc: Detlev Zundel <dzu@denx.de>
cc: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>

board/keymile/common/common.c

@@ -39,9 +39,7 @@
 #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
 #include <i2c.h>
 
-extern int i2c_soft_read_pin (void);
-
-int ivm_calc_crc (unsigned char *buf, int len)
+int ivm_calc_crc(unsigned char *buf, int len)
 {
 	const unsigned short crc_tab[16] = {
 		0x0000, 0xCC01, 0xD801, 0x1400,
@@ -71,20 +69,20 @@ int ivm_calc_crc (unsigned char *buf, int len)
 	return crc;
 }
 
-static int  ivm_set_value (char *name, char *value)
+static int ivm_set_value(char *name, char *value)
 {
 	char tempbuf[256];
 
 	if (value != NULL) {
-		sprintf (tempbuf, "%s=%s", name, value);
-		return set_local_var (tempbuf, 0);
+		sprintf(tempbuf, "%s=%s", name, value);
+		return set_local_var(tempbuf, 0);
 	} else {
-		unset_local_var (name);
+		unset_local_var(name);
 	}
 	return 0;
 }
 
-static int ivm_get_value (unsigned char *buf, int len, char *name, int off,
+static int ivm_get_value(unsigned char *buf, int len, char *name, int off,
 				int check)
 {
 	unsigned short	val;
@@ -92,21 +90,21 @@ static int ivm_get_value (unsigned char *buf, int len, char *name, int off,
 
 	if ((buf[off + 0] != buf[off + 2]) &&
 	    (buf[off + 2] != buf[off + 4])) {
-		printf ("%s Error corrupted %s\n", __FUNCTION__, name);
+		printf("%s Error corrupted %s\n", __func__, name);
 		val = -1;
 	} else {
 		val = buf[off + 0] + (buf[off + 1] << 8);
 		if ((val == 0) && (check == 1))
 			val = -1;
 	}
-	sprintf ((char *)valbuf, "%x", val);
-	ivm_set_value (name, (char *)valbuf);
+	sprintf((char *)valbuf, "%x", val);
+	ivm_set_value(name, (char *)valbuf);
 	return val;
 }
 
-#define INVENTORYBLOCKSIZE	0x100
-#define INVENTORYDATAADDRESS	0x21
-#define INVENTORYDATASIZE	(INVENTORYBLOCKSIZE - INVENTORYDATAADDRESS - 3)
+#define INV_BLOCKSIZE		0x100
+#define INV_DATAADDRESS		0x21
+#define INVENTORYDATASIZE	(INV_BLOCKSIZE - INV_DATAADDRESS - 3)
 
 #define IVM_POS_SHORT_TEXT		0
 #define IVM_POS_MANU_ID			1
@@ -121,19 +119,19 @@ static int ivm_get_value (unsigned char *buf, int len, char *name, int off,
 #define IVM_POS_HISTORY			10
 #define IVM_POS_SYMBOL_ONLY		11
 
-static char convert_char (char c)
+static char convert_char(char c)
 {
 	return (c < ' ' || c > '~') ? '.' : c;
 }
 
-static int ivm_findinventorystring (int type,
+static int ivm_findinventorystring(int type,
 					unsigned char* const string,
 					unsigned long maxlen,
 					unsigned char *buf)
 {
 	int xcode = 0;
 	unsigned long cr = 0;
-	unsigned long addr = INVENTORYDATAADDRESS;
+	unsigned long addr = INV_DATAADDRESS;
 	unsigned long size = 0;
 	unsigned long nr = type;
 	int stop = 0; 	/* stop on semicolon */
@@ -157,8 +155,10 @@ static int ivm_findinventorystring (int type,
 		addr++;
 	}
 
-	/* the expected number of CR was found until the end of the IVM
-	 *  content --> fill string */
+	/*
+	 * the expected number of CR was found until the end of the IVM
+	 *  content --> fill string
+	 */
 	if (addr < INVENTORYDATASIZE) {
 		/* Copy the IVM string in the corresponding string */
 		for (; (buf[addr] != '\r')			&&
@@ -170,64 +170,62 @@ static int ivm_findinventorystring (int type,
 						convert_char (buf[addr]));
 		}
 
-		/* copy phase is done: check if everything is ok. If not,
+		/*
+		 * copy phase is done: check if everything is ok. If not,
 		 * the inventory data is most probably corrupted: tell
-		 * the world there is a problem! */
+		 * the world there is a problem!
+		 */
 		if (addr == INVENTORYDATASIZE) {
 			xcode = -1;
-			printf ("Error end of string not found\n");
+			printf("Error end of string not found\n");
 		} else if ((size >= (maxlen - 1)) &&
 			   (buf[addr] != '\r')) {
 			xcode = -1;
-			printf ("string too long till next CR\n");
+			printf("string too long till next CR\n");
 		}
 	} else {
-		/* some CR are missing...
-		 * the inventory data is most probably corrupted */
+		/*
+		 * some CR are missing...
+		 * the inventory data is most probably corrupted
+		 */
 		xcode = -1;
-		printf ("not enough cr found\n");
+		printf("not enough cr found\n");
 	}
 	return xcode;
 }
 
 #define GET_STRING(name, which, len) \
-	if (ivm_findinventorystring (which, valbuf, len, buf) == 0) { \
-		ivm_set_value (name, (char *)valbuf); \
+	if (ivm_findinventorystring(which, valbuf, len, buf) == 0) { \
+		ivm_set_value(name, (char *)valbuf); \
 	}
 
-static int ivm_check_crc (unsigned char *buf, int block)
+static int ivm_check_crc(unsigned char *buf, int block)
 {
 	unsigned long	crc;
 	unsigned long	crceeprom;
 
-	crc = ivm_calc_crc (buf, CONFIG_SYS_IVM_EEPROM_PAGE_LEN - 2);
+	crc = ivm_calc_crc(buf, CONFIG_SYS_IVM_EEPROM_PAGE_LEN - 2);
 	crceeprom = (buf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN - 1] + \
 			buf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN - 2] * 256);
 	if (crc != crceeprom) {
 		if (block == 0)
-			printf ("Error CRC Block: %d EEprom: calculated: \
+			printf("Error CRC Block: %d EEprom: calculated: \
 			%lx EEprom: %lx\n", block, crc, crceeprom);
 		return -1;
 	}
 	return 0;
 }
 
-static int ivm_analyze_block2 (unsigned char *buf, int len)
+static int ivm_analyze_block2(unsigned char *buf, int len)
 {
 	unsigned char	valbuf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN];
 	unsigned long	count;
 
 	/* IVM_MacAddress */
-	sprintf ((char *)valbuf, "%02X:%02X:%02X:%02X:%02X:%02X",
-			buf[1],
-			buf[2],
-			buf[3],
-			buf[4],
-			buf[5],
-			buf[6]);
-	ivm_set_value ("IVM_MacAddress", (char *)valbuf);
-	if (getenv ("ethaddr") == NULL)
-		setenv ((char *)"ethaddr", (char *)valbuf);
+	sprintf((char *)valbuf, "%pM", buf);
+	ivm_set_value("IVM_MacAddress", (char *)valbuf);
+	if (getenv("ethaddr") == NULL)
+		setenv((char *)"ethaddr", (char *)valbuf);
 	/* IVM_MacCount */
 	count = (buf[10] << 24) +
 		   (buf[11] << 16) +
@@ -235,48 +233,52 @@ static int ivm_analyze_block2 (unsigned char *buf, int len)
 		    buf[13];
 	if (count == 0xffffffff)
 		count = 1;
-	sprintf ((char *)valbuf, "%lx", count);
-	ivm_set_value ("IVM_MacCount", (char *)valbuf);
+	sprintf((char *)valbuf, "%lx", count);
+	ivm_set_value("IVM_MacCount", (char *)valbuf);
 	return 0;
 }
 
-int ivm_analyze_eeprom (unsigned char *buf, int len)
+int ivm_analyze_eeprom(unsigned char *buf, int len)
 {
 	unsigned short	val;
 	unsigned char	valbuf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN];
 	unsigned char	*tmp;
 
-	if (ivm_check_crc (buf, 0) != 0)
+	if (ivm_check_crc(buf, 0) != 0)
 		return -1;
 
-	ivm_get_value (buf, CONFIG_SYS_IVM_EEPROM_PAGE_LEN, "IVM_BoardId", 0, 1);
-	val = ivm_get_value (buf, CONFIG_SYS_IVM_EEPROM_PAGE_LEN, "IVM_HWKey", 6, 1);
+	ivm_get_value(buf, CONFIG_SYS_IVM_EEPROM_PAGE_LEN,
+			"IVM_BoardId", 0, 1);
+	val = ivm_get_value(buf, CONFIG_SYS_IVM_EEPROM_PAGE_LEN,
+			"IVM_HWKey", 6, 1);
 	if (val != 0xffff) {
-		sprintf ((char *)valbuf, "%x", ((val /100) % 10));
-		ivm_set_value ("IVM_HWVariant", (char *)valbuf);
-		sprintf ((char *)valbuf, "%x", (val % 100));
-		ivm_set_value ("IVM_HWVersion", (char *)valbuf);
+		sprintf((char *)valbuf, "%x", ((val / 100) % 10));
+		ivm_set_value("IVM_HWVariant", (char *)valbuf);
+		sprintf((char *)valbuf, "%x", (val % 100));
+		ivm_set_value("IVM_HWVersion", (char *)valbuf);
 	}
-	ivm_get_value (buf, CONFIG_SYS_IVM_EEPROM_PAGE_LEN, "IVM_Functions", 12, 0);
+	ivm_get_value(buf, CONFIG_SYS_IVM_EEPROM_PAGE_LEN,
+		"IVM_Functions", 12, 0);
 
 	GET_STRING("IVM_Symbol", IVM_POS_SYMBOL_ONLY, 8)
 	GET_STRING("IVM_DeviceName", IVM_POS_SHORT_TEXT, 64)
 	tmp = (unsigned char *) getenv("IVM_DeviceName");
 	if (tmp) {
-		int	len = strlen ((char *)tmp);
+		int	len = strlen((char *)tmp);
 		int	i = 0;
 
 		while (i < len) {
 			if (tmp[i] == ';') {
-				ivm_set_value ("IVM_ShortText", (char *)&tmp[i + 1]);
+				ivm_set_value("IVM_ShortText",
+					(char *)&tmp[i + 1]);
 				break;
 			}
 			i++;
 		}
 		if (i >= len)
-			ivm_set_value ("IVM_ShortText", NULL);
+			ivm_set_value("IVM_ShortText", NULL);
 	} else {
-		ivm_set_value ("IVM_ShortText", NULL);
+		ivm_set_value("IVM_ShortText", NULL);
 	}
 	GET_STRING("IVM_ManufacturerID", IVM_POS_MANU_ID, 32)
 	GET_STRING("IVM_ManufacturerSerialNumber", IVM_POS_MANU_SERIAL, 20)
@@ -288,14 +290,15 @@ int ivm_analyze_eeprom (unsigned char *buf, int len)
 	GET_STRING("IVM_CustomerID", IVM_POS_CUSTOMER_ID, 32)
 	GET_STRING("IVM_CustomerProductID", IVM_POS_CUSTOMER_PROD_ID, 32)
 
-	if (ivm_check_crc (&buf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN * 2], 2) != 0)
+	if (ivm_check_crc(&buf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN * 2], 2) != 0)
 		return 0;
-	ivm_analyze_block2 (&buf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN * 2], CONFIG_SYS_IVM_EEPROM_PAGE_LEN);
+	ivm_analyze_block2(&buf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN * 2],
+		CONFIG_SYS_IVM_EEPROM_PAGE_LEN);
 
 	return 0;
 }
 
-int ivm_read_eeprom (void)
+int ivm_read_eeprom(void)
 {
 #if defined(CONFIG_I2C_MUX)
 	I2C_MUX_DEVICE *dev = NULL;
@@ -303,33 +306,36 @@ int ivm_read_eeprom (void)
 	uchar i2c_buffer[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
 	uchar	*buf;
 	unsigned dev_addr = CONFIG_SYS_IVM_EEPROM_ADR;
+	int ret;
 
 #if defined(CONFIG_I2C_MUX)
 	/* First init the Bus, select the Bus */
 #if defined(CONFIG_SYS_I2C_IVM_BUS)
-	dev = i2c_mux_ident_muxstring ((uchar *)CONFIG_SYS_I2C_IVM_BUS);
+	dev = i2c_mux_ident_muxstring((uchar *)CONFIG_SYS_I2C_IVM_BUS);
 #else
-	buf = (unsigned char *) getenv ("EEprom_ivm");
+	buf = (unsigned char *) getenv("EEprom_ivm");
 	if (buf != NULL)
-		dev = i2c_mux_ident_muxstring (buf);
+		dev = i2c_mux_ident_muxstring(buf);
 #endif
 	if (dev == NULL) {
-		printf ("Error couldnt add Bus for IVM\n");
+		printf("Error couldnt add Bus for IVM\n");
 		return -1;
 	}
-	i2c_set_bus_num (dev->busid);
+	i2c_set_bus_num(dev->busid);
 #endif
 
-	buf = (unsigned char *) getenv ("EEprom_ivm_addr");
+	buf = (unsigned char *) getenv("EEprom_ivm_addr");
 	if (buf != NULL)
-		dev_addr = simple_strtoul ((char *)buf, NULL, 16);
+		dev_addr = simple_strtoul((char *)buf, NULL, 16);
 
-	if (i2c_read(dev_addr, 0, 1, i2c_buffer, CONFIG_SYS_IVM_EEPROM_MAX_LEN) != 0) {
+	ret = i2c_read(dev_addr, 0, 1, i2c_buffer,
+			CONFIG_SYS_IVM_EEPROM_MAX_LEN);
+	if (ret != 0) {
 		printf ("Error reading EEprom\n");
 		return -2;
 	}
 
-	return ivm_analyze_eeprom (i2c_buffer, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
+	return ivm_analyze_eeprom(i2c_buffer, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
 }
 
 #if defined(CONFIG_SYS_I2C_INIT_BOARD)
@@ -339,145 +345,117 @@ int ivm_read_eeprom (void)
 #if defined(CONFIG_MGCOGE)
 #define SDA_MASK	0x00010000
 #define SCL_MASK	0x00020000
-static void set_pin (int state, unsigned long mask)
+static void set_pin(int state, unsigned long mask)
 {
-	volatile ioport_t *iop = ioport_addr ((immap_t *)CONFIG_SYS_IMMR, 3);
+	ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3);
 
 	if (state)
-		iop->pdat |= (mask);
+		setbits_be32(&iop->pdat, mask);
 	else
-		iop->pdat &= ~(mask);
+		clrbits_be32(&iop->pdat, mask);
 
-	iop->pdir |= (mask);
+	setbits_be32(&iop->pdir, mask);
 }
 
-static int get_pin (unsigned long mask)
+static int get_pin(unsigned long mask)
 {
-	volatile ioport_t *iop = ioport_addr ((immap_t *)CONFIG_SYS_IMMR, 3);
+	ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3);
 
-	iop->pdir &= ~(mask);
-	return (0 != (iop->pdat & (mask)));
+	clrbits_be32(&iop->pdir, mask);
+	return 0 != (in_be32(&iop->pdat) & mask);
 }
 
-static void set_sda (int state)
+static void set_sda(int state)
 {
-	set_pin (state, SDA_MASK);
+	set_pin(state, SDA_MASK);
 }
 
-static void set_scl (int state)
+static void set_scl(int state)
 {
-	set_pin (state, SCL_MASK);
+	set_pin(state, SCL_MASK);
 }
 
-static int get_sda (void)
+static int get_sda(void)
 {
-	return get_pin (SDA_MASK);
+	return get_pin(SDA_MASK);
 }
 
-static int get_scl (void)
+static int get_scl(void)
 {
-	return get_pin (SCL_MASK);
+	return get_pin(SCL_MASK);
 }
 
 #if defined(CONFIG_HARD_I2C)
-static void setports (int gpio)
+static void setports(int gpio)
 {
-	volatile ioport_t *iop = ioport_addr ((immap_t *)CONFIG_SYS_IMMR, 3);
+	ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3);
 
 	if (gpio) {
-		iop->ppar &= ~(SDA_MASK | SCL_MASK);
-		iop->podr &= ~(SDA_MASK | SCL_MASK);
+		clrbits_be32(&iop->ppar, (SDA_MASK | SCL_MASK));
+		clrbits_be32(&iop->podr, (SDA_MASK | SCL_MASK));
 	} else {
-		iop->ppar |= (SDA_MASK | SCL_MASK);
-		iop->pdir &= ~(SDA_MASK | SCL_MASK);
-		iop->podr |= (SDA_MASK | SCL_MASK);
+		setbits_be32(&iop->ppar, (SDA_MASK | SCL_MASK));
+		clrbits_be32(&iop->pdir, (SDA_MASK | SCL_MASK));
+		setbits_be32(&iop->podr, (SDA_MASK | SCL_MASK));
 	}
 }
 #endif
 #endif
 
-#if defined(CONFIG_KM8XX)
-static void set_sda (int state)
-{
-	I2C_SDA(state);
-}
-
-static void set_scl (int state)
-{
-	I2C_SCL(state);
-}
-
-static int get_sda (void)
-{
-	return I2C_READ;
-}
-
-static int get_scl (void)
-{
-	int	val;
-
-	*(unsigned short *)(I2C_BASE_DIR) &=  ~SCL_CONF;
-	udelay (1);
-	val = *(unsigned char *)(I2C_BASE_PORT);
-
-	return ((val & SCL_BIT) == SCL_BIT);
-}
-#endif
-
 #if !defined(CONFIG_KMETER1)
-static void writeStartSeq (void)
+static void writeStartSeq(void)
 {
-	set_sda (1);
-	udelay (DELAY_HALF_PERIOD);
-	set_scl (1);
-	udelay (DELAY_HALF_PERIOD);
-	set_sda (0);
-	udelay (DELAY_HALF_PERIOD);
-	set_scl (0);
-	udelay (DELAY_HALF_PERIOD);
+	set_sda(1);
+	udelay(DELAY_HALF_PERIOD);
+	set_scl(1);
+	udelay(DELAY_HALF_PERIOD);
+	set_sda(0);
+	udelay(DELAY_HALF_PERIOD);
+	set_scl(0);
+	udelay(DELAY_HALF_PERIOD);
 }
 
-/* I2C is a synchronous protocol and resets of the processor in the middle
-   of an access can block the I2C Bus until a powerdown of the full unit is
-   done. This function toggles the SCL until the SCL and SCA line are
-   released, but max. 16 times, after this a I2C start-sequence is sent.
-   This I2C Deblocking mechanism was developed by Keymile in association
-   with Anatech and Atmel in 1998.
+/*
+ * I2C is a synchronous protocol and resets of the processor in the middle
+ * of an access can block the I2C Bus until a powerdown of the full unit is
+ * done. This function toggles the SCL until the SCL and SCA line are
+ * released, but max. 16 times, after this a I2C start-sequence is sent.
+ * This I2C Deblocking mechanism was developed by Keymile in association
+ * with Anatech and Atmel in 1998.
  */
-static int i2c_make_abort (void)
+static int i2c_make_abort(void)
 {
 	int	scl_state = 0;
 	int	sda_state = 0;
 	int	i = 0;
 	int	ret = 0;
 
-	if (!get_sda ()) {
+	if (!get_sda()) {
 		ret = -1;
 		while (i < 16) {
 			i++;
-			set_scl (0);
-			udelay (DELAY_ABORT_SEQ);
-			set_scl (1);
-			udelay (DELAY_ABORT_SEQ);
-			scl_state = get_scl ();
-			sda_state = get_sda ();
+			set_scl(0);
+			udelay(DELAY_ABORT_SEQ);
+			set_scl(1);
+			udelay(DELAY_ABORT_SEQ);
+			scl_state = get_scl();
+			sda_state = get_sda();
 			if (scl_state && sda_state) {
 				ret = 0;
 				break;
 			}
 		}
 	}
-	if (ret == 0) {
-		for (i =0; i < 5; i++) {
-			writeStartSeq ();
-		}
-	}
-	get_sda ();
+	if (ret == 0)
+		for (i = 0; i < 5; i++)
+			writeStartSeq();
+
+	get_sda();
 	return ret;
 }
 #endif
 
-/**
+/*
  * i2c_init_board - reset i2c bus. When the board is powercycled during a
  * bus transfer it might hang; for details see doc/I2C_Edge_Conditions.
  */
@@ -488,36 +466,37 @@ void i2c_init_board(void)
 	dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET);
 	uchar	dummy;
 
-	out_8 (&dev->cr, (I2C_CR_MSTA));
-	out_8 (&dev->cr, (I2C_CR_MEN | I2C_CR_MSTA));
+	out_8(&dev->cr, (I2C_CR_MSTA));
+	out_8(&dev->cr, (I2C_CR_MEN | I2C_CR_MSTA));
 	dummy = in_8(&dev->dr);
 	dummy = in_8(&dev->dr);
 	if (dummy != 0xff) {
 		dummy = in_8(&dev->dr);
 	}
-	out_8 (&dev->cr, (I2C_CR_MEN));
-	out_8 (&dev->cr, 0x00);
-	out_8 (&dev->cr, (I2C_CR_MEN));
-
+	out_8(&dev->cr, (I2C_CR_MEN));
+	out_8(&dev->cr, 0x00);
+	out_8(&dev->cr, (I2C_CR_MEN));
 #else
 #if defined(CONFIG_HARD_I2C) && !defined(MACH_TYPE_KM_KIRKWOOD)
-	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ;
-	volatile i2c8260_t *i2c	= (i2c8260_t *)&immap->im_i2c;
+	immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ;
+	i2c8260_t *i2c	= (i2c8260_t *)&immap->im_i2c;
 
-	/* disable I2C controller first, otherwhise it thinks we want to    */
-	/* talk to the slave port...                                        */
-	i2c->i2c_i2mod &= ~0x01;
+	/*
+	 * disable I2C controller first, otherwhise it thinks we want to
+	 * talk to the slave port...
+	 */
+	clrbits_8(&i2c->i2c_i2mod, 0x01);
 
 	/* Set the PortPins to GPIO */
-	setports (1);
+	setports(1);
 #endif
 
 	/* Now run the AbortSequence() */
-	i2c_make_abort ();
+	i2c_make_abort();
 
 #if defined(CONFIG_HARD_I2C)
 	/* Set the PortPins back to use for I2C */
-	setports (0);
+	setports(0);
 #endif
 #endif
 }
@@ -525,7 +504,7 @@ void i2c_init_board(void)
 #endif
 
 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
-int fdt_set_node_and_value (void *blob,
+int fdt_set_node_and_value(void *blob,
 				char *nodename,
 				char *regname,
 				void *var,
@@ -534,21 +513,22 @@ int fdt_set_node_and_value (void *blob,
 	int ret = 0;
 	int nodeoffset = 0;
 
-	nodeoffset = fdt_path_offset (blob, nodename);
+	nodeoffset = fdt_path_offset(blob, nodename);
 	if (nodeoffset >= 0) {
-		ret = fdt_setprop (blob, nodeoffset, regname, var,
+		ret = fdt_setprop(blob, nodeoffset, regname, var,
 					size);
 		if (ret < 0)
 			printf("ft_blob_update(): cannot set %s/%s "
 				"property err:%s\n", nodename, regname,
-				fdt_strerror (ret));
+				fdt_strerror(ret));
 	} else {
 		printf("ft_blob_update(): cannot find %s node "
-			"err:%s\n", nodename, fdt_strerror (nodeoffset));
+			"err:%s\n", nodename, fdt_strerror(nodeoffset));
 	}
 	return ret;
 }
-int fdt_get_node_and_value (void *blob,
+
+int fdt_get_node_and_value(void *blob,
 				char *nodename,
 				char *propname,
 				void **var)
@@ -556,42 +536,43 @@ int fdt_get_node_and_value (void *blob,
 	int len;
 	int nodeoffset = 0;
 
-	nodeoffset = fdt_path_offset (blob, nodename);
+	nodeoffset = fdt_path_offset(blob, nodename);
 	if (nodeoffset >= 0) {
-		*var = (void *)fdt_getprop (blob, nodeoffset, propname, &len);
+		*var = (void *)fdt_getprop(blob, nodeoffset, propname, &len);
 		if (len == 0) {
 			/* no value */
-			printf ("%s no value\n", __FUNCTION__);
+			printf("%s no value\n", __func__);
 			return -1;
 		} else if (len > 0) {
 			return len;
 		} else {
-			printf ("libfdt fdt_getprop(): %s\n",
+			printf("libfdt fdt_getprop(): %s\n",
 				fdt_strerror(len));
 			return -2;
 		}
 	} else {
-		printf("%s: cannot find %s node err:%s\n", __FUNCTION__,
-			nodename, fdt_strerror (nodeoffset));
+		printf("%s: cannot find %s node err:%s\n", __func__,
+			nodename, fdt_strerror(nodeoffset));
 		return -3;
 	}
 }
 #endif
 
 #if !defined(MACH_TYPE_KM_KIRKWOOD)
-int ethernet_present (void)
+int ethernet_present(void)
 {
-	return (in_8((u8 *)CONFIG_SYS_PIGGY_BASE + CONFIG_SYS_SLOT_ID_OFF) & 0x80);
+	struct km_bec_fpga *base = (struct km_bec_fpga *)CONFIG_SYS_PIGGY_BASE;
+
+	return in_8(&base->bprth) & PIGGY_PRESENT;
 }
 #endif
 
-int board_eth_init (bd_t *bis)
+int board_eth_init(bd_t *bis)
 {
 #ifdef CONFIG_KEYMILE_HDLC_ENET
-	(void)keymile_hdlc_enet_initialize (bis);
+	(void)keymile_hdlc_enet_initialize(bis);
 #endif
-	if (ethernet_present ()) {
+	if (ethernet_present())
 		return -1;
-	}
 	return 0;
 }

board/keymile/common/common.h

@@ -11,20 +11,50 @@
 #ifndef __KEYMILE_COMMON_H
 #define __KEYMILE_COMMON_H
 
-int ethernet_present (void);
-int ivm_read_eeprom (void);
+#define WRG_RESET	0x80
+#define H_OPORTS_14	0x40
+#define WRG_LED		0x02
+#define WRL_BOOT	0x01
+
+#define H_OPORTS_SCC4_ENA	0x10
+#define H_OPORTS_SCC4_FD_ENA	0x04
+#define H_OPORTS_FCC1_PW_DWN	0x01
+
+#define PIGGY_PRESENT	0x80
+
+struct km_bec_fpga {
+	unsigned char	id;
+	unsigned char	rev;
+	unsigned char	oprth;
+	unsigned char	oprtl;
+	unsigned char	res1[3];
+	unsigned char	bprth;
+	unsigned char	bprtl;
+	unsigned char	res2[6];
+	unsigned char	prst;
+	unsigned char	res3[0xfff0];
+	unsigned char	pgy_id;
+	unsigned char	pgy_rev;
+	unsigned char	pgy_outputs;
+	unsigned char	pgy_eth;
+};
+
+int ethernet_present(void);
+int ivm_read_eeprom(void);
 
 #ifdef CONFIG_KEYMILE_HDLC_ENET
-int keymile_hdlc_enet_initialize (bd_t *bis);
+int keymile_hdlc_enet_initialize(bd_t *bis);
 #endif
 
-int fdt_set_node_and_value (void *blob,
+int fdt_set_node_and_value(void *blob,
 			char *nodename,
 			char *regname,
 			void *var,
 			int size);
-int fdt_get_node_and_value (void *blob,
+int fdt_get_node_and_value(void *blob,
 				char *nodename,
 				char *propname,
 				void **var);
+
+int i2c_soft_read_pin(void);
 #endif /* __KEYMILE_COMMON_H */

board/keymile/km_arm/km_arm.c

@@ -108,12 +108,12 @@ int ethernet_present(void)
 	int	ret = 0;
 
 	if (i2c_read(0x10, 2, 1, &buf, 1) != 0) {
-		printf ("%s: Error reading Boco\n", __FUNCTION__);
+		printf("%s: Error reading Boco\n", __func__);
 		return -1;
 	}
-	if ((buf & 0x40) == 0x40) {
+	if ((buf & 0x40) == 0x40)
 		ret = 1;
-	}
+
 	return ret;
 }
 
@@ -258,15 +258,15 @@ void reset_phy(void)
 }
 
 #if defined(CONFIG_HUSH_INIT_VAR)
-int hush_init_var (void)
+int hush_init_var(void)
 {
-	ivm_read_eeprom ();
+	ivm_read_eeprom();
 	return 0;
 }
 #endif
 
 #if defined(CONFIG_BOOTCOUNT_LIMIT)
-void bootcount_store (ulong a)
+void bootcount_store(ulong a)
 {
 	volatile ulong *save_addr;
 	volatile ulong size = 0;
@@ -279,7 +279,7 @@ void bootcount_store (ulong a)
 	writel(BOOTCOUNT_MAGIC, &save_addr[1]);
 }
 
-ulong bootcount_load (void)
+ulong bootcount_load(void)
 {
 	volatile ulong *save_addr;
 	volatile ulong size = 0;
@@ -296,31 +296,31 @@ ulong bootcount_load (void)
 #endif
 
 #if defined(CONFIG_SOFT_I2C)
-void set_sda (int state)
+void set_sda(int state)
 {
 	I2C_ACTIVE;
 	I2C_SDA(state);
 }
 
-void set_scl (int state)
+void set_scl(int state)
 {
 	I2C_SCL(state);
 }
 
-int get_sda (void)
+int get_sda(void)
 {
 	I2C_TRISTATE;
 	return I2C_READ;
 }
 
-int get_scl (void)
+int get_scl(void)
 {
 	return (kw_gpio_get_value(SUEN3_SCL_PIN) ? 1 : 0);
 }
 #endif
 
 #if defined(CONFIG_SYS_EEPROM_WREN)
-int eeprom_write_enable (unsigned dev_addr, int state)
+int eeprom_write_enable(unsigned dev_addr, int state)
 {
 	kw_gpio_set_value(SUEN3_ENV_WP, !state);
 

board/keymile/kmeter1/kmeter1.c

@@ -30,8 +30,6 @@
 
 #include "../common/common.h"
 
-extern void disable_addr_trans (void);
-extern void enable_addr_trans (void);
 const qe_iop_conf_t qe_iop_conf_tab[] = {
 	/* port pin dir open_drain assign */
 
@@ -62,131 +60,140 @@ const qe_iop_conf_t qe_iop_conf_tab[] = {
 	{0,  0, 0, 0, QE_IOP_TAB_END},
 };
 
-static int board_init_i2c_busses (void)
+static int board_init_i2c_busses(void)
 {
 	I2C_MUX_DEVICE *dev = NULL;
 	uchar	*buf;
 
 	/* Set up the Bus for the DTTs */
-	buf = (unsigned char *) getenv ("dtt_bus");
+	buf = (unsigned char *) getenv("dtt_bus");
 	if (buf != NULL)
-		dev = i2c_mux_ident_muxstring (buf);
+		dev = i2c_mux_ident_muxstring(buf);
 	if (dev == NULL) {
-		printf ("Error couldn't add Bus for DTT\n");
-		printf ("please setup dtt_bus to where your\n");
-		printf ("DTT is found.\n");
+		printf("Error couldn't add Bus for DTT\n");
+		printf("please setup dtt_bus to where your\n");
+		printf("DTT is found.\n");
 	}
 	return 0;
 }
 
-int board_early_init_r (void)
+int board_early_init_r(void)
 {
+	struct km_bec_fpga *base = (struct km_bec_fpga *)CONFIG_SYS_PIGGY_BASE;
 	unsigned short	svid;
 
 	/*
 	 * Because of errata in the UCCs, we have to write to the reserved
 	 * registers to slow the clocks down.
 	 */
-	svid =  SVR_REV(mfspr (SVR));
+	svid =  SVR_REV(mfspr(SVR));
 	switch (svid) {
 	case 0x0020:
+		/*
+		 * MPC8360ECE.pdf QE_ENET10 table 4:
+		 * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2)
+		 * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1)
+		 */
 		setbits_be32((void *)(CONFIG_SYS_IMMR + 0x14a8), 0x0c003000);
 		break;
 	case 0x0021:
+		/*
+		 * MPC8360ECE.pdf QE_ENET10 table 4:
+		 * IMMR + 0x14AC[24:27] = 1010
+		 */
 		clrsetbits_be32((void *)(CONFIG_SYS_IMMR + 0x14ac),
 			0x00000050, 0x000000a0);
 		break;
 	}
 	/* enable the PHY on the PIGGY */
-	setbits (8, (void *)(CONFIG_SYS_PIGGY_BASE + 0x10003), 0x01);
+	setbits_8(&base->pgy_eth, 0x01);
 	/* enable the Unit LED (green) */
-	setbits (8, (void *)(CONFIG_SYS_PIGGY_BASE + 0x00002), 0x01);
+	setbits_8(&base->oprth, WRL_BOOT);
 	/* take FE/GbE PHYs out of reset */
-	setbits (8, (void *)(CONFIG_SYS_PIGGY_BASE + 0x0000f), 0x1c);
+	setbits_8(&base->prst, 0x1c);
 
 	return 0;
 }
 
-int misc_init_r (void)
+int misc_init_r(void)
 {
 	/* add board specific i2c busses */
-	board_init_i2c_busses ();
+	board_init_i2c_busses();
 	return 0;
 }
 
 int fixed_sdram(void)
 {
-	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 	u32 msize = 0;
 	u32 ddr_size;
 	u32 ddr_size_log2;
 
-	im->sysconf.ddrlaw[0].ar = LAWAR_EN | 0x1e;
-	im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
-	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
-	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
-	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
-	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
-	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
-	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
-	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
-	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
-	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
-	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
-	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
-	udelay (200);
-	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
+	out_be32(&im->sysconf.ddrlaw[0].ar, (LAWAR_EN | 0x1e));
+	out_be32(&im->ddr.csbnds[0].csbnds, CONFIG_SYS_DDR_CS0_BNDS);
+	out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
+	out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
+	out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
+	out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
+	out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
+	out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
+	out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2);
+	out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
+	out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2);
+	out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
+	out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL);
+	udelay(200);
+	out_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
 
 	msize = CONFIG_SYS_DDR_SIZE << 20;
-	disable_addr_trans ();
-	msize = get_ram_size (CONFIG_SYS_DDR_BASE, msize);
-	enable_addr_trans ();
+	disable_addr_trans();
+	msize = get_ram_size(CONFIG_SYS_DDR_BASE, msize);
+	enable_addr_trans();
 	msize /= (1024 * 1024);
 	if (CONFIG_SYS_DDR_SIZE != msize) {
 		for (ddr_size = msize << 20, ddr_size_log2 = 0;
-		     (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++)
+			(ddr_size > 1);
+			ddr_size = ddr_size >> 1, ddr_size_log2++)
 			if (ddr_size & 1)
 				return -1;
-		im->sysconf.ddrlaw[0].ar =
-		    LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
-		im->ddr.csbnds[0].csbnds = (((msize / 16) - 1) & 0xff);
+		out_be32(&im->sysconf.ddrlaw[0].ar,
+			(LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE)));
+		out_be32(&im->ddr.csbnds[0].csbnds,
+			(((msize / 16) - 1) & 0xff));
 	}
 
 	return msize;
 }
 
-phys_size_t initdram (int board_type)
+phys_size_t initdram(int board_type)
 {
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-	extern void ddr_enable_ecc (unsigned int dram_size);
-#endif
-	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 	u32 msize = 0;
 
-	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
+	if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
 		return -1;
 
-	/* DDR SDRAM - Main SODIMM */
-	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
-	msize = fixed_sdram ();
+	out_be32(&im->sysconf.ddrlaw[0].bar,
+		CONFIG_SYS_DDR_BASE & LAWBAR_BAR);
+	msize = fixed_sdram();
 
 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 	/*
 	 * Initialize DDR ECC byte
 	 */
-	ddr_enable_ecc (msize * 1024 * 1024);
+	ddr_enable_ecc(msize * 1024 * 1024);
 #endif
 
 	/* return total bus SDRAM size(bytes)  -- DDR */
 	return (msize * 1024 * 1024);
 }
 
-int checkboard (void)
+int checkboard(void)
 {
-	puts ("Board: Keymile kmeter1");
-	if (ethernet_present ())
-		puts (" with PIGGY.");
-	puts ("\n");
+	puts("Board: Keymile kmeter1");
+	if (ethernet_present())
+		puts(" with PIGGY.");
+	puts("\n");
 	return 0;
 }
 
@@ -194,13 +201,13 @@ int checkboard (void)
 /*
  * update property in the blob
  */
-void ft_blob_update (void *blob, bd_t *bd)
+void ft_blob_update(void *blob, bd_t *bd)
 {
   /* no board specific update */
 }
 
 
-void ft_board_setup (void *blob, bd_t *bd)
+void ft_board_setup(void *blob, bd_t *bd)
 {
 	ft_cpu_setup (blob, bd);
 	ft_blob_update (blob, bd);
@@ -208,10 +215,9 @@ void ft_board_setup (void *blob, bd_t *bd)
 #endif
 
 #if defined(CONFIG_HUSH_INIT_VAR)
-extern int ivm_read_eeprom (void);
-int hush_init_var (void)
+int hush_init_var(void)
 {
-	ivm_read_eeprom ();
+	ivm_read_eeprom();
 	return 0;
 }
 #endif

board/keymile/mgcoge/mgcoge.c

@@ -195,33 +195,30 @@ const iop_conf_t iop_conf_tab[4][32] = {
     }
 };
 
-/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
+/*
+ * Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
  *
  * This routine performs standard 8260 initialization sequence
  * and calculates the available memory size. It may be called
  * several times to try different SDRAM configurations on both
  * 60x and local buses.
  */
-static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
-						  ulong orx, volatile uchar * base)
+static long int try_init(memctl8260_t *memctl, ulong sdmr,
+				  ulong orx, uchar *base)
 {
-	volatile uchar c = 0xff;
-	volatile uint *sdmr_ptr;
-	volatile uint *orx_ptr;
+	uchar c = 0xff;
 	ulong maxsize, size;
 	int i;
 
-	/* We must be able to test a location outsize the maximum legal size
+	/*
+	 * We must be able to test a location outsize the maximum legal size
 	 * to find out THAT we are outside; but this address still has to be
 	 * mapped by the controller. That means, that the initial mapping has
 	 * to be (at least) twice as large as the maximum expected size.
 	 */
 	maxsize = (1 + (~orx | 0x7fff))/* / 2*/;
 
-	sdmr_ptr = &memctl->memc_psdmr;
-	orx_ptr = &memctl->memc_or1;
-
-	*orx_ptr = orx;
+	out_be32(&memctl->memc_or1, orx);
 
 	/*
 	 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
@@ -243,53 +240,54 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
 	 * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
 	 */
 
-	*sdmr_ptr = sdmr | PSDMR_OP_PREA;
-	*base = c;
+	out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_PREA);
+	out_8(base, c);
 
-	*sdmr_ptr = sdmr | PSDMR_OP_CBRR;
+	out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_CBRR);
 	for (i = 0; i < 8; i++)
-		*base = c;
+		out_8(base, c);
 
-	*sdmr_ptr = sdmr | PSDMR_OP_MRW;
-	*(base + CONFIG_SYS_MRS_OFFS) = c;	/* setting MR on address lines */
+	out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_MRW);
+	/* setting MR on address lines */
+	out_8((uchar *)(base + CONFIG_SYS_MRS_OFFS), c);
 
-	*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
-	*base = c;
+	out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_NORM | PSDMR_RFEN);
+	out_8(base, c);
 
-	size = get_ram_size ((long *)base, maxsize);
-	*orx_ptr = orx | ~(size - 1);
+	size = get_ram_size((long *)base, maxsize);
+	out_be32(&memctl->memc_or1, orx | ~(size - 1));
 
 	return (size);
 }
 
-phys_size_t initdram (int board_type)
+phys_size_t initdram(int board_type)
 {
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile memctl8260_t *memctl = &immap->im_memctl;
+	immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	memctl8260_t *memctl = &immap->im_memctl;
 
 	long psize;
 
-	memctl->memc_psrt = CONFIG_SYS_PSRT;
-	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
+	out_8(&memctl->memc_psrt, CONFIG_SYS_PSRT);
+	out_be16(&memctl->memc_mptpr, CONFIG_SYS_MPTPR);
 
 #ifndef CONFIG_SYS_RAMBOOT
 	/* 60x SDRAM setup:
 	 */
-	psize = try_init (memctl, CONFIG_SYS_PSDMR, CONFIG_SYS_OR1,
-						  (uchar *) CONFIG_SYS_SDRAM_BASE);
+	psize = try_init(memctl, CONFIG_SYS_PSDMR, CONFIG_SYS_OR1,
+				  (uchar *) CONFIG_SYS_SDRAM_BASE);
 #endif /* CONFIG_SYS_RAMBOOT */
 
-	icache_enable ();
+	icache_enable();
 
 	return (psize);
 }
 
 int checkboard(void)
 {
-	puts ("Board: Keymile mgcoge");
-	if (ethernet_present ())
-		puts (" with PIGGY.");
-	puts ("\n");
+	puts("Board: Keymile mgcoge");
+	if (ethernet_present())
+		puts(" with PIGGY.");
+	puts("\n");
 	return 0;
 }
 
@@ -314,25 +312,29 @@ int last_stage_init(void)
 /*
  * Early board initalization.
  */
-int board_early_init_r (void)
+int board_early_init_r(void)
 {
+	struct km_bec_fpga *base = (struct km_bec_fpga *)CONFIG_SYS_PIGGY_BASE;
+
 	/* setup the UPIOx */
 	/* General Unit Reset disabled, Flash Bank enabled, UnitLed on */
-	out_8((u8 *)(CONFIG_SYS_PIGGY_BASE + 0x02), 0xc2);
+	out_8(&base->oprth, (WRG_RESET | H_OPORTS_14 | WRG_LED));
 	/* SCC4 enable, halfduplex, FCC1 powerdown */
-	out_8((u8 *)(CONFIG_SYS_PIGGY_BASE + 0x03), 0x15);
+	out_8(&base->oprtl, (H_OPORTS_SCC4_ENA | H_OPORTS_SCC4_FD_ENA |
+		H_OPORTS_FCC1_PW_DWN));
+
 	return 0;
 }
 
-int hush_init_var (void)
+int hush_init_var(void)
 {
-	ivm_read_eeprom ();
+	ivm_read_eeprom();
 	return 0;
 }
 
 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
-void ft_board_setup (void *blob, bd_t *bd)
+void ft_board_setup(void *blob, bd_t *bd)
 {
-	ft_cpu_setup (blob, bd);
+	ft_cpu_setup(blob, bd);
 }
 #endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */

include/configs/keymile-common.h

@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2008
+ * (C) Copyright 2008-2011
  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -25,7 +25,7 @@
 #define __CONFIG_KEYMILE_H
 
 /* Do boardspecific init for all boards */
-#define CONFIG_BOARD_EARLY_INIT_R       1
+#define CONFIG_BOARD_EARLY_INIT_R
 
 #define CONFIG_BOOTCOUNT_LIMIT
 
@@ -63,44 +63,44 @@
 #define CONFIG_JFFS2_CMDLINE
 #define CONFIG_CMD_MTDPARTS
 
-#undef	CONFIG_WATCHDOG			/* disable platform specific watchdog */
+#undef	CONFIG_WATCHDOG		/* disable platform specific watchdog */
 
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
-#undef	CONFIG_BOOTARGS			/* the boot command will set bootargs */
+#define CONFIG_BOOTDELAY	5 /* autoboot after 5 seconds */
+#undef	CONFIG_BOOTARGS		/* the boot command will set bootargs */
 
 /*
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
-#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
-#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	  */
+#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt */
 #if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
 #else
-#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
 #endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size  */
-#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size  */
-#define CONFIG_CMDLINE_EDITING		1	/* add command line history     */
-#define CONFIG_AUTO_COMPLETE		/* add autocompletion support	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
 
-#define CONFIG_HUSH_INIT_VAR	1
+#define CONFIG_HUSH_INIT_VAR
 
 #define CONFIG_SYS_ALT_MEMTEST		/* memory test, takes time */
-#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
-#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x00100000
+#define CONFIG_SYS_MEMTEST_END		0x00f00000 /* 1 ... 15 MB in DRAM */
 
-#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x100000
 
-#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ			1000	/* decr. freq: 1 ms ticks */
 
-#define CONFIG_BAUDRATE		115200
+#define CONFIG_BAUDRATE			115200
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+#define CONFIG_LOADS_ECHO
+#define CONFIG_SYS_LOADS_BAUD_CHANGE
 #define CONFIG_SYS_BOARD_DRAM_INIT	/* Used board specific dram_init */
 
 /*
@@ -108,28 +108,28 @@
  * to modify in a centralized location.  This is used in the HDLC
  * driver to set the MAC.
 */
-#define CONFIG_CHECK_ETHERNET_PRESENT	1
+#define CONFIG_CHECK_ETHERNET_PRESENT
 #define CONFIG_SYS_SLOT_ID_BASE		CONFIG_SYS_PIGGY_BASE
 #define CONFIG_SYS_SLOT_ID_OFF		(0x07)	/* register offset */
 #define CONFIG_SYS_SLOT_ID_MASK		(0x3f)	/* mask for slot ID bits */
 
-#define CONFIG_I2C_MULTI_BUS	1
+#define CONFIG_I2C_MULTI_BUS
 #define CONFIG_SYS_MAX_I2C_BUS		1
-#define CONFIG_SYS_I2C_INIT_BOARD	1
-#define CONFIG_I2C_MUX		1
+#define CONFIG_SYS_I2C_INIT_BOARD
+#define CONFIG_I2C_MUX
 
 /* EEprom support */
-#define CONFIG_SYS_I2C_MULTI_EEPROMS	1
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
 
 /* Support the IVM EEprom */
 #define	CONFIG_SYS_IVM_EEPROM_ADR	0x50
 #define CONFIG_SYS_IVM_EEPROM_MAX_LEN	0x400
 #define CONFIG_SYS_IVM_EEPROM_PAGE_LEN	0x100
 
-#define	CONFIG_SYS_FLASH_PROTECTION 1
+#define	CONFIG_SYS_FLASH_PROTECTION
 
 /*
  * BOOTP options
@@ -141,7 +141,7 @@
 
 #define CONFIG_ENV_SIZE		0x04000 /* Size of Environment */
 
-#define CONFIG_SYS_MALLOC_LEN	(4 * 1024 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
 
 /* UBI Support for all Keymile boards */
 #define CONFIG_CMD_UBI

include/configs/km_arm.h

@@ -6,6 +6,9 @@
  * (C) Copyright 2009
  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  *
+ * (C) Copyright 2010-2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
@@ -25,7 +28,10 @@
  * MA 02110-1301 USA
  */
 
-/* for linking errors see http://lists.denx.de/pipermail/u-boot/2009-July/057350.html */
+/*
+ * for linking errors see
+ * http://lists.denx.de/pipermail/u-boot/2009-July/057350.html
+ */
 
 #ifndef _CONFIG_KM_ARM_H
 #define _CONFIG_KM_ARM_H

include/configs/kmeter1.h

@@ -23,11 +23,9 @@
 /*
  * High Level Configuration Options
  */
-#define CONFIG_E300		1 /* E300 family */
-#define CONFIG_QE		1 /* Has QE */
-#define CONFIG_MPC83xx		1 /* MPC83xx family */
-#define CONFIG_MPC8360		1 /* MPC8360 CPU specific */
-#define CONFIG_KMETER1		1 /* KMETER1 board specific */
+#define CONFIG_QE		/* Has QE */
+#define CONFIG_MPC8360		/* MPC8360 CPU specific */
+#define CONFIG_KMETER1		/* KMETER1 board specific */
 #define CONFIG_HOSTNAME		kmeter1
 
 #define	CONFIG_SYS_TEXT_BASE	0xF0000000
@@ -42,7 +40,7 @@
 	"mtdparts=boot:768k(u-boot),128k(env),128k(envred),"	\
 	"-(" CONFIG_KM_UBI_PARTITION_NAME ")"
 
-#define CONFIG_MISC_INIT_R	1
+#define CONFIG_MISC_INIT_R
 /*
  * System Clock Setup
  */
@@ -114,8 +112,9 @@
 #define CONFIG_SYS_DDR_SIZE		2048 /* MB */
 #define CONFIG_SYS_DDR_CS0_BNDS		0x0000007f
 #define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN | CSCONFIG_AP | \
-					 CSCONFIG_ROW_BIT_13 | \
-					 CSCONFIG_COL_BIT_10 | CSCONFIG_ODT_WR_ACS)
+					CSCONFIG_ROW_BIT_13 | \
+					CSCONFIG_COL_BIT_10 | \
+					CSCONFIG_ODT_WR_ACS)
 
 #define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SDRAM_TYPE_DDR2 | \
 					 SDRAM_CFG_SREN)
@@ -137,14 +136,14 @@
 				 (0 << TIMING_CFG0_WRT_SHIFT) | \
 				 (0 << TIMING_CFG0_RWT_SHIFT))
 
-#define CONFIG_SYS_DDR_TIMING_1	((      TIMING_CFG1_CASLAT_50) | \
-				 ( 2 << TIMING_CFG1_WRTORD_SHIFT) | \
-				 ( 2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
-				 ( 3 << TIMING_CFG1_WRREC_SHIFT) | \
-				 ( 7 << TIMING_CFG1_REFREC_SHIFT) | \
-				 ( 3 << TIMING_CFG1_ACTTORW_SHIFT) | \
-				 ( 8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
-				 ( 3 << TIMING_CFG1_PRETOACT_SHIFT))
+#define CONFIG_SYS_DDR_TIMING_1	((TIMING_CFG1_CASLAT_50) | \
+				 (2 << TIMING_CFG1_WRTORD_SHIFT) | \
+				 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
+				 (3 << TIMING_CFG1_WRREC_SHIFT) | \
+				 (7 << TIMING_CFG1_REFREC_SHIFT) | \
+				 (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
+				 (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
+				 (3 << TIMING_CFG1_PRETOACT_SHIFT))
 
 #define CONFIG_SYS_DDR_TIMING_2	((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
 				 (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
@@ -172,7 +171,7 @@
 #undef	CONFIG_SYS_RAMBOOT
 #endif
 
-#define CONFIG_SYS_MONITOR_LEN		(384 * 1024) /* Reserve 384 kB for Mon */
+#define CONFIG_SYS_MONITOR_LEN		(384 * 1024) /* Reserve for Mon */
 
 /*
  * Initial RAM Base Address Setup
@@ -180,7 +179,8 @@
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
 #define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					GENERATED_GBL_DATA_SIZE)
 
 /*
  * Local Bus Configuration & Clock Setup
@@ -208,7 +208,7 @@
 #define CONFIG_SYS_FLASH_PROTECTION	1
 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
 
-#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE /* Window base at flash base */
+#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
 #define CONFIG_SYS_LBLAWAR0_PRELIM	0x8000001b /* 256MB window size */
 
 #define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE | \
@@ -220,8 +220,9 @@
 				OR_GPCM_SCY_5 | \
 				OR_GPCM_TRLX | OR_GPCM_EAD)
 
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of flash banks	*/
-#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max num of sects on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of flash banks */
+/* max num of sects on one chip */
+#define CONFIG_SYS_MAX_FLASH_SECT	512
 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
 
 #undef	CONFIG_SYS_FLASH_CHECKSUM
@@ -229,13 +230,13 @@
 /*
  * PRIO1/PIGGY on the local bus CS1
  */
-#define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_PIGGY_BASE /* Window base at flash base */
+#define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_PIGGY_BASE
 #define CONFIG_SYS_LBLAWAR1_PRELIM	0x8000001A /* 128MB window size */
 
 #define CONFIG_SYS_BR1_PRELIM	(CONFIG_SYS_PIGGY_BASE | \
 				(1 << BR_PS_SHIFT) | /* 8 bit port size */ \
 				BR_V)
-#define CONFIG_SYS_OR1_PRELIM		(MEG_TO_AM(CONFIG_SYS_PIGGY_SIZE) | /* 128MB */ \
+#define CONFIG_SYS_OR1_PRELIM	(MEG_TO_AM(CONFIG_SYS_PIGGY_SIZE) | \
 				OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
 				OR_GPCM_SCY_2 | \
 				OR_GPCM_TRLX | OR_GPCM_EAD)
@@ -243,7 +244,7 @@
 /*
  * PAXE on the local bus CS3
  */
-#define CONFIG_SYS_LBLAWBAR3_PRELIM	CONFIG_SYS_PAXE_BASE /* Window base at flash base */
+#define CONFIG_SYS_LBLAWBAR3_PRELIM	CONFIG_SYS_PAXE_BASE
 #define CONFIG_SYS_LBLAWAR3_PRELIM	0x8000001C /* 512MB window size */
 
 #define CONFIG_SYS_BR3_PRELIM	(CONFIG_SYS_PAXE_BASE | \
@@ -267,8 +268,8 @@
 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
 
 /* Pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
 #define CONFIG_OF_STDOUT_VIA_ALIAS
 
 /*
@@ -278,7 +279,7 @@
 #undef CONFIG_PCI		/* No PCI */
 
 #ifndef CONFIG_NET_MULTI
-#define CONFIG_NET_MULTI	1
+#define CONFIG_NET_MULTI
 #endif
 /*
  * QE UEC ethernet configuration
@@ -291,7 +292,7 @@
 
 #ifdef CONFIG_UEC_ETH1
 #define CONFIG_SYS_UEC1_UCC_NUM	3	/* UCC4 */
-#define CONFIG_SYS_UEC1_RX_CLK		QE_CLK_NONE	/* not used in RMII Mode */
+#define CONFIG_SYS_UEC1_RX_CLK		QE_CLK_NONE /* not used in RMII */
 #define CONFIG_SYS_UEC1_TX_CLK		QE_CLK17
 #define CONFIG_SYS_UEC1_ETH_TYPE	FAST_ETH
 #define CONFIG_SYS_UEC1_PHY_ADDR	0
@@ -305,17 +306,19 @@
 
 #ifndef CONFIG_SYS_RAMBOOT
 #define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + \
+				CONFIG_SYS_MONITOR_LEN)
 #define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K(one sector) for env */
 #define CONFIG_ENV_OFFSET	(CONFIG_SYS_MONITOR_LEN)
 
 /* Address and size of Redundant Environment Sector	*/
-#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + \
+					CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
 
 #else /* CFG_RAMBOOT */
-#define CONFIG_SYS_NO_FLASH		1	/* Flash is not usable now */
-#define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
+#define CONFIG_SYS_NO_FLASH	/* Flash is not usable now */
+#define CONFIG_ENV_IS_NOWHERE	/* Store ENV in memory only */
 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
 #define CONFIG_ENV_SIZE		0x2000
 #endif /* CFG_RAMBOOT */
@@ -333,9 +336,9 @@
 /* EEprom support */
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
 
-/* I2C SYSMON (LM75, AD7414 is almost compatible)			*/
-#define CONFIG_DTT_LM75		1	/* ON Semi's LM75		*/
-#define CONFIG_DTT_SENSORS	{0, 1, 2, 3}	/* Sensor addresses		*/
+/* I2C SYSMON (LM75, AD7414 is almost compatible) */
+#define CONFIG_DTT_LM75		/* ON Semi's LM75 */
+#define CONFIG_DTT_SENSORS	{0, 1, 2, 3}	/* Sensor addresses */
 #define CONFIG_SYS_DTT_MAX_TEMP	70
 #define CONFIG_SYS_DTT_LOW_TEMP	-30
 #define CONFIG_SYS_DTT_HYSTERESIS	3
@@ -361,7 +364,7 @@
  * have to be in the first 256 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CONFIG_SYS_BOOTMAPSZ		(256 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(256 << 20)
 
 /*
  * Core HID Setup
@@ -375,45 +378,54 @@
  * MMU Setup
  */
 
-#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+#define CONFIG_HIGH_BATS	/* High BATs supported */
 
 /* DDR: cache cacheable */
 #define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \
 				BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
+				BATU_VS | BATU_VP)
 #define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
 #define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
 
 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
 #define CONFIG_SYS_IBAT1L	(CONFIG_SYS_IMMR | BATL_PP_10 | \
 				BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | \
+				BATU_VP)
 #define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
 #define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
 
 /* PRIO1, PIGGY:  icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_PIGGY_BASE | BATU_BL_128M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | \
+				BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_PIGGY_BASE | BATU_BL_128M | \
+				BATU_VS | BATU_VP)
 #define CONFIG_SYS_DBAT2L	(CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | \
 				 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
 
 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
+				BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \
+				BATU_VS | BATU_VP)
 #define CONFIG_SYS_DBAT3L	(CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
 				 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
 
 /* Stack in dcache: cacheable, no memory coherence */
 #define CONFIG_SYS_IBAT4L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
-#define CONFIG_SYS_IBAT4U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT4U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
+				BATU_VS | BATU_VP)
 #define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
 #define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
 
 /* PAXE:  icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_PAXE_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_PAXE_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_PAXE_BASE | BATL_PP_10 | \
+				BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_PAXE_BASE | BATU_BL_256M | \
+				BATU_VS | BATU_VP)
 #define CONFIG_SYS_DBAT5L	(CONFIG_SYS_PAXE_BASE | BATL_PP_10 | \
 				 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U

include/configs/mgcoge.h

@@ -29,15 +29,12 @@
  * (easy to change)
  */
 
-#define CONFIG_MPC8247		1
-#define CONFIG_MPC8272_FAMILY   1
-#define CONFIG_MGCOGE		1
+#define CONFIG_MPC8247
+#define CONFIG_MGCOGE
 #define CONFIG_HOSTNAME		mgcoge
 
 #define	CONFIG_SYS_TEXT_BASE	0xFE000000
 
-#define CONFIG_CPM2		1	/* Has a CPM2 */
-
 /* include common defines/options for all Keymile boards */
 #include "keymile-common.h"
 
@@ -69,13 +66,13 @@
 #define	CONFIG_ETHER_ON_SCC		/* Ethernet is on SCC */
 #undef	CONFIG_ETHER_ON_FCC		/* Ethernet is not on FCC     */
 #undef	CONFIG_ETHER_NONE		/* No external Ethernet   */
-#define CONFIG_NET_MULTI	1
+#define CONFIG_NET_MULTI
 
 #define CONFIG_ETHER_INDEX	4
 #define CONFIG_HAS_ETH0
 #define CONFIG_SYS_SCC_TOUT_LOOP	10000000
 
-# define CONFIG_SYS_CMXSCR_VALUE	(CMXSCR_RS4CS_CLK7 | CMXSCR_TS4CS_CLK8)
+# define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS4CS_CLK7 | CMXSCR_TS4CS_CLK8)
 
 #ifndef CONFIG_8260_CLKIN
 #define CONFIG_8260_CLKIN	66000000	/* in Hz */
@@ -113,8 +110,9 @@
 #define CONFIG_SYS_FLASH_SIZE		32
 #define CONFIG_SYS_FLASH_CFI
 #define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_MAX_FLASH_BANKS	3	/* max num of flash banks	*/
-#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max num of sects on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	3
+/* max num of sects on one chip */
+#define CONFIG_SYS_MAX_FLASH_SECT	512
 
 #define CONFIG_SYS_FLASH_BASE_1	0x50000000
 #define CONFIG_SYS_FLASH_SIZE_1	32
@@ -130,24 +128,26 @@
 #define CONFIG_SYS_RAMBOOT
 #endif
 
-#define CONFIG_SYS_MONITOR_LEN		(384 << 10)	/* Reserve 384KB for Monitor */
+#define CONFIG_SYS_MONITOR_LEN		(384 << 10)
 
 #define CONFIG_ENV_IS_IN_FLASH
 
 #ifdef CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_SECT_SIZE	0x20000
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + \
+				CONFIG_SYS_MONITOR_LEN)
 #define CONFIG_ENV_OFFSET	CONFIG_SYS_MONITOR_LEN
 
 /* Address and size of Redundant Environment Sector	*/
-#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + \
+					CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_SIZE_REDUND		(CONFIG_ENV_SIZE)
 #endif /* CONFIG_ENV_IS_IN_FLASH */
-#define CONFIG_ENV_BUFFER_PRINT		1
+#define CONFIG_ENV_BUFFER_PRINT
 
 /* enable I2C and select the hardware/software driver */
 #undef	CONFIG_HARD_I2C			/* I2C with hardware support	*/
-#define	CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
+#define	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
 #define CONFIG_SYS_I2C_SPEED		50000	/* I2C speed and slave address	*/
 #define CONFIG_SYS_I2C_SLAVE		0x7F
 
@@ -159,15 +159,23 @@
 #define I2C_ACTIVE	(iop->pdir |=  0x00010000)
 #define I2C_TRISTATE	(iop->pdir &= ~0x00010000)
 #define I2C_READ	((iop->pdat & 0x00010000) != 0)
-#define I2C_SDA(bit)	if(bit) iop->pdat |=  0x00010000; \
-			else    iop->pdat &= ~0x00010000
-#define I2C_SCL(bit)	if(bit) iop->pdat |=  0x00020000; \
-			else    iop->pdat &= ~0x00020000
+#define I2C_SDA(bit)	do { \
+				if (bit) \
+					iop->pdat |=  0x00010000; \
+				else \
+					iop->pdat &= ~0x00010000; \
+			} while (0)
+#define I2C_SCL(bit)	do { \
+				if (bit) \
+					iop->pdat |=  0x00020000; \
+				else \
+					iop->pdat &= ~0x00020000; \
+			} while (0)
 #define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
 
-/* I2C SYSMON (LM75, AD7414 is almost compatible)			*/
-#define CONFIG_DTT_LM75		1	/* ON Semi's LM75		*/
-#define CONFIG_DTT_SENSORS	{0}	/* Sensor addresses		*/
+/* I2C SYSMON (LM75, AD7414 is almost compatible) */
+#define CONFIG_DTT_LM75		/* ON Semi's LM75 */
+#define CONFIG_DTT_SENSORS	{0}	/* Sensor addresses */
 #define CONFIG_SYS_DTT_MAX_TEMP	70
 #define CONFIG_SYS_DTT_LOW_TEMP	-30
 #define CONFIG_SYS_DTT_HYSTERESIS	3
@@ -178,8 +186,9 @@
 #define CONFIG_SYS_IMMR		0xF0000000
 
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE	0x2000	/* Size of used area in DPRAM	*/
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2000
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /* Hard reset configuration word */
@@ -194,11 +203,11 @@
 #define CONFIG_SYS_HRCW_SLAVE6		0
 #define CONFIG_SYS_HRCW_SLAVE7		0
 
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)
 
 #define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8260 CPUs */
 #if defined(CONFIG_CMD_KGDB)
-#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#  define CONFIG_SYS_CACHELINE_SHIFT	5 /* log base 2 of the above value */
 #endif
 
 #define CONFIG_SYS_HID0_INIT		0
@@ -211,14 +220,16 @@
 #define CONFIG_SYS_BCR			0x10000000
 #define CONFIG_SYS_SCCR		(SCCR_PCI_MODE | SCCR_PCI_MODCK)
 
-/*-----------------------------------------------------------------------
+/*
+ *-----------------------------------------------------------------------
  * RMR - Reset Mode Register                                     5-5
  *-----------------------------------------------------------------------
  * turn on Checkstop Reset Enable
  */
 #define CONFIG_SYS_RMR         0
 
-/*-----------------------------------------------------------------------
+/*
+ *-----------------------------------------------------------------------
  * TMCNTSC - Time Counter Status and Control                     4-40
  *-----------------------------------------------------------------------
  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
@@ -226,7 +237,8 @@
  */
 #define CONFIG_SYS_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 
-/*-----------------------------------------------------------------------
+/*
+ *-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control                 4-42
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
@@ -234,7 +246,8 @@
  */
 #define CONFIG_SYS_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
 
-/*-----------------------------------------------------------------------
+/*
+ *-----------------------------------------------------------------------
  * RCCR - RISC Controller Configuration                         13-7
  *-----------------------------------------------------------------------
  */
@@ -265,14 +278,16 @@
 			 ORxG_TRLX )
 
 
-/* Bank 1 - 60x bus SDRAM
+/*
+ * Bank 1 - 60x bus SDRAM
  */
 #define SDRAM_MAX_SIZE	0x08000000	/* max. 128 MB		*/
-#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT	(256 << 20)	/* less than 256 MB */
+#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT	(256 << 20)
 
 #define CONFIG_SYS_MPTPR       0x1800
 
-/*-----------------------------------------------------------------------------
+/*
+ *-----------------------------------------------------------------------------
  * Address for Mode Register Set (MRS) command
  *-----------------------------------------------------------------------------
  */
@@ -286,8 +301,9 @@
 
 #define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR1
 
-/* SDRAM initialization values
-*/
+/*
+ * SDRAM initialization values
+ */
 
 #define CONFIG_SYS_OR1    ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
 			 ORxS_BPD_8                     |\
@@ -304,8 +320,9 @@
 			 PSDMR_WRC_1C                   |\
 			 PSDMR_CL_2)
 
-/* GPIO/PIGGY on CS3 initialization values
-*/
+/*
+ * GPIO/PIGGY on CS3 initialization values
+ */
 #define CONFIG_SYS_PIGGY_BASE	0x30000000
 #define CONFIG_SYS_PIGGY_SIZE	128
 
@@ -316,8 +333,9 @@
 			 ORxG_CSNT | ORxG_ACS_DIV2 |\
 			 ORxG_SCY_3_CLK | ORxG_TRLX )
 
-/* Board FPGA on CS4 initialization values
-*/
+/*
+ * Board FPGA on CS4 initialization values
+ */
 #define CONFIG_SYS_FPGA_BASE	0x40000000
 #define CONFIG_SYS_FPGA_SIZE	1 /*1KB*/
 
@@ -328,8 +346,9 @@
 			 ORxG_CSNT | ORxG_ACS_DIV2 |\
 			 ORxG_SCY_3_CLK | ORxG_TRLX )
 
-/* CFG-Flash on CS5 initialization values
-*/
+/*
+ * CFG-Flash on CS5 initialization values
+ */
 #define CONFIG_SYS_BR5_PRELIM	((CONFIG_SYS_FLASH_BASE_1 & BRx_BA_MSK) |\
 			 BRx_PS_16 | BRx_MS_GPCM_P | BRx_V)
 
@@ -338,12 +357,12 @@
 				 ORxG_CSNT | ORxG_ACS_DIV2 |\
 				 ORxG_SCY_5_CLK | ORxG_TRLX )
 
-#define	CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC	/* "bad" address		*/
+#define	CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC	/* "bad" address */
 
 /* pass open firmware flat tree */
-#define CONFIG_FIT		1
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
+#define CONFIG_FIT
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
 
 #define OF_TBCLK		(bd->bi_busfreq / 4)
 #define OF_STDOUT_PATH		"/soc/cpm/serial@11a90"