Patch by Steven Scholz, 06 Apr 2005:

- creating SoC subdir for Atmel AT91RM9200 cpu/arm920t/at91rm9200
- moving code out of cpu/at91rm9200 into cpu/arm920t/at91rm9200

CHANGELOG

@@ -2,6 +2,10 @@
 Changes for U-Boot 1.1.3:
 ======================================================================
 
+* Patch by Steven Scholz, 06 Apr 2005:
+  - creating SoC subdir for Atmel AT91RM9200 cpu/arm920t/at91rm9200
+  - moving code out of cpu/at91rm9200 into cpu/arm920t/at91rm9200
+
 * Patches by Robert Whaley, 29 Nov 2004:
   - update the pxa-regs.h file for PXA27x chips
   - add PXA27x based ADSVIX board

Makefile

@@ -1285,6 +1285,12 @@ xtract_omap1610xxx = $(subst _cs0boot,,$(subst _cs3boot,,$(subst _cs_autoboot,,$
 
 xtract_omap730p2 = $(subst _cs0boot,,$(subst _cs3boot,, $(subst _config,,$1)))
 
+at91rm9200dk_config	:	unconfig
+	@./mkconfig $(@:_config=) arm arm920t at91rm9200dk NULL at91rm9200
+
+cmc_pu2_config	:	unconfig
+	@./mkconfig $(@:_config=) arm arm920t cmc_pu2 NULL at91rm9200
+
 integratorap_config :	unconfig
 	@./mkconfig $(@:_config=) arm arm926ejs integratorap
 
@@ -1418,16 +1424,6 @@ modnet50_config :	unconfig
 evb4510_config :	unconfig
 	@./mkconfig $(@:_config=) arm arm720t evb4510
 
-#########################################################################
-## AT91RM9200 Systems
-#########################################################################
-
-at91rm9200dk_config	:	unconfig
-	@./mkconfig $(@:_config=) arm at91rm9200 at91rm9200dk
-
-cmc_pu2_config	:	unconfig
-	@./mkconfig $(@:_config=) arm at91rm9200 cmc_pu2
-
 #########################################################################
 ## XScale Systems
 #########################################################################

README

@@ -126,12 +126,12 @@ Directory Hierarchy:
   - 74xx_7xx	Files specific to Freescale MPC74xx and 7xx CPUs
   - arm720t	Files specific to ARM 720 CPUs
   - arm920t	Files specific to ARM 920 CPUs
+    - at91rm9200 Files specific to Atmel AT91RM9200 CPU
     - imx	Files specific to Freescale MC9328 i.MX CPUs
     - s3c24x0	Files specific to Samsung S3C24X0 CPUs
   - arm925t	Files specific to ARM 925 CPUs
   - arm926ejs	Files specific to ARM 926 CPUs
   - arm1136	Files specific to ARM 1136 CPUs
-  - at91rm9200	Files specific to Atmel AT91RM9200 CPUs
   - i386	Files specific to i386 CPUs
   - ixp		Files specific to Intel XScale IXP CPUs
   - mcf52x2	Files specific to Freescale ColdFire MCF52x2 CPUs

board/adsvix/Makefile

@@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk
 LIB	= lib$(BOARD).a
 
 OBJS	:= adsvix.o pcmcia.o
-SOBJS	:= memsetup.o pxavoltage.o
+SOBJS	:= lowlevel_init.o pxavoltage.o
 
 $(LIB):	$(OBJS) $(SOBJS)
 	$(AR) crv $@ $(OBJS) $(SOBJS)

board/adsvix/memsetup.S → board/adsvix/lowlevel_init.S

@@ -5,7 +5,7 @@
  *
  * NOTE: I haven't clean this up considerably, just enough to get it
  * running. See hal_platform_setup.h for the source. See
- * board/cradle/memsetup.S for another PXA250 setup that is
+ * board/cradle/lowlevel_init.S for another PXA250 setup that is
  * much cleaner.
  *
  * See file CREDITS for list of people who contributed to this
@@ -43,8 +43,8 @@
  *	Memory setup
  */
 
-.globl memsetup
-memsetup:
+.globl lowlevel_init
+lowlevel_init:
 
 	/* Set up GPIO pins first ----------------------------------------- */
 
@@ -445,7 +445,6 @@ initclks:
     str r1, [r0]
 	/* FIXME */
 
-// #define NODEBUG
 #ifdef NODEBUG
 	/*Disable software and data breakpoints */
 	mov	r0,#0
@@ -456,13 +455,12 @@ initclks:
 	/*Enable all debug functionality */
 	mov	r0,#0x80000000
 	mcr	p14,0,r0,c10,c0,0  /* dcsr */
-
 #endif
 
 	/* ---------------------------------------------------------------- */
-	/* End memsetup							    */
+	/* End lowlevel_init							    */
 	/* ---------------------------------------------------------------- */
 
-endmemsetup:
+endlowlevel_init:
 
 	mov	pc, lr

board/adsvix/pxavoltage.S

@@ -228,4 +228,3 @@ setleds:
 	bne		1b
 
 	mov		pc, lr
-

board/at91rm9200dk/u-boot.lds

@@ -32,7 +32,7 @@ SECTIONS
 	. = ALIGN(4);
 	.text      :
 	{
-	  cpu/at91rm9200/start.o	(.text)
+	  cpu/arm920t/start.o	(.text)
 	  *(.text)
 	}
 

board/cmc_pu2/u-boot.lds

@@ -32,7 +32,7 @@ SECTIONS
 	. = ALIGN(4);
 	.text      :
 	{
-	  cpu/at91rm9200/start.o	(.text)
+	  cpu/arm920t/start.o	(.text)
 	  *(.text)
 	}
 

cpu/at91rm9200/Makefile → cpu/arm920t/at91rm9200/Makefile

@@ -1,5 +1,5 @@
 #
-# (C) Copyright 2003
+# (C) Copyright 2000-2005
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # See file CREDITS for list of people who contributed to this
@@ -23,22 +23,20 @@
 
 include $(TOPDIR)/config.mk
 
-LIB	= lib$(CPU).a
+LIB	= lib$(SOC).a
 
-START	= start.o
-OBJS	= serial.o interrupts.o cpu.o \
-	  at91rm9200_ether.o i2c.o
-SOBJS	= lowlevel.o
+OBJS	= ether.o i2c.o interrupts.o serial.o
+SOBJS	= lowlevel_init.o
 
-all:	.depend $(START) $(LIB)
+all:	.depend $(LIB)
 
 $(LIB):	$(OBJS) $(SOBJS)
 	$(AR) crv $@ $(OBJS) $(SOBJS)
 
 #########################################################################
 
-.depend:	Makefile $(START:.o=.S) $(OBJS:.o=.c)
-		$(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@
+.depend:	Makefile $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
 
 sinclude .depend
 

cpu/at91rm9200/interrupts.c → cpu/arm920t/at91rm9200/interrupts.c

@@ -31,9 +31,9 @@
  */
 
 #include <common.h>
-#include <asm/io.h>
+/*#include <asm/io.h>*/
 #include <asm/arch/hardware.h>
-#include <asm/proc/ptrace.h>
+/*#include <asm/proc/ptrace.h>*/
 
 /* the number of clocks per CFG_HZ */
 #define TIMER_LOAD_VAL (CFG_HZ_CLOCK/CFG_HZ)
@@ -42,119 +42,11 @@
 #define READ_TIMER (tmr->TC_CV & 0x0000ffff)
 AT91PS_TC tmr;
 
-#ifdef CONFIG_USE_IRQ
-#error There is no IRQ support for AT91RM9200 in U-Boot yet.
-#else
-void enable_interrupts (void)
-{
-	return;
-}
-int disable_interrupts (void)
-{
-	return 0;
-}
-#endif
-
-
-void bad_mode (void)
-{
-	panic ("Resetting CPU ...\n");
-	reset_cpu (0);
-}
-
-void show_regs (struct pt_regs *regs)
-{
-	unsigned long flags;
-	const char *processor_modes[] = {
-	"USER_26",	"FIQ_26",	"IRQ_26",	"SVC_26",
-	"UK4_26",	"UK5_26",	"UK6_26",	"UK7_26",
-	"UK8_26",	"UK9_26",	"UK10_26",	"UK11_26",
-	"UK12_26",	"UK13_26",	"UK14_26",	"UK15_26",
-	"USER_32",	"FIQ_32",	"IRQ_32",	"SVC_32",
-	"UK4_32",	"UK5_32",	"UK6_32",	"ABT_32",
-	"UK8_32",	"UK9_32",	"UK10_32",	"UND_32",
-	"UK12_32",	"UK13_32",	"UK14_32",	"SYS_32",
-	};
-
-	flags = condition_codes (regs);
-
-	printf ("pc : [<%08lx>]    lr : [<%08lx>]\n"
-		"sp : %08lx  ip : %08lx  fp : %08lx\n",
-		instruction_pointer (regs),
-		regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp);
-	printf ("r10: %08lx  r9 : %08lx  r8 : %08lx\n",
-		regs->ARM_r10, regs->ARM_r9, regs->ARM_r8);
-	printf ("r7 : %08lx  r6 : %08lx  r5 : %08lx  r4 : %08lx\n",
-		regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4);
-	printf ("r3 : %08lx  r2 : %08lx  r1 : %08lx  r0 : %08lx\n",
-		regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0);
-	printf ("Flags: %c%c%c%c",
-		flags & CC_N_BIT ? 'N' : 'n',
-		flags & CC_Z_BIT ? 'Z' : 'z',
-		flags & CC_C_BIT ? 'C' : 'c',
-		flags & CC_V_BIT ? 'V' : 'v');
-	printf ("  IRQs %s  FIQs %s  Mode %s%s\n",
-		interrupts_enabled (regs) ? "on" : "off",
-		fast_interrupts_enabled (regs) ? "on" : "off",
-		processor_modes[processor_mode (regs)],
-		thumb_mode (regs) ? " (T)" : "");
-}
-
-void do_undefined_instruction (struct pt_regs *pt_regs)
-{
-	printf ("undefined instruction\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
-void do_software_interrupt (struct pt_regs *pt_regs)
-{
-	printf ("software interrupt\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
-void do_prefetch_abort (struct pt_regs *pt_regs)
-{
-	printf ("prefetch abort\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
-void do_data_abort (struct pt_regs *pt_regs)
-{
-	printf ("data abort\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
-void do_not_used (struct pt_regs *pt_regs)
-{
-	printf ("not used\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
-void do_fiq (struct pt_regs *pt_regs)
-{
-	printf ("fast interrupt request\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
-void do_irq (struct pt_regs *pt_regs)
-{
-	printf ("interrupt request\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
 static ulong timestamp;
 static ulong lastinc;
 
 int interrupt_init (void)
 {
-
 	tmr = AT91C_BASE_TC0;
 
 	/* enables TC1.0 clock */
@@ -266,3 +158,53 @@ ulong get_tbclk (void)
 	tbclk = CFG_HZ;
 	return tbclk;
 }
+
+/*
+ * Reset the cpu by setting up the watchdog timer and let him time out
+ * or toggle a GPIO pin on the AT91RM9200DK board
+ */
+void reset_cpu (ulong ignored)
+{
+
+#ifdef CONFIG_DBGU
+	AT91PS_USART us = (AT91PS_USART) AT91C_BASE_DBGU;
+#endif
+#ifdef CONFIG_USART0
+	AT91PS_USART us = AT91C_BASE_US0;
+#endif
+#ifdef CONFIG_USART1
+	AT91PS_USART us = AT91C_BASE_US1;
+#endif
+#ifdef CONFIG_AT91RM9200DK
+	AT91PS_PIO pio = AT91C_BASE_PIOA;
+#endif
+
+	/*shutdown the console to avoid strange chars during reset */
+	us->US_CR = (AT91C_US_RSTRX | AT91C_US_RSTTX);
+
+#ifdef CONFIG_AT91RM9200DK
+	/* Clear PA19 to trigger the hard reset */
+	pio->PIO_CODR = 0x00080000;
+	pio->PIO_OER  = 0x00080000;
+	pio->PIO_PER  = 0x00080000;
+#endif
+
+	/* this is the way Linux does it */
+
+	/* FIXME:
+	 * These defines should be moved into
+	 * include/asm-arm/arch-at91rm9200/AT91RM9200.h
+	 * as soon as the whitespace fix gets applied.
+	 */
+	#define AT91C_ST_RSTEN (0x1 << 16)
+	#define AT91C_ST_EXTEN (0x1 << 17)
+	#define AT91C_ST_WDRST (0x1 <<  0)
+	#define ST_WDMR *((unsigned long *)0xfffffd08)	/* watchdog mode register */
+	#define ST_CR *((unsigned long *)0xfffffd00)	/* system clock control register */
+
+	ST_WDMR = AT91C_ST_RSTEN | AT91C_ST_EXTEN | 1 ;
+	ST_CR = AT91C_ST_WDRST;
+
+	while (1);
+	/* Never reached */
+}

cpu/at91rm9200/config.mk

@@ -1,27 +0,0 @@
-#
-# (C) Copyright 2002
-# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
-# Marius Groeger <mgroeger@sysgo.de>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-PLATFORM_RELFLAGS += -fno-strict-aliasing  -fno-common -ffixed-r8 \
-	-mshort-load-bytes -msoft-float
-
-PLATFORM_CPPFLAGS += -mapcs-32 -march=armv4 -mtune=arm7tdmi

cpu/at91rm9200/cpu.c

@@ -1,200 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * CPU specific code
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-
-#if !defined(CONFIG_DBGU) && !defined(CONFIG_USART0) && !defined(CONFIG_USART1)
-#error must define one of CONFIG_DBGU or CONFIG_USART0 or CONFIG_USART1
-#endif
-
-/* read co-processor 15, register #1 (control register) */
-static unsigned long read_p15_c1(void)
-{
-    unsigned long value;
-
-    __asm__ __volatile__(
-	"mrc     p15, 0, %0, c1, c0, 0   @ read control reg\n"
-	: "=r" (value)
-	:
-	: "memory");
-    /*printf("p15/c1 is = %08lx\n", value); */
-    return value;
-}
-
-/* write to co-processor 15, register #1 (control register) */
-static void write_p15_c1(unsigned long value)
-{
-    /*printf("write %08lx to p15/c1\n", value); */
-    __asm__ __volatile__(
-	"mcr     p15, 0, %0, c1, c0, 0   @ write it back\n"
-	: "=r" (value)
-	:
-	: "memory");
-
-    read_p15_c1();
-}
-
-static void cp_delay(void)
-{
-    volatile int i;
-
-    /* copro seems to need some delay between reading and writing */
-    for (i=0; i<100; i++);
-}
-/* See also ARM Ref. Man. */
-#define C1_MMU		(1<<0)	/* mmu off/on */
-#define C1_ALIGN	(1<<1)	/* alignment faults off/on */
-#define C1_IDC		(1<<2)	/* icache and/or dcache off/on */
-#define C1_WRITE_BUFFER	(1<<3)	/* write buffer off/on */
-#define C1_BIG_ENDIAN	(1<<7)	/* big endian off/on */
-#define C1_SYS_PROT	(1<<8)	/* system protection */
-#define C1_ROM_PROT	(1<<9)	/* ROM protection */
-#define C1_HIGH_VECTORS	(1<<13)	/* location of vectors: low/high addresses */
-
-int cpu_init(void)
-{
-	/*
-	 * setup up stacks if necessary
-	 */
-#ifdef CONFIG_USE_IRQ
-	DECLARE_GLOBAL_DATA_PTR;
-
-	IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
-	FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
-#endif
-	return 0;
-}
-
-int cleanup_before_linux(void)
-{
-    /*
-     * this function is called just before we call linux
-     * it prepares the processor for linux
-     *
-     * we turn off caches etc ...
-     * and we set the CPU-speed to 73 MHz - see start.S for details
-     */
-
-    disable_interrupts();
-    return 0;
-}
-
-int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
-
-#ifdef CFG_SOFT_RESET
-    disable_interrupts();
-    reset_cpu(0);
-#else
-#ifdef CONFIG_DBGU
-   AT91PS_USART us = (AT91PS_USART) AT91C_BASE_DBGU;
-#endif
-#ifdef CONFIG_USART0
-   AT91PS_USART us = AT91C_BASE_US0;
-#endif
-#ifdef CONFIG_USART1
-   AT91PS_USART us = AT91C_BASE_US1;
-#endif
-   AT91PS_PIO pio = AT91C_BASE_PIOA;
-
-   /*shutdown the console to avoid strange chars during reset */
-   us->US_CR = (AT91C_US_RSTRX | AT91C_US_RSTTX);
-
-#ifdef CONFIG_AT91RM9200DK
-   /* Clear PA19 to trigger the hard reset */
-   pio->PIO_CODR = 0x00080000;
-   pio->PIO_OER  = 0x00080000;
-   pio->PIO_PER  = 0x00080000;
-#endif
-#ifdef CONFIG_CMC_PU2
-/* this is the way Linux does it */
-#define AT91C_ST_RSTEN (0x1 << 16)
-#define AT91C_ST_EXTEN (0x1 << 17)
-#define AT91C_ST_WDRST (0x1 <<  0)
-/* watchdog mode register */
-#define ST_WDMR *((unsigned long *)0xfffffd08)
-/* system clock control register */
-#define ST_CR *((unsigned long *)0xfffffd00)
-	ST_WDMR = AT91C_ST_RSTEN | AT91C_ST_EXTEN | 1 ;
-	ST_CR = AT91C_ST_WDRST;
-   /* Never reached */
-#endif
-#endif
-   return 0;
-}
-
-void icache_enable(void)
-{
-    ulong reg;
-    reg = read_p15_c1();
-    cp_delay();
-    write_p15_c1(reg | C1_IDC);
-}
-
-void icache_disable(void)
-{
-    ulong reg;
-    reg = read_p15_c1();
-    cp_delay();
-    write_p15_c1(reg & ~C1_IDC);
-}
-
-int icache_status(void)
-{
-    return (read_p15_c1() & C1_IDC) != 0;
-    return 0;
-}
-
-void dcache_enable(void)
-{
-    ulong reg;
-    reg = read_p15_c1();
-    cp_delay();
-    write_p15_c1(reg | C1_IDC);
-}
-
-void dcache_disable(void)
-{
-    ulong reg;
-    reg = read_p15_c1();
-    cp_delay();
-    write_p15_c1(reg & ~C1_IDC);
-}
-
-int dcache_status(void)
-{
-    return (read_p15_c1() & C1_IDC) != 0;
-    return 0;
-}

cpu/at91rm9200/start.S

@@ -1,391 +0,0 @@
-/*
- *  armboot - Startup Code for ARM720 CPU-core
- *
- *  Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
- *  Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-#include "config.h"
-#include "version.h"
-
-
-/*
- *************************************************************************
- *
- * Jump vector table as in table 3.1 in [1]
- *
- *************************************************************************
- */
-
-
-.globl _start
-_start:	b       reset
-	ldr	pc, _undefined_instruction
-	ldr	pc, _software_interrupt
-	ldr	pc, _prefetch_abort
-	ldr	pc, _data_abort
-	ldr	pc, _not_used
-	ldr	pc, _irq
-	ldr	pc, _fiq
-
-_undefined_instruction:	.word undefined_instruction
-_software_interrupt:	.word software_interrupt
-_prefetch_abort:	.word prefetch_abort
-_data_abort:		.word data_abort
-_not_used:		.word not_used
-_irq:			.word irq
-_fiq:			.word fiq
-
-	.balignl 16,0xdeadbeef
-
-
-/*
- *************************************************************************
- *
- * Startup Code (reset vector)
- *
- * do important init only if we don't start from memory!
- * relocate armboot to ram
- * setup stack
- * jump to second stage
- *
- *************************************************************************
- */
-
-_TEXT_BASE:
-	.word	TEXT_BASE
-
-.globl _armboot_start
-_armboot_start:
-	.word _start
-
-/*
- * These are defined in the board-specific linker script.
- */
-.globl _bss_start
-_bss_start:
-	.word __bss_start
-
-.globl _bss_end
-_bss_end:
-	.word _end
-
-#ifdef CONFIG_USE_IRQ
-/* IRQ stack memory (calculated at run-time) */
-.globl IRQ_STACK_START
-IRQ_STACK_START:
-	.word	0x0badc0de
-
-/* IRQ stack memory (calculated at run-time) */
-.globl FIQ_STACK_START
-FIQ_STACK_START:
-	.word 0x0badc0de
-#endif
-
-
-/*
- * the actual reset code
- */
-
-reset:
-	/*
-	 * set the cpu to SVC32 mode
-	 */
-	mrs     r0,cpsr
-	bic     r0,r0,#0x1f
-	orr     r0,r0,#0xd3 /* was 13 */
-	msr     cpsr,r0
-
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-	/* scratch stack */
-/****	ldr 	r1, =0x00204000		****/
-	/* Insure word alignment */
-/****	bic     r1, r1, #3		****/
-	/* Init stack SYS	 */
-/****	mov     sp, r1			****/
-	/*
-	 * This does a lot more than just set up the memory, which
-	 * is why it's called lowlevel_init
-	 */
-	bl	lowlevel_init /* in lowlevel.S */
-
-	/*
-	 * Read/modify/write CP15 control register
-	 * disable MMU, enable I-Cache, select Asychronous Clocking Mode
-	 */
-
-	mrc     p15, 0, r0, c1, c0, 0	@ read cp15 control register (cp15 r1) in r0
-	bic	r0, r0, #0x00002300	@ clear bits 13, 9:8 (--V- --RS)
-	bic	r0, r0, #0x0000008f	@ clear bits 7, 3:0 (B--- WCAM)
-	orr	r0, r0, #0x00000002	@ set bit 2 (A) Align
-	orr	r0, r0, #0x00000004	@ set bit 3 (C) D-Cache
-	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-Cache
-	orr	r0, r0, #0xC0000000	@ set bits 31:30 (iA, nF)
-	mcr     p15, 0, r0, c1, c0, 0	@ write r0 in cp15 control register (cp15 r1)
-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
-	/*
-	 * relocate exeception table
-	 */
-	ldr	r0, =_start
-	ldr	r1, =0x0
-	mov	r2, #16
-copyex:
-	subs	r2, r2, #1
-	ldr	r3, [r0], #4
-	str	r3, [r1], #4
-	bne	copyex
-
-	/*
-	 * we do sys-critical inits only at reboot,
-	 * not when booting from ram!
-	 */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-	bl      cpu_init_crit
-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
-
-#ifndef CONFIG_SKIP_RELOCATE_UBOOT
-relocate:				/* relocate U-Boot to RAM	    */
-	adr	r0, _start		/* r0 <- current position of code   */
-	ldr	r1, _TEXT_BASE		/* test if we run from flash or RAM */
-	cmp     r0, r1                  /* don't reloc during debug         */
-	beq     stack_setup
-
-	ldr	r2, _armboot_start
-	ldr	r3, _bss_start
-	sub	r2, r3, r2		/* r2 <- size of armboot            */
-	add	r2, r0, r2		/* r2 <- source end address         */
-
-copy_loop:
-	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
-	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end addreee [r2]    */
-	ble	copy_loop
-#endif	/* CONFIG_SKIP_RELOCATE_UBOOT */
-
-	/* Set up the stack						    */
-stack_setup:
-	ldr	r0, _TEXT_BASE		/* upper 128 KiB: relocated uboot   */
-	sub	r0, r0, #CFG_MALLOC_LEN	/* malloc area                      */
-	sub	r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo                        */
-#ifdef CONFIG_USE_IRQ
-	sub	r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
-#endif
-	sub	sp, r0, #12		/* leave 3 words for abort-stack    */
-
-clear_bss:
-	ldr	r0, _bss_start		/* find start of bss segment        */
-	ldr	r1, _bss_end		/* stop here                        */
-	mov 	r2, #0x00000000		/* clear                            */
-
-clbss_l:str	r2, [r0]		/* clear loop...                    */
-	add	r0, r0, #4
-	cmp	r0, r1
-	ble	clbss_l
-
-	ldr pc,_start_armboot
-
-_start_armboot: .word start_armboot
-
-/*
- *************************************************************************
- *
- * CPU_init_critical registers
- *
- *************************************************************************
- */
-
-cpu_init_crit:
-	/* do nothing for now */
-	mov	pc, lr
-
-
-/*
- *************************************************************************
- *
- * Interrupt handling
- *
- *************************************************************************
- */
-
-@
-@ IRQ stack frame.
-@
-#define S_FRAME_SIZE	72
-
-#define S_OLD_R0	68
-#define S_PSR		64
-#define S_PC		60
-#define S_LR		56
-#define S_SP		52
-
-#define S_IP		48
-#define S_FP		44
-#define S_R10		40
-#define S_R9		36
-#define S_R8		32
-#define S_R7		28
-#define S_R6		24
-#define S_R5		20
-#define S_R4		16
-#define S_R3		12
-#define S_R2		8
-#define S_R1		4
-#define S_R0		0
-
-#define MODE_SVC 0x13
-#define I_BIT	 0x80
-
-/*
- * use bad_save_user_regs for abort/prefetch/undef/swi ...
- * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
- */
-
-	.macro	bad_save_user_regs
-	sub	sp, sp, #S_FRAME_SIZE
-	stmia	sp, {r0 - r12}			@ Calling r0-r12
-	add     r8, sp, #S_PC
-
-	ldr	r2, _armboot_start
-	sub	r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
-	sub	r2, r2, #(CFG_GBL_DATA_SIZE+8)  @ set base 2 words into abort stack
-	ldmia	r2, {r2 - r4}                   @ get pc, cpsr, old_r0
-	add	r0, sp, #S_FRAME_SIZE		@ restore sp_SVC
-
-	add	r5, sp, #S_SP
-	mov	r1, lr
-	stmia	r5, {r0 - r4}                   @ save sp_SVC, lr_SVC, pc, cpsr, old_r
-	mov	r0, sp
-	.endm
-
-	.macro	irq_save_user_regs
-	sub	sp, sp, #S_FRAME_SIZE
-	stmia	sp, {r0 - r12}			@ Calling r0-r12
-	add     r8, sp, #S_PC
-	stmdb   r8, {sp, lr}^                   @ Calling SP, LR
-	str     lr, [r8, #0]                    @ Save calling PC
-	mrs     r6, spsr
-	str     r6, [r8, #4]                    @ Save CPSR
-	str     r0, [r8, #8]                    @ Save OLD_R0
-	mov	r0, sp
-	.endm
-
-	.macro	irq_restore_user_regs
-	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
-	mov	r0, r0
-	ldr	lr, [sp, #S_PC]			@ Get PC
-	add	sp, sp, #S_FRAME_SIZE
-	subs	pc, lr, #4			@ return & move spsr_svc into cpsr
-	.endm
-
-	.macro get_bad_stack
-	ldr	r13, _armboot_start		@ setup our mode stack
-	sub	r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
-	sub	r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
-
-	str	lr, [r13]			@ save caller lr / spsr
-	mrs	lr, spsr
-	str     lr, [r13, #4]
-
-	mov	r13, #MODE_SVC			@ prepare SVC-Mode
-	msr	spsr_c, r13
-	mov	lr, pc
-	movs	pc, lr
-	.endm
-
-	.macro get_irq_stack			@ setup IRQ stack
-	ldr	sp, IRQ_STACK_START
-	.endm
-
-	.macro get_fiq_stack			@ setup FIQ stack
-	ldr	sp, FIQ_STACK_START
-	.endm
-
-/*
- * exception handlers
- */
-	.align  5
-undefined_instruction:
-	get_bad_stack
-	bad_save_user_regs
-	bl 	do_undefined_instruction
-
-	.align	5
-software_interrupt:
-	get_bad_stack
-	bad_save_user_regs
-	bl 	do_software_interrupt
-
-	.align	5
-prefetch_abort:
-	get_bad_stack
-	bad_save_user_regs
-	bl 	do_prefetch_abort
-
-	.align	5
-data_abort:
-	get_bad_stack
-	bad_save_user_regs
-	bl 	do_data_abort
-
-	.align	5
-not_used:
-	get_bad_stack
-	bad_save_user_regs
-	bl 	do_not_used
-
-#ifdef CONFIG_USE_IRQ
-
-	.align	5
-irq:
-	get_irq_stack
-	irq_save_user_regs
-	bl 	do_irq
-	irq_restore_user_regs
-
-	.align	5
-fiq:
-	get_fiq_stack
-	/* someone ought to write a more effiction fiq_save_user_regs */
-	irq_save_user_regs
-	bl 	do_fiq
-	irq_restore_user_regs
-
-#else
-
-	.align	5
-irq:
-	get_bad_stack
-	bad_save_user_regs
-	bl 	do_irq
-
-	.align	5
-fiq:
-	get_bad_stack
-	bad_save_user_regs
-	bl 	do_fiq
-
-#endif
-
-	.align	5
-.globl reset_cpu
-reset_cpu:
-	mov     pc, r0

include/configs/adsvix.h

@@ -33,13 +33,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-/*
- * If we are developing, we might want to start armboot from ram
- * so we MUST NOT initialize critical regs like mem-timing ...
- */
-#define CONFIG_INIT_CRITICAL		/* undef for developing */
-#define RTC
-
 /*
  * High Level Configuration Options
  * (easy to change)
@@ -51,6 +44,8 @@
 
 #undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */
 
+#define RTC
+
 /*
  * Size of malloc() pool
  */

include/configs/at91rm9200dk.h

@@ -32,8 +32,12 @@
 
 #define AT91_SLOW_CLOCK		32768	/* slow clock */
 
-#define CONFIG_AT91RM9200DK	1	/* on an AT91RM9200DK Board	 */
-#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */
+#define CONFIG_ARM920T		1	/* This is an ARM920T Core	*/
+#define CONFIG_AT91RM9200	1	/* It's an Atmel AT91RM9200 SoC	*/
+#define CONFIG_AT91RM9200DK	1	/* on an AT91RM9200DK Board	*/
+#undef  CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/
+#define USE_920T_MMU		1
+
 #define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs	*/
 #define CONFIG_SETUP_MEMORY_TAGS 1
 #define CONFIG_INITRD_TAG	1

include/configs/cmc_pu2.h

@@ -31,9 +31,13 @@
 
 #define AT91_SLOW_CLOCK		32768	/* slow clock */
 
-#define CONFIG_AT91RM9200DK	1	/* on an AT91RM9200DK Board	 */
-#define CONFIG_CMC_PU2		1	/* on an CMC_PU2 Board	 */
-#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */
+#define CONFIG_ARM920T		1	/* This is an ARM920T Core	*/
+#define CONFIG_AT91RM9200	1	/* It's an Atmel AT91RM9200 SoC	*/
+#define CONFIG_AT91RM9200DK	1	/* on an AT91RM9200DK Board	*/
+#define CONFIG_CMC_PU2		1	/* on an CMC_PU2 Board		*/
+#undef  CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/
+#define USE_920T_MMU		1
+
 #define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs	*/
 #define CONFIG_SETUP_MEMORY_TAGS 1
 #define CONFIG_INITRD_TAG	1