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@@ -33,6 +33,7 @@
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DECLARE_GLOBAL_DATA_PTR;
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DECLARE_GLOBAL_DATA_PTR;
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+#ifndef CONFIG_PRELOADER
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int dram_init(void)
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int dram_init(void)
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{
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{
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/* dram_init must store complete ramsize in gd->ram_size */
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/* dram_init must store complete ramsize in gd->ram_size */
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@@ -47,6 +48,7 @@ void dram_init_banksize(void)
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gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
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gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
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gd->bd->bi_dram[0].size = gd->ram_size;
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gd->bd->bi_dram[0].size = gd->ram_size;
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}
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}
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+#endif
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#ifdef CONFIG_DRIVER_TI_EMAC
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#ifdef CONFIG_DRIVER_TI_EMAC
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@@ -75,6 +77,22 @@ err:
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return 0;
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return 0;
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}
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}
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+/*
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+ * Set the mii mode as MII or RMII
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+ */
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+#if defined(CONFIG_DRIVER_TI_EMAC)
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+void davinci_emac_mii_mode_sel(int mode_sel)
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+{
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+ int val;
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+
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+ val = readl(&davinci_syscfg_regs->cfgchip3);
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+ if (mode_sel == 0)
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+ val &= ~(1 << 8);
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+ else
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+ val |= (1 << 8);
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+ writel(val, &davinci_syscfg_regs->cfgchip3);
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+}
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+#endif
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/*
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/*
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* If there is no MAC address in the environment, then it will be initialized
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* If there is no MAC address in the environment, then it will be initialized
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* (silently) from the value in the EEPROM.
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* (silently) from the value in the EEPROM.
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@@ -94,4 +112,38 @@ void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr)
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}
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}
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}
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}
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-#endif /* DAVINCI_EMAC */
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+#endif /* CONFIG_DRIVER_TI_EMAC */
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+
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+#if defined(CONFIG_SOC_DA8XX)
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+#ifndef CONFIG_USE_IRQ
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+void irq_init(void)
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+{
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+ /*
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+ * Mask all IRQs by clearing the global enable and setting
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+ * the enable clear for all the 90 interrupts.
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+ */
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+
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+ writel(0, &davinci_aintc_regs->ger);
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+
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+ writel(0, &davinci_aintc_regs->hier);
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+
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+ writel(0xffffffff, &davinci_aintc_regs->ecr1);
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+ writel(0xffffffff, &davinci_aintc_regs->ecr2);
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+ writel(0xffffffff, &davinci_aintc_regs->ecr3);
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+}
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+#endif
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+
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+/*
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+ * Enable PSC for various peripherals.
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+ */
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+int da8xx_configure_lpsc_items(const struct lpsc_resource *item,
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+ const int n_items)
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+{
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+ int i;
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+
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+ for (i = 0; i < n_items; i++)
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+ lpsc_on(item[i].lpsc_no);
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+
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+ return 0;
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+}
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+#endif
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